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dissertation_thesis
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ariths-gen
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ariths-gen
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ariths_gen
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core
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honzastor
cfb5bba3ec
Bitwise and operation fix.
2021-10-10 00:02:58 +02:00
..
arithmetic_circuits
Added signedness support for the output C code representation. Also modified the testing scripts and the chr2c.py converter accordingly and did some documentation changes (even made a small change in readme.md). Signedness support for the output python representation is TBD.
2021-10-09 23:45:54 +02:00
logic_gate_circuits
Bitwise and operation fix.
2021-10-10 00:02:58 +02:00
one_bit_circuits
Bitwise and operation fix.
2021-10-10 00:02:58 +02:00
__init__.py
Optimized circuits generation, refactored code, fixed cla, added new csa, array divider circuits and create yosys equivalence check script. TBD: Documentation and sample generated circuits.
2021-04-21 11:33:07 +02:00