mirror of
https://github.com/ehw-fit/ariths-gen.git
synced 2025-04-22 06:41:22 +01:00
56c86c13ca
* #10 CGP Circuits as inputs (#11) * CGP Circuits as inputs * #10 support of signed output in general circuit * input as output works * output connected to input (c) * automated verilog testing * output rename * Implemented CSA and Wallace tree multiplier composing of CSAs. Also did some code cleanup. * Typos fix and code cleanup. * Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats. * Updated automated testing scripts. * Small bugfix in python code generation (I initially thought this line is useless). * Updated generated circuits folder. Co-authored-by: Vojta Mrazek <mrazek@fit.vutbr.cz>
80 lines
3.9 KiB
C
80 lines
3.9 KiB
C
#include <stdio.h>
|
|
#include <stdint.h>
|
|
|
|
uint64_t u_cla4(uint64_t a, uint64_t b){
|
|
uint8_t u_cla4_out = 0;
|
|
uint8_t u_cla4_pg_logic0_or0 = 0;
|
|
uint8_t u_cla4_pg_logic0_and0 = 0;
|
|
uint8_t u_cla4_pg_logic0_xor0 = 0;
|
|
uint8_t u_cla4_pg_logic1_or0 = 0;
|
|
uint8_t u_cla4_pg_logic1_and0 = 0;
|
|
uint8_t u_cla4_pg_logic1_xor0 = 0;
|
|
uint8_t u_cla4_xor1 = 0;
|
|
uint8_t u_cla4_and0 = 0;
|
|
uint8_t u_cla4_or0 = 0;
|
|
uint8_t u_cla4_pg_logic2_or0 = 0;
|
|
uint8_t u_cla4_pg_logic2_and0 = 0;
|
|
uint8_t u_cla4_pg_logic2_xor0 = 0;
|
|
uint8_t u_cla4_xor2 = 0;
|
|
uint8_t u_cla4_and1 = 0;
|
|
uint8_t u_cla4_and2 = 0;
|
|
uint8_t u_cla4_and3 = 0;
|
|
uint8_t u_cla4_and4 = 0;
|
|
uint8_t u_cla4_or1 = 0;
|
|
uint8_t u_cla4_or2 = 0;
|
|
uint8_t u_cla4_pg_logic3_or0 = 0;
|
|
uint8_t u_cla4_pg_logic3_and0 = 0;
|
|
uint8_t u_cla4_pg_logic3_xor0 = 0;
|
|
uint8_t u_cla4_xor3 = 0;
|
|
uint8_t u_cla4_and5 = 0;
|
|
uint8_t u_cla4_and6 = 0;
|
|
uint8_t u_cla4_and7 = 0;
|
|
uint8_t u_cla4_and8 = 0;
|
|
uint8_t u_cla4_and9 = 0;
|
|
uint8_t u_cla4_and10 = 0;
|
|
uint8_t u_cla4_and11 = 0;
|
|
uint8_t u_cla4_or3 = 0;
|
|
uint8_t u_cla4_or4 = 0;
|
|
uint8_t u_cla4_or5 = 0;
|
|
|
|
u_cla4_pg_logic0_or0 = ((a >> 0) & 0x01) | ((b >> 0) & 0x01);
|
|
u_cla4_pg_logic0_and0 = ((a >> 0) & 0x01) & ((b >> 0) & 0x01);
|
|
u_cla4_pg_logic0_xor0 = ((a >> 0) & 0x01) ^ ((b >> 0) & 0x01);
|
|
u_cla4_pg_logic1_or0 = ((a >> 1) & 0x01) | ((b >> 1) & 0x01);
|
|
u_cla4_pg_logic1_and0 = ((a >> 1) & 0x01) & ((b >> 1) & 0x01);
|
|
u_cla4_pg_logic1_xor0 = ((a >> 1) & 0x01) ^ ((b >> 1) & 0x01);
|
|
u_cla4_xor1 = ((u_cla4_pg_logic1_xor0 >> 0) & 0x01) ^ ((u_cla4_pg_logic0_and0 >> 0) & 0x01);
|
|
u_cla4_and0 = ((u_cla4_pg_logic0_and0 >> 0) & 0x01) & ((u_cla4_pg_logic1_or0 >> 0) & 0x01);
|
|
u_cla4_or0 = ((u_cla4_pg_logic1_and0 >> 0) & 0x01) | ((u_cla4_and0 >> 0) & 0x01);
|
|
u_cla4_pg_logic2_or0 = ((a >> 2) & 0x01) | ((b >> 2) & 0x01);
|
|
u_cla4_pg_logic2_and0 = ((a >> 2) & 0x01) & ((b >> 2) & 0x01);
|
|
u_cla4_pg_logic2_xor0 = ((a >> 2) & 0x01) ^ ((b >> 2) & 0x01);
|
|
u_cla4_xor2 = ((u_cla4_pg_logic2_xor0 >> 0) & 0x01) ^ ((u_cla4_or0 >> 0) & 0x01);
|
|
u_cla4_and1 = ((u_cla4_pg_logic2_or0 >> 0) & 0x01) & ((u_cla4_pg_logic0_or0 >> 0) & 0x01);
|
|
u_cla4_and2 = ((u_cla4_pg_logic0_and0 >> 0) & 0x01) & ((u_cla4_pg_logic2_or0 >> 0) & 0x01);
|
|
u_cla4_and3 = ((u_cla4_and2 >> 0) & 0x01) & ((u_cla4_pg_logic1_or0 >> 0) & 0x01);
|
|
u_cla4_and4 = ((u_cla4_pg_logic1_and0 >> 0) & 0x01) & ((u_cla4_pg_logic2_or0 >> 0) & 0x01);
|
|
u_cla4_or1 = ((u_cla4_and3 >> 0) & 0x01) | ((u_cla4_and4 >> 0) & 0x01);
|
|
u_cla4_or2 = ((u_cla4_pg_logic2_and0 >> 0) & 0x01) | ((u_cla4_or1 >> 0) & 0x01);
|
|
u_cla4_pg_logic3_or0 = ((a >> 3) & 0x01) | ((b >> 3) & 0x01);
|
|
u_cla4_pg_logic3_and0 = ((a >> 3) & 0x01) & ((b >> 3) & 0x01);
|
|
u_cla4_pg_logic3_xor0 = ((a >> 3) & 0x01) ^ ((b >> 3) & 0x01);
|
|
u_cla4_xor3 = ((u_cla4_pg_logic3_xor0 >> 0) & 0x01) ^ ((u_cla4_or2 >> 0) & 0x01);
|
|
u_cla4_and5 = ((u_cla4_pg_logic3_or0 >> 0) & 0x01) & ((u_cla4_pg_logic1_or0 >> 0) & 0x01);
|
|
u_cla4_and6 = ((u_cla4_pg_logic0_and0 >> 0) & 0x01) & ((u_cla4_pg_logic2_or0 >> 0) & 0x01);
|
|
u_cla4_and7 = ((u_cla4_pg_logic3_or0 >> 0) & 0x01) & ((u_cla4_pg_logic1_or0 >> 0) & 0x01);
|
|
u_cla4_and8 = ((u_cla4_and6 >> 0) & 0x01) & ((u_cla4_and7 >> 0) & 0x01);
|
|
u_cla4_and9 = ((u_cla4_pg_logic1_and0 >> 0) & 0x01) & ((u_cla4_pg_logic3_or0 >> 0) & 0x01);
|
|
u_cla4_and10 = ((u_cla4_and9 >> 0) & 0x01) & ((u_cla4_pg_logic2_or0 >> 0) & 0x01);
|
|
u_cla4_and11 = ((u_cla4_pg_logic2_and0 >> 0) & 0x01) & ((u_cla4_pg_logic3_or0 >> 0) & 0x01);
|
|
u_cla4_or3 = ((u_cla4_and8 >> 0) & 0x01) | ((u_cla4_and11 >> 0) & 0x01);
|
|
u_cla4_or4 = ((u_cla4_and10 >> 0) & 0x01) | ((u_cla4_or3 >> 0) & 0x01);
|
|
u_cla4_or5 = ((u_cla4_pg_logic3_and0 >> 0) & 0x01) | ((u_cla4_or4 >> 0) & 0x01);
|
|
|
|
u_cla4_out |= ((u_cla4_pg_logic0_xor0 >> 0) & 0x01ull) << 0;
|
|
u_cla4_out |= ((u_cla4_xor1 >> 0) & 0x01ull) << 1;
|
|
u_cla4_out |= ((u_cla4_xor2 >> 0) & 0x01ull) << 2;
|
|
u_cla4_out |= ((u_cla4_xor3 >> 0) & 0x01ull) << 3;
|
|
u_cla4_out |= ((u_cla4_or5 >> 0) & 0x01ull) << 4;
|
|
return u_cla4_out;
|
|
} |