This website requires JavaScript.
Explore
Help
Sign In
dissertation_thesis
/
ariths-gen
Watch
1
Star
0
Fork
0
You've already forked ariths-gen
mirror of
https://github.com/ehw-fit/ariths-gen.git
synced
2025-04-22 06:41:22 +01:00
Code
Issues
Actions
Packages
Projects
Releases
Wiki
Activity
ariths-gen
/
Tests
/
C_circuits
/
Logic_gates
History
honzastor
c9ddb834f7
Generated flat Verilog adder and gate circuits. Minor update to C code logic gates.
2021-02-16 10:38:36 +01:00
..
and_gate.c
Generated flat Verilog adder and gate circuits. Minor update to C code logic gates.
2021-02-16 10:38:36 +01:00
nand_gate.c
Generated flat Verilog adder and gate circuits. Minor update to C code logic gates.
2021-02-16 10:38:36 +01:00
nor_gate.c
Generated flat Verilog adder and gate circuits. Minor update to C code logic gates.
2021-02-16 10:38:36 +01:00
not_gate.c
Generated flat Verilog adder and gate circuits. Minor update to C code logic gates.
2021-02-16 10:38:36 +01:00
or_gate.c
Generated flat Verilog adder and gate circuits. Minor update to C code logic gates.
2021-02-16 10:38:36 +01:00
xnor_gate.c
Generated flat Verilog adder and gate circuits. Minor update to C code logic gates.
2021-02-16 10:38:36 +01:00
xor_gate.c
Generated flat Verilog adder and gate circuits. Minor update to C code logic gates.
2021-02-16 10:38:36 +01:00
