Vojta Mrazek c6e542231c CGP tests; reversed output order

2021-06-23 13:43:58 +02:00

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arithmetic_circuits

CGP tests; reversed output order

2021-06-23 13:43:58 +02:00

logic_gate_circuits

Fixed proper connections in submodules instantiation in hierarchical Verilog generation. Sample generated circuits were also accordingly updated.

2021-04-23 11:49:24 +02:00

one_bit_circuits

Fixed proper connections in submodules instantiation in hierarchical Verilog generation. Sample generated circuits were also accordingly updated.

2021-04-23 11:49:24 +02:00

__init__.py

Optimized circuits generation, refactored code, fixed cla, added new csa, array divider circuits and create yosys equivalence check script. TBD: Documentation and sample generated circuits.

2021-04-21 11:33:07 +02:00