mirror of
https://github.com/ehw-fit/ariths-gen.git
synced 2025-04-19 13:30:56 +01:00
484 lines
24 KiB
Python
484 lines
24 KiB
Python
from logic_gates import logic_gate, and_gate, nand_gate, or_gate, nor_gate, xor_gate, xnor_gate, not_gate
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from wire_components import wire, bus
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import math
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""" ARITHMETIC CIRCUITS """
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class arithmetic_circuit():
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def __init__(self):
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self.components = []
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self.circuit_wires = []
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self.inputs = []
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self.circuit_gates = []
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self.c_data_type = "uint64_t"
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self.N = 1
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def add_component(self, component):
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self.components.append(component)
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def get_previous_component(self, number: int = 1):
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return self.components[-number]
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def get_instance_num(self, cls):
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return sum(isinstance(c, cls) for c in self.components)
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def get_unique_one_bit_components(self):
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one_bit_comps = []
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for c in self.components:
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if isinstance(c, logic_gate):
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continue
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elif type(getattr(c, 'a')) == wire:
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one_bit_comps.append(c)
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else:
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one_bit_comps.extend(c.get_unique_one_bit_components())
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return one_bit_comps
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def get_unique_multi_bit_components(self):
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multi_bit_comps = []
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for c in self.components:
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if isinstance(c, logic_gate):
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continue
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elif type(getattr(c, 'a')) == wire:
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continue
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else:
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multi_bit_comps.append(c)
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return multi_bit_comps
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@staticmethod
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def get_unique_types(components: list):
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return list({type(c): c for c in components}.values())
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def get_component_types(self):
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gate_comps = self.get_unique_types(components=self.get_circuit_gates())
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one_bit_comps = self.get_unique_types(components=self.get_unique_one_bit_components())
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multi_bit_comps = self.get_unique_types(components=self.get_unique_multi_bit_components())
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all_components = gate_comps + one_bit_comps + multi_bit_comps
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return all_components
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def get_sum_wire(self):
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return self.out.get_wire(0)
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def get_carry_wire(self):
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return self.out.get_wire(1)
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def get_circuit_wires(self):
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self.circuit_wires = []
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for component in self.components:
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if not [item for item in self.circuit_wires if item[1] == component.a.name]:
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self.circuit_wires.append((component.a, component.a.name, len(self.circuit_wires)))
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if not [item for item in self.circuit_wires if item[1] == component.b.name]:
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self.circuit_wires.append((component.b, component.b.name, len(self.circuit_wires)))
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if not [item for item in self.circuit_wires if item[1] == component.out.name]:
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self.circuit_wires.append((component.out, component.out.name, len(self.circuit_wires)))
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# Get unique names of all inner input circuits (mainly used in one bit circuits)
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self.inputs = [i[0] for i in self.circuit_wires if i[0] not in [o.out for o in self.components]]
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# Search for circuit's wire unique index for cgp chromosome generation
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def get_circuit_wire_index(self, wire: wire):
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for w in self.circuit_wires:
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if wire.name.endswith(w[1]):
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return w[2]
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# Get list of all gates present in circuit
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def get_circuit_gates(self):
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gates = []
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for c in self.components:
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if isinstance(c, logic_gate):
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gates.append(c)
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else:
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gates.extend((c.get_circuit_gates()))
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return gates
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# Get list of all wires in circuit along with their index position for cgp chromosome generation
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def get_cgp_wires(self):
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self.circuit_wires = []
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if isinstance(self.a, bus):
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[self.circuit_wires.append((w, f"_{w.name}", len(self.circuit_wires))) for w in self.a.bus]
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[self.circuit_wires.append((w, f"_{w.name}", len(self.circuit_wires))) for w in self.b.bus]
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else:
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self.circuit_wires.append((self.a, f"_{self.a.name}", len(self.circuit_wires)))
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self.circuit_wires.append((self.b, f"_{self.b.name}", len(self.circuit_wires)))
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if hasattr(self, 'c'):
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self.circuit_wires.append((self.c, f"_{self.c.name}", len(self.circuit_wires)))
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for gate in self.circuit_gates:
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if not [item for item in self.circuit_wires if gate.a.name.endswith(item[1])]:
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self.circuit_wires.append((gate.a, gate.a.name, len(self.circuit_wires)))
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if not [item for item in self.circuit_wires if gate.b.name.endswith(item[1])]:
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self.circuit_wires.append((gate.b, gate.b.name, len(self.circuit_wires)))
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if not [item for item in self.circuit_wires if gate.out.name.endswith(item[1])]:
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self.circuit_wires.append((gate.out, gate.out.name, len(self.circuit_wires)))
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""" C CODE GENERATION """
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# FLAT C #
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@staticmethod
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def get_includes_c():
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return f"#include <stdio.h>\n#include <stdint.h>\n\n"
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def get_prototype_c(self):
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return f"{self.c_data_type} {self.prefix}({self.c_data_type} {self.a.prefix}, {self.c_data_type} {self.b.prefix})" + "{" + "\n"
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def get_declarations_c_flat(self):
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return f"{self.a.get_wire_declaration_c()}" + \
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f"{self.b.get_wire_declaration_c()}" + \
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f"".join([c.get_declaration_c_flat() for c in self.components])
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# For multi-bit circuit wires declaration
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def get_declaration_c_flat(self):
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return f"".join([c.get_declaration_c_flat() for c in self.components])
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def get_inits_c_flat(self):
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return f"{self.a.get_wire_assign_c()}" + \
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f"{self.b.get_wire_assign_c()}" + \
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"".join([c.get_assign_c_flat() if isinstance(c, logic_gate) else c.get_init_c_flat() for c in self.components])
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# For multi-bit circuit wires initialization
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def get_init_c_flat(self):
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return "".join([c.get_assign_c_flat() if isinstance(c, logic_gate) else c.get_init_c_flat() for c in self.components])
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def get_function_out_c_flat(self):
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return "".join([f" {self.out.prefix} |= {o.return_wire_value_c(offset=self.out.bus.index(o))};\n" for o in self.out.bus])
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# Generating flat C code representation of circuit
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def get_c_code_flat(self, file_object):
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file_object.write(self.get_includes_c())
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file_object.write(self.get_prototype_c())
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file_object.write(self.out.get_declaration_c())
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file_object.write(self.get_declarations_c_flat()+"\n")
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file_object.write(self.get_inits_c_flat()+"\n")
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file_object.write(self.get_function_out_c_flat())
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file_object.write(f" return {self.out.prefix}"+";\n}")
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file_object.close()
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# HIERARCHICAL C #
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def get_function_blocks_c(self):
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# Add unique component types composing this circuit
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self.component_types = self.get_component_types()
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return "".join([c.get_function_block_c() for c in self.component_types])
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def get_function_block_c(self):
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adder_block = type(self)(a=bus(N=self.N, prefix="a"), b=bus(N=self.N, prefix="b"))
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return f"{adder_block.get_circuit_c()}\n\n"
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def get_declaration_c_hier(self):
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return "".join(self.a.get_wire_declaration_c()) + \
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"".join(self.b.get_wire_declaration_c()) + \
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"".join([c.out.get_declaration_c() if isinstance(c, logic_gate) else c.get_wire_declaration_c_hier() for c in self.components])
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def get_wire_declaration_c_hier(self):
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return f" {self.c_data_type} {self.prefix}_{self.a.prefix} = 0;\n" + \
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f" {self.c_data_type} {self.prefix}_{self.b.prefix} = 0;\n" + \
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f" {self.c_data_type} {self.prefix}_{self.out.prefix} = 0;\n" + \
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f"{self.out.get_wire_declaration_c()}"
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def get_init_c_hier(self):
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return f"{self.a.get_wire_assign_c()}" + \
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f"{self.b.get_wire_assign_c()}" + \
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"".join([f" {c.out.name} = {c.get_gate_invocation_c()}" if isinstance(c, logic_gate) else c.get_out_invocation_c(circuit_prefix=self.prefix) for c in self.components])
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def get_out_invocation_c(self, circuit_prefix: str):
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# Getting name of circuit type and insitu copying out bus for proper C code generation without affecting actual generated composition
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circuit_type = self.prefix.replace(circuit_prefix+"_", "")
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out = bus(prefix=self.prefix+"_"+self.out.prefix, wires_list=self.out.bus)
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return "".join([f" {self.prefix}_{self.a.prefix} |= {w.return_wire_value_c(offset=self.a.bus.index(w))};\n" for w in self.a.bus]) + \
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"".join([f" {self.prefix}_{self.b.prefix} |= {w.return_wire_value_c(offset=self.b.bus.index(w))};\n" for w in self.b.bus]) + \
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f" {out.prefix} = {circuit_type}({self.prefix}_{self.a.prefix}, {self.prefix}_{self.b.prefix});\n" + \
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f"{out.get_wire_assign_c()}"
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def get_function_out_c_hier(self):
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return "".join([f" {self.out.prefix} |= {o.return_wire_value_c(offset=self.out.bus.index(o))};\n" for o in self.out.bus])
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def get_circuit_c(self):
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return f"{self.get_prototype_c()}" + \
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f"{self.out.get_declaration_c()}" + \
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f"{self.get_declaration_c_hier()}\n" + \
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f"{self.get_init_c_hier()}\n" + \
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f"{self.get_function_out_c_hier()}" + \
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f" return {self.out.prefix}"+";\n}"
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# Generating hierarchical C code representation of circuit
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def get_c_code_hier(self, file_object):
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file_object.write(self.get_includes_c())
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file_object.write(self.get_function_blocks_c())
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file_object.write(self.get_circuit_c())
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file_object.close()
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""" VERILOG CODE GENERATION """
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# FLAT VERILOG #
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def get_prototype_v(self):
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return f"module {self.prefix}(input [{self.N-1}:0] {self.a.prefix}, input [{self.N-1}:0] {self.b.prefix}, output [{self.out.N-1}:0] {self.out.prefix});\n"
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def get_declarations_v_flat(self):
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return f"{self.a.get_wire_declaration_v()}" + \
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f"{self.b.get_wire_declaration_v()}" + \
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f"".join([c.get_declaration_v_flat() for c in self.components])
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def get_declaration_v_flat(self):
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return f"".join([c.get_declaration_v_flat() for c in self.components])
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def get_inits_v_flat(self):
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return f"{self.a.get_wire_assign_v()}" + \
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f"{self.b.get_wire_assign_v()}" + \
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"".join([c.get_assign_v_flat() if isinstance(c, logic_gate) else c.get_init_v_flat() for c in self.components])
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def get_init_v_flat(self):
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return "".join([c.get_assign_v_flat() if isinstance(c, logic_gate) else c.get_init_v_flat() for c in self.components])
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def get_function_out_v_flat(self):
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return "".join([f" assign {self.out.prefix}[{self.out.bus.index(o)}] = {o.prefix};\n" for o in self.out.bus])
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# Generating flat Verilog code representation of circuit
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def get_v_code_flat(self, file_object):
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file_object.write(self.get_prototype_v())
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file_object.write(self.get_declarations_v_flat()+"\n")
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file_object.write(self.get_inits_v_flat() + "\n")
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file_object.write(self.get_function_out_v_flat())
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file_object.write(f"endmodule")
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file_object.close()
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# HIERARCHICAL VERILOG #
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def get_function_blocks_v(self):
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# Add unique component types composing this circuit
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self.component_types = self.get_component_types()
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return "".join([c.get_function_block_v() for c in self.component_types])
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def get_function_block_v(self):
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adder_block = type(self)(a=bus(N=self.N, prefix="a"), b=bus(N=self.N, prefix="b"))
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return f"{adder_block.get_circuit_v()}\n\n"
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def get_declaration_v_hier(self):
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return "".join(self.a.get_wire_declaration_v()) + \
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"".join(self.b.get_wire_declaration_v()) + \
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"".join([c.out.get_declaration_v() if isinstance(c, logic_gate) else c.get_wire_declaration_v_hier() for c in self.components])
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def get_wire_declaration_v_hier(self):
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return f" wire [{self.a.N-1}:0] {self.prefix}_{self.a.prefix};\n" + \
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f" wire [{self.b.N-1}:0] {self.prefix}_{self.b.prefix};\n" + \
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f" wire [{self.out.N-1}:0] {self.prefix}_{self.out.prefix};\n" + \
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f"{self.out.get_wire_declaration_v()}"
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def get_init_v_hier(self):
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return f"{self.a.get_wire_assign_v()}" + \
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f"{self.b.get_wire_assign_v()}" + \
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"".join([c.get_gate_invocation_v() if isinstance(c, logic_gate) else c.get_invocation_v(circuit_prefix=self.prefix) for c in self.components])
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def get_invocation_v(self, circuit_prefix: str):
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# Getting name of circuit type and insitu copying out bus for proper Verilog code generation without affecting actual generated composition
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circuit_type = self.prefix.replace(circuit_prefix+"_", "")
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out = bus(prefix=self.prefix+"_"+self.out.prefix, wires_list=self.out.bus)
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return "".join([f" assign {self.prefix}_{self.a.prefix}[{self.a.bus.index(w)}] = {w.name};\n" for w in self.a.bus]) + \
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"".join([f" assign {self.prefix}_{self.b.prefix}[{self.b.bus.index(w)}] = {w.name};\n" for w in self.b.bus]) + \
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f" {circuit_type} {circuit_type}_{self.out.prefix}({self.prefix}_{self.a.prefix}, {self.prefix}_{self.b.prefix}, {out.prefix});\n" + \
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f"{out.get_wire_assign_v()}"
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def get_function_out_v_hier(self):
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return "".join([f" assign {self.out.prefix}[{self.out.bus.index(o)}] = {o.name};\n" for o in self.out.bus])
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def get_circuit_v(self):
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return f"{self.get_prototype_v()}" + \
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f"{self.get_declaration_v_hier()}\n" + \
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f"{self.get_init_v_hier()}\n" + \
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f"{self.get_function_out_v_hier()}" + \
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f"endmodule"
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# Generating hierarchical Verilog code representation of circuit
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def get_v_code_hier(self, file_object):
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file_object.write(self.get_function_blocks_v())
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file_object.write(self.get_circuit_v())
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file_object.close()
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""" BLIF CODE GENERATION """
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# FLAT BLIF #
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def get_prototype_blif(self):
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return f".model {self.prefix}\n"
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def get_declaration_blif(self):
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if self.N == 1:
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return f".inputs {self.a.prefix} {self.b.prefix}\n" + \
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f".outputs{self.out.get_wire_declaration_blif()}\n" + \
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f"{self.a.get_wire().get_assign_blif(name=self.a.prefix)}" + \
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f"{self.b.get_wire().get_assign_blif(name=self.b.prefix)}"
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else:
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return f".inputs {self.a.get_wire_declaration_blif()}{self.b.get_wire_declaration_blif()}\n" + \
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f".outputs{self.out.get_wire_declaration_blif()}\n" + \
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f"{self.a.get_wire_assign_blif()}" + \
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f"{self.b.get_wire_assign_blif()}"
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def get_function_blif_flat(self):
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return "".join(c.get_init_function_blif_flat() if isinstance(c, logic_gate) else c.get_function_blif_flat() for c in self.components)
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def get_function_out_blif(self):
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return f"{self.out.get_wire_assign_blif(output=True)}"
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# Generating flat BLIF code representation of circuit
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def get_blif_code_flat(self, file_object):
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file_object.write(self.get_prototype_blif())
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file_object.write(self.get_declaration_blif())
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file_object.write(self.get_function_blif_flat())
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file_object.write(self.get_function_out_blif())
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file_object.write(f".end\n")
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file_object.close()
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# HIERARCHICAL BLIF #
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def get_function_blif_hier(self):
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return "".join(c.get_invocation_blif_hier(init=True) if isinstance(c, logic_gate) else c.get_invocation_blif_hier(circuit_prefix=self.prefix) for c in self.components)
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def get_invocation_blif_hier(self, circuit_prefix: str):
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# Getting name of circuit type for proper Blif code generation without affecting actual generated composition
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circuit_type = self.prefix.replace(circuit_prefix+"_", "")
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return "".join([w.get_assign_blif(name=self.prefix+'_'+self.a.prefix+f'[{self.a.bus.index(w)}]', output=True)for w in self.a.bus]) + \
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"".join([w.get_assign_blif(name=self.prefix+'_'+self.b.prefix+f'[{self.b.bus.index(w)}]', output=True)for w in self.b.bus]) + \
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f".subckt {circuit_type}" + \
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"".join([f" a[{self.a.bus.index(w)}]={self.prefix}_{self.a.prefix}[{self.a.bus.index(w)}]" for w in self.a.bus]) + \
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"".join([f" b[{self.b.bus.index(w)}]={self.prefix}_{self.b.prefix}[{self.b.bus.index(w)}]" for w in self.b.bus]) + \
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"".join([f" out[{self.out.bus.index(o)}]={o.name}" for o in self.out.bus]) + "\n"
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def get_circuit_blif(self):
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return f"{self.get_prototype_blif()}" + \
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f"{self.get_declaration_blif()}" + \
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f"{self.get_function_blif_hier()}" + \
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f"{self.get_function_out_blif()}" + \
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f".end\n"
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def get_function_blocks_blif(self):
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# Add unique component types composing this circuit
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self.component_types = self.get_component_types()
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return "\n".join([c.get_function_block_blif() for c in self.component_types[::-1]])
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def get_function_block_blif(self):
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adder_block = type(self)(a=bus(N=self.N, prefix="a"), b=bus(N=self.N, prefix="b"))
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return f"{adder_block.get_circuit_blif()}"
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# Generating hierarchical BLIF code representation of circuit
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def get_blif_code_hier(self, file_object):
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file_object.write(self.get_circuit_blif()+"\n")
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file_object.write(self.get_function_blocks_blif())
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file_object.close()
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""" CGP CODE GENERATION """
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# FLAT CGP #
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def get_parameters_cgp(self):
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self.circuit_gates = self.get_circuit_gates()
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return f"{{{self.a.N+self.a.N},{self.out.N},1,{len(self.circuit_gates)},2,1,0}}"
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def get_triplet_cgp(self):
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self.get_cgp_wires()
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return "".join([g.get_triplet_cgp(a_index=self.get_circuit_wire_index(g.a), b_index=self.get_circuit_wire_index(g.b)) for g in self.circuit_gates])
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def get_output_cgp(self):
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return "(" + ",".join([str(self.get_circuit_wire_index(o)) for o in self.out.bus[::-1]]) + ")"
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# Generating flat CGP chromosome representation of circuit
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def get_cgp_code(self, file_object):
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file_object.write(self.get_parameters_cgp())
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file_object.write(self.get_triplet_cgp())
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file_object.write(self.get_output_cgp())
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file_object.close()
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""" MULTIPLIER CIRCUITS """
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class multiplier_circuit(arithmetic_circuit):
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def __init__(self):
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super().__init__()
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""" Array multipliers """
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# Used in array multipliers to get previous row's component output wires
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# for further connection to another component's input
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def get_previous_partial_product(self, a_index: int, b_index: int, offset: int = 0):
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# To get the index of previous row's connecting adder and its generated pp
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index = ((b_index-2) * (self.N*2)) + ((self.N-1)+2*(a_index+2)) + offset
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# Get carry wire as input for the last adder in current row
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if a_index == self.N-1:
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index = index-2
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return self.components[index].get_carry_wire()
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# Get sum wire as input for current adder
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else:
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return self.components[index].get_sum_wire()
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""" Dadda multiplier """
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# Used in dadda multipliers to get multiplier's maximum height
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@staticmethod
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def get_maximum_height(initial_value: int):
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stage = 0
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d = 2
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while True:
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stage += 1
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max_height = d
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|
# Calculating maximum height sequence
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# d(j=1) = 2; d(j+1) = floor(1.5*d)
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d = math.floor(1.5*d)
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if d >= initial_value:
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return stage, max_height
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def init_column_heights(self, signed=False):
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columns = [[num] if num <= self.N else [num - (num - self.N)*2] for num in range(1, self.out.N)]
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columns = [self.add_column_wires(column=col, column_index=columns.index(col)) for col in columns]
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return columns
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def add_column_wires(self, column: list, column_index: int):
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|
[column.append([]) for _ in range(column[0])]
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if column_index <= self.N-1:
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[column[column[0]-index].append(self.a.get_wire(index)) for index in range(0, column[0])]
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[column[index+1].append(self.b.get_wire(index)) for index in range(0, column[0])]
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else:
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|
[column[self.a.N-index].append(self.a.get_wire(index)) for index in range(self.a.N-1, self.a.N-column[0]-1, -1)]
|
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[column[index-(self.a.N-1-column[0])].append(self.b.get_wire(index)) for index in range(self.a.N-column[0], self.a.N)]
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|
|
|
# TODO check and refactor
|
|
# Filling unsigned pp matrix with AND gates
|
|
if self.__class__.__name__ == "unsigned_dadda_multiplier" or self.__class__.__name__ == "unsigned_wallace_multiplier":
|
|
column[1:] = [and_gate(a=column[i][0], b=column[i][1], prefix=self.prefix+'_and_'+str(column[i][0].index)+'_'+str(column[i][1].index)) for i in range(1, len(column))]
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|
# Filling signed pp matrix with AND/NAND gates (based on Baugh-Wooley multiplication algorithm)
|
|
else:
|
|
# First half of partial product columns contains only AND gates
|
|
if column_index < self.N-1 or column_index == self.out.N-2:
|
|
column[1:] = [and_gate(a=column[i][0], b=column[i][1], prefix=self.prefix+'_and_'+str(column[i][0].index)+'_'+str(column[i][1].index)) for i in range(1, len(column))]
|
|
# Second half of partial product columns contains NAND/AND gates
|
|
else:
|
|
column[1] = nand_gate(a=column[1][0], b=column[1][1], prefix=self.prefix+'_nand_'+str(column[1][0].index)+'_'+str(column[1][1].index))
|
|
column[-1] = nand_gate(a=column[-1][0], b=column[-1][1], prefix=self.prefix+'_nand_'+str(column[-1][0].index)+'_'+str(column[-1][1].index))
|
|
if len(column[2:-1]) != 0:
|
|
column[2:-1] = [and_gate(a=column[i][0], b=column[i][1], prefix=self.prefix+'_and_'+str(column[i][0].index)+'_'+str(column[i][1].index)) for i in range(2, len(column)-1)]
|
|
|
|
return column
|
|
|
|
def get_column_height(self, column_num: int):
|
|
return self.columns[column_num][0]
|
|
|
|
def update_column_heights(self, curr_column: int, curr_height_change: int, next_column: int = 0, next_height_change: int = 0):
|
|
self.columns[curr_column][0] = self.get_column_height(curr_column)+curr_height_change
|
|
if next_column-1 == curr_column:
|
|
self.columns[next_column][0] = self.get_column_height(next_column)+next_height_change
|
|
|
|
def get_column_wire(self, column: int, bit: int):
|
|
if isinstance(self.columns[column][bit], and_gate) or isinstance(self.columns[column][bit], nand_gate):
|
|
self.add_component(self.columns[column][bit])
|
|
return self.get_previous_component(1).out
|
|
else:
|
|
return self.columns[column][bit]
|
|
|
|
def update_column_wires(self, curr_column: int, adder: arithmetic_circuit, next_column: int = 0):
|
|
if hasattr(adder, "c"):
|
|
self.columns[curr_column].pop(1)
|
|
self.columns[curr_column].pop(1)
|
|
self.columns[curr_column].pop(1)
|
|
self.columns[curr_column].insert(self.get_column_height(curr_column), adder.get_sum_wire())
|
|
else:
|
|
self.columns[curr_column].pop(1)
|
|
self.columns[curr_column].pop(1)
|
|
self.columns[curr_column].insert(self.get_column_height(curr_column), adder.get_sum_wire())
|
|
|
|
if next_column-1 == curr_column:
|
|
self.columns[next_column].insert(1, adder.get_carry_wire())
|