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ariths-gen/Tests/Verilog_circuits/Hierarchical_circuits/Multipliers
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honzastor d86ddcac09 Implemented unsigned dadda multiplier circuit. Updated generation of export formats. TBD: Proper testing, modification of dadda with cla adder, write shell script for Verilog and Blif equivalence check.
2021-03-15 01:08:47 +01:00
..
h_s_arr_mul1_test.v
Generated and tested generated circuits.
2021-03-04 18:59:33 +01:00
h_s_arr_mul1.v
Generated and tested generated circuits.
2021-03-04 18:59:33 +01:00
h_s_arr_mul2_test.v
Generated and tested generated circuits.
2021-03-04 18:59:33 +01:00
h_s_arr_mul2.v
Generated and tested generated circuits.
2021-03-04 18:59:33 +01:00
h_s_arr_mul3_test.v
Generated and tested generated circuits.
2021-03-04 18:59:33 +01:00
h_s_arr_mul3.v
Generated and tested generated circuits.
2021-03-04 18:59:33 +01:00
h_s_arr_mul5_test.v
Generated and tested generated circuits.
2021-03-04 18:59:33 +01:00
h_s_arr_mul5.v
Generated and tested generated circuits.
2021-03-04 18:59:33 +01:00
h_s_arr_mul8_test.v
Generated and tested generated circuits.
2021-03-04 18:59:33 +01:00
h_s_arr_mul8.v
Generated and tested generated circuits.
2021-03-04 18:59:33 +01:00
h_s_arr_mul10_test.v
Generated and tested generated circuits.
2021-03-04 18:59:33 +01:00
h_s_arr_mul10.v
Generated and tested generated circuits.
2021-03-04 18:59:33 +01:00
h_u_arr_mul1_test.v
Generated and tested generated circuits.
2021-03-04 18:59:33 +01:00
h_u_arr_mul1.v
Generated and tested generated circuits.
2021-03-04 18:59:33 +01:00
h_u_arr_mul2_test.v
Generated and tested generated circuits.
2021-03-04 18:59:33 +01:00
h_u_arr_mul2.v
Generated and tested generated circuits.
2021-03-04 18:59:33 +01:00
h_u_arr_mul3_test.v
Generated and tested generated circuits.
2021-03-04 18:59:33 +01:00
h_u_arr_mul3.v
Generated and tested generated circuits.
2021-03-04 18:59:33 +01:00
h_u_arr_mul5_test.v
Generated and tested generated circuits.
2021-03-04 18:59:33 +01:00
h_u_arr_mul5.v
Generated and tested generated circuits.
2021-03-04 18:59:33 +01:00
h_u_arr_mul8_test.v
Generated and tested generated circuits.
2021-03-04 18:59:33 +01:00
h_u_arr_mul8.v
Generated and tested generated circuits.
2021-03-04 18:59:33 +01:00
h_u_arr_mul10_test.v
Generated and tested generated circuits.
2021-03-04 18:59:33 +01:00
h_u_arr_mul10.v
Generated and tested generated circuits.
2021-03-04 18:59:33 +01:00
h_u_dadda_mul2.v
Implemented unsigned dadda multiplier circuit. Updated generation of export formats. TBD: Proper testing, modification of dadda with cla adder, write shell script for Verilog and Blif equivalence check.
2021-03-15 01:08:47 +01:00
h_u_dadda_mul4.v
Implemented unsigned dadda multiplier circuit. Updated generation of export formats. TBD: Proper testing, modification of dadda with cla adder, write shell script for Verilog and Blif equivalence check.
2021-03-15 01:08:47 +01:00
h_u_dadda_mul6.v
Implemented unsigned dadda multiplier circuit. Updated generation of export formats. TBD: Proper testing, modification of dadda with cla adder, write shell script for Verilog and Blif equivalence check.
2021-03-15 01:08:47 +01:00
h_u_dadda_mul8.v
Implemented unsigned dadda multiplier circuit. Updated generation of export formats. TBD: Proper testing, modification of dadda with cla adder, write shell script for Verilog and Blif equivalence check.
2021-03-15 01:08:47 +01:00