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56c86c13ca
* #10 CGP Circuits as inputs (#11) * CGP Circuits as inputs * #10 support of signed output in general circuit * input as output works * output connected to input (c) * automated verilog testing * output rename * Implemented CSA and Wallace tree multiplier composing of CSAs. Also did some code cleanup. * Typos fix and code cleanup. * Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats. * Updated automated testing scripts. * Small bugfix in python code generation (I initially thought this line is useless). * Updated generated circuits folder. Co-authored-by: Vojta Mrazek <mrazek@fit.vutbr.cz>
108 lines
2.3 KiB
Plaintext
108 lines
2.3 KiB
Plaintext
.model s_cla4
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.inputs a[0] a[1] a[2] a[3] b[0] b[1] b[2] b[3]
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.outputs s_cla4_out[0] s_cla4_out[1] s_cla4_out[2] s_cla4_out[3] s_cla4_out[4]
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.names vdd
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1
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.names gnd
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0
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.names a[0] b[0] s_cla4_pg_logic0_or0
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1- 1
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-1 1
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.names a[0] b[0] s_cla4_pg_logic0_and0
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11 1
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.names a[0] b[0] s_cla4_pg_logic0_xor0
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01 1
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10 1
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.names a[1] b[1] s_cla4_pg_logic1_or0
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1- 1
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-1 1
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.names a[1] b[1] s_cla4_pg_logic1_and0
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11 1
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.names a[1] b[1] s_cla4_pg_logic1_xor0
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01 1
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10 1
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.names s_cla4_pg_logic1_xor0 s_cla4_pg_logic0_and0 s_cla4_xor1
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01 1
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10 1
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.names s_cla4_pg_logic0_and0 s_cla4_pg_logic1_or0 s_cla4_and0
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11 1
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.names s_cla4_pg_logic1_and0 s_cla4_and0 s_cla4_or0
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1- 1
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-1 1
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.names a[2] b[2] s_cla4_pg_logic2_or0
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1- 1
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-1 1
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.names a[2] b[2] s_cla4_pg_logic2_and0
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11 1
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.names a[2] b[2] s_cla4_pg_logic2_xor0
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01 1
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10 1
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.names s_cla4_pg_logic2_xor0 s_cla4_or0 s_cla4_xor2
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01 1
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10 1
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.names s_cla4_pg_logic2_or0 s_cla4_pg_logic0_or0 s_cla4_and1
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11 1
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.names s_cla4_pg_logic0_and0 s_cla4_pg_logic2_or0 s_cla4_and2
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11 1
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.names s_cla4_and2 s_cla4_pg_logic1_or0 s_cla4_and3
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11 1
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.names s_cla4_pg_logic1_and0 s_cla4_pg_logic2_or0 s_cla4_and4
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11 1
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.names s_cla4_and3 s_cla4_and4 s_cla4_or1
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1- 1
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-1 1
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.names s_cla4_pg_logic2_and0 s_cla4_or1 s_cla4_or2
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1- 1
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-1 1
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.names a[3] b[3] s_cla4_pg_logic3_or0
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1- 1
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-1 1
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.names a[3] b[3] s_cla4_pg_logic3_and0
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11 1
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.names a[3] b[3] s_cla4_pg_logic3_xor0
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01 1
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10 1
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.names s_cla4_pg_logic3_xor0 s_cla4_or2 s_cla4_xor3
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01 1
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10 1
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.names s_cla4_pg_logic3_or0 s_cla4_pg_logic1_or0 s_cla4_and5
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11 1
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.names s_cla4_pg_logic0_and0 s_cla4_pg_logic2_or0 s_cla4_and6
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11 1
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.names s_cla4_pg_logic3_or0 s_cla4_pg_logic1_or0 s_cla4_and7
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11 1
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.names s_cla4_and6 s_cla4_and7 s_cla4_and8
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11 1
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.names s_cla4_pg_logic1_and0 s_cla4_pg_logic3_or0 s_cla4_and9
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11 1
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.names s_cla4_and9 s_cla4_pg_logic2_or0 s_cla4_and10
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11 1
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.names s_cla4_pg_logic2_and0 s_cla4_pg_logic3_or0 s_cla4_and11
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11 1
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.names s_cla4_and8 s_cla4_and11 s_cla4_or3
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1- 1
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-1 1
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.names s_cla4_and10 s_cla4_or3 s_cla4_or4
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1- 1
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-1 1
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.names s_cla4_pg_logic3_and0 s_cla4_or4 s_cla4_or5
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1- 1
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-1 1
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.names a[3] b[3] s_cla4_xor4
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01 1
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10 1
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.names s_cla4_xor4 s_cla4_or5 s_cla4_xor5
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01 1
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10 1
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.names s_cla4_pg_logic0_xor0 s_cla4_out[0]
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1 1
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.names s_cla4_xor1 s_cla4_out[1]
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1 1
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.names s_cla4_xor2 s_cla4_out[2]
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1 1
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.names s_cla4_xor3 s_cla4_out[3]
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1 1
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.names s_cla4_xor5 s_cla4_out[4]
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1 1
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.end
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