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https://github.com/ehw-fit/ariths-gen.git
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47 lines
1.9 KiB
Verilog
47 lines
1.9 KiB
Verilog
module s_pg_rca4(input [3:0] a, input [3:0] b, output [4:0] s_pg_rca4_out);
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wire s_pg_rca4_pg_fa0_xor0;
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wire s_pg_rca4_pg_fa0_and0;
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wire s_pg_rca4_pg_fa1_xor0;
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wire s_pg_rca4_pg_fa1_and0;
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wire s_pg_rca4_pg_fa1_xor1;
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wire s_pg_rca4_and1;
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wire s_pg_rca4_or1;
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wire s_pg_rca4_pg_fa2_xor0;
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wire s_pg_rca4_pg_fa2_and0;
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wire s_pg_rca4_pg_fa2_xor1;
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wire s_pg_rca4_and2;
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wire s_pg_rca4_or2;
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wire s_pg_rca4_pg_fa3_xor0;
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wire s_pg_rca4_pg_fa3_and0;
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wire s_pg_rca4_pg_fa3_xor1;
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wire s_pg_rca4_and3;
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wire s_pg_rca4_or3;
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wire s_pg_rca4_xor0;
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wire s_pg_rca4_xor1;
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assign s_pg_rca4_pg_fa0_xor0 = a[0] ^ b[0];
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assign s_pg_rca4_pg_fa0_and0 = a[0] & b[0];
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assign s_pg_rca4_pg_fa1_xor0 = a[1] ^ b[1];
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assign s_pg_rca4_pg_fa1_and0 = a[1] & b[1];
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assign s_pg_rca4_pg_fa1_xor1 = s_pg_rca4_pg_fa1_xor0 ^ s_pg_rca4_pg_fa0_and0;
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assign s_pg_rca4_and1 = s_pg_rca4_pg_fa0_and0 & s_pg_rca4_pg_fa1_xor0;
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assign s_pg_rca4_or1 = s_pg_rca4_and1 | s_pg_rca4_pg_fa1_and0;
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assign s_pg_rca4_pg_fa2_xor0 = a[2] ^ b[2];
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assign s_pg_rca4_pg_fa2_and0 = a[2] & b[2];
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assign s_pg_rca4_pg_fa2_xor1 = s_pg_rca4_pg_fa2_xor0 ^ s_pg_rca4_or1;
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assign s_pg_rca4_and2 = s_pg_rca4_or1 & s_pg_rca4_pg_fa2_xor0;
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assign s_pg_rca4_or2 = s_pg_rca4_and2 | s_pg_rca4_pg_fa2_and0;
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assign s_pg_rca4_pg_fa3_xor0 = a[3] ^ b[3];
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assign s_pg_rca4_pg_fa3_and0 = a[3] & b[3];
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assign s_pg_rca4_pg_fa3_xor1 = s_pg_rca4_pg_fa3_xor0 ^ s_pg_rca4_or2;
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assign s_pg_rca4_and3 = s_pg_rca4_or2 & s_pg_rca4_pg_fa3_xor0;
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assign s_pg_rca4_or3 = s_pg_rca4_and3 | s_pg_rca4_pg_fa3_and0;
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assign s_pg_rca4_xor0 = a[3] ^ b[3];
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assign s_pg_rca4_xor1 = s_pg_rca4_xor0 ^ s_pg_rca4_or3;
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assign s_pg_rca4_out[0] = s_pg_rca4_pg_fa0_xor0;
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assign s_pg_rca4_out[1] = s_pg_rca4_pg_fa1_xor1;
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assign s_pg_rca4_out[2] = s_pg_rca4_pg_fa2_xor1;
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assign s_pg_rca4_out[3] = s_pg_rca4_pg_fa3_xor1;
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assign s_pg_rca4_out[4] = s_pg_rca4_xor1;
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endmodule |