mirror of
https://github.com/ehw-fit/ariths-gen.git
synced 2025-04-22 14:51:22 +01:00
654 lines
31 KiB
C
654 lines
31 KiB
C
#include <stdio.h>
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#include <stdint.h>
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uint8_t xor_gate(uint8_t _a, uint8_t _b){
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return ((_a >> 0) & 0x01) ^ ((_b >> 0) & 0x01);
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}
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uint8_t xnor_gate(uint8_t _a, uint8_t _b){
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return ~(((_a >> 0) & 0x01) ^ ((_b >> 0) & 0x01)) & 0x01 << 0;
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}
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uint8_t nor_gate(uint8_t _a, uint8_t _b){
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return ~(((_a >> 0) & 0x01) | ((_b >> 0) & 0x01)) & 0x01 << 0;
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}
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uint8_t or_gate(uint8_t _a, uint8_t _b){
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return ((_a >> 0) & 0x01) | ((_b >> 0) & 0x01);
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}
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uint8_t and_gate(uint8_t _a, uint8_t _b){
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return ((_a >> 0) & 0x01) & ((_b >> 0) & 0x01);
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}
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uint8_t constant_wire_value_0(uint8_t a, uint8_t b){
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uint8_t out = 0;
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uint8_t constant_wire_value_0_a = 0;
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uint8_t constant_wire_value_0_b = 0;
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uint8_t constant_wire_value_0_y0 = 0;
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uint8_t constant_wire_value_0_y1 = 0;
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uint8_t constant_wire_0 = 0;
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constant_wire_value_0_a = ((a >> 0) & 0x01);
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constant_wire_value_0_b = ((b >> 0) & 0x01);
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constant_wire_value_0_y0 = xor_gate(constant_wire_value_0_a, constant_wire_value_0_b);
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constant_wire_value_0_y1 = xnor_gate(constant_wire_value_0_a, constant_wire_value_0_b);
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constant_wire_0 = nor_gate(constant_wire_value_0_y0, constant_wire_value_0_y1);
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out |= (constant_wire_0 & 0x01) << 0;
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return out;
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}
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uint8_t pg_logic(uint8_t a, uint8_t b){
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uint8_t out = 0;
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uint8_t pg_logic_a = 0;
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uint8_t pg_logic_b = 0;
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uint8_t pg_logic_y0 = 0;
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uint8_t pg_logic_y1 = 0;
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uint8_t pg_logic_y2 = 0;
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pg_logic_a = ((a >> 0) & 0x01);
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pg_logic_b = ((b >> 0) & 0x01);
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pg_logic_y0 = or_gate(pg_logic_a, pg_logic_b);
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pg_logic_y1 = and_gate(pg_logic_a, pg_logic_b);
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pg_logic_y2 = xor_gate(pg_logic_a, pg_logic_b);
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out |= (pg_logic_y0 & 0x01) << 0;
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out |= (pg_logic_y1 & 0x01) << 1;
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out |= (pg_logic_y2 & 0x01) << 2;
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return out;
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}
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uint64_t h_u_cla8(uint64_t a, uint64_t b){
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uint64_t out = 0;
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uint8_t a_0 = 0;
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uint8_t a_1 = 0;
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uint8_t a_2 = 0;
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uint8_t a_3 = 0;
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uint8_t a_4 = 0;
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uint8_t a_5 = 0;
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uint8_t a_6 = 0;
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uint8_t a_7 = 0;
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uint8_t b_0 = 0;
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uint8_t b_1 = 0;
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uint8_t b_2 = 0;
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uint8_t b_3 = 0;
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uint8_t b_4 = 0;
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uint8_t b_5 = 0;
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uint8_t b_6 = 0;
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uint8_t b_7 = 0;
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uint8_t constant_wire_0 = 0;
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uint8_t h_u_cla8_pg_logic0_y0 = 0;
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uint8_t h_u_cla8_pg_logic0_y1 = 0;
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uint8_t h_u_cla8_pg_logic0_y2 = 0;
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uint8_t h_u_cla8_xor0_y0 = 0;
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uint8_t h_u_cla8_and0_y0 = 0;
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uint8_t h_u_cla8_or0_y0 = 0;
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uint8_t h_u_cla8_pg_logic1_y0 = 0;
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uint8_t h_u_cla8_pg_logic1_y1 = 0;
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uint8_t h_u_cla8_pg_logic1_y2 = 0;
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uint8_t h_u_cla8_xor1_y0 = 0;
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uint8_t h_u_cla8_and1_y0 = 0;
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uint8_t h_u_cla8_and2_y0 = 0;
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uint8_t h_u_cla8_and3_y0 = 0;
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uint8_t h_u_cla8_and4_y0 = 0;
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uint8_t h_u_cla8_or1_y0 = 0;
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uint8_t h_u_cla8_or2_y0 = 0;
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uint8_t h_u_cla8_pg_logic2_y0 = 0;
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uint8_t h_u_cla8_pg_logic2_y1 = 0;
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uint8_t h_u_cla8_pg_logic2_y2 = 0;
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uint8_t h_u_cla8_xor2_y0 = 0;
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uint8_t h_u_cla8_and5_y0 = 0;
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uint8_t h_u_cla8_and6_y0 = 0;
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uint8_t h_u_cla8_and7_y0 = 0;
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uint8_t h_u_cla8_and8_y0 = 0;
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uint8_t h_u_cla8_and9_y0 = 0;
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uint8_t h_u_cla8_and10_y0 = 0;
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uint8_t h_u_cla8_and11_y0 = 0;
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uint8_t h_u_cla8_and12_y0 = 0;
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uint8_t h_u_cla8_and13_y0 = 0;
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uint8_t h_u_cla8_or3_y0 = 0;
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uint8_t h_u_cla8_or4_y0 = 0;
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uint8_t h_u_cla8_or5_y0 = 0;
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uint8_t h_u_cla8_pg_logic3_y0 = 0;
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uint8_t h_u_cla8_pg_logic3_y1 = 0;
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uint8_t h_u_cla8_pg_logic3_y2 = 0;
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uint8_t h_u_cla8_xor3_y0 = 0;
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uint8_t h_u_cla8_and14_y0 = 0;
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uint8_t h_u_cla8_and15_y0 = 0;
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uint8_t h_u_cla8_and16_y0 = 0;
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uint8_t h_u_cla8_and17_y0 = 0;
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uint8_t h_u_cla8_and18_y0 = 0;
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uint8_t h_u_cla8_and19_y0 = 0;
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uint8_t h_u_cla8_and20_y0 = 0;
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uint8_t h_u_cla8_and21_y0 = 0;
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uint8_t h_u_cla8_and22_y0 = 0;
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uint8_t h_u_cla8_and23_y0 = 0;
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uint8_t h_u_cla8_and24_y0 = 0;
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uint8_t h_u_cla8_and25_y0 = 0;
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uint8_t h_u_cla8_and26_y0 = 0;
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uint8_t h_u_cla8_and27_y0 = 0;
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uint8_t h_u_cla8_and28_y0 = 0;
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uint8_t h_u_cla8_and29_y0 = 0;
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uint8_t h_u_cla8_or6_y0 = 0;
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uint8_t h_u_cla8_or7_y0 = 0;
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uint8_t h_u_cla8_or8_y0 = 0;
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uint8_t h_u_cla8_or9_y0 = 0;
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uint8_t h_u_cla8_pg_logic4_y0 = 0;
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uint8_t h_u_cla8_pg_logic4_y1 = 0;
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uint8_t h_u_cla8_pg_logic4_y2 = 0;
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uint8_t h_u_cla8_xor4_y0 = 0;
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uint8_t h_u_cla8_and30_y0 = 0;
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uint8_t h_u_cla8_and31_y0 = 0;
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uint8_t h_u_cla8_and32_y0 = 0;
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uint8_t h_u_cla8_and33_y0 = 0;
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uint8_t h_u_cla8_and34_y0 = 0;
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uint8_t h_u_cla8_and35_y0 = 0;
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uint8_t h_u_cla8_and36_y0 = 0;
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uint8_t h_u_cla8_and37_y0 = 0;
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uint8_t h_u_cla8_and38_y0 = 0;
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uint8_t h_u_cla8_and39_y0 = 0;
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uint8_t h_u_cla8_and40_y0 = 0;
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uint8_t h_u_cla8_and41_y0 = 0;
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uint8_t h_u_cla8_and42_y0 = 0;
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uint8_t h_u_cla8_and43_y0 = 0;
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uint8_t h_u_cla8_and44_y0 = 0;
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uint8_t h_u_cla8_and45_y0 = 0;
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uint8_t h_u_cla8_and46_y0 = 0;
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uint8_t h_u_cla8_and47_y0 = 0;
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uint8_t h_u_cla8_and48_y0 = 0;
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uint8_t h_u_cla8_and49_y0 = 0;
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uint8_t h_u_cla8_and50_y0 = 0;
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uint8_t h_u_cla8_and51_y0 = 0;
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uint8_t h_u_cla8_and52_y0 = 0;
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uint8_t h_u_cla8_and53_y0 = 0;
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uint8_t h_u_cla8_and54_y0 = 0;
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uint8_t h_u_cla8_or10_y0 = 0;
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uint8_t h_u_cla8_or11_y0 = 0;
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uint8_t h_u_cla8_or12_y0 = 0;
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uint8_t h_u_cla8_or13_y0 = 0;
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uint8_t h_u_cla8_or14_y0 = 0;
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uint8_t h_u_cla8_pg_logic5_y0 = 0;
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uint8_t h_u_cla8_pg_logic5_y1 = 0;
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uint8_t h_u_cla8_pg_logic5_y2 = 0;
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uint8_t h_u_cla8_xor5_y0 = 0;
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uint8_t h_u_cla8_and55_y0 = 0;
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uint8_t h_u_cla8_and56_y0 = 0;
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uint8_t h_u_cla8_and57_y0 = 0;
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uint8_t h_u_cla8_and58_y0 = 0;
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uint8_t h_u_cla8_and59_y0 = 0;
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uint8_t h_u_cla8_and60_y0 = 0;
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uint8_t h_u_cla8_and61_y0 = 0;
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uint8_t h_u_cla8_and62_y0 = 0;
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uint8_t h_u_cla8_and63_y0 = 0;
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uint8_t h_u_cla8_and64_y0 = 0;
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uint8_t h_u_cla8_and65_y0 = 0;
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uint8_t h_u_cla8_and66_y0 = 0;
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uint8_t h_u_cla8_and67_y0 = 0;
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uint8_t h_u_cla8_and68_y0 = 0;
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uint8_t h_u_cla8_and69_y0 = 0;
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uint8_t h_u_cla8_and70_y0 = 0;
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uint8_t h_u_cla8_and71_y0 = 0;
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uint8_t h_u_cla8_and72_y0 = 0;
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uint8_t h_u_cla8_and73_y0 = 0;
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uint8_t h_u_cla8_and74_y0 = 0;
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uint8_t h_u_cla8_and75_y0 = 0;
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uint8_t h_u_cla8_and76_y0 = 0;
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uint8_t h_u_cla8_and77_y0 = 0;
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uint8_t h_u_cla8_and78_y0 = 0;
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uint8_t h_u_cla8_and79_y0 = 0;
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uint8_t h_u_cla8_and80_y0 = 0;
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uint8_t h_u_cla8_and81_y0 = 0;
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uint8_t h_u_cla8_and82_y0 = 0;
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uint8_t h_u_cla8_and83_y0 = 0;
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uint8_t h_u_cla8_and84_y0 = 0;
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uint8_t h_u_cla8_and85_y0 = 0;
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uint8_t h_u_cla8_and86_y0 = 0;
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uint8_t h_u_cla8_and87_y0 = 0;
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uint8_t h_u_cla8_and88_y0 = 0;
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uint8_t h_u_cla8_and89_y0 = 0;
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uint8_t h_u_cla8_and90_y0 = 0;
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uint8_t h_u_cla8_or15_y0 = 0;
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uint8_t h_u_cla8_or16_y0 = 0;
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uint8_t h_u_cla8_or17_y0 = 0;
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uint8_t h_u_cla8_or18_y0 = 0;
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uint8_t h_u_cla8_or19_y0 = 0;
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uint8_t h_u_cla8_or20_y0 = 0;
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uint8_t h_u_cla8_pg_logic6_y0 = 0;
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uint8_t h_u_cla8_pg_logic6_y1 = 0;
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uint8_t h_u_cla8_pg_logic6_y2 = 0;
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uint8_t h_u_cla8_xor6_y0 = 0;
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uint8_t h_u_cla8_and91_y0 = 0;
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uint8_t h_u_cla8_and92_y0 = 0;
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uint8_t h_u_cla8_and93_y0 = 0;
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uint8_t h_u_cla8_and94_y0 = 0;
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uint8_t h_u_cla8_and95_y0 = 0;
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uint8_t h_u_cla8_and96_y0 = 0;
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uint8_t h_u_cla8_and97_y0 = 0;
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uint8_t h_u_cla8_and98_y0 = 0;
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uint8_t h_u_cla8_and99_y0 = 0;
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uint8_t h_u_cla8_and100_y0 = 0;
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uint8_t h_u_cla8_and101_y0 = 0;
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uint8_t h_u_cla8_and102_y0 = 0;
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uint8_t h_u_cla8_and103_y0 = 0;
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uint8_t h_u_cla8_and104_y0 = 0;
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uint8_t h_u_cla8_and105_y0 = 0;
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uint8_t h_u_cla8_and106_y0 = 0;
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uint8_t h_u_cla8_and107_y0 = 0;
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uint8_t h_u_cla8_and108_y0 = 0;
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uint8_t h_u_cla8_and109_y0 = 0;
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uint8_t h_u_cla8_and110_y0 = 0;
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uint8_t h_u_cla8_and111_y0 = 0;
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uint8_t h_u_cla8_and112_y0 = 0;
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uint8_t h_u_cla8_and113_y0 = 0;
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uint8_t h_u_cla8_and114_y0 = 0;
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uint8_t h_u_cla8_and115_y0 = 0;
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uint8_t h_u_cla8_and116_y0 = 0;
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uint8_t h_u_cla8_and117_y0 = 0;
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uint8_t h_u_cla8_and118_y0 = 0;
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uint8_t h_u_cla8_and119_y0 = 0;
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uint8_t h_u_cla8_and120_y0 = 0;
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uint8_t h_u_cla8_and121_y0 = 0;
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uint8_t h_u_cla8_and122_y0 = 0;
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uint8_t h_u_cla8_and123_y0 = 0;
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uint8_t h_u_cla8_and124_y0 = 0;
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uint8_t h_u_cla8_and125_y0 = 0;
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uint8_t h_u_cla8_and126_y0 = 0;
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uint8_t h_u_cla8_and127_y0 = 0;
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uint8_t h_u_cla8_and128_y0 = 0;
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uint8_t h_u_cla8_and129_y0 = 0;
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uint8_t h_u_cla8_and130_y0 = 0;
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uint8_t h_u_cla8_and131_y0 = 0;
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uint8_t h_u_cla8_and132_y0 = 0;
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uint8_t h_u_cla8_and133_y0 = 0;
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uint8_t h_u_cla8_and134_y0 = 0;
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uint8_t h_u_cla8_and135_y0 = 0;
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uint8_t h_u_cla8_and136_y0 = 0;
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uint8_t h_u_cla8_and137_y0 = 0;
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uint8_t h_u_cla8_and138_y0 = 0;
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uint8_t h_u_cla8_and139_y0 = 0;
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uint8_t h_u_cla8_or21_y0 = 0;
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uint8_t h_u_cla8_or22_y0 = 0;
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uint8_t h_u_cla8_or23_y0 = 0;
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uint8_t h_u_cla8_or24_y0 = 0;
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uint8_t h_u_cla8_or25_y0 = 0;
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uint8_t h_u_cla8_or26_y0 = 0;
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uint8_t h_u_cla8_or27_y0 = 0;
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uint8_t h_u_cla8_pg_logic7_y0 = 0;
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uint8_t h_u_cla8_pg_logic7_y1 = 0;
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uint8_t h_u_cla8_pg_logic7_y2 = 0;
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uint8_t h_u_cla8_xor7_y0 = 0;
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uint8_t h_u_cla8_and140_y0 = 0;
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uint8_t h_u_cla8_and141_y0 = 0;
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uint8_t h_u_cla8_and142_y0 = 0;
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uint8_t h_u_cla8_and143_y0 = 0;
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uint8_t h_u_cla8_and144_y0 = 0;
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uint8_t h_u_cla8_and145_y0 = 0;
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uint8_t h_u_cla8_and146_y0 = 0;
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uint8_t h_u_cla8_and147_y0 = 0;
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uint8_t h_u_cla8_and148_y0 = 0;
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uint8_t h_u_cla8_and149_y0 = 0;
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uint8_t h_u_cla8_and150_y0 = 0;
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uint8_t h_u_cla8_and151_y0 = 0;
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uint8_t h_u_cla8_and152_y0 = 0;
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uint8_t h_u_cla8_and153_y0 = 0;
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uint8_t h_u_cla8_and154_y0 = 0;
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uint8_t h_u_cla8_and155_y0 = 0;
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uint8_t h_u_cla8_and156_y0 = 0;
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uint8_t h_u_cla8_and157_y0 = 0;
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uint8_t h_u_cla8_and158_y0 = 0;
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uint8_t h_u_cla8_and159_y0 = 0;
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uint8_t h_u_cla8_and160_y0 = 0;
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uint8_t h_u_cla8_and161_y0 = 0;
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uint8_t h_u_cla8_and162_y0 = 0;
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uint8_t h_u_cla8_and163_y0 = 0;
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uint8_t h_u_cla8_and164_y0 = 0;
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uint8_t h_u_cla8_and165_y0 = 0;
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uint8_t h_u_cla8_and166_y0 = 0;
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uint8_t h_u_cla8_and167_y0 = 0;
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uint8_t h_u_cla8_and168_y0 = 0;
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uint8_t h_u_cla8_and169_y0 = 0;
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uint8_t h_u_cla8_and170_y0 = 0;
|
|
uint8_t h_u_cla8_and171_y0 = 0;
|
|
uint8_t h_u_cla8_and172_y0 = 0;
|
|
uint8_t h_u_cla8_and173_y0 = 0;
|
|
uint8_t h_u_cla8_and174_y0 = 0;
|
|
uint8_t h_u_cla8_and175_y0 = 0;
|
|
uint8_t h_u_cla8_and176_y0 = 0;
|
|
uint8_t h_u_cla8_and177_y0 = 0;
|
|
uint8_t h_u_cla8_and178_y0 = 0;
|
|
uint8_t h_u_cla8_and179_y0 = 0;
|
|
uint8_t h_u_cla8_and180_y0 = 0;
|
|
uint8_t h_u_cla8_and181_y0 = 0;
|
|
uint8_t h_u_cla8_and182_y0 = 0;
|
|
uint8_t h_u_cla8_and183_y0 = 0;
|
|
uint8_t h_u_cla8_and184_y0 = 0;
|
|
uint8_t h_u_cla8_and185_y0 = 0;
|
|
uint8_t h_u_cla8_and186_y0 = 0;
|
|
uint8_t h_u_cla8_and187_y0 = 0;
|
|
uint8_t h_u_cla8_and188_y0 = 0;
|
|
uint8_t h_u_cla8_and189_y0 = 0;
|
|
uint8_t h_u_cla8_and190_y0 = 0;
|
|
uint8_t h_u_cla8_and191_y0 = 0;
|
|
uint8_t h_u_cla8_and192_y0 = 0;
|
|
uint8_t h_u_cla8_and193_y0 = 0;
|
|
uint8_t h_u_cla8_and194_y0 = 0;
|
|
uint8_t h_u_cla8_and195_y0 = 0;
|
|
uint8_t h_u_cla8_and196_y0 = 0;
|
|
uint8_t h_u_cla8_and197_y0 = 0;
|
|
uint8_t h_u_cla8_and198_y0 = 0;
|
|
uint8_t h_u_cla8_and199_y0 = 0;
|
|
uint8_t h_u_cla8_and200_y0 = 0;
|
|
uint8_t h_u_cla8_and201_y0 = 0;
|
|
uint8_t h_u_cla8_and202_y0 = 0;
|
|
uint8_t h_u_cla8_and203_y0 = 0;
|
|
uint8_t h_u_cla8_or28_y0 = 0;
|
|
uint8_t h_u_cla8_or29_y0 = 0;
|
|
uint8_t h_u_cla8_or30_y0 = 0;
|
|
uint8_t h_u_cla8_or31_y0 = 0;
|
|
uint8_t h_u_cla8_or32_y0 = 0;
|
|
uint8_t h_u_cla8_or33_y0 = 0;
|
|
uint8_t h_u_cla8_or34_y0 = 0;
|
|
uint8_t h_u_cla8_or35_y0 = 0;
|
|
|
|
a_0 = ((a >> 0) & 0x01);
|
|
a_1 = ((a >> 1) & 0x01);
|
|
a_2 = ((a >> 2) & 0x01);
|
|
a_3 = ((a >> 3) & 0x01);
|
|
a_4 = ((a >> 4) & 0x01);
|
|
a_5 = ((a >> 5) & 0x01);
|
|
a_6 = ((a >> 6) & 0x01);
|
|
a_7 = ((a >> 7) & 0x01);
|
|
b_0 = ((b >> 0) & 0x01);
|
|
b_1 = ((b >> 1) & 0x01);
|
|
b_2 = ((b >> 2) & 0x01);
|
|
b_3 = ((b >> 3) & 0x01);
|
|
b_4 = ((b >> 4) & 0x01);
|
|
b_5 = ((b >> 5) & 0x01);
|
|
b_6 = ((b >> 6) & 0x01);
|
|
b_7 = ((b >> 7) & 0x01);
|
|
constant_wire_0 = (constant_wire_value_0(a_0, b_0) >> 0) & 0x01;
|
|
h_u_cla8_pg_logic0_y0 = (pg_logic(a_0, b_0) >> 0) & 0x01;
|
|
h_u_cla8_pg_logic0_y1 = (pg_logic(a_0, b_0) >> 1) & 0x01;
|
|
h_u_cla8_pg_logic0_y2 = (pg_logic(a_0, b_0) >> 2) & 0x01;
|
|
h_u_cla8_xor0_y0 = xor_gate(h_u_cla8_pg_logic0_y2, constant_wire_0);
|
|
h_u_cla8_and0_y0 = and_gate(h_u_cla8_pg_logic0_y0, constant_wire_0);
|
|
h_u_cla8_or0_y0 = or_gate(h_u_cla8_pg_logic0_y1, h_u_cla8_and0_y0);
|
|
h_u_cla8_pg_logic1_y0 = (pg_logic(a_1, b_1) >> 0) & 0x01;
|
|
h_u_cla8_pg_logic1_y1 = (pg_logic(a_1, b_1) >> 1) & 0x01;
|
|
h_u_cla8_pg_logic1_y2 = (pg_logic(a_1, b_1) >> 2) & 0x01;
|
|
h_u_cla8_xor1_y0 = xor_gate(h_u_cla8_pg_logic1_y2, h_u_cla8_or0_y0);
|
|
h_u_cla8_and1_y0 = and_gate(h_u_cla8_pg_logic0_y0, constant_wire_0);
|
|
h_u_cla8_and2_y0 = and_gate(h_u_cla8_pg_logic1_y0, constant_wire_0);
|
|
h_u_cla8_and3_y0 = and_gate(h_u_cla8_and2_y0, h_u_cla8_and1_y0);
|
|
h_u_cla8_and4_y0 = and_gate(h_u_cla8_pg_logic1_y0, h_u_cla8_pg_logic0_y1);
|
|
h_u_cla8_or1_y0 = or_gate(h_u_cla8_and4_y0, h_u_cla8_and3_y0);
|
|
h_u_cla8_or2_y0 = or_gate(h_u_cla8_pg_logic1_y1, h_u_cla8_or1_y0);
|
|
h_u_cla8_pg_logic2_y0 = (pg_logic(a_2, b_2) >> 0) & 0x01;
|
|
h_u_cla8_pg_logic2_y1 = (pg_logic(a_2, b_2) >> 1) & 0x01;
|
|
h_u_cla8_pg_logic2_y2 = (pg_logic(a_2, b_2) >> 2) & 0x01;
|
|
h_u_cla8_xor2_y0 = xor_gate(h_u_cla8_pg_logic2_y2, h_u_cla8_or2_y0);
|
|
h_u_cla8_and5_y0 = and_gate(h_u_cla8_pg_logic0_y0, constant_wire_0);
|
|
h_u_cla8_and6_y0 = and_gate(h_u_cla8_pg_logic1_y0, constant_wire_0);
|
|
h_u_cla8_and7_y0 = and_gate(h_u_cla8_and6_y0, h_u_cla8_and5_y0);
|
|
h_u_cla8_and8_y0 = and_gate(h_u_cla8_pg_logic2_y0, constant_wire_0);
|
|
h_u_cla8_and9_y0 = and_gate(h_u_cla8_and8_y0, h_u_cla8_and7_y0);
|
|
h_u_cla8_and10_y0 = and_gate(h_u_cla8_pg_logic1_y0, h_u_cla8_pg_logic0_y1);
|
|
h_u_cla8_and11_y0 = and_gate(h_u_cla8_pg_logic2_y0, h_u_cla8_pg_logic0_y1);
|
|
h_u_cla8_and12_y0 = and_gate(h_u_cla8_and11_y0, h_u_cla8_and10_y0);
|
|
h_u_cla8_and13_y0 = and_gate(h_u_cla8_pg_logic2_y0, h_u_cla8_pg_logic1_y1);
|
|
h_u_cla8_or3_y0 = or_gate(h_u_cla8_and13_y0, h_u_cla8_and9_y0);
|
|
h_u_cla8_or4_y0 = or_gate(h_u_cla8_or3_y0, h_u_cla8_and12_y0);
|
|
h_u_cla8_or5_y0 = or_gate(h_u_cla8_pg_logic2_y1, h_u_cla8_or4_y0);
|
|
h_u_cla8_pg_logic3_y0 = (pg_logic(a_3, b_3) >> 0) & 0x01;
|
|
h_u_cla8_pg_logic3_y1 = (pg_logic(a_3, b_3) >> 1) & 0x01;
|
|
h_u_cla8_pg_logic3_y2 = (pg_logic(a_3, b_3) >> 2) & 0x01;
|
|
h_u_cla8_xor3_y0 = xor_gate(h_u_cla8_pg_logic3_y2, h_u_cla8_or5_y0);
|
|
h_u_cla8_and14_y0 = and_gate(h_u_cla8_pg_logic0_y0, constant_wire_0);
|
|
h_u_cla8_and15_y0 = and_gate(h_u_cla8_pg_logic1_y0, constant_wire_0);
|
|
h_u_cla8_and16_y0 = and_gate(h_u_cla8_and15_y0, h_u_cla8_and14_y0);
|
|
h_u_cla8_and17_y0 = and_gate(h_u_cla8_pg_logic2_y0, constant_wire_0);
|
|
h_u_cla8_and18_y0 = and_gate(h_u_cla8_and17_y0, h_u_cla8_and16_y0);
|
|
h_u_cla8_and19_y0 = and_gate(h_u_cla8_pg_logic3_y0, constant_wire_0);
|
|
h_u_cla8_and20_y0 = and_gate(h_u_cla8_and19_y0, h_u_cla8_and18_y0);
|
|
h_u_cla8_and21_y0 = and_gate(h_u_cla8_pg_logic1_y0, h_u_cla8_pg_logic0_y1);
|
|
h_u_cla8_and22_y0 = and_gate(h_u_cla8_pg_logic2_y0, h_u_cla8_pg_logic0_y1);
|
|
h_u_cla8_and23_y0 = and_gate(h_u_cla8_and22_y0, h_u_cla8_and21_y0);
|
|
h_u_cla8_and24_y0 = and_gate(h_u_cla8_pg_logic3_y0, h_u_cla8_pg_logic0_y1);
|
|
h_u_cla8_and25_y0 = and_gate(h_u_cla8_and24_y0, h_u_cla8_and23_y0);
|
|
h_u_cla8_and26_y0 = and_gate(h_u_cla8_pg_logic2_y0, h_u_cla8_pg_logic1_y1);
|
|
h_u_cla8_and27_y0 = and_gate(h_u_cla8_pg_logic3_y0, h_u_cla8_pg_logic1_y1);
|
|
h_u_cla8_and28_y0 = and_gate(h_u_cla8_and27_y0, h_u_cla8_and26_y0);
|
|
h_u_cla8_and29_y0 = and_gate(h_u_cla8_pg_logic3_y0, h_u_cla8_pg_logic2_y1);
|
|
h_u_cla8_or6_y0 = or_gate(h_u_cla8_and29_y0, h_u_cla8_and20_y0);
|
|
h_u_cla8_or7_y0 = or_gate(h_u_cla8_or6_y0, h_u_cla8_and25_y0);
|
|
h_u_cla8_or8_y0 = or_gate(h_u_cla8_or7_y0, h_u_cla8_and28_y0);
|
|
h_u_cla8_or9_y0 = or_gate(h_u_cla8_pg_logic3_y1, h_u_cla8_or8_y0);
|
|
h_u_cla8_pg_logic4_y0 = (pg_logic(a_4, b_4) >> 0) & 0x01;
|
|
h_u_cla8_pg_logic4_y1 = (pg_logic(a_4, b_4) >> 1) & 0x01;
|
|
h_u_cla8_pg_logic4_y2 = (pg_logic(a_4, b_4) >> 2) & 0x01;
|
|
h_u_cla8_xor4_y0 = xor_gate(h_u_cla8_pg_logic4_y2, h_u_cla8_or9_y0);
|
|
h_u_cla8_and30_y0 = and_gate(h_u_cla8_pg_logic0_y0, constant_wire_0);
|
|
h_u_cla8_and31_y0 = and_gate(h_u_cla8_pg_logic1_y0, constant_wire_0);
|
|
h_u_cla8_and32_y0 = and_gate(h_u_cla8_and31_y0, h_u_cla8_and30_y0);
|
|
h_u_cla8_and33_y0 = and_gate(h_u_cla8_pg_logic2_y0, constant_wire_0);
|
|
h_u_cla8_and34_y0 = and_gate(h_u_cla8_and33_y0, h_u_cla8_and32_y0);
|
|
h_u_cla8_and35_y0 = and_gate(h_u_cla8_pg_logic3_y0, constant_wire_0);
|
|
h_u_cla8_and36_y0 = and_gate(h_u_cla8_and35_y0, h_u_cla8_and34_y0);
|
|
h_u_cla8_and37_y0 = and_gate(h_u_cla8_pg_logic4_y0, constant_wire_0);
|
|
h_u_cla8_and38_y0 = and_gate(h_u_cla8_and37_y0, h_u_cla8_and36_y0);
|
|
h_u_cla8_and39_y0 = and_gate(h_u_cla8_pg_logic1_y0, h_u_cla8_pg_logic0_y1);
|
|
h_u_cla8_and40_y0 = and_gate(h_u_cla8_pg_logic2_y0, h_u_cla8_pg_logic0_y1);
|
|
h_u_cla8_and41_y0 = and_gate(h_u_cla8_and40_y0, h_u_cla8_and39_y0);
|
|
h_u_cla8_and42_y0 = and_gate(h_u_cla8_pg_logic3_y0, h_u_cla8_pg_logic0_y1);
|
|
h_u_cla8_and43_y0 = and_gate(h_u_cla8_and42_y0, h_u_cla8_and41_y0);
|
|
h_u_cla8_and44_y0 = and_gate(h_u_cla8_pg_logic4_y0, h_u_cla8_pg_logic0_y1);
|
|
h_u_cla8_and45_y0 = and_gate(h_u_cla8_and44_y0, h_u_cla8_and43_y0);
|
|
h_u_cla8_and46_y0 = and_gate(h_u_cla8_pg_logic2_y0, h_u_cla8_pg_logic1_y1);
|
|
h_u_cla8_and47_y0 = and_gate(h_u_cla8_pg_logic3_y0, h_u_cla8_pg_logic1_y1);
|
|
h_u_cla8_and48_y0 = and_gate(h_u_cla8_and47_y0, h_u_cla8_and46_y0);
|
|
h_u_cla8_and49_y0 = and_gate(h_u_cla8_pg_logic4_y0, h_u_cla8_pg_logic1_y1);
|
|
h_u_cla8_and50_y0 = and_gate(h_u_cla8_and49_y0, h_u_cla8_and48_y0);
|
|
h_u_cla8_and51_y0 = and_gate(h_u_cla8_pg_logic3_y0, h_u_cla8_pg_logic2_y1);
|
|
h_u_cla8_and52_y0 = and_gate(h_u_cla8_pg_logic4_y0, h_u_cla8_pg_logic2_y1);
|
|
h_u_cla8_and53_y0 = and_gate(h_u_cla8_and52_y0, h_u_cla8_and51_y0);
|
|
h_u_cla8_and54_y0 = and_gate(h_u_cla8_pg_logic4_y0, h_u_cla8_pg_logic3_y1);
|
|
h_u_cla8_or10_y0 = or_gate(h_u_cla8_and54_y0, h_u_cla8_and38_y0);
|
|
h_u_cla8_or11_y0 = or_gate(h_u_cla8_or10_y0, h_u_cla8_and45_y0);
|
|
h_u_cla8_or12_y0 = or_gate(h_u_cla8_or11_y0, h_u_cla8_and50_y0);
|
|
h_u_cla8_or13_y0 = or_gate(h_u_cla8_or12_y0, h_u_cla8_and53_y0);
|
|
h_u_cla8_or14_y0 = or_gate(h_u_cla8_pg_logic4_y1, h_u_cla8_or13_y0);
|
|
h_u_cla8_pg_logic5_y0 = (pg_logic(a_5, b_5) >> 0) & 0x01;
|
|
h_u_cla8_pg_logic5_y1 = (pg_logic(a_5, b_5) >> 1) & 0x01;
|
|
h_u_cla8_pg_logic5_y2 = (pg_logic(a_5, b_5) >> 2) & 0x01;
|
|
h_u_cla8_xor5_y0 = xor_gate(h_u_cla8_pg_logic5_y2, h_u_cla8_or14_y0);
|
|
h_u_cla8_and55_y0 = and_gate(h_u_cla8_pg_logic0_y0, constant_wire_0);
|
|
h_u_cla8_and56_y0 = and_gate(h_u_cla8_pg_logic1_y0, constant_wire_0);
|
|
h_u_cla8_and57_y0 = and_gate(h_u_cla8_and56_y0, h_u_cla8_and55_y0);
|
|
h_u_cla8_and58_y0 = and_gate(h_u_cla8_pg_logic2_y0, constant_wire_0);
|
|
h_u_cla8_and59_y0 = and_gate(h_u_cla8_and58_y0, h_u_cla8_and57_y0);
|
|
h_u_cla8_and60_y0 = and_gate(h_u_cla8_pg_logic3_y0, constant_wire_0);
|
|
h_u_cla8_and61_y0 = and_gate(h_u_cla8_and60_y0, h_u_cla8_and59_y0);
|
|
h_u_cla8_and62_y0 = and_gate(h_u_cla8_pg_logic4_y0, constant_wire_0);
|
|
h_u_cla8_and63_y0 = and_gate(h_u_cla8_and62_y0, h_u_cla8_and61_y0);
|
|
h_u_cla8_and64_y0 = and_gate(h_u_cla8_pg_logic5_y0, constant_wire_0);
|
|
h_u_cla8_and65_y0 = and_gate(h_u_cla8_and64_y0, h_u_cla8_and63_y0);
|
|
h_u_cla8_and66_y0 = and_gate(h_u_cla8_pg_logic1_y0, h_u_cla8_pg_logic0_y1);
|
|
h_u_cla8_and67_y0 = and_gate(h_u_cla8_pg_logic2_y0, h_u_cla8_pg_logic0_y1);
|
|
h_u_cla8_and68_y0 = and_gate(h_u_cla8_and67_y0, h_u_cla8_and66_y0);
|
|
h_u_cla8_and69_y0 = and_gate(h_u_cla8_pg_logic3_y0, h_u_cla8_pg_logic0_y1);
|
|
h_u_cla8_and70_y0 = and_gate(h_u_cla8_and69_y0, h_u_cla8_and68_y0);
|
|
h_u_cla8_and71_y0 = and_gate(h_u_cla8_pg_logic4_y0, h_u_cla8_pg_logic0_y1);
|
|
h_u_cla8_and72_y0 = and_gate(h_u_cla8_and71_y0, h_u_cla8_and70_y0);
|
|
h_u_cla8_and73_y0 = and_gate(h_u_cla8_pg_logic5_y0, h_u_cla8_pg_logic0_y1);
|
|
h_u_cla8_and74_y0 = and_gate(h_u_cla8_and73_y0, h_u_cla8_and72_y0);
|
|
h_u_cla8_and75_y0 = and_gate(h_u_cla8_pg_logic2_y0, h_u_cla8_pg_logic1_y1);
|
|
h_u_cla8_and76_y0 = and_gate(h_u_cla8_pg_logic3_y0, h_u_cla8_pg_logic1_y1);
|
|
h_u_cla8_and77_y0 = and_gate(h_u_cla8_and76_y0, h_u_cla8_and75_y0);
|
|
h_u_cla8_and78_y0 = and_gate(h_u_cla8_pg_logic4_y0, h_u_cla8_pg_logic1_y1);
|
|
h_u_cla8_and79_y0 = and_gate(h_u_cla8_and78_y0, h_u_cla8_and77_y0);
|
|
h_u_cla8_and80_y0 = and_gate(h_u_cla8_pg_logic5_y0, h_u_cla8_pg_logic1_y1);
|
|
h_u_cla8_and81_y0 = and_gate(h_u_cla8_and80_y0, h_u_cla8_and79_y0);
|
|
h_u_cla8_and82_y0 = and_gate(h_u_cla8_pg_logic3_y0, h_u_cla8_pg_logic2_y1);
|
|
h_u_cla8_and83_y0 = and_gate(h_u_cla8_pg_logic4_y0, h_u_cla8_pg_logic2_y1);
|
|
h_u_cla8_and84_y0 = and_gate(h_u_cla8_and83_y0, h_u_cla8_and82_y0);
|
|
h_u_cla8_and85_y0 = and_gate(h_u_cla8_pg_logic5_y0, h_u_cla8_pg_logic2_y1);
|
|
h_u_cla8_and86_y0 = and_gate(h_u_cla8_and85_y0, h_u_cla8_and84_y0);
|
|
h_u_cla8_and87_y0 = and_gate(h_u_cla8_pg_logic4_y0, h_u_cla8_pg_logic3_y1);
|
|
h_u_cla8_and88_y0 = and_gate(h_u_cla8_pg_logic5_y0, h_u_cla8_pg_logic3_y1);
|
|
h_u_cla8_and89_y0 = and_gate(h_u_cla8_and88_y0, h_u_cla8_and87_y0);
|
|
h_u_cla8_and90_y0 = and_gate(h_u_cla8_pg_logic5_y0, h_u_cla8_pg_logic4_y1);
|
|
h_u_cla8_or15_y0 = or_gate(h_u_cla8_and90_y0, h_u_cla8_and65_y0);
|
|
h_u_cla8_or16_y0 = or_gate(h_u_cla8_or15_y0, h_u_cla8_and74_y0);
|
|
h_u_cla8_or17_y0 = or_gate(h_u_cla8_or16_y0, h_u_cla8_and81_y0);
|
|
h_u_cla8_or18_y0 = or_gate(h_u_cla8_or17_y0, h_u_cla8_and86_y0);
|
|
h_u_cla8_or19_y0 = or_gate(h_u_cla8_or18_y0, h_u_cla8_and89_y0);
|
|
h_u_cla8_or20_y0 = or_gate(h_u_cla8_pg_logic5_y1, h_u_cla8_or19_y0);
|
|
h_u_cla8_pg_logic6_y0 = (pg_logic(a_6, b_6) >> 0) & 0x01;
|
|
h_u_cla8_pg_logic6_y1 = (pg_logic(a_6, b_6) >> 1) & 0x01;
|
|
h_u_cla8_pg_logic6_y2 = (pg_logic(a_6, b_6) >> 2) & 0x01;
|
|
h_u_cla8_xor6_y0 = xor_gate(h_u_cla8_pg_logic6_y2, h_u_cla8_or20_y0);
|
|
h_u_cla8_and91_y0 = and_gate(h_u_cla8_pg_logic0_y0, constant_wire_0);
|
|
h_u_cla8_and92_y0 = and_gate(h_u_cla8_pg_logic1_y0, constant_wire_0);
|
|
h_u_cla8_and93_y0 = and_gate(h_u_cla8_and92_y0, h_u_cla8_and91_y0);
|
|
h_u_cla8_and94_y0 = and_gate(h_u_cla8_pg_logic2_y0, constant_wire_0);
|
|
h_u_cla8_and95_y0 = and_gate(h_u_cla8_and94_y0, h_u_cla8_and93_y0);
|
|
h_u_cla8_and96_y0 = and_gate(h_u_cla8_pg_logic3_y0, constant_wire_0);
|
|
h_u_cla8_and97_y0 = and_gate(h_u_cla8_and96_y0, h_u_cla8_and95_y0);
|
|
h_u_cla8_and98_y0 = and_gate(h_u_cla8_pg_logic4_y0, constant_wire_0);
|
|
h_u_cla8_and99_y0 = and_gate(h_u_cla8_and98_y0, h_u_cla8_and97_y0);
|
|
h_u_cla8_and100_y0 = and_gate(h_u_cla8_pg_logic5_y0, constant_wire_0);
|
|
h_u_cla8_and101_y0 = and_gate(h_u_cla8_and100_y0, h_u_cla8_and99_y0);
|
|
h_u_cla8_and102_y0 = and_gate(h_u_cla8_pg_logic6_y0, constant_wire_0);
|
|
h_u_cla8_and103_y0 = and_gate(h_u_cla8_and102_y0, h_u_cla8_and101_y0);
|
|
h_u_cla8_and104_y0 = and_gate(h_u_cla8_pg_logic1_y0, h_u_cla8_pg_logic0_y1);
|
|
h_u_cla8_and105_y0 = and_gate(h_u_cla8_pg_logic2_y0, h_u_cla8_pg_logic0_y1);
|
|
h_u_cla8_and106_y0 = and_gate(h_u_cla8_and105_y0, h_u_cla8_and104_y0);
|
|
h_u_cla8_and107_y0 = and_gate(h_u_cla8_pg_logic3_y0, h_u_cla8_pg_logic0_y1);
|
|
h_u_cla8_and108_y0 = and_gate(h_u_cla8_and107_y0, h_u_cla8_and106_y0);
|
|
h_u_cla8_and109_y0 = and_gate(h_u_cla8_pg_logic4_y0, h_u_cla8_pg_logic0_y1);
|
|
h_u_cla8_and110_y0 = and_gate(h_u_cla8_and109_y0, h_u_cla8_and108_y0);
|
|
h_u_cla8_and111_y0 = and_gate(h_u_cla8_pg_logic5_y0, h_u_cla8_pg_logic0_y1);
|
|
h_u_cla8_and112_y0 = and_gate(h_u_cla8_and111_y0, h_u_cla8_and110_y0);
|
|
h_u_cla8_and113_y0 = and_gate(h_u_cla8_pg_logic6_y0, h_u_cla8_pg_logic0_y1);
|
|
h_u_cla8_and114_y0 = and_gate(h_u_cla8_and113_y0, h_u_cla8_and112_y0);
|
|
h_u_cla8_and115_y0 = and_gate(h_u_cla8_pg_logic2_y0, h_u_cla8_pg_logic1_y1);
|
|
h_u_cla8_and116_y0 = and_gate(h_u_cla8_pg_logic3_y0, h_u_cla8_pg_logic1_y1);
|
|
h_u_cla8_and117_y0 = and_gate(h_u_cla8_and116_y0, h_u_cla8_and115_y0);
|
|
h_u_cla8_and118_y0 = and_gate(h_u_cla8_pg_logic4_y0, h_u_cla8_pg_logic1_y1);
|
|
h_u_cla8_and119_y0 = and_gate(h_u_cla8_and118_y0, h_u_cla8_and117_y0);
|
|
h_u_cla8_and120_y0 = and_gate(h_u_cla8_pg_logic5_y0, h_u_cla8_pg_logic1_y1);
|
|
h_u_cla8_and121_y0 = and_gate(h_u_cla8_and120_y0, h_u_cla8_and119_y0);
|
|
h_u_cla8_and122_y0 = and_gate(h_u_cla8_pg_logic6_y0, h_u_cla8_pg_logic1_y1);
|
|
h_u_cla8_and123_y0 = and_gate(h_u_cla8_and122_y0, h_u_cla8_and121_y0);
|
|
h_u_cla8_and124_y0 = and_gate(h_u_cla8_pg_logic3_y0, h_u_cla8_pg_logic2_y1);
|
|
h_u_cla8_and125_y0 = and_gate(h_u_cla8_pg_logic4_y0, h_u_cla8_pg_logic2_y1);
|
|
h_u_cla8_and126_y0 = and_gate(h_u_cla8_and125_y0, h_u_cla8_and124_y0);
|
|
h_u_cla8_and127_y0 = and_gate(h_u_cla8_pg_logic5_y0, h_u_cla8_pg_logic2_y1);
|
|
h_u_cla8_and128_y0 = and_gate(h_u_cla8_and127_y0, h_u_cla8_and126_y0);
|
|
h_u_cla8_and129_y0 = and_gate(h_u_cla8_pg_logic6_y0, h_u_cla8_pg_logic2_y1);
|
|
h_u_cla8_and130_y0 = and_gate(h_u_cla8_and129_y0, h_u_cla8_and128_y0);
|
|
h_u_cla8_and131_y0 = and_gate(h_u_cla8_pg_logic4_y0, h_u_cla8_pg_logic3_y1);
|
|
h_u_cla8_and132_y0 = and_gate(h_u_cla8_pg_logic5_y0, h_u_cla8_pg_logic3_y1);
|
|
h_u_cla8_and133_y0 = and_gate(h_u_cla8_and132_y0, h_u_cla8_and131_y0);
|
|
h_u_cla8_and134_y0 = and_gate(h_u_cla8_pg_logic6_y0, h_u_cla8_pg_logic3_y1);
|
|
h_u_cla8_and135_y0 = and_gate(h_u_cla8_and134_y0, h_u_cla8_and133_y0);
|
|
h_u_cla8_and136_y0 = and_gate(h_u_cla8_pg_logic5_y0, h_u_cla8_pg_logic4_y1);
|
|
h_u_cla8_and137_y0 = and_gate(h_u_cla8_pg_logic6_y0, h_u_cla8_pg_logic4_y1);
|
|
h_u_cla8_and138_y0 = and_gate(h_u_cla8_and137_y0, h_u_cla8_and136_y0);
|
|
h_u_cla8_and139_y0 = and_gate(h_u_cla8_pg_logic6_y0, h_u_cla8_pg_logic5_y1);
|
|
h_u_cla8_or21_y0 = or_gate(h_u_cla8_and139_y0, h_u_cla8_and103_y0);
|
|
h_u_cla8_or22_y0 = or_gate(h_u_cla8_or21_y0, h_u_cla8_and114_y0);
|
|
h_u_cla8_or23_y0 = or_gate(h_u_cla8_or22_y0, h_u_cla8_and123_y0);
|
|
h_u_cla8_or24_y0 = or_gate(h_u_cla8_or23_y0, h_u_cla8_and130_y0);
|
|
h_u_cla8_or25_y0 = or_gate(h_u_cla8_or24_y0, h_u_cla8_and135_y0);
|
|
h_u_cla8_or26_y0 = or_gate(h_u_cla8_or25_y0, h_u_cla8_and138_y0);
|
|
h_u_cla8_or27_y0 = or_gate(h_u_cla8_pg_logic6_y1, h_u_cla8_or26_y0);
|
|
h_u_cla8_pg_logic7_y0 = (pg_logic(a_7, b_7) >> 0) & 0x01;
|
|
h_u_cla8_pg_logic7_y1 = (pg_logic(a_7, b_7) >> 1) & 0x01;
|
|
h_u_cla8_pg_logic7_y2 = (pg_logic(a_7, b_7) >> 2) & 0x01;
|
|
h_u_cla8_xor7_y0 = xor_gate(h_u_cla8_pg_logic7_y2, h_u_cla8_or27_y0);
|
|
h_u_cla8_and140_y0 = and_gate(h_u_cla8_pg_logic0_y0, constant_wire_0);
|
|
h_u_cla8_and141_y0 = and_gate(h_u_cla8_pg_logic1_y0, constant_wire_0);
|
|
h_u_cla8_and142_y0 = and_gate(h_u_cla8_and141_y0, h_u_cla8_and140_y0);
|
|
h_u_cla8_and143_y0 = and_gate(h_u_cla8_pg_logic2_y0, constant_wire_0);
|
|
h_u_cla8_and144_y0 = and_gate(h_u_cla8_and143_y0, h_u_cla8_and142_y0);
|
|
h_u_cla8_and145_y0 = and_gate(h_u_cla8_pg_logic3_y0, constant_wire_0);
|
|
h_u_cla8_and146_y0 = and_gate(h_u_cla8_and145_y0, h_u_cla8_and144_y0);
|
|
h_u_cla8_and147_y0 = and_gate(h_u_cla8_pg_logic4_y0, constant_wire_0);
|
|
h_u_cla8_and148_y0 = and_gate(h_u_cla8_and147_y0, h_u_cla8_and146_y0);
|
|
h_u_cla8_and149_y0 = and_gate(h_u_cla8_pg_logic5_y0, constant_wire_0);
|
|
h_u_cla8_and150_y0 = and_gate(h_u_cla8_and149_y0, h_u_cla8_and148_y0);
|
|
h_u_cla8_and151_y0 = and_gate(h_u_cla8_pg_logic6_y0, constant_wire_0);
|
|
h_u_cla8_and152_y0 = and_gate(h_u_cla8_and151_y0, h_u_cla8_and150_y0);
|
|
h_u_cla8_and153_y0 = and_gate(h_u_cla8_pg_logic7_y0, constant_wire_0);
|
|
h_u_cla8_and154_y0 = and_gate(h_u_cla8_and153_y0, h_u_cla8_and152_y0);
|
|
h_u_cla8_and155_y0 = and_gate(h_u_cla8_pg_logic1_y0, h_u_cla8_pg_logic0_y1);
|
|
h_u_cla8_and156_y0 = and_gate(h_u_cla8_pg_logic2_y0, h_u_cla8_pg_logic0_y1);
|
|
h_u_cla8_and157_y0 = and_gate(h_u_cla8_and156_y0, h_u_cla8_and155_y0);
|
|
h_u_cla8_and158_y0 = and_gate(h_u_cla8_pg_logic3_y0, h_u_cla8_pg_logic0_y1);
|
|
h_u_cla8_and159_y0 = and_gate(h_u_cla8_and158_y0, h_u_cla8_and157_y0);
|
|
h_u_cla8_and160_y0 = and_gate(h_u_cla8_pg_logic4_y0, h_u_cla8_pg_logic0_y1);
|
|
h_u_cla8_and161_y0 = and_gate(h_u_cla8_and160_y0, h_u_cla8_and159_y0);
|
|
h_u_cla8_and162_y0 = and_gate(h_u_cla8_pg_logic5_y0, h_u_cla8_pg_logic0_y1);
|
|
h_u_cla8_and163_y0 = and_gate(h_u_cla8_and162_y0, h_u_cla8_and161_y0);
|
|
h_u_cla8_and164_y0 = and_gate(h_u_cla8_pg_logic6_y0, h_u_cla8_pg_logic0_y1);
|
|
h_u_cla8_and165_y0 = and_gate(h_u_cla8_and164_y0, h_u_cla8_and163_y0);
|
|
h_u_cla8_and166_y0 = and_gate(h_u_cla8_pg_logic7_y0, h_u_cla8_pg_logic0_y1);
|
|
h_u_cla8_and167_y0 = and_gate(h_u_cla8_and166_y0, h_u_cla8_and165_y0);
|
|
h_u_cla8_and168_y0 = and_gate(h_u_cla8_pg_logic2_y0, h_u_cla8_pg_logic1_y1);
|
|
h_u_cla8_and169_y0 = and_gate(h_u_cla8_pg_logic3_y0, h_u_cla8_pg_logic1_y1);
|
|
h_u_cla8_and170_y0 = and_gate(h_u_cla8_and169_y0, h_u_cla8_and168_y0);
|
|
h_u_cla8_and171_y0 = and_gate(h_u_cla8_pg_logic4_y0, h_u_cla8_pg_logic1_y1);
|
|
h_u_cla8_and172_y0 = and_gate(h_u_cla8_and171_y0, h_u_cla8_and170_y0);
|
|
h_u_cla8_and173_y0 = and_gate(h_u_cla8_pg_logic5_y0, h_u_cla8_pg_logic1_y1);
|
|
h_u_cla8_and174_y0 = and_gate(h_u_cla8_and173_y0, h_u_cla8_and172_y0);
|
|
h_u_cla8_and175_y0 = and_gate(h_u_cla8_pg_logic6_y0, h_u_cla8_pg_logic1_y1);
|
|
h_u_cla8_and176_y0 = and_gate(h_u_cla8_and175_y0, h_u_cla8_and174_y0);
|
|
h_u_cla8_and177_y0 = and_gate(h_u_cla8_pg_logic7_y0, h_u_cla8_pg_logic1_y1);
|
|
h_u_cla8_and178_y0 = and_gate(h_u_cla8_and177_y0, h_u_cla8_and176_y0);
|
|
h_u_cla8_and179_y0 = and_gate(h_u_cla8_pg_logic3_y0, h_u_cla8_pg_logic2_y1);
|
|
h_u_cla8_and180_y0 = and_gate(h_u_cla8_pg_logic4_y0, h_u_cla8_pg_logic2_y1);
|
|
h_u_cla8_and181_y0 = and_gate(h_u_cla8_and180_y0, h_u_cla8_and179_y0);
|
|
h_u_cla8_and182_y0 = and_gate(h_u_cla8_pg_logic5_y0, h_u_cla8_pg_logic2_y1);
|
|
h_u_cla8_and183_y0 = and_gate(h_u_cla8_and182_y0, h_u_cla8_and181_y0);
|
|
h_u_cla8_and184_y0 = and_gate(h_u_cla8_pg_logic6_y0, h_u_cla8_pg_logic2_y1);
|
|
h_u_cla8_and185_y0 = and_gate(h_u_cla8_and184_y0, h_u_cla8_and183_y0);
|
|
h_u_cla8_and186_y0 = and_gate(h_u_cla8_pg_logic7_y0, h_u_cla8_pg_logic2_y1);
|
|
h_u_cla8_and187_y0 = and_gate(h_u_cla8_and186_y0, h_u_cla8_and185_y0);
|
|
h_u_cla8_and188_y0 = and_gate(h_u_cla8_pg_logic4_y0, h_u_cla8_pg_logic3_y1);
|
|
h_u_cla8_and189_y0 = and_gate(h_u_cla8_pg_logic5_y0, h_u_cla8_pg_logic3_y1);
|
|
h_u_cla8_and190_y0 = and_gate(h_u_cla8_and189_y0, h_u_cla8_and188_y0);
|
|
h_u_cla8_and191_y0 = and_gate(h_u_cla8_pg_logic6_y0, h_u_cla8_pg_logic3_y1);
|
|
h_u_cla8_and192_y0 = and_gate(h_u_cla8_and191_y0, h_u_cla8_and190_y0);
|
|
h_u_cla8_and193_y0 = and_gate(h_u_cla8_pg_logic7_y0, h_u_cla8_pg_logic3_y1);
|
|
h_u_cla8_and194_y0 = and_gate(h_u_cla8_and193_y0, h_u_cla8_and192_y0);
|
|
h_u_cla8_and195_y0 = and_gate(h_u_cla8_pg_logic5_y0, h_u_cla8_pg_logic4_y1);
|
|
h_u_cla8_and196_y0 = and_gate(h_u_cla8_pg_logic6_y0, h_u_cla8_pg_logic4_y1);
|
|
h_u_cla8_and197_y0 = and_gate(h_u_cla8_and196_y0, h_u_cla8_and195_y0);
|
|
h_u_cla8_and198_y0 = and_gate(h_u_cla8_pg_logic7_y0, h_u_cla8_pg_logic4_y1);
|
|
h_u_cla8_and199_y0 = and_gate(h_u_cla8_and198_y0, h_u_cla8_and197_y0);
|
|
h_u_cla8_and200_y0 = and_gate(h_u_cla8_pg_logic6_y0, h_u_cla8_pg_logic5_y1);
|
|
h_u_cla8_and201_y0 = and_gate(h_u_cla8_pg_logic7_y0, h_u_cla8_pg_logic5_y1);
|
|
h_u_cla8_and202_y0 = and_gate(h_u_cla8_and201_y0, h_u_cla8_and200_y0);
|
|
h_u_cla8_and203_y0 = and_gate(h_u_cla8_pg_logic7_y0, h_u_cla8_pg_logic6_y1);
|
|
h_u_cla8_or28_y0 = or_gate(h_u_cla8_and203_y0, h_u_cla8_and154_y0);
|
|
h_u_cla8_or29_y0 = or_gate(h_u_cla8_or28_y0, h_u_cla8_and167_y0);
|
|
h_u_cla8_or30_y0 = or_gate(h_u_cla8_or29_y0, h_u_cla8_and178_y0);
|
|
h_u_cla8_or31_y0 = or_gate(h_u_cla8_or30_y0, h_u_cla8_and187_y0);
|
|
h_u_cla8_or32_y0 = or_gate(h_u_cla8_or31_y0, h_u_cla8_and194_y0);
|
|
h_u_cla8_or33_y0 = or_gate(h_u_cla8_or32_y0, h_u_cla8_and199_y0);
|
|
h_u_cla8_or34_y0 = or_gate(h_u_cla8_or33_y0, h_u_cla8_and202_y0);
|
|
h_u_cla8_or35_y0 = or_gate(h_u_cla8_pg_logic7_y1, h_u_cla8_or34_y0);
|
|
|
|
out |= (h_u_cla8_xor0_y0 & 0x01) << 0;
|
|
out |= (h_u_cla8_xor1_y0 & 0x01) << 1;
|
|
out |= (h_u_cla8_xor2_y0 & 0x01) << 2;
|
|
out |= (h_u_cla8_xor3_y0 & 0x01) << 3;
|
|
out |= (h_u_cla8_xor4_y0 & 0x01) << 4;
|
|
out |= (h_u_cla8_xor5_y0 & 0x01) << 5;
|
|
out |= (h_u_cla8_xor6_y0 & 0x01) << 6;
|
|
out |= (h_u_cla8_xor7_y0 & 0x01) << 7;
|
|
out |= (h_u_cla8_or35_y0 & 0x01) << 8;
|
|
return out;
|
|
} |