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257 lines
12 KiB
Plaintext
257 lines
12 KiB
Plaintext
.model h_s_cska32
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.inputs a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] a[8] a[9] a[10] a[11] a[12] a[13] a[14] a[15] a[16] a[17] a[18] a[19] a[20] a[21] a[22] a[23] a[24] a[25] a[26] a[27] a[28] a[29] a[30] a[31] b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9] b[10] b[11] b[12] b[13] b[14] b[15] b[16] b[17] b[18] b[19] b[20] b[21] b[22] b[23] b[24] b[25] b[26] b[27] b[28] b[29] b[30] b[31]
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.outputs h_s_cska32_out[0] h_s_cska32_out[1] h_s_cska32_out[2] h_s_cska32_out[3] h_s_cska32_out[4] h_s_cska32_out[5] h_s_cska32_out[6] h_s_cska32_out[7] h_s_cska32_out[8] h_s_cska32_out[9] h_s_cska32_out[10] h_s_cska32_out[11] h_s_cska32_out[12] h_s_cska32_out[13] h_s_cska32_out[14] h_s_cska32_out[15] h_s_cska32_out[16] h_s_cska32_out[17] h_s_cska32_out[18] h_s_cska32_out[19] h_s_cska32_out[20] h_s_cska32_out[21] h_s_cska32_out[22] h_s_cska32_out[23] h_s_cska32_out[24] h_s_cska32_out[25] h_s_cska32_out[26] h_s_cska32_out[27] h_s_cska32_out[28] h_s_cska32_out[29] h_s_cska32_out[30] h_s_cska32_out[31] h_s_cska32_out[32]
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.names vdd
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1
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.names gnd
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0
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.subckt xor_gate a=a[0] b=b[0] out=h_s_cska32_xor0
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.subckt ha a=a[0] b=b[0] ha_xor0=h_s_cska32_ha0_xor0 ha_and0=h_s_cska32_ha0_and0
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.subckt xor_gate a=a[1] b=b[1] out=h_s_cska32_xor1
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.subckt fa a=a[1] b=b[1] cin=h_s_cska32_ha0_and0 fa_xor1=h_s_cska32_fa0_xor1 fa_or0=h_s_cska32_fa0_or0
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.subckt xor_gate a=a[2] b=b[2] out=h_s_cska32_xor2
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.subckt fa a=a[2] b=b[2] cin=h_s_cska32_fa0_or0 fa_xor1=h_s_cska32_fa1_xor1 fa_or0=h_s_cska32_fa1_or0
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.subckt xor_gate a=a[3] b=b[3] out=h_s_cska32_xor3
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.subckt fa a=a[3] b=b[3] cin=h_s_cska32_fa1_or0 fa_xor1=h_s_cska32_fa2_xor1 fa_or0=h_s_cska32_fa2_or0
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.subckt and_gate a=h_s_cska32_xor0 b=h_s_cska32_xor2 out=h_s_cska32_and_propagate00
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.subckt and_gate a=h_s_cska32_xor1 b=h_s_cska32_xor3 out=h_s_cska32_and_propagate01
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.subckt and_gate a=h_s_cska32_and_propagate00 b=h_s_cska32_and_propagate01 out=h_s_cska32_and_propagate02
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.subckt mux2to1 d0=h_s_cska32_fa2_or0 d1=gnd sel=h_s_cska32_and_propagate02 mux2to1_xor0=h_s_cska32_mux2to10_and1
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.subckt xor_gate a=a[4] b=b[4] out=h_s_cska32_xor4
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.subckt fa a=a[4] b=b[4] cin=h_s_cska32_mux2to10_and1 fa_xor1=h_s_cska32_fa3_xor1 fa_or0=h_s_cska32_fa3_or0
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.subckt xor_gate a=a[5] b=b[5] out=h_s_cska32_xor5
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.subckt fa a=a[5] b=b[5] cin=h_s_cska32_fa3_or0 fa_xor1=h_s_cska32_fa4_xor1 fa_or0=h_s_cska32_fa4_or0
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.subckt xor_gate a=a[6] b=b[6] out=h_s_cska32_xor6
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.subckt fa a=a[6] b=b[6] cin=h_s_cska32_fa4_or0 fa_xor1=h_s_cska32_fa5_xor1 fa_or0=h_s_cska32_fa5_or0
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.subckt xor_gate a=a[7] b=b[7] out=h_s_cska32_xor7
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.subckt fa a=a[7] b=b[7] cin=h_s_cska32_fa5_or0 fa_xor1=h_s_cska32_fa6_xor1 fa_or0=h_s_cska32_fa6_or0
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.subckt and_gate a=h_s_cska32_xor4 b=h_s_cska32_xor6 out=h_s_cska32_and_propagate13
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.subckt and_gate a=h_s_cska32_xor5 b=h_s_cska32_xor7 out=h_s_cska32_and_propagate14
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.subckt and_gate a=h_s_cska32_and_propagate13 b=h_s_cska32_and_propagate14 out=h_s_cska32_and_propagate15
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.subckt mux2to1 d0=h_s_cska32_fa6_or0 d1=h_s_cska32_mux2to10_and1 sel=h_s_cska32_and_propagate15 mux2to1_xor0=h_s_cska32_mux2to11_xor0
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.subckt xor_gate a=a[8] b=b[8] out=h_s_cska32_xor8
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.subckt fa a=a[8] b=b[8] cin=h_s_cska32_mux2to11_xor0 fa_xor1=h_s_cska32_fa7_xor1 fa_or0=h_s_cska32_fa7_or0
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.subckt xor_gate a=a[9] b=b[9] out=h_s_cska32_xor9
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.subckt fa a=a[9] b=b[9] cin=h_s_cska32_fa7_or0 fa_xor1=h_s_cska32_fa8_xor1 fa_or0=h_s_cska32_fa8_or0
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.subckt xor_gate a=a[10] b=b[10] out=h_s_cska32_xor10
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.subckt fa a=a[10] b=b[10] cin=h_s_cska32_fa8_or0 fa_xor1=h_s_cska32_fa9_xor1 fa_or0=h_s_cska32_fa9_or0
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.subckt xor_gate a=a[11] b=b[11] out=h_s_cska32_xor11
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.subckt fa a=a[11] b=b[11] cin=h_s_cska32_fa9_or0 fa_xor1=h_s_cska32_fa10_xor1 fa_or0=h_s_cska32_fa10_or0
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.subckt and_gate a=h_s_cska32_xor8 b=h_s_cska32_xor10 out=h_s_cska32_and_propagate26
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.subckt and_gate a=h_s_cska32_xor9 b=h_s_cska32_xor11 out=h_s_cska32_and_propagate27
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.subckt and_gate a=h_s_cska32_and_propagate26 b=h_s_cska32_and_propagate27 out=h_s_cska32_and_propagate28
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.subckt mux2to1 d0=h_s_cska32_fa10_or0 d1=h_s_cska32_mux2to11_xor0 sel=h_s_cska32_and_propagate28 mux2to1_xor0=h_s_cska32_mux2to12_xor0
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.subckt xor_gate a=a[12] b=b[12] out=h_s_cska32_xor12
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.subckt fa a=a[12] b=b[12] cin=h_s_cska32_mux2to12_xor0 fa_xor1=h_s_cska32_fa11_xor1 fa_or0=h_s_cska32_fa11_or0
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.subckt xor_gate a=a[13] b=b[13] out=h_s_cska32_xor13
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.subckt fa a=a[13] b=b[13] cin=h_s_cska32_fa11_or0 fa_xor1=h_s_cska32_fa12_xor1 fa_or0=h_s_cska32_fa12_or0
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.subckt xor_gate a=a[14] b=b[14] out=h_s_cska32_xor14
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.subckt fa a=a[14] b=b[14] cin=h_s_cska32_fa12_or0 fa_xor1=h_s_cska32_fa13_xor1 fa_or0=h_s_cska32_fa13_or0
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.subckt xor_gate a=a[15] b=b[15] out=h_s_cska32_xor15
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.subckt fa a=a[15] b=b[15] cin=h_s_cska32_fa13_or0 fa_xor1=h_s_cska32_fa14_xor1 fa_or0=h_s_cska32_fa14_or0
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.subckt and_gate a=h_s_cska32_xor12 b=h_s_cska32_xor14 out=h_s_cska32_and_propagate39
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.subckt and_gate a=h_s_cska32_xor13 b=h_s_cska32_xor15 out=h_s_cska32_and_propagate310
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.subckt and_gate a=h_s_cska32_and_propagate39 b=h_s_cska32_and_propagate310 out=h_s_cska32_and_propagate311
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.subckt mux2to1 d0=h_s_cska32_fa14_or0 d1=h_s_cska32_mux2to12_xor0 sel=h_s_cska32_and_propagate311 mux2to1_xor0=h_s_cska32_mux2to13_xor0
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.subckt xor_gate a=a[16] b=b[16] out=h_s_cska32_xor16
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.subckt fa a=a[16] b=b[16] cin=h_s_cska32_mux2to13_xor0 fa_xor1=h_s_cska32_fa15_xor1 fa_or0=h_s_cska32_fa15_or0
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.subckt xor_gate a=a[17] b=b[17] out=h_s_cska32_xor17
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.subckt fa a=a[17] b=b[17] cin=h_s_cska32_fa15_or0 fa_xor1=h_s_cska32_fa16_xor1 fa_or0=h_s_cska32_fa16_or0
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.subckt xor_gate a=a[18] b=b[18] out=h_s_cska32_xor18
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.subckt fa a=a[18] b=b[18] cin=h_s_cska32_fa16_or0 fa_xor1=h_s_cska32_fa17_xor1 fa_or0=h_s_cska32_fa17_or0
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.subckt xor_gate a=a[19] b=b[19] out=h_s_cska32_xor19
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.subckt fa a=a[19] b=b[19] cin=h_s_cska32_fa17_or0 fa_xor1=h_s_cska32_fa18_xor1 fa_or0=h_s_cska32_fa18_or0
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.subckt and_gate a=h_s_cska32_xor16 b=h_s_cska32_xor18 out=h_s_cska32_and_propagate412
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.subckt and_gate a=h_s_cska32_xor17 b=h_s_cska32_xor19 out=h_s_cska32_and_propagate413
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.subckt and_gate a=h_s_cska32_and_propagate412 b=h_s_cska32_and_propagate413 out=h_s_cska32_and_propagate414
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.subckt mux2to1 d0=h_s_cska32_fa18_or0 d1=h_s_cska32_mux2to13_xor0 sel=h_s_cska32_and_propagate414 mux2to1_xor0=h_s_cska32_mux2to14_xor0
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.subckt xor_gate a=a[20] b=b[20] out=h_s_cska32_xor20
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.subckt fa a=a[20] b=b[20] cin=h_s_cska32_mux2to14_xor0 fa_xor1=h_s_cska32_fa19_xor1 fa_or0=h_s_cska32_fa19_or0
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.subckt xor_gate a=a[21] b=b[21] out=h_s_cska32_xor21
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.subckt fa a=a[21] b=b[21] cin=h_s_cska32_fa19_or0 fa_xor1=h_s_cska32_fa20_xor1 fa_or0=h_s_cska32_fa20_or0
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.subckt xor_gate a=a[22] b=b[22] out=h_s_cska32_xor22
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.subckt fa a=a[22] b=b[22] cin=h_s_cska32_fa20_or0 fa_xor1=h_s_cska32_fa21_xor1 fa_or0=h_s_cska32_fa21_or0
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.subckt xor_gate a=a[23] b=b[23] out=h_s_cska32_xor23
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.subckt fa a=a[23] b=b[23] cin=h_s_cska32_fa21_or0 fa_xor1=h_s_cska32_fa22_xor1 fa_or0=h_s_cska32_fa22_or0
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.subckt and_gate a=h_s_cska32_xor20 b=h_s_cska32_xor22 out=h_s_cska32_and_propagate515
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.subckt and_gate a=h_s_cska32_xor21 b=h_s_cska32_xor23 out=h_s_cska32_and_propagate516
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.subckt and_gate a=h_s_cska32_and_propagate515 b=h_s_cska32_and_propagate516 out=h_s_cska32_and_propagate517
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.subckt mux2to1 d0=h_s_cska32_fa22_or0 d1=h_s_cska32_mux2to14_xor0 sel=h_s_cska32_and_propagate517 mux2to1_xor0=h_s_cska32_mux2to15_xor0
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.subckt xor_gate a=a[24] b=b[24] out=h_s_cska32_xor24
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.subckt fa a=a[24] b=b[24] cin=h_s_cska32_mux2to15_xor0 fa_xor1=h_s_cska32_fa23_xor1 fa_or0=h_s_cska32_fa23_or0
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.subckt xor_gate a=a[25] b=b[25] out=h_s_cska32_xor25
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.subckt fa a=a[25] b=b[25] cin=h_s_cska32_fa23_or0 fa_xor1=h_s_cska32_fa24_xor1 fa_or0=h_s_cska32_fa24_or0
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.subckt xor_gate a=a[26] b=b[26] out=h_s_cska32_xor26
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.subckt fa a=a[26] b=b[26] cin=h_s_cska32_fa24_or0 fa_xor1=h_s_cska32_fa25_xor1 fa_or0=h_s_cska32_fa25_or0
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.subckt xor_gate a=a[27] b=b[27] out=h_s_cska32_xor27
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.subckt fa a=a[27] b=b[27] cin=h_s_cska32_fa25_or0 fa_xor1=h_s_cska32_fa26_xor1 fa_or0=h_s_cska32_fa26_or0
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.subckt and_gate a=h_s_cska32_xor24 b=h_s_cska32_xor26 out=h_s_cska32_and_propagate618
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.subckt and_gate a=h_s_cska32_xor25 b=h_s_cska32_xor27 out=h_s_cska32_and_propagate619
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.subckt and_gate a=h_s_cska32_and_propagate618 b=h_s_cska32_and_propagate619 out=h_s_cska32_and_propagate620
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.subckt mux2to1 d0=h_s_cska32_fa26_or0 d1=h_s_cska32_mux2to15_xor0 sel=h_s_cska32_and_propagate620 mux2to1_xor0=h_s_cska32_mux2to16_xor0
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.subckt xor_gate a=a[28] b=b[28] out=h_s_cska32_xor28
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.subckt fa a=a[28] b=b[28] cin=h_s_cska32_mux2to16_xor0 fa_xor1=h_s_cska32_fa27_xor1 fa_or0=h_s_cska32_fa27_or0
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.subckt xor_gate a=a[29] b=b[29] out=h_s_cska32_xor29
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.subckt fa a=a[29] b=b[29] cin=h_s_cska32_fa27_or0 fa_xor1=h_s_cska32_fa28_xor1 fa_or0=h_s_cska32_fa28_or0
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.subckt xor_gate a=a[30] b=b[30] out=h_s_cska32_xor30
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.subckt fa a=a[30] b=b[30] cin=h_s_cska32_fa28_or0 fa_xor1=h_s_cska32_fa29_xor1 fa_or0=h_s_cska32_fa29_or0
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.subckt xor_gate a=a[31] b=b[31] out=h_s_cska32_xor31
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.subckt fa a=a[31] b=b[31] cin=h_s_cska32_fa29_or0 fa_xor1=h_s_cska32_fa30_xor1 fa_or0=h_s_cska32_fa30_or0
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.subckt and_gate a=h_s_cska32_xor28 b=h_s_cska32_xor30 out=h_s_cska32_and_propagate721
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.subckt and_gate a=h_s_cska32_xor29 b=h_s_cska32_xor31 out=h_s_cska32_and_propagate722
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.subckt and_gate a=h_s_cska32_and_propagate721 b=h_s_cska32_and_propagate722 out=h_s_cska32_and_propagate723
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.subckt mux2to1 d0=h_s_cska32_fa30_or0 d1=h_s_cska32_mux2to16_xor0 sel=h_s_cska32_and_propagate723 mux2to1_xor0=h_s_cska32_mux2to17_xor0
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.subckt xor_gate a=a[31] b=b[31] out=h_s_cska32_xor32
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.subckt xor_gate a=h_s_cska32_xor32 b=h_s_cska32_mux2to17_xor0 out=h_s_cska32_xor33
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.names h_s_cska32_ha0_xor0 h_s_cska32_out[0]
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1 1
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.names h_s_cska32_fa0_xor1 h_s_cska32_out[1]
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1 1
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.names h_s_cska32_fa1_xor1 h_s_cska32_out[2]
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1 1
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.names h_s_cska32_fa2_xor1 h_s_cska32_out[3]
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1 1
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.names h_s_cska32_fa3_xor1 h_s_cska32_out[4]
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1 1
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.names h_s_cska32_fa4_xor1 h_s_cska32_out[5]
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1 1
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.names h_s_cska32_fa5_xor1 h_s_cska32_out[6]
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1 1
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.names h_s_cska32_fa6_xor1 h_s_cska32_out[7]
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1 1
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.names h_s_cska32_fa7_xor1 h_s_cska32_out[8]
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1 1
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.names h_s_cska32_fa8_xor1 h_s_cska32_out[9]
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1 1
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.names h_s_cska32_fa9_xor1 h_s_cska32_out[10]
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1 1
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.names h_s_cska32_fa10_xor1 h_s_cska32_out[11]
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1 1
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.names h_s_cska32_fa11_xor1 h_s_cska32_out[12]
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1 1
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.names h_s_cska32_fa12_xor1 h_s_cska32_out[13]
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1 1
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.names h_s_cska32_fa13_xor1 h_s_cska32_out[14]
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1 1
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.names h_s_cska32_fa14_xor1 h_s_cska32_out[15]
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1 1
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.names h_s_cska32_fa15_xor1 h_s_cska32_out[16]
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1 1
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.names h_s_cska32_fa16_xor1 h_s_cska32_out[17]
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1 1
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.names h_s_cska32_fa17_xor1 h_s_cska32_out[18]
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1 1
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.names h_s_cska32_fa18_xor1 h_s_cska32_out[19]
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1 1
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.names h_s_cska32_fa19_xor1 h_s_cska32_out[20]
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1 1
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.names h_s_cska32_fa20_xor1 h_s_cska32_out[21]
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1 1
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.names h_s_cska32_fa21_xor1 h_s_cska32_out[22]
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1 1
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.names h_s_cska32_fa22_xor1 h_s_cska32_out[23]
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1 1
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.names h_s_cska32_fa23_xor1 h_s_cska32_out[24]
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1 1
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.names h_s_cska32_fa24_xor1 h_s_cska32_out[25]
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1 1
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.names h_s_cska32_fa25_xor1 h_s_cska32_out[26]
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1 1
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.names h_s_cska32_fa26_xor1 h_s_cska32_out[27]
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1 1
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.names h_s_cska32_fa27_xor1 h_s_cska32_out[28]
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1 1
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.names h_s_cska32_fa28_xor1 h_s_cska32_out[29]
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1 1
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.names h_s_cska32_fa29_xor1 h_s_cska32_out[30]
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1 1
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.names h_s_cska32_fa30_xor1 h_s_cska32_out[31]
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1 1
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.names h_s_cska32_xor33 h_s_cska32_out[32]
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1 1
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.end
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.model mux2to1
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.inputs d0 d1 sel
|
|
.outputs mux2to1_xor0
|
|
.names vdd
|
|
1
|
|
.names gnd
|
|
0
|
|
.subckt and_gate a=d1 b=sel out=mux2to1_and0
|
|
.subckt not_gate a=sel out=mux2to1_not0
|
|
.subckt and_gate a=d0 b=mux2to1_not0 out=mux2to1_and1
|
|
.subckt xor_gate a=mux2to1_and0 b=mux2to1_and1 out=mux2to1_xor0
|
|
.end
|
|
|
|
.model fa
|
|
.inputs a b cin
|
|
.outputs fa_xor1 fa_or0
|
|
.names vdd
|
|
1
|
|
.names gnd
|
|
0
|
|
.subckt xor_gate a=a b=b out=fa_xor0
|
|
.subckt and_gate a=a b=b out=fa_and0
|
|
.subckt xor_gate a=fa_xor0 b=cin out=fa_xor1
|
|
.subckt and_gate a=fa_xor0 b=cin out=fa_and1
|
|
.subckt or_gate a=fa_and0 b=fa_and1 out=fa_or0
|
|
.end
|
|
|
|
.model ha
|
|
.inputs a b
|
|
.outputs ha_xor0 ha_and0
|
|
.names vdd
|
|
1
|
|
.names gnd
|
|
0
|
|
.subckt xor_gate a=a b=b out=ha_xor0
|
|
.subckt and_gate a=a b=b out=ha_and0
|
|
.end
|
|
|
|
.model not_gate
|
|
.inputs a
|
|
.outputs out
|
|
.names vdd
|
|
1
|
|
.names gnd
|
|
0
|
|
.names a out
|
|
0 1
|
|
.end
|
|
|
|
.model or_gate
|
|
.inputs a b
|
|
.outputs out
|
|
.names vdd
|
|
1
|
|
.names gnd
|
|
0
|
|
.names a b out
|
|
1- 1
|
|
-1 1
|
|
.end
|
|
|
|
.model and_gate
|
|
.inputs a b
|
|
.outputs out
|
|
.names vdd
|
|
1
|
|
.names gnd
|
|
0
|
|
.names a b out
|
|
11 1
|
|
.end
|
|
|
|
.model xor_gate
|
|
.inputs a b
|
|
.outputs out
|
|
.names vdd
|
|
1
|
|
.names gnd
|
|
0
|
|
.names a b out
|
|
01 1
|
|
10 1
|
|
.end
|