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231 lines
14 KiB
Plaintext
231 lines
14 KiB
Plaintext
.model h_s_cla16
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.inputs a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] a[8] a[9] a[10] a[11] a[12] a[13] a[14] a[15] b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9] b[10] b[11] b[12] b[13] b[14] b[15]
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.outputs h_s_cla16_out[0] h_s_cla16_out[1] h_s_cla16_out[2] h_s_cla16_out[3] h_s_cla16_out[4] h_s_cla16_out[5] h_s_cla16_out[6] h_s_cla16_out[7] h_s_cla16_out[8] h_s_cla16_out[9] h_s_cla16_out[10] h_s_cla16_out[11] h_s_cla16_out[12] h_s_cla16_out[13] h_s_cla16_out[14] h_s_cla16_out[15] h_s_cla16_out[16]
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.names vdd
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1
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.names gnd
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0
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.subckt pg_logic a=a[0] b=b[0] pg_logic_or0=h_s_cla16_pg_logic0_or0 pg_logic_and0=h_s_cla16_pg_logic0_and0 pg_logic_xor0=h_s_cla16_pg_logic0_xor0
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.subckt pg_logic a=a[1] b=b[1] pg_logic_or0=h_s_cla16_pg_logic1_or0 pg_logic_and0=h_s_cla16_pg_logic1_and0 pg_logic_xor0=h_s_cla16_pg_logic1_xor0
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.subckt xor_gate a=h_s_cla16_pg_logic1_xor0 b=h_s_cla16_pg_logic0_and0 out=h_s_cla16_xor1
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.subckt and_gate a=h_s_cla16_pg_logic0_and0 b=h_s_cla16_pg_logic1_or0 out=h_s_cla16_and0
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.subckt or_gate a=h_s_cla16_pg_logic1_and0 b=h_s_cla16_and0 out=h_s_cla16_or0
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.subckt pg_logic a=a[2] b=b[2] pg_logic_or0=h_s_cla16_pg_logic2_or0 pg_logic_and0=h_s_cla16_pg_logic2_and0 pg_logic_xor0=h_s_cla16_pg_logic2_xor0
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.subckt xor_gate a=h_s_cla16_pg_logic2_xor0 b=h_s_cla16_or0 out=h_s_cla16_xor2
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.subckt and_gate a=h_s_cla16_pg_logic2_or0 b=h_s_cla16_pg_logic0_or0 out=h_s_cla16_and1
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.subckt and_gate a=h_s_cla16_pg_logic0_and0 b=h_s_cla16_pg_logic2_or0 out=h_s_cla16_and2
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.subckt and_gate a=h_s_cla16_and2 b=h_s_cla16_pg_logic1_or0 out=h_s_cla16_and3
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.subckt and_gate a=h_s_cla16_pg_logic1_and0 b=h_s_cla16_pg_logic2_or0 out=h_s_cla16_and4
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.subckt or_gate a=h_s_cla16_and3 b=h_s_cla16_and4 out=h_s_cla16_or1
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.subckt or_gate a=h_s_cla16_pg_logic2_and0 b=h_s_cla16_or1 out=h_s_cla16_or2
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.subckt pg_logic a=a[3] b=b[3] pg_logic_or0=h_s_cla16_pg_logic3_or0 pg_logic_and0=h_s_cla16_pg_logic3_and0 pg_logic_xor0=h_s_cla16_pg_logic3_xor0
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.subckt xor_gate a=h_s_cla16_pg_logic3_xor0 b=h_s_cla16_or2 out=h_s_cla16_xor3
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.subckt and_gate a=h_s_cla16_pg_logic3_or0 b=h_s_cla16_pg_logic1_or0 out=h_s_cla16_and5
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.subckt and_gate a=h_s_cla16_pg_logic0_and0 b=h_s_cla16_pg_logic2_or0 out=h_s_cla16_and6
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.subckt and_gate a=h_s_cla16_pg_logic3_or0 b=h_s_cla16_pg_logic1_or0 out=h_s_cla16_and7
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.subckt and_gate a=h_s_cla16_and6 b=h_s_cla16_and7 out=h_s_cla16_and8
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.subckt and_gate a=h_s_cla16_pg_logic1_and0 b=h_s_cla16_pg_logic3_or0 out=h_s_cla16_and9
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.subckt and_gate a=h_s_cla16_and9 b=h_s_cla16_pg_logic2_or0 out=h_s_cla16_and10
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.subckt and_gate a=h_s_cla16_pg_logic2_and0 b=h_s_cla16_pg_logic3_or0 out=h_s_cla16_and11
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.subckt or_gate a=h_s_cla16_and8 b=h_s_cla16_and11 out=h_s_cla16_or3
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.subckt or_gate a=h_s_cla16_and10 b=h_s_cla16_or3 out=h_s_cla16_or4
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.subckt or_gate a=h_s_cla16_pg_logic3_and0 b=h_s_cla16_or4 out=h_s_cla16_or5
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.subckt pg_logic a=a[4] b=b[4] pg_logic_or0=h_s_cla16_pg_logic4_or0 pg_logic_and0=h_s_cla16_pg_logic4_and0 pg_logic_xor0=h_s_cla16_pg_logic4_xor0
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.subckt xor_gate a=h_s_cla16_pg_logic4_xor0 b=h_s_cla16_or5 out=h_s_cla16_xor4
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.subckt and_gate a=h_s_cla16_or5 b=h_s_cla16_pg_logic4_or0 out=h_s_cla16_and12
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.subckt or_gate a=h_s_cla16_pg_logic4_and0 b=h_s_cla16_and12 out=h_s_cla16_or6
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.subckt pg_logic a=a[5] b=b[5] pg_logic_or0=h_s_cla16_pg_logic5_or0 pg_logic_and0=h_s_cla16_pg_logic5_and0 pg_logic_xor0=h_s_cla16_pg_logic5_xor0
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.subckt xor_gate a=h_s_cla16_pg_logic5_xor0 b=h_s_cla16_or6 out=h_s_cla16_xor5
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.subckt and_gate a=h_s_cla16_or5 b=h_s_cla16_pg_logic5_or0 out=h_s_cla16_and13
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.subckt and_gate a=h_s_cla16_and13 b=h_s_cla16_pg_logic4_or0 out=h_s_cla16_and14
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.subckt and_gate a=h_s_cla16_pg_logic4_and0 b=h_s_cla16_pg_logic5_or0 out=h_s_cla16_and15
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.subckt or_gate a=h_s_cla16_and14 b=h_s_cla16_and15 out=h_s_cla16_or7
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.subckt or_gate a=h_s_cla16_pg_logic5_and0 b=h_s_cla16_or7 out=h_s_cla16_or8
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.subckt pg_logic a=a[6] b=b[6] pg_logic_or0=h_s_cla16_pg_logic6_or0 pg_logic_and0=h_s_cla16_pg_logic6_and0 pg_logic_xor0=h_s_cla16_pg_logic6_xor0
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.subckt xor_gate a=h_s_cla16_pg_logic6_xor0 b=h_s_cla16_or8 out=h_s_cla16_xor6
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.subckt and_gate a=h_s_cla16_or5 b=h_s_cla16_pg_logic5_or0 out=h_s_cla16_and16
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.subckt and_gate a=h_s_cla16_pg_logic6_or0 b=h_s_cla16_pg_logic4_or0 out=h_s_cla16_and17
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.subckt and_gate a=h_s_cla16_and16 b=h_s_cla16_and17 out=h_s_cla16_and18
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.subckt and_gate a=h_s_cla16_pg_logic4_and0 b=h_s_cla16_pg_logic6_or0 out=h_s_cla16_and19
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.subckt and_gate a=h_s_cla16_and19 b=h_s_cla16_pg_logic5_or0 out=h_s_cla16_and20
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.subckt and_gate a=h_s_cla16_pg_logic5_and0 b=h_s_cla16_pg_logic6_or0 out=h_s_cla16_and21
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.subckt or_gate a=h_s_cla16_and18 b=h_s_cla16_and20 out=h_s_cla16_or9
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.subckt or_gate a=h_s_cla16_or9 b=h_s_cla16_and21 out=h_s_cla16_or10
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.subckt or_gate a=h_s_cla16_pg_logic6_and0 b=h_s_cla16_or10 out=h_s_cla16_or11
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.subckt pg_logic a=a[7] b=b[7] pg_logic_or0=h_s_cla16_pg_logic7_or0 pg_logic_and0=h_s_cla16_pg_logic7_and0 pg_logic_xor0=h_s_cla16_pg_logic7_xor0
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.subckt xor_gate a=h_s_cla16_pg_logic7_xor0 b=h_s_cla16_or11 out=h_s_cla16_xor7
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.subckt and_gate a=h_s_cla16_or5 b=h_s_cla16_pg_logic6_or0 out=h_s_cla16_and22
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.subckt and_gate a=h_s_cla16_pg_logic7_or0 b=h_s_cla16_pg_logic5_or0 out=h_s_cla16_and23
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.subckt and_gate a=h_s_cla16_and22 b=h_s_cla16_and23 out=h_s_cla16_and24
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.subckt and_gate a=h_s_cla16_and24 b=h_s_cla16_pg_logic4_or0 out=h_s_cla16_and25
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.subckt and_gate a=h_s_cla16_pg_logic4_and0 b=h_s_cla16_pg_logic6_or0 out=h_s_cla16_and26
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.subckt and_gate a=h_s_cla16_pg_logic7_or0 b=h_s_cla16_pg_logic5_or0 out=h_s_cla16_and27
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.subckt and_gate a=h_s_cla16_and26 b=h_s_cla16_and27 out=h_s_cla16_and28
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.subckt and_gate a=h_s_cla16_pg_logic5_and0 b=h_s_cla16_pg_logic7_or0 out=h_s_cla16_and29
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.subckt and_gate a=h_s_cla16_and29 b=h_s_cla16_pg_logic6_or0 out=h_s_cla16_and30
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.subckt and_gate a=h_s_cla16_pg_logic6_and0 b=h_s_cla16_pg_logic7_or0 out=h_s_cla16_and31
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.subckt or_gate a=h_s_cla16_and25 b=h_s_cla16_and30 out=h_s_cla16_or12
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.subckt or_gate a=h_s_cla16_and28 b=h_s_cla16_and31 out=h_s_cla16_or13
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.subckt or_gate a=h_s_cla16_or12 b=h_s_cla16_or13 out=h_s_cla16_or14
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.subckt or_gate a=h_s_cla16_pg_logic7_and0 b=h_s_cla16_or14 out=h_s_cla16_or15
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.subckt pg_logic a=a[8] b=b[8] pg_logic_or0=h_s_cla16_pg_logic8_or0 pg_logic_and0=h_s_cla16_pg_logic8_and0 pg_logic_xor0=h_s_cla16_pg_logic8_xor0
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.subckt xor_gate a=h_s_cla16_pg_logic8_xor0 b=h_s_cla16_or15 out=h_s_cla16_xor8
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.subckt and_gate a=h_s_cla16_or15 b=h_s_cla16_pg_logic8_or0 out=h_s_cla16_and32
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.subckt or_gate a=h_s_cla16_pg_logic8_and0 b=h_s_cla16_and32 out=h_s_cla16_or16
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.subckt pg_logic a=a[9] b=b[9] pg_logic_or0=h_s_cla16_pg_logic9_or0 pg_logic_and0=h_s_cla16_pg_logic9_and0 pg_logic_xor0=h_s_cla16_pg_logic9_xor0
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.subckt xor_gate a=h_s_cla16_pg_logic9_xor0 b=h_s_cla16_or16 out=h_s_cla16_xor9
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.subckt and_gate a=h_s_cla16_or15 b=h_s_cla16_pg_logic9_or0 out=h_s_cla16_and33
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.subckt and_gate a=h_s_cla16_and33 b=h_s_cla16_pg_logic8_or0 out=h_s_cla16_and34
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.subckt and_gate a=h_s_cla16_pg_logic8_and0 b=h_s_cla16_pg_logic9_or0 out=h_s_cla16_and35
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.subckt or_gate a=h_s_cla16_and34 b=h_s_cla16_and35 out=h_s_cla16_or17
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.subckt or_gate a=h_s_cla16_pg_logic9_and0 b=h_s_cla16_or17 out=h_s_cla16_or18
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.subckt pg_logic a=a[10] b=b[10] pg_logic_or0=h_s_cla16_pg_logic10_or0 pg_logic_and0=h_s_cla16_pg_logic10_and0 pg_logic_xor0=h_s_cla16_pg_logic10_xor0
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.subckt xor_gate a=h_s_cla16_pg_logic10_xor0 b=h_s_cla16_or18 out=h_s_cla16_xor10
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.subckt and_gate a=h_s_cla16_or15 b=h_s_cla16_pg_logic9_or0 out=h_s_cla16_and36
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.subckt and_gate a=h_s_cla16_pg_logic10_or0 b=h_s_cla16_pg_logic8_or0 out=h_s_cla16_and37
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.subckt and_gate a=h_s_cla16_and36 b=h_s_cla16_and37 out=h_s_cla16_and38
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.subckt and_gate a=h_s_cla16_pg_logic8_and0 b=h_s_cla16_pg_logic10_or0 out=h_s_cla16_and39
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.subckt and_gate a=h_s_cla16_and39 b=h_s_cla16_pg_logic9_or0 out=h_s_cla16_and40
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.subckt and_gate a=h_s_cla16_pg_logic9_and0 b=h_s_cla16_pg_logic10_or0 out=h_s_cla16_and41
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.subckt or_gate a=h_s_cla16_and38 b=h_s_cla16_and40 out=h_s_cla16_or19
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.subckt or_gate a=h_s_cla16_or19 b=h_s_cla16_and41 out=h_s_cla16_or20
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.subckt or_gate a=h_s_cla16_pg_logic10_and0 b=h_s_cla16_or20 out=h_s_cla16_or21
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.subckt pg_logic a=a[11] b=b[11] pg_logic_or0=h_s_cla16_pg_logic11_or0 pg_logic_and0=h_s_cla16_pg_logic11_and0 pg_logic_xor0=h_s_cla16_pg_logic11_xor0
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.subckt xor_gate a=h_s_cla16_pg_logic11_xor0 b=h_s_cla16_or21 out=h_s_cla16_xor11
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.subckt and_gate a=h_s_cla16_or15 b=h_s_cla16_pg_logic10_or0 out=h_s_cla16_and42
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.subckt and_gate a=h_s_cla16_pg_logic11_or0 b=h_s_cla16_pg_logic9_or0 out=h_s_cla16_and43
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.subckt and_gate a=h_s_cla16_and42 b=h_s_cla16_and43 out=h_s_cla16_and44
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.subckt and_gate a=h_s_cla16_and44 b=h_s_cla16_pg_logic8_or0 out=h_s_cla16_and45
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.subckt and_gate a=h_s_cla16_pg_logic8_and0 b=h_s_cla16_pg_logic10_or0 out=h_s_cla16_and46
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.subckt and_gate a=h_s_cla16_pg_logic11_or0 b=h_s_cla16_pg_logic9_or0 out=h_s_cla16_and47
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.subckt and_gate a=h_s_cla16_and46 b=h_s_cla16_and47 out=h_s_cla16_and48
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.subckt and_gate a=h_s_cla16_pg_logic9_and0 b=h_s_cla16_pg_logic11_or0 out=h_s_cla16_and49
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.subckt and_gate a=h_s_cla16_and49 b=h_s_cla16_pg_logic10_or0 out=h_s_cla16_and50
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.subckt and_gate a=h_s_cla16_pg_logic10_and0 b=h_s_cla16_pg_logic11_or0 out=h_s_cla16_and51
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.subckt or_gate a=h_s_cla16_and45 b=h_s_cla16_and50 out=h_s_cla16_or22
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.subckt or_gate a=h_s_cla16_and48 b=h_s_cla16_and51 out=h_s_cla16_or23
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.subckt or_gate a=h_s_cla16_or22 b=h_s_cla16_or23 out=h_s_cla16_or24
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.subckt or_gate a=h_s_cla16_pg_logic11_and0 b=h_s_cla16_or24 out=h_s_cla16_or25
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.subckt pg_logic a=a[12] b=b[12] pg_logic_or0=h_s_cla16_pg_logic12_or0 pg_logic_and0=h_s_cla16_pg_logic12_and0 pg_logic_xor0=h_s_cla16_pg_logic12_xor0
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.subckt xor_gate a=h_s_cla16_pg_logic12_xor0 b=h_s_cla16_or25 out=h_s_cla16_xor12
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.subckt and_gate a=h_s_cla16_or25 b=h_s_cla16_pg_logic12_or0 out=h_s_cla16_and52
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.subckt or_gate a=h_s_cla16_pg_logic12_and0 b=h_s_cla16_and52 out=h_s_cla16_or26
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.subckt pg_logic a=a[13] b=b[13] pg_logic_or0=h_s_cla16_pg_logic13_or0 pg_logic_and0=h_s_cla16_pg_logic13_and0 pg_logic_xor0=h_s_cla16_pg_logic13_xor0
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.subckt xor_gate a=h_s_cla16_pg_logic13_xor0 b=h_s_cla16_or26 out=h_s_cla16_xor13
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.subckt and_gate a=h_s_cla16_or25 b=h_s_cla16_pg_logic13_or0 out=h_s_cla16_and53
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.subckt and_gate a=h_s_cla16_and53 b=h_s_cla16_pg_logic12_or0 out=h_s_cla16_and54
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.subckt and_gate a=h_s_cla16_pg_logic12_and0 b=h_s_cla16_pg_logic13_or0 out=h_s_cla16_and55
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.subckt or_gate a=h_s_cla16_and54 b=h_s_cla16_and55 out=h_s_cla16_or27
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.subckt or_gate a=h_s_cla16_pg_logic13_and0 b=h_s_cla16_or27 out=h_s_cla16_or28
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.subckt pg_logic a=a[14] b=b[14] pg_logic_or0=h_s_cla16_pg_logic14_or0 pg_logic_and0=h_s_cla16_pg_logic14_and0 pg_logic_xor0=h_s_cla16_pg_logic14_xor0
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.subckt xor_gate a=h_s_cla16_pg_logic14_xor0 b=h_s_cla16_or28 out=h_s_cla16_xor14
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.subckt and_gate a=h_s_cla16_or25 b=h_s_cla16_pg_logic13_or0 out=h_s_cla16_and56
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.subckt and_gate a=h_s_cla16_pg_logic14_or0 b=h_s_cla16_pg_logic12_or0 out=h_s_cla16_and57
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.subckt and_gate a=h_s_cla16_and56 b=h_s_cla16_and57 out=h_s_cla16_and58
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.subckt and_gate a=h_s_cla16_pg_logic12_and0 b=h_s_cla16_pg_logic14_or0 out=h_s_cla16_and59
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.subckt and_gate a=h_s_cla16_and59 b=h_s_cla16_pg_logic13_or0 out=h_s_cla16_and60
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.subckt and_gate a=h_s_cla16_pg_logic13_and0 b=h_s_cla16_pg_logic14_or0 out=h_s_cla16_and61
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.subckt or_gate a=h_s_cla16_and58 b=h_s_cla16_and60 out=h_s_cla16_or29
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.subckt or_gate a=h_s_cla16_or29 b=h_s_cla16_and61 out=h_s_cla16_or30
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.subckt or_gate a=h_s_cla16_pg_logic14_and0 b=h_s_cla16_or30 out=h_s_cla16_or31
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.subckt pg_logic a=a[15] b=b[15] pg_logic_or0=h_s_cla16_pg_logic15_or0 pg_logic_and0=h_s_cla16_pg_logic15_and0 pg_logic_xor0=h_s_cla16_pg_logic15_xor0
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.subckt xor_gate a=h_s_cla16_pg_logic15_xor0 b=h_s_cla16_or31 out=h_s_cla16_xor15
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.subckt and_gate a=h_s_cla16_or25 b=h_s_cla16_pg_logic14_or0 out=h_s_cla16_and62
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.subckt and_gate a=h_s_cla16_pg_logic15_or0 b=h_s_cla16_pg_logic13_or0 out=h_s_cla16_and63
|
|
.subckt and_gate a=h_s_cla16_and62 b=h_s_cla16_and63 out=h_s_cla16_and64
|
|
.subckt and_gate a=h_s_cla16_and64 b=h_s_cla16_pg_logic12_or0 out=h_s_cla16_and65
|
|
.subckt and_gate a=h_s_cla16_pg_logic12_and0 b=h_s_cla16_pg_logic14_or0 out=h_s_cla16_and66
|
|
.subckt and_gate a=h_s_cla16_pg_logic15_or0 b=h_s_cla16_pg_logic13_or0 out=h_s_cla16_and67
|
|
.subckt and_gate a=h_s_cla16_and66 b=h_s_cla16_and67 out=h_s_cla16_and68
|
|
.subckt and_gate a=h_s_cla16_pg_logic13_and0 b=h_s_cla16_pg_logic15_or0 out=h_s_cla16_and69
|
|
.subckt and_gate a=h_s_cla16_and69 b=h_s_cla16_pg_logic14_or0 out=h_s_cla16_and70
|
|
.subckt and_gate a=h_s_cla16_pg_logic14_and0 b=h_s_cla16_pg_logic15_or0 out=h_s_cla16_and71
|
|
.subckt or_gate a=h_s_cla16_and65 b=h_s_cla16_and70 out=h_s_cla16_or32
|
|
.subckt or_gate a=h_s_cla16_and68 b=h_s_cla16_and71 out=h_s_cla16_or33
|
|
.subckt or_gate a=h_s_cla16_or32 b=h_s_cla16_or33 out=h_s_cla16_or34
|
|
.subckt or_gate a=h_s_cla16_pg_logic15_and0 b=h_s_cla16_or34 out=h_s_cla16_or35
|
|
.subckt xor_gate a=a[15] b=b[15] out=h_s_cla16_xor16
|
|
.subckt xor_gate a=h_s_cla16_xor16 b=h_s_cla16_or35 out=h_s_cla16_xor17
|
|
.names h_s_cla16_pg_logic0_xor0 h_s_cla16_out[0]
|
|
1 1
|
|
.names h_s_cla16_xor1 h_s_cla16_out[1]
|
|
1 1
|
|
.names h_s_cla16_xor2 h_s_cla16_out[2]
|
|
1 1
|
|
.names h_s_cla16_xor3 h_s_cla16_out[3]
|
|
1 1
|
|
.names h_s_cla16_xor4 h_s_cla16_out[4]
|
|
1 1
|
|
.names h_s_cla16_xor5 h_s_cla16_out[5]
|
|
1 1
|
|
.names h_s_cla16_xor6 h_s_cla16_out[6]
|
|
1 1
|
|
.names h_s_cla16_xor7 h_s_cla16_out[7]
|
|
1 1
|
|
.names h_s_cla16_xor8 h_s_cla16_out[8]
|
|
1 1
|
|
.names h_s_cla16_xor9 h_s_cla16_out[9]
|
|
1 1
|
|
.names h_s_cla16_xor10 h_s_cla16_out[10]
|
|
1 1
|
|
.names h_s_cla16_xor11 h_s_cla16_out[11]
|
|
1 1
|
|
.names h_s_cla16_xor12 h_s_cla16_out[12]
|
|
1 1
|
|
.names h_s_cla16_xor13 h_s_cla16_out[13]
|
|
1 1
|
|
.names h_s_cla16_xor14 h_s_cla16_out[14]
|
|
1 1
|
|
.names h_s_cla16_xor15 h_s_cla16_out[15]
|
|
1 1
|
|
.names h_s_cla16_xor17 h_s_cla16_out[16]
|
|
1 1
|
|
.end
|
|
|
|
.model pg_logic
|
|
.inputs a b
|
|
.outputs pg_logic_or0 pg_logic_and0 pg_logic_xor0
|
|
.names vdd
|
|
1
|
|
.names gnd
|
|
0
|
|
.subckt or_gate a=a b=b out=pg_logic_or0
|
|
.subckt and_gate a=a b=b out=pg_logic_and0
|
|
.subckt xor_gate a=a b=b out=pg_logic_xor0
|
|
.end
|
|
|
|
.model xor_gate
|
|
.inputs a b
|
|
.outputs out
|
|
.names vdd
|
|
1
|
|
.names gnd
|
|
0
|
|
.names a b out
|
|
01 1
|
|
10 1
|
|
.end
|
|
|
|
.model and_gate
|
|
.inputs a b
|
|
.outputs out
|
|
.names vdd
|
|
1
|
|
.names gnd
|
|
0
|
|
.names a b out
|
|
11 1
|
|
.end
|
|
|
|
.model or_gate
|
|
.inputs a b
|
|
.outputs out
|
|
.names vdd
|
|
1
|
|
.names gnd
|
|
0
|
|
.names a b out
|
|
1- 1
|
|
-1 1
|
|
.end
|