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91 lines
2.9 KiB
Plaintext
91 lines
2.9 KiB
Plaintext
.model u_cla4
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.inputs a[0] a[1] a[2] a[3] b[0] b[1] b[2] b[3]
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.outputs u_cla4_out[0] u_cla4_out[1] u_cla4_out[2] u_cla4_out[3] u_cla4_out[4]
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.names vdd
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1
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.names gnd
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0
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.subckt pg_logic a=a[0] b=b[0] pg_logic_or0=u_cla4_pg_logic0_or0 pg_logic_and0=u_cla4_pg_logic0_and0 pg_logic_xor0=u_cla4_pg_logic0_xor0
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.subckt pg_logic a=a[1] b=b[1] pg_logic_or0=u_cla4_pg_logic1_or0 pg_logic_and0=u_cla4_pg_logic1_and0 pg_logic_xor0=u_cla4_pg_logic1_xor0
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.subckt xor_gate a=u_cla4_pg_logic1_xor0 b=u_cla4_pg_logic0_and0 out=u_cla4_xor1
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.subckt and_gate a=u_cla4_pg_logic0_and0 b=u_cla4_pg_logic1_or0 out=u_cla4_and0
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.subckt or_gate a=u_cla4_pg_logic1_and0 b=u_cla4_and0 out=u_cla4_or0
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.subckt pg_logic a=a[2] b=b[2] pg_logic_or0=u_cla4_pg_logic2_or0 pg_logic_and0=u_cla4_pg_logic2_and0 pg_logic_xor0=u_cla4_pg_logic2_xor0
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.subckt xor_gate a=u_cla4_pg_logic2_xor0 b=u_cla4_or0 out=u_cla4_xor2
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.subckt and_gate a=u_cla4_pg_logic2_or0 b=u_cla4_pg_logic0_or0 out=u_cla4_and1
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.subckt and_gate a=u_cla4_pg_logic0_and0 b=u_cla4_pg_logic2_or0 out=u_cla4_and2
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.subckt and_gate a=u_cla4_and2 b=u_cla4_pg_logic1_or0 out=u_cla4_and3
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.subckt and_gate a=u_cla4_pg_logic1_and0 b=u_cla4_pg_logic2_or0 out=u_cla4_and4
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.subckt or_gate a=u_cla4_and3 b=u_cla4_and4 out=u_cla4_or1
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.subckt or_gate a=u_cla4_pg_logic2_and0 b=u_cla4_or1 out=u_cla4_or2
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.subckt pg_logic a=a[3] b=b[3] pg_logic_or0=u_cla4_pg_logic3_or0 pg_logic_and0=u_cla4_pg_logic3_and0 pg_logic_xor0=u_cla4_pg_logic3_xor0
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.subckt xor_gate a=u_cla4_pg_logic3_xor0 b=u_cla4_or2 out=u_cla4_xor3
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.subckt and_gate a=u_cla4_pg_logic3_or0 b=u_cla4_pg_logic1_or0 out=u_cla4_and5
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.subckt and_gate a=u_cla4_pg_logic0_and0 b=u_cla4_pg_logic2_or0 out=u_cla4_and6
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.subckt and_gate a=u_cla4_pg_logic3_or0 b=u_cla4_pg_logic1_or0 out=u_cla4_and7
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.subckt and_gate a=u_cla4_and6 b=u_cla4_and7 out=u_cla4_and8
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.subckt and_gate a=u_cla4_pg_logic1_and0 b=u_cla4_pg_logic3_or0 out=u_cla4_and9
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.subckt and_gate a=u_cla4_and9 b=u_cla4_pg_logic2_or0 out=u_cla4_and10
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.subckt and_gate a=u_cla4_pg_logic2_and0 b=u_cla4_pg_logic3_or0 out=u_cla4_and11
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.subckt or_gate a=u_cla4_and8 b=u_cla4_and11 out=u_cla4_or3
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.subckt or_gate a=u_cla4_and10 b=u_cla4_or3 out=u_cla4_or4
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.subckt or_gate a=u_cla4_pg_logic3_and0 b=u_cla4_or4 out=u_cla4_or5
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.names u_cla4_pg_logic0_xor0 u_cla4_out[0]
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1 1
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.names u_cla4_xor1 u_cla4_out[1]
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1 1
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.names u_cla4_xor2 u_cla4_out[2]
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1 1
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.names u_cla4_xor3 u_cla4_out[3]
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1 1
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.names u_cla4_or5 u_cla4_out[4]
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1 1
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.end
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.model pg_logic
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.inputs a b
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.outputs pg_logic_or0 pg_logic_and0 pg_logic_xor0
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.names vdd
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1
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.names gnd
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0
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.subckt or_gate a=a b=b out=pg_logic_or0
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.subckt and_gate a=a b=b out=pg_logic_and0
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.subckt xor_gate a=a b=b out=pg_logic_xor0
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.end
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.model xor_gate
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.inputs a b
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.outputs out
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.names vdd
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1
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.names gnd
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0
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.names a b out
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01 1
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10 1
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.end
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.model and_gate
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.inputs a b
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.outputs out
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.names vdd
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1
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.names gnd
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0
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.names a b out
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11 1
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.end
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.model or_gate
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.inputs a b
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.outputs out
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.names vdd
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1
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.names gnd
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0
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.names a b out
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1- 1
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-1 1
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.end
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