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<article id="content">
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<header>
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<h1 class="title">Module <code>ariths_gen.wire_components.buses</code></h1>
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</header>
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<section id="section-intro">
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</section>
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<section>
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</section>
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<section>
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</section>
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<section>
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</section>
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<section>
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<h2 class="section-title" id="header-classes">Classes</h2>
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<dl>
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<dt id="ariths_gen.wire_components.buses.Bus"><code class="flex name class">
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<span>class <span class="ident">Bus</span></span>
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<span>(</span><span>prefix: str = 'bus', N: int = 1, wires_list: list = None, out_bus: bool = False, signed: bool = False)</span>
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</code></dt>
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<dd>
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<div class="desc"><p>Class representing bus of wires used as inputs/outputs of bigger circuits.</p>
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<p>Description of the <strong>init</strong> method.</p>
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<h2 id="args">Args</h2>
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<dl>
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<dt><strong><code>prefix</code></strong> : <code>str</code>, optional</dt>
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<dd>Prefix name of the bus. Defaults to "bus".</dd>
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<dt><strong><code>N</code></strong> : <code>int</code>, optional</dt>
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<dd>Number of wires in the bus. Defaults to 1.</dd>
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<dt><strong><code>wires_list</code></strong> : <code>list</code>, optional</dt>
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<dd>List of Wire objects used to clone one bus to another. Defaults to None.</dd>
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<dt><strong><code>out_bus</code></strong> : <code>bool</code>, optional</dt>
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<dd>Specifies whether this Bus is an output bus of some previous component. Defaults to False.</dd>
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<dt><strong><code>signed</code></strong> : <code>bool</code>, optional</dt>
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<dd>Specifies whether this Bus should consider signed numbers or not (used for C code generation). Defaults to False.</dd>
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</dl></div>
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<details class="source">
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<summary>
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<span>Expand source code</span>
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</summary>
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<pre><code class="python">class Bus():
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"""Class representing bus of wires used as inputs/outputs of bigger circuits.
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Description of the __init__ method.
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Args:
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prefix (str, optional): Prefix name of the bus. Defaults to "bus".
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N (int, optional): Number of wires in the bus. Defaults to 1.
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wires_list (list, optional): List of Wire objects used to clone one bus to another. Defaults to None.
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out_bus (bool, optional): Specifies whether this Bus is an output bus of some previous component. Defaults to False.
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signed (bool, optional): Specifies whether this Bus should consider signed numbers or not (used for C code generation). Defaults to False.
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"""
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def __init__(self, prefix: str = "bus", N: int = 1, wires_list: list = None, out_bus: bool = False, signed: bool = False):
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self.out_bus = out_bus
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if wires_list is None:
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self.prefix = prefix
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# Adding wires into current bus's wires list (wire names are concatenated from bus prefix and their index position inside the bus in square brackets)
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self.bus = [Wire(name=prefix+f"[{i}]" if N != 1 else prefix, prefix=prefix, index=i, parent_bus=self) for i in range(N)]
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self.N = N
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else:
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self.prefix = prefix
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self.bus = wires_list
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self.N = len(self.bus)
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# Determine C code signedness
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self.signed = signed
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if self.N > 8:
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self.c_var_size = 64
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if signed is True:
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self.c_type = "int64_t"
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else:
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self.c_type = "uint64_t"
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else:
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self.c_var_size = 8
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if signed is True:
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self.c_type = "int8_t"
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else:
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self.c_type = "uint8_t"
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def is_output_bus(self):
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"""Tells whether this Bus is an output bus.
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Returns:
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bool: Returns True if it is an output bus of some component.
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"""
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return self.out_bus
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def bus_extend(self, N: int, prefix: str = "bus", desired_extension_wire: Wire = ConstantWireValue0()):
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"""Provides bus extension to contain more wires.
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Args:
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N (int): Number of wires in the bus. Defaults to 1.
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prefix (str, optional): Prefix name of the bus. Defaults to "bus".
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desired_extension_wire (Wire, optional): Specifies the wire that should be connected to all of the extending bus wires. Defaults to ConstantWireValue0().
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"""
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# Checks if any extension is neccesarry and if so, proceeds to wire extend the bus
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if self.N < N:
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# Adding wires into current bus's wires list (wire names are concatenated from bus prefix and their index position inside the bus in square brackets)
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self.bus += [Wire(name=prefix+f"[{i}]", prefix=prefix, index=i, parent_bus=self) for i in range(self.N, N)]
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for w_index in range(self.N, N):
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self.connect(bus_wire_index=w_index, inner_component_out_wire=desired_extension_wire)
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self.N = N
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def get_wire(self, wire_index: int = 0):
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"""Retrieves a wire from the bus by a given index.
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Args:
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wire_index (int, optional): Index of wire to be retrieved from the bus. Defaults to 0.
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Returns:
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Wire: Returning wire from the bus.
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"""
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assert wire_index < self.N, f"Wire index {wire_index} is out of bounds of the bus {self.prefix} with size {self.N}"
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return self.bus[wire_index]
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def __getitem__(self, i):
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return self.get_wire(i)
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# Connecting output wire of the inner circuit component to desired position in the described circuit's output bus
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def connect(self, bus_wire_index: int, inner_component_out_wire: Wire, inserted_wire_desired_index: int = -1):
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"""Connects given 'Wire' object to a 'bus_wire_index' within this bus.
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Used for connection of output wire of the inner circuit component
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to the appropriate wire of the circuit's output bus.
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Args:
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bus_wire_index (int): Index in bus to store given wire in.
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inner_component_out_wire (Wire): Wire of some other component (mostly its output) to store in the bus.
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inserted_wire_desired_index(int, optional): Optional desired explicit index, where 'inner_component_out_wire' value resides in the inner components's output bus. Otherwise 'inner_component_out_wire' self index value is used. Defaults to -1.
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"""
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inserted_wire_index = inserted_wire_desired_index if inserted_wire_desired_index != -1 else inner_component_out_wire.index
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# Used for connection of constant wire value into a bus
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if inner_component_out_wire.is_const():
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self.bus[bus_wire_index] = inner_component_out_wire
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# Proper connection of wires that themselves are not yet a member of any other bus and also those that could be part of some bus but do not have `inserted_wire_desired_index` defined
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elif inner_component_out_wire.parent_bus is None or inserted_wire_desired_index == -1:
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self.bus[bus_wire_index] = Wire(name=inner_component_out_wire.name, prefix=inner_component_out_wire.prefix, index=inserted_wire_index, value=inner_component_out_wire.value, parent_bus=self)
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# Proper connection of wires that are already a member of some other bus and are desired to connect value from their previous bus to this one at desired index position
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elif inserted_wire_desired_index != -1:
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self.bus[bus_wire_index] = Wire(name=inner_component_out_wire.name, prefix=inner_component_out_wire.parent_bus.prefix, index=inserted_wire_index, value=inner_component_out_wire.value, parent_bus=self)
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def __setitem__(self, i, v):
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self.connect(i, v)
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def connect_bus(self, connecting_bus: object, start_connection_pos: int = 0, end_connection_pos: int = -1, offset: int = 0):
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"""Ensures connection of specified bus wires to this bus wires.
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Used for connection of some inner circuit component's output bus (`connecting_bus`) wires
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to the appropriate input bus (this `self` bus) wires of some other circuit.
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Args:
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connecting_bus (object): Specifies the connecting bus.
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start_connection_pos (int, optional): Specifies the position from which to start interconnecting wires from the `connecting_bus` to this `self` bus. Defaults to 0.
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end_connection_pos (int, optional): Specifies the position from which to end interconnecting wires from the `connecting_bus` to this `self` bus. Defaults to -1.
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offset (int, optional): Specifies the offset wire index position in the `self` bus for proper connection (i.e. wire at index position 5 in the `connecting_bus` with offset set to 5 will be connected to `self` bus index position 0). Default to 0.
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"""
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if end_connection_pos == -1:
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end_connection_pos = self.N
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[self.connect(o-offset, connecting_bus.get_wire(o), inserted_wire_desired_index=o) for o in range(start_connection_pos, end_connection_pos)]
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""" PYTHON CODE GENERATION """
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def return_bus_wires_values_python_flat(self):
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"""Retrieves values from bus's wires and stores them in bus's corresponding Python variable (object) at proper offset bit position in the bus for flat generation.
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Returns:
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str: Python code for assigning wire values into bus represented in Python code variable.
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"""
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# Ensures correct binding between the bus wire index and the wire itself
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# It is used for the case when multiple of the same wire (e.g. `ContantWireValue0()`) are present in the bus (its id would otherwise be incorrect when using `self.bus.index(_)`)
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mapped_positions = [(w_id, self.bus[w_id]) for w_id in range(self.N)]
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return "".join([f" {self.prefix} = 0\n"] + [f" {self.prefix} = ({self.prefix}) | {w[1].return_wire_value_python_flat(offset=w[0])}" for w in mapped_positions])
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def return_bus_wires_sign_extend_python_flat(self, retype: bool = False):
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"""Sign extends the bus's corresponding Python variable (object) to ensure proper flat Python code variable signedness.
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Returns:
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str: Python code for sign extending the bus variable wire values.
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"""
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if self.signed is True:
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last_bus_wire = self.bus[-1]
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assert self.N < 64, "Sign extension is not supported for bus with more than 64 bits"
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if retype:
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rewrite = f"""
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if hasattr({self.prefix}, 'astype'):
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{self.prefix} = {self.prefix}.astype("int64")
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else:
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from ctypes import c_int64
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{self.prefix} = c_int64({self.prefix}).value\n"""
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else:
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rewrite = ""
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return "".join([f" {self.prefix} = ({self.prefix}) | {last_bus_wire.return_wire_value_python_flat(offset=i)}" for i in range(len(self.bus), 64)]) + rewrite
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else:
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return ""
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def __str__(self):
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return f"<wire N={self.N} prefix={self.prefix} \"" + (",".join([str(w) for w in self.bus])) + "\">"
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""" C CODE GENERATION """
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def get_declaration_c(self):
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"""Bus declaration in C code.
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Returns:
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str: C code for declaration and initialization of bus name.
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"""
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return f" {self.c_type} {self.prefix} = 0;\n"
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def return_bus_wires_values_c_flat(self):
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"""Retrieves values from bus's wires and stores them in bus's corresponding C variable at proper offset bit position in the bus for flat generation.
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Returns:
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str: C code for assigning wire values into bus represented in C code variable.
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"""
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# Ensures correct binding between the bus wire index and the wire itself
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# It is used for the case when multiple of the same wire (e.g. `ContantWireValue0()`) are present in the bus (its id would otherwise be incorrect when using `self.bus.index(_)`)
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mapped_positions = [(w_id, self.bus[w_id]) for w_id in range(self.N)]
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return "".join([f" {self.prefix} |= {w[1].return_wire_value_c_flat(offset=w[0])}" for w in mapped_positions])
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def return_bus_wires_values_c_hier(self):
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"""Retrieves values from bus's wires and stores them in bus's corresponding C variable at proper offset bit position in the bus for hierarchical generation.
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Returns:
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str: C code for assigning wire values into bus represented in C code variable.
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"""
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# Ensures correct binding between the bus wire index and the wire itself
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# It is used for the case when multiple of the same wire (e.g. `ContantWireValue0()`) are present in the bus (its id would otherwise be incorrect when using `self.bus.index(_)`)
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mapped_positions = [(w_id, w) for w_id, w in enumerate(self.bus) if ((w.parent_bus is None) or (w.parent_bus is not None and w.prefix != self.prefix) or (w.is_const()))]
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return "".join([f" {self.prefix} |= {w[1].return_wire_value_c_hier(offset=w[0])}" for w in mapped_positions])
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def return_bus_wires_sign_extend_c_flat(self):
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"""Sign extends the bus's corresponding C variable to ensure proper flat C code variable signedness.
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Returns:
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str: C code for sign extending the bus variable wire values.
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"""
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if self.signed is True:
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last_bus_wire = self.bus[-1]
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return "".join([f" {self.prefix} |= {last_bus_wire.return_wire_value_c_flat(offset=i)}" for i in range(len(self.bus), self.c_var_size)])
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else:
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return ""
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def return_bus_wires_sign_extend_c_hier(self):
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"""Sign extends the bus's corresponding C variable to ensure proper hier C code variable signedness.
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Returns:
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str: C code for sign extending the bus variable wire values.
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"""
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if self.signed is True:
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last_bus_wire = self.bus[-1]
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return "".join([f" {self.prefix} |= {last_bus_wire.return_wire_value_c_hier(offset=i)}" for i in range(len(self.bus), self.c_var_size)])
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else:
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return ""
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""" VERILOG CODE GENERATION """
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def return_bus_wires_values_v_flat(self):
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"""Retrieves values from bus's wires and stores them in bus's corresponding Verilog variable at proper offset bit position in the bus for flat generation.
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Returns:
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str: Verilog code for assigning wire values into bus represented in Verilog code bus variable.
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"""
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# Ensures correct binding between the bus wire index and the wire itself
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# It is used for the case when multiple of the same wire (e.g. `ContantWireValue0()`) are present in the bus (its id would otherwise be incorrect when using `self.bus.index(_)`)
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mapped_positions = [(w_id, self.bus[w_id]) for w_id in range(self.N)]
|
||
return "".join([f" assign {self.prefix}[{w[0]}] = {w[1].return_wire_value_v_flat()}" for w in mapped_positions])
|
||
|
||
def return_bus_wires_values_v_hier(self):
|
||
"""Retrieves values from bus's wires and stores them in bus's corresponding Verilog variable at proper offset bit position in the bus for hierarchical generation.
|
||
|
||
Returns:
|
||
str: Verilog code for assigning wire values into bus represented in Verilog code variable.
|
||
"""
|
||
# Ensures correct binding between the bus wire index and the wire itself
|
||
# It is used for the case when multiple of the same wire (e.g. `ContantWireValue0()`) are present in the bus (its id would otherwise be incorrect when using `self.bus.index(_)`)
|
||
mapped_positions = [(w_id, w) for w_id, w in enumerate(self.bus) if ((w.parent_bus is None) or (w.parent_bus is not None and w.prefix != self.prefix) or (w.is_const()))]
|
||
return "".join([f" assign {self.prefix}[{w[0]}] = {w[1].return_wire_value_v_hier()}" for w in mapped_positions])
|
||
|
||
def get_unique_assign_out_wires_v(self, circuit_block: object):
|
||
"""Returns bus's wires used for hierarchical one bit subcomponent's function block invocation and output wires assignments.
|
||
|
||
Args:
|
||
circuit_block (object): Object describing corresponding function block that is being invoked for proper output wires assignment during instantiation.
|
||
|
||
Returns:
|
||
str: Verilog code unique bus wires for proper subcomponent's function block invocation.
|
||
"""
|
||
unique_out_wires = []
|
||
[unique_out_wires.append(w.prefix) if w.prefix not in unique_out_wires else None for w in self.bus]
|
||
return "".join([f", .{circuit_block.out.get_wire(self.bus.index(o)).prefix}({unique_out_wires.pop(unique_out_wires.index(o.prefix))})" if o.prefix in unique_out_wires else f", .{circuit_block.out.get_wire(self.bus.index(o)).prefix}()" for o in self.bus])
|
||
|
||
def get_wire_declaration_v(self):
|
||
"""Declare the wire in Verilog code representation.
|
||
|
||
Returns:
|
||
str: Verilog code for declaration of individual bus wires.
|
||
"""
|
||
return f" wire [{self.N-1}:0] {self.prefix};\n"
|
||
|
||
""" BLIF CODE GENERATION """
|
||
def get_wire_declaration_blif(self):
|
||
"""Declare each wire from the bus independently in Blif code representation.
|
||
|
||
Returns:
|
||
str: Blif code for declaration of individual bus wires.
|
||
"""
|
||
# Ensures correct binding between the bus wire index and the wire itself
|
||
# It is used for the case when multiple of the same wire (e.g. `ContantWireValue0()`) are present in the bus (its id would otherwise be incorrect when using `self.bus.index(_)`)
|
||
mapped_positions = [(w_id, self.bus[w_id]) for w_id in range(self.N)]
|
||
array = True if self.N > 1 else False
|
||
return "".join([f" {w[1].get_declaration_blif(prefix=self.prefix, offset=w[0], array=array)}" for w in mapped_positions])
|
||
|
||
def get_wire_assign_blif(self, output: bool = False):
|
||
"""Assign all bits from the bus as each individual wires or assign wires into the corresponding output bus position in Blif code representation.
|
||
|
||
Args:
|
||
output (bool, optional): Specifies whether bus wires are used as outputs (True, assigned to) or as inputs (False, assigned from). Defaults to False.
|
||
|
||
Returns:
|
||
str: Blif code for bus wires assignments.
|
||
"""
|
||
# Ensures correct binding between the bus wire index and the wire itself
|
||
# It is used for the case when multiple of the same wire (e.g. `ContantWireValue0()`) are present in the bus (its id would otherwise be incorrect when using `self.bus.index(_)`)
|
||
mapped_positions = [(w_id, self.bus[w_id]) for w_id in range(self.N)]
|
||
if self.N > 1:
|
||
return "".join([w[1].get_assign_blif(prefix=self.prefix+f"[{w[0]}]", output=output) for w in mapped_positions])
|
||
else:
|
||
return "".join([w[1].get_assign_blif(prefix=self.prefix, output=output) for w in mapped_positions])
|
||
|
||
def get_unique_assign_out_wires_blif(self, function_block_out_bus: object):
|
||
"""Assigns unique output wires to their respective outputs of subcomponent's function block modul in hierarchical Blif subcomponent's invocation.
|
||
|
||
Args:
|
||
function_block_out_bus (object): Specifies output bus of corresponding function block's outputs for proper subcomponent modul invocation.
|
||
|
||
Returns:
|
||
str: Blif code for proper subcomponent's function block invocation with respective output wires assignment.
|
||
"""
|
||
unique_out_wires = []
|
||
[unique_out_wires.append(w.prefix) if w.prefix not in unique_out_wires else None for w in self.bus]
|
||
return "".join([f" {function_block_out_bus.get_wire(self.bus.index(o)).name}={unique_out_wires.pop(unique_out_wires.index(o.prefix))}" if o.prefix in unique_out_wires else "" for o in self.bus])</code></pre>
|
||
</details>
|
||
<h3>Methods</h3>
|
||
<dl>
|
||
<dt id="ariths_gen.wire_components.buses.Bus.bus_extend"><code class="name flex">
|
||
<span>def <span class="ident">bus_extend</span></span>(<span>self, N: int, prefix: str = 'bus', desired_extension_wire: <a title="ariths_gen.wire_components.wires.Wire" href="wires.html#ariths_gen.wire_components.wires.Wire">Wire</a> = <ariths_gen.wire_components.wires.ConstantWireValue0 object>)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Provides bus extension to contain more wires.</p>
|
||
<h2 id="args">Args</h2>
|
||
<dl>
|
||
<dt><strong><code>N</code></strong> : <code>int</code></dt>
|
||
<dd>Number of wires in the bus. Defaults to 1.</dd>
|
||
<dt><strong><code>prefix</code></strong> : <code>str</code>, optional</dt>
|
||
<dd>Prefix name of the bus. Defaults to "bus".</dd>
|
||
<dt><strong><code>desired_extension_wire</code></strong> : <code>Wire</code>, optional</dt>
|
||
<dd>Specifies the wire that should be connected to all of the extending bus wires. Defaults to ConstantWireValue0().</dd>
|
||
</dl></div>
|
||
</dd>
|
||
<dt id="ariths_gen.wire_components.buses.Bus.connect"><code class="name flex">
|
||
<span>def <span class="ident">connect</span></span>(<span>self, bus_wire_index: int, inner_component_out_wire: <a title="ariths_gen.wire_components.wires.Wire" href="wires.html#ariths_gen.wire_components.wires.Wire">Wire</a>, inserted_wire_desired_index: int = -1)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Connects given 'Wire' object to a 'bus_wire_index' within this bus.</p>
|
||
<p>Used for connection of output wire of the inner circuit component
|
||
to the appropriate wire of the circuit's output bus.</p>
|
||
<h2 id="args">Args</h2>
|
||
<dl>
|
||
<dt><strong><code>bus_wire_index</code></strong> : <code>int</code></dt>
|
||
<dd>Index in bus to store given wire in.</dd>
|
||
<dt><strong><code>inner_component_out_wire</code></strong> : <code>Wire</code></dt>
|
||
<dd>Wire of some other component (mostly its output) to store in the bus.</dd>
|
||
</dl>
|
||
<p>inserted_wire_desired_index(int, optional): Optional desired explicit index, where 'inner_component_out_wire' value resides in the inner components's output bus. Otherwise 'inner_component_out_wire' self index value is used. Defaults to -1.</p></div>
|
||
</dd>
|
||
<dt id="ariths_gen.wire_components.buses.Bus.connect_bus"><code class="name flex">
|
||
<span>def <span class="ident">connect_bus</span></span>(<span>self, connecting_bus: object, start_connection_pos: int = 0, end_connection_pos: int = -1, offset: int = 0)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Ensures connection of specified bus wires to this bus wires.</p>
|
||
<p>Used for connection of some inner circuit component's output bus (<code>connecting_bus</code>) wires
|
||
to the appropriate input bus (this <code>self</code> bus) wires of some other circuit.</p>
|
||
<h2 id="args">Args</h2>
|
||
<dl>
|
||
<dt><strong><code>connecting_bus</code></strong> : <code>object</code></dt>
|
||
<dd>Specifies the connecting bus.</dd>
|
||
<dt><strong><code>start_connection_pos</code></strong> : <code>int</code>, optional</dt>
|
||
<dd>Specifies the position from which to start interconnecting wires from the <code>connecting_bus</code> to this <code>self</code> bus. Defaults to 0.</dd>
|
||
<dt><strong><code>end_connection_pos</code></strong> : <code>int</code>, optional</dt>
|
||
<dd>Specifies the position from which to end interconnecting wires from the <code>connecting_bus</code> to this <code>self</code> bus. Defaults to -1.</dd>
|
||
<dt><strong><code>offset</code></strong> : <code>int</code>, optional</dt>
|
||
<dd>Specifies the offset wire index position in the <code>self</code> bus for proper connection (i.e. wire at index position 5 in the <code>connecting_bus</code> with offset set to 5 will be connected to <code>self</code> bus index position 0). Default to 0.</dd>
|
||
</dl></div>
|
||
</dd>
|
||
<dt id="ariths_gen.wire_components.buses.Bus.get_declaration_c"><code class="name flex">
|
||
<span>def <span class="ident">get_declaration_c</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Bus declaration in C code.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>C code for declaration and initialization of bus name.</dd>
|
||
</dl></div>
|
||
</dd>
|
||
<dt id="ariths_gen.wire_components.buses.Bus.get_unique_assign_out_wires_blif"><code class="name flex">
|
||
<span>def <span class="ident">get_unique_assign_out_wires_blif</span></span>(<span>self, function_block_out_bus: object)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Assigns unique output wires to their respective outputs of subcomponent's function block modul in hierarchical Blif subcomponent's invocation.</p>
|
||
<h2 id="args">Args</h2>
|
||
<dl>
|
||
<dt><strong><code>function_block_out_bus</code></strong> : <code>object</code></dt>
|
||
<dd>Specifies output bus of corresponding function block's outputs for proper subcomponent modul invocation.</dd>
|
||
</dl>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Blif code for proper subcomponent's function block invocation with respective output wires assignment.</dd>
|
||
</dl></div>
|
||
</dd>
|
||
<dt id="ariths_gen.wire_components.buses.Bus.get_unique_assign_out_wires_v"><code class="name flex">
|
||
<span>def <span class="ident">get_unique_assign_out_wires_v</span></span>(<span>self, circuit_block: object)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Returns bus's wires used for hierarchical one bit subcomponent's function block invocation and output wires assignments.</p>
|
||
<h2 id="args">Args</h2>
|
||
<dl>
|
||
<dt><strong><code>circuit_block</code></strong> : <code>object</code></dt>
|
||
<dd>Object describing corresponding function block that is being invoked for proper output wires assignment during instantiation.</dd>
|
||
</dl>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Verilog code unique bus wires for proper subcomponent's function block invocation.</dd>
|
||
</dl></div>
|
||
</dd>
|
||
<dt id="ariths_gen.wire_components.buses.Bus.get_wire"><code class="name flex">
|
||
<span>def <span class="ident">get_wire</span></span>(<span>self, wire_index: int = 0)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Retrieves a wire from the bus by a given index.</p>
|
||
<h2 id="args">Args</h2>
|
||
<dl>
|
||
<dt><strong><code>wire_index</code></strong> : <code>int</code>, optional</dt>
|
||
<dd>Index of wire to be retrieved from the bus. Defaults to 0.</dd>
|
||
</dl>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>Wire</code></dt>
|
||
<dd>Returning wire from the bus.</dd>
|
||
</dl></div>
|
||
</dd>
|
||
<dt id="ariths_gen.wire_components.buses.Bus.get_wire_assign_blif"><code class="name flex">
|
||
<span>def <span class="ident">get_wire_assign_blif</span></span>(<span>self, output: bool = False)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Assign all bits from the bus as each individual wires or assign wires into the corresponding output bus position in Blif code representation.</p>
|
||
<h2 id="args">Args</h2>
|
||
<dl>
|
||
<dt><strong><code>output</code></strong> : <code>bool</code>, optional</dt>
|
||
<dd>Specifies whether bus wires are used as outputs (True, assigned to) or as inputs (False, assigned from). Defaults to False.</dd>
|
||
</dl>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Blif code for bus wires assignments.</dd>
|
||
</dl></div>
|
||
</dd>
|
||
<dt id="ariths_gen.wire_components.buses.Bus.get_wire_declaration_blif"><code class="name flex">
|
||
<span>def <span class="ident">get_wire_declaration_blif</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Declare each wire from the bus independently in Blif code representation.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Blif code for declaration of individual bus wires.</dd>
|
||
</dl></div>
|
||
</dd>
|
||
<dt id="ariths_gen.wire_components.buses.Bus.get_wire_declaration_v"><code class="name flex">
|
||
<span>def <span class="ident">get_wire_declaration_v</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Declare the wire in Verilog code representation.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Verilog code for declaration of individual bus wires.</dd>
|
||
</dl></div>
|
||
</dd>
|
||
<dt id="ariths_gen.wire_components.buses.Bus.is_output_bus"><code class="name flex">
|
||
<span>def <span class="ident">is_output_bus</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Tells whether this Bus is an output bus.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>bool</code></dt>
|
||
<dd>Returns True if it is an output bus of some component.</dd>
|
||
</dl></div>
|
||
</dd>
|
||
<dt id="ariths_gen.wire_components.buses.Bus.return_bus_wires_sign_extend_c_flat"><code class="name flex">
|
||
<span>def <span class="ident">return_bus_wires_sign_extend_c_flat</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Sign extends the bus's corresponding C variable to ensure proper flat C code variable signedness.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>C code for sign extending the bus variable wire values.</dd>
|
||
</dl></div>
|
||
</dd>
|
||
<dt id="ariths_gen.wire_components.buses.Bus.return_bus_wires_sign_extend_c_hier"><code class="name flex">
|
||
<span>def <span class="ident">return_bus_wires_sign_extend_c_hier</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Sign extends the bus's corresponding C variable to ensure proper hier C code variable signedness.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>C code for sign extending the bus variable wire values.</dd>
|
||
</dl></div>
|
||
</dd>
|
||
<dt id="ariths_gen.wire_components.buses.Bus.return_bus_wires_sign_extend_python_flat"><code class="name flex">
|
||
<span>def <span class="ident">return_bus_wires_sign_extend_python_flat</span></span>(<span>self, retype: bool = False)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Sign extends the bus's corresponding Python variable (object) to ensure proper flat Python code variable signedness.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Python code for sign extending the bus variable wire values.</dd>
|
||
</dl></div>
|
||
</dd>
|
||
<dt id="ariths_gen.wire_components.buses.Bus.return_bus_wires_values_c_flat"><code class="name flex">
|
||
<span>def <span class="ident">return_bus_wires_values_c_flat</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Retrieves values from bus's wires and stores them in bus's corresponding C variable at proper offset bit position in the bus for flat generation.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>C code for assigning wire values into bus represented in C code variable.</dd>
|
||
</dl></div>
|
||
</dd>
|
||
<dt id="ariths_gen.wire_components.buses.Bus.return_bus_wires_values_c_hier"><code class="name flex">
|
||
<span>def <span class="ident">return_bus_wires_values_c_hier</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Retrieves values from bus's wires and stores them in bus's corresponding C variable at proper offset bit position in the bus for hierarchical generation.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>C code for assigning wire values into bus represented in C code variable.</dd>
|
||
</dl></div>
|
||
</dd>
|
||
<dt id="ariths_gen.wire_components.buses.Bus.return_bus_wires_values_python_flat"><code class="name flex">
|
||
<span>def <span class="ident">return_bus_wires_values_python_flat</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Retrieves values from bus's wires and stores them in bus's corresponding Python variable (object) at proper offset bit position in the bus for flat generation.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Python code for assigning wire values into bus represented in Python code variable.</dd>
|
||
</dl></div>
|
||
</dd>
|
||
<dt id="ariths_gen.wire_components.buses.Bus.return_bus_wires_values_v_flat"><code class="name flex">
|
||
<span>def <span class="ident">return_bus_wires_values_v_flat</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Retrieves values from bus's wires and stores them in bus's corresponding Verilog variable at proper offset bit position in the bus for flat generation.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Verilog code for assigning wire values into bus represented in Verilog code bus variable.</dd>
|
||
</dl></div>
|
||
</dd>
|
||
<dt id="ariths_gen.wire_components.buses.Bus.return_bus_wires_values_v_hier"><code class="name flex">
|
||
<span>def <span class="ident">return_bus_wires_values_v_hier</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Retrieves values from bus's wires and stores them in bus's corresponding Verilog variable at proper offset bit position in the bus for hierarchical generation.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Verilog code for assigning wire values into bus represented in Verilog code variable.</dd>
|
||
</dl></div>
|
||
</dd>
|
||
</dl>
|
||
</dd>
|
||
</dl>
|
||
</section>
|
||
</article>
|
||
<nav id="sidebar">
|
||
<div class="toc">
|
||
<ul></ul>
|
||
</div>
|
||
<ul id="index">
|
||
<li><h3>Super-module</h3>
|
||
<ul>
|
||
<li><code><a title="ariths_gen.wire_components" href="index.html">ariths_gen.wire_components</a></code></li>
|
||
</ul>
|
||
</li>
|
||
<li><h3><a href="#header-classes">Classes</a></h3>
|
||
<ul>
|
||
<li>
|
||
<h4><code><a title="ariths_gen.wire_components.buses.Bus" href="#ariths_gen.wire_components.buses.Bus">Bus</a></code></h4>
|
||
<ul class="">
|
||
<li><code><a title="ariths_gen.wire_components.buses.Bus.bus_extend" href="#ariths_gen.wire_components.buses.Bus.bus_extend">bus_extend</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.buses.Bus.connect" href="#ariths_gen.wire_components.buses.Bus.connect">connect</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.buses.Bus.connect_bus" href="#ariths_gen.wire_components.buses.Bus.connect_bus">connect_bus</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.buses.Bus.get_declaration_c" href="#ariths_gen.wire_components.buses.Bus.get_declaration_c">get_declaration_c</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.buses.Bus.get_unique_assign_out_wires_blif" href="#ariths_gen.wire_components.buses.Bus.get_unique_assign_out_wires_blif">get_unique_assign_out_wires_blif</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.buses.Bus.get_unique_assign_out_wires_v" href="#ariths_gen.wire_components.buses.Bus.get_unique_assign_out_wires_v">get_unique_assign_out_wires_v</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.buses.Bus.get_wire" href="#ariths_gen.wire_components.buses.Bus.get_wire">get_wire</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.buses.Bus.get_wire_assign_blif" href="#ariths_gen.wire_components.buses.Bus.get_wire_assign_blif">get_wire_assign_blif</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.buses.Bus.get_wire_declaration_blif" href="#ariths_gen.wire_components.buses.Bus.get_wire_declaration_blif">get_wire_declaration_blif</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.buses.Bus.get_wire_declaration_v" href="#ariths_gen.wire_components.buses.Bus.get_wire_declaration_v">get_wire_declaration_v</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.buses.Bus.is_output_bus" href="#ariths_gen.wire_components.buses.Bus.is_output_bus">is_output_bus</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.buses.Bus.return_bus_wires_sign_extend_c_flat" href="#ariths_gen.wire_components.buses.Bus.return_bus_wires_sign_extend_c_flat">return_bus_wires_sign_extend_c_flat</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.buses.Bus.return_bus_wires_sign_extend_c_hier" href="#ariths_gen.wire_components.buses.Bus.return_bus_wires_sign_extend_c_hier">return_bus_wires_sign_extend_c_hier</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.buses.Bus.return_bus_wires_sign_extend_python_flat" href="#ariths_gen.wire_components.buses.Bus.return_bus_wires_sign_extend_python_flat">return_bus_wires_sign_extend_python_flat</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.buses.Bus.return_bus_wires_values_c_flat" href="#ariths_gen.wire_components.buses.Bus.return_bus_wires_values_c_flat">return_bus_wires_values_c_flat</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.buses.Bus.return_bus_wires_values_c_hier" href="#ariths_gen.wire_components.buses.Bus.return_bus_wires_values_c_hier">return_bus_wires_values_c_hier</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.buses.Bus.return_bus_wires_values_python_flat" href="#ariths_gen.wire_components.buses.Bus.return_bus_wires_values_python_flat">return_bus_wires_values_python_flat</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.buses.Bus.return_bus_wires_values_v_flat" href="#ariths_gen.wire_components.buses.Bus.return_bus_wires_values_v_flat">return_bus_wires_values_v_flat</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.buses.Bus.return_bus_wires_values_v_hier" href="#ariths_gen.wire_components.buses.Bus.return_bus_wires_values_v_hier">return_bus_wires_values_v_hier</a></code></li>
|
||
</ul>
|
||
</li>
|
||
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|
||
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|
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