mirror of
https://github.com/ehw-fit/ariths-gen.git
synced 2025-04-20 05:41:25 +01:00
86 lines
3.0 KiB
Python
86 lines
3.0 KiB
Python
""" WIRE COMPONENTS """
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class wire():
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def __init__(self, name: str, value: int = 0, index: int = 0):
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self.name = name
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if self.name.endswith("_"+str(index)):
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self.prefix = name[0:int(name.rfind(str(index))-1)]
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else:
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self.prefix = name
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self.value = value
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self.index = index
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# C CODE GENERATION #
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def get_declaration_c(self):
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return f" uint8_t {self.name} = {self.value};\n"
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def get_wire_value_c(self, offset: int = 0, prefix: str = ""):
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name = self.name if prefix == "" else prefix
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return f"(({name} >> {offset}) & 0x01)"
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def return_wire_value_c(self, offset: int = 0):
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return f"({self.name} & 0x01) << {offset}"
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# VERILOG CODE GENERATION #
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def get_declaration_v(self):
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return f" wire {self.name};\n"
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def get_declaration_init_v(self):
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return f" wire {self.name} = {self.value};\n"
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def get_wire_value_v(self, offset: int = 0, prefix: str = "", array: bool = False):
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name = self.name if prefix == "" else prefix
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if array is True:
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return f"{name}[{offset}]"
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else:
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return f"{name}"
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def return_wire_value_v(self):
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return f"{self.name}"
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class bus():
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def __init__(self, prefix: str, N: int = 1):
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self.bus = [wire(name=prefix+"_"+str(i), index=i) for i in range(N)]
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self.prefix = prefix
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self.N = N
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def __index__(self, wire):
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return self.bus.index(wire)
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# Connecting output wire of the inner circuit component to the input of another component
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# (or to the wire of the circuit's output bus)
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def connect(self, out_wire_index: int, inner_component_out_wire: wire):
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self.bus[out_wire_index] = inner_component_out_wire
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def get_wire(self, wire_index: int = 0):
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return self.bus[wire_index]
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def bus_extend(self, N: int, prefix: str = "bus"):
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self.bus = [wire(name=prefix+"_"+str(i), index=i) for i in range(N)]
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self.N = N
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# C CODE GENERATION #
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def get_wire_value_c(self, offset: int = 0, prefix: str = ""):
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return self.get_wire(wire_index=offset).get_wire_value_c(offset=offset, prefix=prefix)
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def get_wire_declaration_c(self):
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return "".join([w.get_declaration_c() for w in self.bus])
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def get_declaration_c(self):
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if self.N > 8:
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return f" uint64_t {self.prefix} = 0;\n"
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else:
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return f" uint8_t {self.prefix} = 0;\n"
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def return_wire_value_c(self, offset: int = 0):
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self.get_wire(wire_index=offset).return_wire_value_c(offset=offset)
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# VERILOG CODE GENERATION #
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def get_wire_value_v(self, offset: int = 0, prefix: str = "", array: bool = False):
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return self.get_wire(wire_index=offset).get_wire_value_v(offset=offset, prefix=prefix, array=array)
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def get_wire_declaration_v(self):
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return "".join([w.get_declaration_v() for w in self.bus])
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