mirror of
https://github.com/ehw-fit/ariths-gen.git
synced 2025-04-20 13:51:23 +01:00
109 lines
4.1 KiB
Python
109 lines
4.1 KiB
Python
""" WIRE COMPONENTS """
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class wire():
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def __init__(self, name: str, value: int = 0, index: int = 0):
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self.name = name
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if self.name.endswith("_"+str(index)):
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self.prefix = name[0:int(name.rfind(str(index))-1)]
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else:
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self.prefix = name
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self.value = value
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self.index = index
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""" C CODE GENERATION """
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def get_declaration_c(self):
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return f" uint8_t {self.name} = {self.value};\n"
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def get_wire_value_c(self, name: str = "", offset: int = 0):
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w_name = self.name if name == "" else name
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return f"(({w_name} >> {offset}) & 0x01)"
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def get_assign_c(self, name: str):
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return f" {self.name} = {name};\n"
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def return_wire_value_c(self, offset: int = 0):
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return f"({self.name} & 0x01) << {offset}"
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""" VERILOG CODE GENERATION """
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def get_declaration_v(self):
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return f" wire {self.name};\n"
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def get_assign_v(self, name: str, offset: int = 0, array: bool = False):
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if array is True:
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return f" assign {self.name} = {name}[{offset}];\n"
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else:
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return f" assign {self.name} = {name};\n"
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""" BLIF CODE GENERATION """
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def get_declaration_blif(self, name: str = "", offset: int = 0, array: bool = False):
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if array is True:
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return f" {name}[{offset}]"
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else:
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return f" {self.name}"
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def get_assign_blif(self, name: str, output: bool = False):
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if output is True:
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return f".names {self.name} {name}\n" + \
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f"1 1\n"
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else:
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return f".names {name} {self.name}\n" + \
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f"1 1\n"
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class bus():
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def __init__(self, prefix: str, N: int = 1, wires_list: list = None):
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if wires_list is None:
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self.bus = [wire(name=prefix+"_"+str(i), index=i) for i in range(N)]
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self.prefix = prefix
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self.N = N
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else:
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self.bus = wires_list
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self.prefix = prefix
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self.N = len(self.bus)
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# Connecting output wire of the inner circuit component to the input of another component
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# (or to the wire of the circuit's output bus)
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def connect(self, out_wire_index: int, inner_component_out_wire: wire):
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self.bus[out_wire_index] = inner_component_out_wire
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def get_wire(self, wire_index: int = 0):
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return self.bus[wire_index]
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def bus_extend(self, N: int, prefix: str = "bus"):
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if self.N < N:
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self.bus += [wire(name=prefix+"_"+str(i), index=i) for i in range(self.N, N)]
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self.N = N
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""" C CODE GENERATION """
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def get_declaration_c(self):
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if self.N > 8:
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return f" uint64_t {self.prefix} = 0;\n"
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else:
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return f" uint8_t {self.prefix} = 0;\n"
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def get_wire_declaration_c(self):
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return "".join([w.get_declaration_c() for w in self.bus])
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def get_wire_assign_c(self, bus_prefix: str = ""):
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bus_prefix = self.prefix if bus_prefix == "" else bus_prefix
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return "".join([w.get_assign_c(name=w.get_wire_value_c(name=bus_prefix, offset=self.bus.index(w))) for w in self.bus])
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def return_wire_value_c(self, offset: int = 0):
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self.get_wire(wire_index=offset).return_wire_value_c(offset=offset)
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""" VERILOG CODE GENERATION """
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def get_wire_declaration_v(self):
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return "".join([w.get_declaration_v() for w in self.bus])
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def get_wire_assign_v(self, bus_prefix: str = ""):
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bus_prefix = self.prefix if bus_prefix == "" else bus_prefix
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return "".join([w.get_assign_v(name=self.prefix, offset=self.bus.index(w), array=True) for w in self.bus])
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""" BLIF CODE GENERATION """
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def get_wire_declaration_blif(self):
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return "".join([w.get_declaration_blif(name=self.prefix, offset=self.bus.index(w), array=True) for w in self.bus])
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def get_wire_assign_blif(self, output: bool = False):
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return "".join([w.get_assign_blif(name=self.prefix+f"[{self.bus.index(w)}]", output=output) for w in self.bus])
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