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https://github.com/ehw-fit/ariths-gen.git
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56c86c13ca
* #10 CGP Circuits as inputs (#11) * CGP Circuits as inputs * #10 support of signed output in general circuit * input as output works * output connected to input (c) * automated verilog testing * output rename * Implemented CSA and Wallace tree multiplier composing of CSAs. Also did some code cleanup. * Typos fix and code cleanup. * Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats. * Updated automated testing scripts. * Small bugfix in python code generation (I initially thought this line is useless). * Updated generated circuits folder. Co-authored-by: Vojta Mrazek <mrazek@fit.vutbr.cz>
87 lines
3.2 KiB
Verilog
87 lines
3.2 KiB
Verilog
module u_rca8(input [7:0] a, input [7:0] b, output [8:0] u_rca8_out);
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wire u_rca8_ha_xor0;
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wire u_rca8_ha_and0;
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wire u_rca8_fa1_xor0;
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wire u_rca8_fa1_and0;
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wire u_rca8_fa1_xor1;
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wire u_rca8_fa1_and1;
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wire u_rca8_fa1_or0;
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wire u_rca8_fa2_xor0;
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wire u_rca8_fa2_and0;
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wire u_rca8_fa2_xor1;
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wire u_rca8_fa2_and1;
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wire u_rca8_fa2_or0;
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wire u_rca8_fa3_xor0;
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wire u_rca8_fa3_and0;
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wire u_rca8_fa3_xor1;
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wire u_rca8_fa3_and1;
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wire u_rca8_fa3_or0;
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wire u_rca8_fa4_xor0;
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wire u_rca8_fa4_and0;
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wire u_rca8_fa4_xor1;
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wire u_rca8_fa4_and1;
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wire u_rca8_fa4_or0;
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wire u_rca8_fa5_xor0;
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wire u_rca8_fa5_and0;
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wire u_rca8_fa5_xor1;
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wire u_rca8_fa5_and1;
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wire u_rca8_fa5_or0;
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wire u_rca8_fa6_xor0;
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wire u_rca8_fa6_and0;
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wire u_rca8_fa6_xor1;
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wire u_rca8_fa6_and1;
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wire u_rca8_fa6_or0;
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wire u_rca8_fa7_xor0;
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wire u_rca8_fa7_and0;
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wire u_rca8_fa7_xor1;
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wire u_rca8_fa7_and1;
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wire u_rca8_fa7_or0;
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assign u_rca8_ha_xor0 = a[0] ^ b[0];
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assign u_rca8_ha_and0 = a[0] & b[0];
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assign u_rca8_fa1_xor0 = a[1] ^ b[1];
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assign u_rca8_fa1_and0 = a[1] & b[1];
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assign u_rca8_fa1_xor1 = u_rca8_fa1_xor0 ^ u_rca8_ha_and0;
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assign u_rca8_fa1_and1 = u_rca8_fa1_xor0 & u_rca8_ha_and0;
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assign u_rca8_fa1_or0 = u_rca8_fa1_and0 | u_rca8_fa1_and1;
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assign u_rca8_fa2_xor0 = a[2] ^ b[2];
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assign u_rca8_fa2_and0 = a[2] & b[2];
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assign u_rca8_fa2_xor1 = u_rca8_fa2_xor0 ^ u_rca8_fa1_or0;
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assign u_rca8_fa2_and1 = u_rca8_fa2_xor0 & u_rca8_fa1_or0;
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assign u_rca8_fa2_or0 = u_rca8_fa2_and0 | u_rca8_fa2_and1;
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assign u_rca8_fa3_xor0 = a[3] ^ b[3];
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assign u_rca8_fa3_and0 = a[3] & b[3];
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assign u_rca8_fa3_xor1 = u_rca8_fa3_xor0 ^ u_rca8_fa2_or0;
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assign u_rca8_fa3_and1 = u_rca8_fa3_xor0 & u_rca8_fa2_or0;
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assign u_rca8_fa3_or0 = u_rca8_fa3_and0 | u_rca8_fa3_and1;
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assign u_rca8_fa4_xor0 = a[4] ^ b[4];
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assign u_rca8_fa4_and0 = a[4] & b[4];
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assign u_rca8_fa4_xor1 = u_rca8_fa4_xor0 ^ u_rca8_fa3_or0;
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assign u_rca8_fa4_and1 = u_rca8_fa4_xor0 & u_rca8_fa3_or0;
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assign u_rca8_fa4_or0 = u_rca8_fa4_and0 | u_rca8_fa4_and1;
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assign u_rca8_fa5_xor0 = a[5] ^ b[5];
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assign u_rca8_fa5_and0 = a[5] & b[5];
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assign u_rca8_fa5_xor1 = u_rca8_fa5_xor0 ^ u_rca8_fa4_or0;
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assign u_rca8_fa5_and1 = u_rca8_fa5_xor0 & u_rca8_fa4_or0;
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assign u_rca8_fa5_or0 = u_rca8_fa5_and0 | u_rca8_fa5_and1;
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assign u_rca8_fa6_xor0 = a[6] ^ b[6];
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assign u_rca8_fa6_and0 = a[6] & b[6];
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assign u_rca8_fa6_xor1 = u_rca8_fa6_xor0 ^ u_rca8_fa5_or0;
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assign u_rca8_fa6_and1 = u_rca8_fa6_xor0 & u_rca8_fa5_or0;
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assign u_rca8_fa6_or0 = u_rca8_fa6_and0 | u_rca8_fa6_and1;
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assign u_rca8_fa7_xor0 = a[7] ^ b[7];
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assign u_rca8_fa7_and0 = a[7] & b[7];
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assign u_rca8_fa7_xor1 = u_rca8_fa7_xor0 ^ u_rca8_fa6_or0;
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assign u_rca8_fa7_and1 = u_rca8_fa7_xor0 & u_rca8_fa6_or0;
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assign u_rca8_fa7_or0 = u_rca8_fa7_and0 | u_rca8_fa7_and1;
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assign u_rca8_out[0] = u_rca8_ha_xor0;
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assign u_rca8_out[1] = u_rca8_fa1_xor1;
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assign u_rca8_out[2] = u_rca8_fa2_xor1;
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assign u_rca8_out[3] = u_rca8_fa3_xor1;
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assign u_rca8_out[4] = u_rca8_fa4_xor1;
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assign u_rca8_out[5] = u_rca8_fa5_xor1;
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assign u_rca8_out[6] = u_rca8_fa6_xor1;
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assign u_rca8_out[7] = u_rca8_fa7_xor1;
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assign u_rca8_out[8] = u_rca8_fa7_or0;
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endmodule |