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https://github.com/ehw-fit/ariths-gen.git
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56c86c13ca
* #10 CGP Circuits as inputs (#11) * CGP Circuits as inputs * #10 support of signed output in general circuit * input as output works * output connected to input (c) * automated verilog testing * output rename * Implemented CSA and Wallace tree multiplier composing of CSAs. Also did some code cleanup. * Typos fix and code cleanup. * Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats. * Updated automated testing scripts. * Small bugfix in python code generation (I initially thought this line is useless). * Updated generated circuits folder. Co-authored-by: Vojta Mrazek <mrazek@fit.vutbr.cz>
121 lines
4.0 KiB
Plaintext
121 lines
4.0 KiB
Plaintext
.model arrdiv4
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.inputs a[0] a[1] a[2] a[3] b[0] b[1] b[2] b[3]
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.outputs arrdiv4_out[0] arrdiv4_out[1] arrdiv4_out[2] arrdiv4_out[3]
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.names vdd
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1
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.names gnd
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0
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.subckt fs a=a[3] b=b[0] bin=gnd fs_xor1=arrdiv4_fs0_xor0 fs_or0=arrdiv4_fs0_and0
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.subckt fs a=gnd b=b[1] bin=arrdiv4_fs0_and0 fs_xor1=arrdiv4_fs1_xor1 fs_or0=arrdiv4_fs1_or0
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.subckt fs a=gnd b=b[2] bin=arrdiv4_fs1_or0 fs_xor1=arrdiv4_fs2_xor1 fs_or0=arrdiv4_fs2_or0
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.subckt fs a=gnd b=b[3] bin=arrdiv4_fs2_or0 fs_xor1=arrdiv4_fs3_xor1 fs_or0=arrdiv4_fs3_or0
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.subckt mux2to1 d0=arrdiv4_fs0_xor0 d1=a[3] sel=arrdiv4_fs3_or0 mux2to1_xor0=arrdiv4_mux2to10_xor0
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.subckt mux2to1 d0=arrdiv4_fs1_xor1 d1=gnd sel=arrdiv4_fs3_or0 mux2to1_xor0=arrdiv4_mux2to11_and1
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.subckt mux2to1 d0=arrdiv4_fs2_xor1 d1=gnd sel=arrdiv4_fs3_or0 mux2to1_xor0=arrdiv4_mux2to12_and1
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.subckt not_gate a=arrdiv4_fs3_or0 out=arrdiv4_not0
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.subckt fs a=a[2] b=b[0] bin=gnd fs_xor1=arrdiv4_fs4_xor0 fs_or0=arrdiv4_fs4_and0
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.subckt fs a=arrdiv4_mux2to10_xor0 b=b[1] bin=arrdiv4_fs4_and0 fs_xor1=arrdiv4_fs5_xor1 fs_or0=arrdiv4_fs5_or0
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.subckt fs a=arrdiv4_mux2to11_and1 b=b[2] bin=arrdiv4_fs5_or0 fs_xor1=arrdiv4_fs6_xor1 fs_or0=arrdiv4_fs6_or0
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.subckt fs a=arrdiv4_mux2to12_and1 b=b[3] bin=arrdiv4_fs6_or0 fs_xor1=arrdiv4_fs7_xor1 fs_or0=arrdiv4_fs7_or0
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.subckt mux2to1 d0=arrdiv4_fs4_xor0 d1=a[2] sel=arrdiv4_fs7_or0 mux2to1_xor0=arrdiv4_mux2to13_xor0
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.subckt mux2to1 d0=arrdiv4_fs5_xor1 d1=arrdiv4_mux2to10_xor0 sel=arrdiv4_fs7_or0 mux2to1_xor0=arrdiv4_mux2to14_xor0
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.subckt mux2to1 d0=arrdiv4_fs6_xor1 d1=arrdiv4_mux2to11_and1 sel=arrdiv4_fs7_or0 mux2to1_xor0=arrdiv4_mux2to15_xor0
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.subckt not_gate a=arrdiv4_fs7_or0 out=arrdiv4_not1
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.subckt fs a=a[1] b=b[0] bin=gnd fs_xor1=arrdiv4_fs8_xor0 fs_or0=arrdiv4_fs8_and0
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.subckt fs a=arrdiv4_mux2to13_xor0 b=b[1] bin=arrdiv4_fs8_and0 fs_xor1=arrdiv4_fs9_xor1 fs_or0=arrdiv4_fs9_or0
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.subckt fs a=arrdiv4_mux2to14_xor0 b=b[2] bin=arrdiv4_fs9_or0 fs_xor1=arrdiv4_fs10_xor1 fs_or0=arrdiv4_fs10_or0
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.subckt fs a=arrdiv4_mux2to15_xor0 b=b[3] bin=arrdiv4_fs10_or0 fs_xor1=arrdiv4_fs11_xor1 fs_or0=arrdiv4_fs11_or0
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.subckt mux2to1 d0=arrdiv4_fs8_xor0 d1=a[1] sel=arrdiv4_fs11_or0 mux2to1_xor0=arrdiv4_mux2to16_xor0
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.subckt mux2to1 d0=arrdiv4_fs9_xor1 d1=arrdiv4_mux2to13_xor0 sel=arrdiv4_fs11_or0 mux2to1_xor0=arrdiv4_mux2to17_xor0
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.subckt mux2to1 d0=arrdiv4_fs10_xor1 d1=arrdiv4_mux2to14_xor0 sel=arrdiv4_fs11_or0 mux2to1_xor0=arrdiv4_mux2to18_xor0
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.subckt not_gate a=arrdiv4_fs11_or0 out=arrdiv4_not2
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.subckt fs a=a[0] b=b[0] bin=gnd fs_xor1=arrdiv4_fs12_xor0 fs_or0=arrdiv4_fs12_and0
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.subckt fs a=arrdiv4_mux2to16_xor0 b=b[1] bin=arrdiv4_fs12_and0 fs_xor1=arrdiv4_fs13_xor1 fs_or0=arrdiv4_fs13_or0
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.subckt fs a=arrdiv4_mux2to17_xor0 b=b[2] bin=arrdiv4_fs13_or0 fs_xor1=arrdiv4_fs14_xor1 fs_or0=arrdiv4_fs14_or0
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.subckt fs a=arrdiv4_mux2to18_xor0 b=b[3] bin=arrdiv4_fs14_or0 fs_xor1=arrdiv4_fs15_xor1 fs_or0=arrdiv4_fs15_or0
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.subckt not_gate a=arrdiv4_fs15_or0 out=arrdiv4_not3
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.names arrdiv4_not3 arrdiv4_out[0]
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1 1
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.names arrdiv4_not2 arrdiv4_out[1]
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1 1
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.names arrdiv4_not1 arrdiv4_out[2]
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1 1
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.names arrdiv4_not0 arrdiv4_out[3]
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1 1
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.end
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.model mux2to1
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.inputs d0 d1 sel
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.outputs mux2to1_xor0
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.names vdd
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1
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.names gnd
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0
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.subckt and_gate a=d1 b=sel out=mux2to1_and0
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.subckt not_gate a=sel out=mux2to1_not0
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.subckt and_gate a=d0 b=mux2to1_not0 out=mux2to1_and1
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.subckt xor_gate a=mux2to1_and0 b=mux2to1_and1 out=mux2to1_xor0
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.end
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.model fs
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.inputs a b bin
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.outputs fs_xor1 fs_or0
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.names vdd
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1
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.names gnd
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0
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.subckt xor_gate a=a b=b out=fs_xor0
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.subckt not_gate a=a out=fs_not0
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.subckt and_gate a=fs_not0 b=b out=fs_and0
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.subckt xor_gate a=bin b=fs_xor0 out=fs_xor1
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.subckt not_gate a=fs_xor0 out=fs_not1
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.subckt and_gate a=fs_not1 b=bin out=fs_and1
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.subckt or_gate a=fs_and1 b=fs_and0 out=fs_or0
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.end
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.model or_gate
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.inputs a b
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.outputs out
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.names vdd
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1
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.names gnd
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0
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.names a b out
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1- 1
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-1 1
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.end
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.model and_gate
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.inputs a b
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.outputs out
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.names vdd
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1
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.names gnd
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0
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.names a b out
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11 1
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.end
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.model not_gate
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.inputs a
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.outputs out
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.names vdd
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1
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.names gnd
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0
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.names a out
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0 1
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.end
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.model xor_gate
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.inputs a b
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.outputs out
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.names vdd
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1
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.names gnd
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0
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.names a b out
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01 1
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10 1
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.end
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