mirror of
https://github.com/ehw-fit/ariths-gen.git
synced 2025-04-23 15:21:22 +01:00
56c86c13ca
* #10 CGP Circuits as inputs (#11) * CGP Circuits as inputs * #10 support of signed output in general circuit * input as output works * output connected to input (c) * automated verilog testing * output rename * Implemented CSA and Wallace tree multiplier composing of CSAs. Also did some code cleanup. * Typos fix and code cleanup. * Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats. * Updated automated testing scripts. * Small bugfix in python code generation (I initially thought this line is useless). * Updated generated circuits folder. Co-authored-by: Vojta Mrazek <mrazek@fit.vutbr.cz>
201 lines
6.4 KiB
Plaintext
201 lines
6.4 KiB
Plaintext
.model u_csamul_cla4
|
|
.inputs a[0] a[1] a[2] a[3] b[0] b[1] b[2] b[3]
|
|
.outputs u_csamul_cla4_out[0] u_csamul_cla4_out[1] u_csamul_cla4_out[2] u_csamul_cla4_out[3] u_csamul_cla4_out[4] u_csamul_cla4_out[5] u_csamul_cla4_out[6] u_csamul_cla4_out[7]
|
|
.names vdd
|
|
1
|
|
.names gnd
|
|
0
|
|
.names a[0] b[0] u_csamul_cla4_and0_0
|
|
11 1
|
|
.names a[1] b[0] u_csamul_cla4_and1_0
|
|
11 1
|
|
.names a[2] b[0] u_csamul_cla4_and2_0
|
|
11 1
|
|
.names a[3] b[0] u_csamul_cla4_and3_0
|
|
11 1
|
|
.names a[0] b[1] u_csamul_cla4_and0_1
|
|
11 1
|
|
.names u_csamul_cla4_and0_1 u_csamul_cla4_and1_0 u_csamul_cla4_ha0_1_xor0
|
|
01 1
|
|
10 1
|
|
.names u_csamul_cla4_and0_1 u_csamul_cla4_and1_0 u_csamul_cla4_ha0_1_and0
|
|
11 1
|
|
.names a[1] b[1] u_csamul_cla4_and1_1
|
|
11 1
|
|
.names u_csamul_cla4_and1_1 u_csamul_cla4_and2_0 u_csamul_cla4_ha1_1_xor0
|
|
01 1
|
|
10 1
|
|
.names u_csamul_cla4_and1_1 u_csamul_cla4_and2_0 u_csamul_cla4_ha1_1_and0
|
|
11 1
|
|
.names a[2] b[1] u_csamul_cla4_and2_1
|
|
11 1
|
|
.names u_csamul_cla4_and2_1 u_csamul_cla4_and3_0 u_csamul_cla4_ha2_1_xor0
|
|
01 1
|
|
10 1
|
|
.names u_csamul_cla4_and2_1 u_csamul_cla4_and3_0 u_csamul_cla4_ha2_1_and0
|
|
11 1
|
|
.names a[3] b[1] u_csamul_cla4_and3_1
|
|
11 1
|
|
.names a[0] b[2] u_csamul_cla4_and0_2
|
|
11 1
|
|
.names u_csamul_cla4_and0_2 u_csamul_cla4_ha1_1_xor0 u_csamul_cla4_fa0_2_xor0
|
|
01 1
|
|
10 1
|
|
.names u_csamul_cla4_and0_2 u_csamul_cla4_ha1_1_xor0 u_csamul_cla4_fa0_2_and0
|
|
11 1
|
|
.names u_csamul_cla4_fa0_2_xor0 u_csamul_cla4_ha0_1_and0 u_csamul_cla4_fa0_2_xor1
|
|
01 1
|
|
10 1
|
|
.names u_csamul_cla4_fa0_2_xor0 u_csamul_cla4_ha0_1_and0 u_csamul_cla4_fa0_2_and1
|
|
11 1
|
|
.names u_csamul_cla4_fa0_2_and0 u_csamul_cla4_fa0_2_and1 u_csamul_cla4_fa0_2_or0
|
|
1- 1
|
|
-1 1
|
|
.names a[1] b[2] u_csamul_cla4_and1_2
|
|
11 1
|
|
.names u_csamul_cla4_and1_2 u_csamul_cla4_ha2_1_xor0 u_csamul_cla4_fa1_2_xor0
|
|
01 1
|
|
10 1
|
|
.names u_csamul_cla4_and1_2 u_csamul_cla4_ha2_1_xor0 u_csamul_cla4_fa1_2_and0
|
|
11 1
|
|
.names u_csamul_cla4_fa1_2_xor0 u_csamul_cla4_ha1_1_and0 u_csamul_cla4_fa1_2_xor1
|
|
01 1
|
|
10 1
|
|
.names u_csamul_cla4_fa1_2_xor0 u_csamul_cla4_ha1_1_and0 u_csamul_cla4_fa1_2_and1
|
|
11 1
|
|
.names u_csamul_cla4_fa1_2_and0 u_csamul_cla4_fa1_2_and1 u_csamul_cla4_fa1_2_or0
|
|
1- 1
|
|
-1 1
|
|
.names a[2] b[2] u_csamul_cla4_and2_2
|
|
11 1
|
|
.names u_csamul_cla4_and2_2 u_csamul_cla4_and3_1 u_csamul_cla4_fa2_2_xor0
|
|
01 1
|
|
10 1
|
|
.names u_csamul_cla4_and2_2 u_csamul_cla4_and3_1 u_csamul_cla4_fa2_2_and0
|
|
11 1
|
|
.names u_csamul_cla4_fa2_2_xor0 u_csamul_cla4_ha2_1_and0 u_csamul_cla4_fa2_2_xor1
|
|
01 1
|
|
10 1
|
|
.names u_csamul_cla4_fa2_2_xor0 u_csamul_cla4_ha2_1_and0 u_csamul_cla4_fa2_2_and1
|
|
11 1
|
|
.names u_csamul_cla4_fa2_2_and0 u_csamul_cla4_fa2_2_and1 u_csamul_cla4_fa2_2_or0
|
|
1- 1
|
|
-1 1
|
|
.names a[3] b[2] u_csamul_cla4_and3_2
|
|
11 1
|
|
.names a[0] b[3] u_csamul_cla4_and0_3
|
|
11 1
|
|
.names u_csamul_cla4_and0_3 u_csamul_cla4_fa1_2_xor1 u_csamul_cla4_fa0_3_xor0
|
|
01 1
|
|
10 1
|
|
.names u_csamul_cla4_and0_3 u_csamul_cla4_fa1_2_xor1 u_csamul_cla4_fa0_3_and0
|
|
11 1
|
|
.names u_csamul_cla4_fa0_3_xor0 u_csamul_cla4_fa0_2_or0 u_csamul_cla4_fa0_3_xor1
|
|
01 1
|
|
10 1
|
|
.names u_csamul_cla4_fa0_3_xor0 u_csamul_cla4_fa0_2_or0 u_csamul_cla4_fa0_3_and1
|
|
11 1
|
|
.names u_csamul_cla4_fa0_3_and0 u_csamul_cla4_fa0_3_and1 u_csamul_cla4_fa0_3_or0
|
|
1- 1
|
|
-1 1
|
|
.names a[1] b[3] u_csamul_cla4_and1_3
|
|
11 1
|
|
.names u_csamul_cla4_and1_3 u_csamul_cla4_fa2_2_xor1 u_csamul_cla4_fa1_3_xor0
|
|
01 1
|
|
10 1
|
|
.names u_csamul_cla4_and1_3 u_csamul_cla4_fa2_2_xor1 u_csamul_cla4_fa1_3_and0
|
|
11 1
|
|
.names u_csamul_cla4_fa1_3_xor0 u_csamul_cla4_fa1_2_or0 u_csamul_cla4_fa1_3_xor1
|
|
01 1
|
|
10 1
|
|
.names u_csamul_cla4_fa1_3_xor0 u_csamul_cla4_fa1_2_or0 u_csamul_cla4_fa1_3_and1
|
|
11 1
|
|
.names u_csamul_cla4_fa1_3_and0 u_csamul_cla4_fa1_3_and1 u_csamul_cla4_fa1_3_or0
|
|
1- 1
|
|
-1 1
|
|
.names a[2] b[3] u_csamul_cla4_and2_3
|
|
11 1
|
|
.names u_csamul_cla4_and2_3 u_csamul_cla4_and3_2 u_csamul_cla4_fa2_3_xor0
|
|
01 1
|
|
10 1
|
|
.names u_csamul_cla4_and2_3 u_csamul_cla4_and3_2 u_csamul_cla4_fa2_3_and0
|
|
11 1
|
|
.names u_csamul_cla4_fa2_3_xor0 u_csamul_cla4_fa2_2_or0 u_csamul_cla4_fa2_3_xor1
|
|
01 1
|
|
10 1
|
|
.names u_csamul_cla4_fa2_3_xor0 u_csamul_cla4_fa2_2_or0 u_csamul_cla4_fa2_3_and1
|
|
11 1
|
|
.names u_csamul_cla4_fa2_3_and0 u_csamul_cla4_fa2_3_and1 u_csamul_cla4_fa2_3_or0
|
|
1- 1
|
|
-1 1
|
|
.names a[3] b[3] u_csamul_cla4_and3_3
|
|
11 1
|
|
.names u_csamul_cla4_fa1_3_xor1 u_csamul_cla4_fa0_3_or0 u_csamul_cla4_u_cla4_pg_logic0_or0
|
|
1- 1
|
|
-1 1
|
|
.names u_csamul_cla4_fa1_3_xor1 u_csamul_cla4_fa0_3_or0 u_csamul_cla4_u_cla4_pg_logic0_and0
|
|
11 1
|
|
.names u_csamul_cla4_fa1_3_xor1 u_csamul_cla4_fa0_3_or0 u_csamul_cla4_u_cla4_pg_logic0_xor0
|
|
01 1
|
|
10 1
|
|
.names u_csamul_cla4_fa2_3_xor1 u_csamul_cla4_fa1_3_or0 u_csamul_cla4_u_cla4_pg_logic1_or0
|
|
1- 1
|
|
-1 1
|
|
.names u_csamul_cla4_fa2_3_xor1 u_csamul_cla4_fa1_3_or0 u_csamul_cla4_u_cla4_pg_logic1_and0
|
|
11 1
|
|
.names u_csamul_cla4_fa2_3_xor1 u_csamul_cla4_fa1_3_or0 u_csamul_cla4_u_cla4_pg_logic1_xor0
|
|
01 1
|
|
10 1
|
|
.names u_csamul_cla4_u_cla4_pg_logic1_xor0 u_csamul_cla4_u_cla4_pg_logic0_and0 u_csamul_cla4_u_cla4_xor1
|
|
01 1
|
|
10 1
|
|
.names u_csamul_cla4_u_cla4_pg_logic0_and0 u_csamul_cla4_u_cla4_pg_logic1_or0 u_csamul_cla4_u_cla4_and0
|
|
11 1
|
|
.names u_csamul_cla4_u_cla4_pg_logic1_and0 u_csamul_cla4_u_cla4_and0 u_csamul_cla4_u_cla4_or0
|
|
1- 1
|
|
-1 1
|
|
.names u_csamul_cla4_and3_3 u_csamul_cla4_fa2_3_or0 u_csamul_cla4_u_cla4_pg_logic2_or0
|
|
1- 1
|
|
-1 1
|
|
.names u_csamul_cla4_and3_3 u_csamul_cla4_fa2_3_or0 u_csamul_cla4_u_cla4_pg_logic2_and0
|
|
11 1
|
|
.names u_csamul_cla4_and3_3 u_csamul_cla4_fa2_3_or0 u_csamul_cla4_u_cla4_pg_logic2_xor0
|
|
01 1
|
|
10 1
|
|
.names u_csamul_cla4_u_cla4_pg_logic2_xor0 u_csamul_cla4_u_cla4_or0 u_csamul_cla4_u_cla4_xor2
|
|
01 1
|
|
10 1
|
|
.names u_csamul_cla4_u_cla4_pg_logic2_or0 u_csamul_cla4_u_cla4_pg_logic0_or0 u_csamul_cla4_u_cla4_and1
|
|
11 1
|
|
.names u_csamul_cla4_u_cla4_pg_logic0_and0 u_csamul_cla4_u_cla4_pg_logic2_or0 u_csamul_cla4_u_cla4_and2
|
|
11 1
|
|
.names u_csamul_cla4_u_cla4_and2 u_csamul_cla4_u_cla4_pg_logic1_or0 u_csamul_cla4_u_cla4_and3
|
|
11 1
|
|
.names u_csamul_cla4_u_cla4_pg_logic1_and0 u_csamul_cla4_u_cla4_pg_logic2_or0 u_csamul_cla4_u_cla4_and4
|
|
11 1
|
|
.names u_csamul_cla4_u_cla4_and3 u_csamul_cla4_u_cla4_and4 u_csamul_cla4_u_cla4_or1
|
|
1- 1
|
|
-1 1
|
|
.names u_csamul_cla4_u_cla4_pg_logic2_and0 u_csamul_cla4_u_cla4_or1 u_csamul_cla4_u_cla4_or2
|
|
1- 1
|
|
-1 1
|
|
.names u_csamul_cla4_u_cla4_pg_logic0_and0 u_csamul_cla4_u_cla4_pg_logic2_or0 u_csamul_cla4_u_cla4_and5
|
|
11 1
|
|
.names u_csamul_cla4_and0_0 u_csamul_cla4_out[0]
|
|
1 1
|
|
.names u_csamul_cla4_ha0_1_xor0 u_csamul_cla4_out[1]
|
|
1 1
|
|
.names u_csamul_cla4_fa0_2_xor1 u_csamul_cla4_out[2]
|
|
1 1
|
|
.names u_csamul_cla4_fa0_3_xor1 u_csamul_cla4_out[3]
|
|
1 1
|
|
.names u_csamul_cla4_u_cla4_pg_logic0_xor0 u_csamul_cla4_out[4]
|
|
1 1
|
|
.names u_csamul_cla4_u_cla4_xor1 u_csamul_cla4_out[5]
|
|
1 1
|
|
.names u_csamul_cla4_u_cla4_xor2 u_csamul_cla4_out[6]
|
|
1 1
|
|
.names u_csamul_cla4_u_cla4_or2 u_csamul_cla4_out[7]
|
|
1 1
|
|
.end
|