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56c86c13ca
* #10 CGP Circuits as inputs (#11) * CGP Circuits as inputs * #10 support of signed output in general circuit * input as output works * output connected to input (c) * automated verilog testing * output rename * Implemented CSA and Wallace tree multiplier composing of CSAs. Also did some code cleanup. * Typos fix and code cleanup. * Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats. * Updated automated testing scripts. * Small bugfix in python code generation (I initially thought this line is useless). * Updated generated circuits folder. Co-authored-by: Vojta Mrazek <mrazek@fit.vutbr.cz>
468 lines
11 KiB
Plaintext
468 lines
11 KiB
Plaintext
.model u_cla16
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.inputs a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] a[8] a[9] a[10] a[11] a[12] a[13] a[14] a[15] b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9] b[10] b[11] b[12] b[13] b[14] b[15]
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.outputs u_cla16_out[0] u_cla16_out[1] u_cla16_out[2] u_cla16_out[3] u_cla16_out[4] u_cla16_out[5] u_cla16_out[6] u_cla16_out[7] u_cla16_out[8] u_cla16_out[9] u_cla16_out[10] u_cla16_out[11] u_cla16_out[12] u_cla16_out[13] u_cla16_out[14] u_cla16_out[15] u_cla16_out[16]
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.names vdd
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1
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.names gnd
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0
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.names a[0] b[0] u_cla16_pg_logic0_or0
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1- 1
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-1 1
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.names a[0] b[0] u_cla16_pg_logic0_and0
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11 1
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.names a[0] b[0] u_cla16_pg_logic0_xor0
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01 1
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10 1
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.names a[1] b[1] u_cla16_pg_logic1_or0
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1- 1
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-1 1
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.names a[1] b[1] u_cla16_pg_logic1_and0
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11 1
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.names a[1] b[1] u_cla16_pg_logic1_xor0
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01 1
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10 1
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.names u_cla16_pg_logic1_xor0 u_cla16_pg_logic0_and0 u_cla16_xor1
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01 1
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10 1
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.names u_cla16_pg_logic0_and0 u_cla16_pg_logic1_or0 u_cla16_and0
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11 1
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.names u_cla16_pg_logic1_and0 u_cla16_and0 u_cla16_or0
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1- 1
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-1 1
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.names a[2] b[2] u_cla16_pg_logic2_or0
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1- 1
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-1 1
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.names a[2] b[2] u_cla16_pg_logic2_and0
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11 1
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.names a[2] b[2] u_cla16_pg_logic2_xor0
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01 1
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10 1
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.names u_cla16_pg_logic2_xor0 u_cla16_or0 u_cla16_xor2
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01 1
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10 1
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.names u_cla16_pg_logic2_or0 u_cla16_pg_logic0_or0 u_cla16_and1
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11 1
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.names u_cla16_pg_logic0_and0 u_cla16_pg_logic2_or0 u_cla16_and2
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11 1
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.names u_cla16_and2 u_cla16_pg_logic1_or0 u_cla16_and3
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11 1
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.names u_cla16_pg_logic1_and0 u_cla16_pg_logic2_or0 u_cla16_and4
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11 1
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.names u_cla16_and3 u_cla16_and4 u_cla16_or1
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1- 1
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-1 1
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.names u_cla16_pg_logic2_and0 u_cla16_or1 u_cla16_or2
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1- 1
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-1 1
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.names a[3] b[3] u_cla16_pg_logic3_or0
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1- 1
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-1 1
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.names a[3] b[3] u_cla16_pg_logic3_and0
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11 1
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.names a[3] b[3] u_cla16_pg_logic3_xor0
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01 1
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10 1
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.names u_cla16_pg_logic3_xor0 u_cla16_or2 u_cla16_xor3
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01 1
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10 1
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.names u_cla16_pg_logic3_or0 u_cla16_pg_logic1_or0 u_cla16_and5
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11 1
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.names u_cla16_pg_logic0_and0 u_cla16_pg_logic2_or0 u_cla16_and6
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11 1
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.names u_cla16_pg_logic3_or0 u_cla16_pg_logic1_or0 u_cla16_and7
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11 1
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.names u_cla16_and6 u_cla16_and7 u_cla16_and8
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11 1
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.names u_cla16_pg_logic1_and0 u_cla16_pg_logic3_or0 u_cla16_and9
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11 1
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.names u_cla16_and9 u_cla16_pg_logic2_or0 u_cla16_and10
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11 1
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.names u_cla16_pg_logic2_and0 u_cla16_pg_logic3_or0 u_cla16_and11
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11 1
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.names u_cla16_and8 u_cla16_and11 u_cla16_or3
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1- 1
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-1 1
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.names u_cla16_and10 u_cla16_or3 u_cla16_or4
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1- 1
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-1 1
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.names u_cla16_pg_logic3_and0 u_cla16_or4 u_cla16_or5
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1- 1
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-1 1
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.names a[4] b[4] u_cla16_pg_logic4_or0
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1- 1
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-1 1
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.names a[4] b[4] u_cla16_pg_logic4_and0
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11 1
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.names a[4] b[4] u_cla16_pg_logic4_xor0
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01 1
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10 1
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.names u_cla16_pg_logic4_xor0 u_cla16_or5 u_cla16_xor4
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01 1
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10 1
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.names u_cla16_or5 u_cla16_pg_logic4_or0 u_cla16_and12
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11 1
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.names u_cla16_pg_logic4_and0 u_cla16_and12 u_cla16_or6
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1- 1
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-1 1
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.names a[5] b[5] u_cla16_pg_logic5_or0
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1- 1
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-1 1
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.names a[5] b[5] u_cla16_pg_logic5_and0
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11 1
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.names a[5] b[5] u_cla16_pg_logic5_xor0
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01 1
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10 1
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.names u_cla16_pg_logic5_xor0 u_cla16_or6 u_cla16_xor5
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01 1
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10 1
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.names u_cla16_or5 u_cla16_pg_logic5_or0 u_cla16_and13
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11 1
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.names u_cla16_and13 u_cla16_pg_logic4_or0 u_cla16_and14
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11 1
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.names u_cla16_pg_logic4_and0 u_cla16_pg_logic5_or0 u_cla16_and15
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11 1
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.names u_cla16_and14 u_cla16_and15 u_cla16_or7
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1- 1
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-1 1
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.names u_cla16_pg_logic5_and0 u_cla16_or7 u_cla16_or8
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1- 1
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-1 1
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.names a[6] b[6] u_cla16_pg_logic6_or0
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1- 1
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-1 1
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.names a[6] b[6] u_cla16_pg_logic6_and0
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11 1
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.names a[6] b[6] u_cla16_pg_logic6_xor0
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01 1
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10 1
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.names u_cla16_pg_logic6_xor0 u_cla16_or8 u_cla16_xor6
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01 1
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10 1
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.names u_cla16_or5 u_cla16_pg_logic5_or0 u_cla16_and16
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11 1
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.names u_cla16_pg_logic6_or0 u_cla16_pg_logic4_or0 u_cla16_and17
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11 1
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.names u_cla16_and16 u_cla16_and17 u_cla16_and18
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11 1
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.names u_cla16_pg_logic4_and0 u_cla16_pg_logic6_or0 u_cla16_and19
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11 1
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.names u_cla16_and19 u_cla16_pg_logic5_or0 u_cla16_and20
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11 1
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.names u_cla16_pg_logic5_and0 u_cla16_pg_logic6_or0 u_cla16_and21
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11 1
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.names u_cla16_and18 u_cla16_and20 u_cla16_or9
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1- 1
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-1 1
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.names u_cla16_or9 u_cla16_and21 u_cla16_or10
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1- 1
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-1 1
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.names u_cla16_pg_logic6_and0 u_cla16_or10 u_cla16_or11
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1- 1
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-1 1
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.names a[7] b[7] u_cla16_pg_logic7_or0
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1- 1
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-1 1
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.names a[7] b[7] u_cla16_pg_logic7_and0
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11 1
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.names a[7] b[7] u_cla16_pg_logic7_xor0
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01 1
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10 1
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.names u_cla16_pg_logic7_xor0 u_cla16_or11 u_cla16_xor7
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01 1
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10 1
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.names u_cla16_or5 u_cla16_pg_logic6_or0 u_cla16_and22
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11 1
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.names u_cla16_pg_logic7_or0 u_cla16_pg_logic5_or0 u_cla16_and23
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11 1
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.names u_cla16_and22 u_cla16_and23 u_cla16_and24
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11 1
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.names u_cla16_and24 u_cla16_pg_logic4_or0 u_cla16_and25
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11 1
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.names u_cla16_pg_logic4_and0 u_cla16_pg_logic6_or0 u_cla16_and26
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11 1
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.names u_cla16_pg_logic7_or0 u_cla16_pg_logic5_or0 u_cla16_and27
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11 1
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.names u_cla16_and26 u_cla16_and27 u_cla16_and28
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11 1
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.names u_cla16_pg_logic5_and0 u_cla16_pg_logic7_or0 u_cla16_and29
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11 1
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.names u_cla16_and29 u_cla16_pg_logic6_or0 u_cla16_and30
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11 1
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.names u_cla16_pg_logic6_and0 u_cla16_pg_logic7_or0 u_cla16_and31
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11 1
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.names u_cla16_and25 u_cla16_and30 u_cla16_or12
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1- 1
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-1 1
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.names u_cla16_and28 u_cla16_and31 u_cla16_or13
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1- 1
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-1 1
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.names u_cla16_or12 u_cla16_or13 u_cla16_or14
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1- 1
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-1 1
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.names u_cla16_pg_logic7_and0 u_cla16_or14 u_cla16_or15
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1- 1
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-1 1
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.names a[8] b[8] u_cla16_pg_logic8_or0
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1- 1
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-1 1
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.names a[8] b[8] u_cla16_pg_logic8_and0
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11 1
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.names a[8] b[8] u_cla16_pg_logic8_xor0
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01 1
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10 1
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.names u_cla16_pg_logic8_xor0 u_cla16_or15 u_cla16_xor8
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01 1
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10 1
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.names u_cla16_or15 u_cla16_pg_logic8_or0 u_cla16_and32
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11 1
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.names u_cla16_pg_logic8_and0 u_cla16_and32 u_cla16_or16
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1- 1
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-1 1
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.names a[9] b[9] u_cla16_pg_logic9_or0
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1- 1
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-1 1
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.names a[9] b[9] u_cla16_pg_logic9_and0
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11 1
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.names a[9] b[9] u_cla16_pg_logic9_xor0
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01 1
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10 1
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.names u_cla16_pg_logic9_xor0 u_cla16_or16 u_cla16_xor9
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01 1
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10 1
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.names u_cla16_or15 u_cla16_pg_logic9_or0 u_cla16_and33
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11 1
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.names u_cla16_and33 u_cla16_pg_logic8_or0 u_cla16_and34
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11 1
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.names u_cla16_pg_logic8_and0 u_cla16_pg_logic9_or0 u_cla16_and35
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11 1
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.names u_cla16_and34 u_cla16_and35 u_cla16_or17
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1- 1
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-1 1
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.names u_cla16_pg_logic9_and0 u_cla16_or17 u_cla16_or18
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1- 1
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-1 1
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.names a[10] b[10] u_cla16_pg_logic10_or0
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1- 1
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-1 1
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.names a[10] b[10] u_cla16_pg_logic10_and0
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11 1
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.names a[10] b[10] u_cla16_pg_logic10_xor0
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01 1
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10 1
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.names u_cla16_pg_logic10_xor0 u_cla16_or18 u_cla16_xor10
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01 1
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10 1
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.names u_cla16_or15 u_cla16_pg_logic9_or0 u_cla16_and36
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11 1
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.names u_cla16_pg_logic10_or0 u_cla16_pg_logic8_or0 u_cla16_and37
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11 1
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.names u_cla16_and36 u_cla16_and37 u_cla16_and38
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11 1
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.names u_cla16_pg_logic8_and0 u_cla16_pg_logic10_or0 u_cla16_and39
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11 1
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.names u_cla16_and39 u_cla16_pg_logic9_or0 u_cla16_and40
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11 1
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.names u_cla16_pg_logic9_and0 u_cla16_pg_logic10_or0 u_cla16_and41
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11 1
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.names u_cla16_and38 u_cla16_and40 u_cla16_or19
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-1 1
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.names u_cla16_or19 u_cla16_and41 u_cla16_or20
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-1 1
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.names u_cla16_pg_logic10_and0 u_cla16_or20 u_cla16_or21
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1- 1
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-1 1
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.names a[11] b[11] u_cla16_pg_logic11_or0
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1- 1
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-1 1
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.names a[11] b[11] u_cla16_pg_logic11_and0
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11 1
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.names a[11] b[11] u_cla16_pg_logic11_xor0
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01 1
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10 1
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.names u_cla16_pg_logic11_xor0 u_cla16_or21 u_cla16_xor11
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01 1
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10 1
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.names u_cla16_or15 u_cla16_pg_logic10_or0 u_cla16_and42
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11 1
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.names u_cla16_pg_logic11_or0 u_cla16_pg_logic9_or0 u_cla16_and43
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11 1
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.names u_cla16_and42 u_cla16_and43 u_cla16_and44
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11 1
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.names u_cla16_and44 u_cla16_pg_logic8_or0 u_cla16_and45
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11 1
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.names u_cla16_pg_logic8_and0 u_cla16_pg_logic10_or0 u_cla16_and46
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11 1
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.names u_cla16_pg_logic11_or0 u_cla16_pg_logic9_or0 u_cla16_and47
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11 1
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.names u_cla16_and46 u_cla16_and47 u_cla16_and48
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11 1
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.names u_cla16_pg_logic9_and0 u_cla16_pg_logic11_or0 u_cla16_and49
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11 1
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.names u_cla16_and49 u_cla16_pg_logic10_or0 u_cla16_and50
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11 1
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.names u_cla16_pg_logic10_and0 u_cla16_pg_logic11_or0 u_cla16_and51
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11 1
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.names u_cla16_and45 u_cla16_and50 u_cla16_or22
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1- 1
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-1 1
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.names u_cla16_and48 u_cla16_and51 u_cla16_or23
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1- 1
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-1 1
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.names u_cla16_or22 u_cla16_or23 u_cla16_or24
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-1 1
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.names u_cla16_pg_logic11_and0 u_cla16_or24 u_cla16_or25
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1- 1
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-1 1
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.names a[12] b[12] u_cla16_pg_logic12_or0
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1- 1
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-1 1
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.names a[12] b[12] u_cla16_pg_logic12_and0
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11 1
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.names a[12] b[12] u_cla16_pg_logic12_xor0
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01 1
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10 1
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.names u_cla16_pg_logic12_xor0 u_cla16_or25 u_cla16_xor12
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01 1
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10 1
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.names u_cla16_or25 u_cla16_pg_logic12_or0 u_cla16_and52
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11 1
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.names u_cla16_pg_logic12_and0 u_cla16_and52 u_cla16_or26
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1- 1
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-1 1
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.names a[13] b[13] u_cla16_pg_logic13_or0
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1- 1
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-1 1
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.names a[13] b[13] u_cla16_pg_logic13_and0
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11 1
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.names a[13] b[13] u_cla16_pg_logic13_xor0
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01 1
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10 1
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.names u_cla16_pg_logic13_xor0 u_cla16_or26 u_cla16_xor13
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01 1
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10 1
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.names u_cla16_or25 u_cla16_pg_logic13_or0 u_cla16_and53
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11 1
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.names u_cla16_and53 u_cla16_pg_logic12_or0 u_cla16_and54
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11 1
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.names u_cla16_pg_logic12_and0 u_cla16_pg_logic13_or0 u_cla16_and55
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11 1
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.names u_cla16_and54 u_cla16_and55 u_cla16_or27
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1- 1
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-1 1
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.names u_cla16_pg_logic13_and0 u_cla16_or27 u_cla16_or28
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1- 1
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-1 1
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.names a[14] b[14] u_cla16_pg_logic14_or0
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1- 1
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-1 1
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.names a[14] b[14] u_cla16_pg_logic14_and0
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11 1
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.names a[14] b[14] u_cla16_pg_logic14_xor0
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01 1
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10 1
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.names u_cla16_pg_logic14_xor0 u_cla16_or28 u_cla16_xor14
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01 1
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10 1
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.names u_cla16_or25 u_cla16_pg_logic13_or0 u_cla16_and56
|
|
11 1
|
|
.names u_cla16_pg_logic14_or0 u_cla16_pg_logic12_or0 u_cla16_and57
|
|
11 1
|
|
.names u_cla16_and56 u_cla16_and57 u_cla16_and58
|
|
11 1
|
|
.names u_cla16_pg_logic12_and0 u_cla16_pg_logic14_or0 u_cla16_and59
|
|
11 1
|
|
.names u_cla16_and59 u_cla16_pg_logic13_or0 u_cla16_and60
|
|
11 1
|
|
.names u_cla16_pg_logic13_and0 u_cla16_pg_logic14_or0 u_cla16_and61
|
|
11 1
|
|
.names u_cla16_and58 u_cla16_and60 u_cla16_or29
|
|
1- 1
|
|
-1 1
|
|
.names u_cla16_or29 u_cla16_and61 u_cla16_or30
|
|
1- 1
|
|
-1 1
|
|
.names u_cla16_pg_logic14_and0 u_cla16_or30 u_cla16_or31
|
|
1- 1
|
|
-1 1
|
|
.names a[15] b[15] u_cla16_pg_logic15_or0
|
|
1- 1
|
|
-1 1
|
|
.names a[15] b[15] u_cla16_pg_logic15_and0
|
|
11 1
|
|
.names a[15] b[15] u_cla16_pg_logic15_xor0
|
|
01 1
|
|
10 1
|
|
.names u_cla16_pg_logic15_xor0 u_cla16_or31 u_cla16_xor15
|
|
01 1
|
|
10 1
|
|
.names u_cla16_or25 u_cla16_pg_logic14_or0 u_cla16_and62
|
|
11 1
|
|
.names u_cla16_pg_logic15_or0 u_cla16_pg_logic13_or0 u_cla16_and63
|
|
11 1
|
|
.names u_cla16_and62 u_cla16_and63 u_cla16_and64
|
|
11 1
|
|
.names u_cla16_and64 u_cla16_pg_logic12_or0 u_cla16_and65
|
|
11 1
|
|
.names u_cla16_pg_logic12_and0 u_cla16_pg_logic14_or0 u_cla16_and66
|
|
11 1
|
|
.names u_cla16_pg_logic15_or0 u_cla16_pg_logic13_or0 u_cla16_and67
|
|
11 1
|
|
.names u_cla16_and66 u_cla16_and67 u_cla16_and68
|
|
11 1
|
|
.names u_cla16_pg_logic13_and0 u_cla16_pg_logic15_or0 u_cla16_and69
|
|
11 1
|
|
.names u_cla16_and69 u_cla16_pg_logic14_or0 u_cla16_and70
|
|
11 1
|
|
.names u_cla16_pg_logic14_and0 u_cla16_pg_logic15_or0 u_cla16_and71
|
|
11 1
|
|
.names u_cla16_and65 u_cla16_and70 u_cla16_or32
|
|
1- 1
|
|
-1 1
|
|
.names u_cla16_and68 u_cla16_and71 u_cla16_or33
|
|
1- 1
|
|
-1 1
|
|
.names u_cla16_or32 u_cla16_or33 u_cla16_or34
|
|
1- 1
|
|
-1 1
|
|
.names u_cla16_pg_logic15_and0 u_cla16_or34 u_cla16_or35
|
|
1- 1
|
|
-1 1
|
|
.names u_cla16_pg_logic0_xor0 u_cla16_out[0]
|
|
1 1
|
|
.names u_cla16_xor1 u_cla16_out[1]
|
|
1 1
|
|
.names u_cla16_xor2 u_cla16_out[2]
|
|
1 1
|
|
.names u_cla16_xor3 u_cla16_out[3]
|
|
1 1
|
|
.names u_cla16_xor4 u_cla16_out[4]
|
|
1 1
|
|
.names u_cla16_xor5 u_cla16_out[5]
|
|
1 1
|
|
.names u_cla16_xor6 u_cla16_out[6]
|
|
1 1
|
|
.names u_cla16_xor7 u_cla16_out[7]
|
|
1 1
|
|
.names u_cla16_xor8 u_cla16_out[8]
|
|
1 1
|
|
.names u_cla16_xor9 u_cla16_out[9]
|
|
1 1
|
|
.names u_cla16_xor10 u_cla16_out[10]
|
|
1 1
|
|
.names u_cla16_xor11 u_cla16_out[11]
|
|
1 1
|
|
.names u_cla16_xor12 u_cla16_out[12]
|
|
1 1
|
|
.names u_cla16_xor13 u_cla16_out[13]
|
|
1 1
|
|
.names u_cla16_xor14 u_cla16_out[14]
|
|
1 1
|
|
.names u_cla16_xor15 u_cla16_out[15]
|
|
1 1
|
|
.names u_cla16_or35 u_cla16_out[16]
|
|
1 1
|
|
.end
|