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11 lines
249 B
Verilog
11 lines
249 B
Verilog
module f_ha(input a, input b, output f_ha_y0, output f_ha_y1);
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wire f_ha_a;
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wire f_ha_b;
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wire f_ha_y0;
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wire f_ha_y1;
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assign f_ha_a = a;
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assign f_ha_b = b;
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assign f_ha_y0 = f_ha_a ^ f_ha_b;
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assign f_ha_y1 = f_ha_a & f_ha_b;
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endmodule |