ariths-gen/generated_circuits/blif_circuits/hier/s_csamul_rca4.blif

.model s_csamul_rca4
.inputs a[0] a[1] a[2] a[3] b[0] b[1] b[2] b[3]
.outputs s_csamul_rca4_out[0] s_csamul_rca4_out[1] s_csamul_rca4_out[2] s_csamul_rca4_out[3] s_csamul_rca4_out[4] s_csamul_rca4_out[5] s_csamul_rca4_out[6] s_csamul_rca4_out[7]
.names vdd
1
.names gnd
0
.subckt and_gate a=a[0] b=b[0] out=s_csamul_rca4_and0_0
.subckt and_gate a=a[1] b=b[0] out=s_csamul_rca4_and1_0
.subckt and_gate a=a[2] b=b[0] out=s_csamul_rca4_and2_0
.subckt nand_gate a=a[3] b=b[0] out=s_csamul_rca4_nand3_0
.subckt and_gate a=a[0] b=b[1] out=s_csamul_rca4_and0_1
.subckt ha a=s_csamul_rca4_and0_1 b=s_csamul_rca4_and1_0 ha_xor0=s_csamul_rca4_ha0_1_xor0 ha_and0=s_csamul_rca4_ha0_1_and0
.subckt and_gate a=a[1] b=b[1] out=s_csamul_rca4_and1_1
.subckt ha a=s_csamul_rca4_and1_1 b=s_csamul_rca4_and2_0 ha_xor0=s_csamul_rca4_ha1_1_xor0 ha_and0=s_csamul_rca4_ha1_1_and0
.subckt and_gate a=a[2] b=b[1] out=s_csamul_rca4_and2_1
.subckt ha a=s_csamul_rca4_and2_1 b=s_csamul_rca4_nand3_0 ha_xor0=s_csamul_rca4_ha2_1_xor0 ha_and0=s_csamul_rca4_ha2_1_and0
.subckt nand_gate a=a[3] b=b[1] out=s_csamul_rca4_nand3_1
.subckt ha a=s_csamul_rca4_nand3_1 b=vdd ha_xor0=s_csamul_rca4_ha3_1_xor0 ha_and0=s_csamul_rca4_nand3_1
.subckt and_gate a=a[0] b=b[2] out=s_csamul_rca4_and0_2
.subckt fa a=s_csamul_rca4_and0_2 b=s_csamul_rca4_ha1_1_xor0 cin=s_csamul_rca4_ha0_1_and0 fa_xor1=s_csamul_rca4_fa0_2_xor1 fa_or0=s_csamul_rca4_fa0_2_or0
.subckt and_gate a=a[1] b=b[2] out=s_csamul_rca4_and1_2
.subckt fa a=s_csamul_rca4_and1_2 b=s_csamul_rca4_ha2_1_xor0 cin=s_csamul_rca4_ha1_1_and0 fa_xor1=s_csamul_rca4_fa1_2_xor1 fa_or0=s_csamul_rca4_fa1_2_or0
.subckt and_gate a=a[2] b=b[2] out=s_csamul_rca4_and2_2
.subckt fa a=s_csamul_rca4_and2_2 b=s_csamul_rca4_ha3_1_xor0 cin=s_csamul_rca4_ha2_1_and0 fa_xor1=s_csamul_rca4_fa2_2_xor1 fa_or0=s_csamul_rca4_fa2_2_or0
.subckt nand_gate a=a[3] b=b[2] out=s_csamul_rca4_nand3_2
.subckt ha a=s_csamul_rca4_nand3_2 b=s_csamul_rca4_nand3_1 ha_xor0=s_csamul_rca4_ha3_2_xor0 ha_and0=s_csamul_rca4_ha3_2_and0
.subckt nand_gate a=a[0] b=b[3] out=s_csamul_rca4_nand0_3
.subckt fa a=s_csamul_rca4_nand0_3 b=s_csamul_rca4_fa1_2_xor1 cin=s_csamul_rca4_fa0_2_or0 fa_xor1=s_csamul_rca4_fa0_3_xor1 fa_or0=s_csamul_rca4_fa0_3_or0
.subckt nand_gate a=a[1] b=b[3] out=s_csamul_rca4_nand1_3
.subckt fa a=s_csamul_rca4_nand1_3 b=s_csamul_rca4_fa2_2_xor1 cin=s_csamul_rca4_fa1_2_or0 fa_xor1=s_csamul_rca4_fa1_3_xor1 fa_or0=s_csamul_rca4_fa1_3_or0
.subckt nand_gate a=a[2] b=b[3] out=s_csamul_rca4_nand2_3
.subckt fa a=s_csamul_rca4_nand2_3 b=s_csamul_rca4_ha3_2_xor0 cin=s_csamul_rca4_fa2_2_or0 fa_xor1=s_csamul_rca4_fa2_3_xor1 fa_or0=s_csamul_rca4_fa2_3_or0
.subckt and_gate a=a[3] b=b[3] out=s_csamul_rca4_and3_3
.subckt ha a=s_csamul_rca4_and3_3 b=s_csamul_rca4_ha3_2_and0 ha_xor0=s_csamul_rca4_ha3_3_xor0 ha_and0=s_csamul_rca4_ha3_3_and0
.names s_csamul_rca4_fa1_3_xor1 s_csamul_rca4_u_rca4_a[0]
1 1
.names s_csamul_rca4_fa2_3_xor1 s_csamul_rca4_u_rca4_a[1]
1 1
.names s_csamul_rca4_ha3_3_xor0 s_csamul_rca4_u_rca4_a[2]
1 1
.names vdd s_csamul_rca4_u_rca4_a[3]
1 1
.names s_csamul_rca4_fa0_3_or0 s_csamul_rca4_u_rca4_b[0]
1 1
.names s_csamul_rca4_fa1_3_or0 s_csamul_rca4_u_rca4_b[1]
1 1
.names s_csamul_rca4_fa2_3_or0 s_csamul_rca4_u_rca4_b[2]
1 1
.names s_csamul_rca4_ha3_3_and0 s_csamul_rca4_u_rca4_b[3]
1 1
.subckt u_rca4 a[0]=s_csamul_rca4_u_rca4_a[0] a[1]=s_csamul_rca4_u_rca4_a[1] a[2]=s_csamul_rca4_u_rca4_a[2] a[3]=s_csamul_rca4_u_rca4_a[3] b[0]=s_csamul_rca4_u_rca4_b[0] b[1]=s_csamul_rca4_u_rca4_b[1] b[2]=s_csamul_rca4_u_rca4_b[2] b[3]=s_csamul_rca4_u_rca4_b[3] u_rca4_out[0]=s_csamul_rca4_u_rca4_ha_xor0 u_rca4_out[1]=s_csamul_rca4_u_rca4_fa1_xor1 u_rca4_out[2]=s_csamul_rca4_u_rca4_fa2_xor1 u_rca4_out[3]=s_csamul_rca4_u_rca4_fa3_xor1 u_rca4_out[4]=s_csamul_rca4_u_rca4_fa3_or0
.names s_csamul_rca4_and0_0 s_csamul_rca4_out[0]
1 1
.names s_csamul_rca4_ha0_1_xor0 s_csamul_rca4_out[1]
1 1
.names s_csamul_rca4_fa0_2_xor1 s_csamul_rca4_out[2]
1 1
.names s_csamul_rca4_fa0_3_xor1 s_csamul_rca4_out[3]
1 1
.names s_csamul_rca4_u_rca4_ha_xor0 s_csamul_rca4_out[4]
1 1
.names s_csamul_rca4_u_rca4_fa1_xor1 s_csamul_rca4_out[5]
1 1
.names s_csamul_rca4_u_rca4_fa2_xor1 s_csamul_rca4_out[6]
1 1
.names s_csamul_rca4_u_rca4_fa3_xor1 s_csamul_rca4_out[7]
1 1
.end

.model u_rca4
.inputs a[0] a[1] a[2] a[3] b[0] b[1] b[2] b[3]
.outputs u_rca4_out[0] u_rca4_out[1] u_rca4_out[2] u_rca4_out[3] u_rca4_out[4]
.names vdd
1
.names gnd
0
.subckt ha a=a[0] b=b[0] ha_xor0=u_rca4_ha_xor0 ha_and0=u_rca4_ha_and0
.subckt fa a=a[1] b=b[1] cin=u_rca4_ha_and0 fa_xor1=u_rca4_fa1_xor1 fa_or0=u_rca4_fa1_or0
.subckt fa a=a[2] b=b[2] cin=u_rca4_fa1_or0 fa_xor1=u_rca4_fa2_xor1 fa_or0=u_rca4_fa2_or0
.subckt fa a=a[3] b=b[3] cin=u_rca4_fa2_or0 fa_xor1=u_rca4_fa3_xor1 fa_or0=u_rca4_fa3_or0
.names u_rca4_ha_xor0 u_rca4_out[0]
1 1
.names u_rca4_fa1_xor1 u_rca4_out[1]
1 1
.names u_rca4_fa2_xor1 u_rca4_out[2]
1 1
.names u_rca4_fa3_xor1 u_rca4_out[3]
1 1
.names u_rca4_fa3_or0 u_rca4_out[4]
1 1
.end

.model fa
.inputs a b cin
.outputs fa_xor1 fa_or0
.names vdd
1
.names gnd
0
.subckt xor_gate a=a b=b out=fa_xor0
.subckt and_gate a=a b=b out=fa_and0
.subckt xor_gate a=fa_xor0 b=cin out=fa_xor1
.subckt and_gate a=fa_xor0 b=cin out=fa_and1
.subckt or_gate a=fa_and0 b=fa_and1 out=fa_or0
.end

.model ha
.inputs a b
.outputs ha_xor0 ha_and0
.names vdd
1
.names gnd
0
.subckt xor_gate a=a b=b out=ha_xor0
.subckt and_gate a=a b=b out=ha_and0
.end

.model or_gate
.inputs a b
.outputs out
.names vdd
1
.names gnd
0
.names a b out
1- 1
-1 1
.end

.model not_gate
.inputs a
.outputs out
.names vdd
1
.names gnd
0
.names a out
0 1
.end

.model xor_gate
.inputs a b
.outputs out
.names vdd
1
.names gnd
0
.names a b out
01 1
10 1
.end

.model nand_gate
.inputs a b
.outputs out
.names vdd
1
.names gnd
0
.names a b out
0- 1
-0 1
.end

.model and_gate
.inputs a b
.outputs out
.names vdd
1
.names gnd
0
.names a b out
11 1
.end