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911 lines
72 KiB
Plaintext
911 lines
72 KiB
Plaintext
.model s_csamul_cla16
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.inputs a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] a[8] a[9] a[10] a[11] a[12] a[13] a[14] a[15] b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9] b[10] b[11] b[12] b[13] b[14] b[15]
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.outputs s_csamul_cla16_out[0] s_csamul_cla16_out[1] s_csamul_cla16_out[2] s_csamul_cla16_out[3] s_csamul_cla16_out[4] s_csamul_cla16_out[5] s_csamul_cla16_out[6] s_csamul_cla16_out[7] s_csamul_cla16_out[8] s_csamul_cla16_out[9] s_csamul_cla16_out[10] s_csamul_cla16_out[11] s_csamul_cla16_out[12] s_csamul_cla16_out[13] s_csamul_cla16_out[14] s_csamul_cla16_out[15] s_csamul_cla16_out[16] s_csamul_cla16_out[17] s_csamul_cla16_out[18] s_csamul_cla16_out[19] s_csamul_cla16_out[20] s_csamul_cla16_out[21] s_csamul_cla16_out[22] s_csamul_cla16_out[23] s_csamul_cla16_out[24] s_csamul_cla16_out[25] s_csamul_cla16_out[26] s_csamul_cla16_out[27] s_csamul_cla16_out[28] s_csamul_cla16_out[29] s_csamul_cla16_out[30] s_csamul_cla16_out[31]
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.names vdd
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1
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.names gnd
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0
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.subckt and_gate a=a[0] b=b[0] out=s_csamul_cla16_and0_0
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.subckt and_gate a=a[1] b=b[0] out=s_csamul_cla16_and1_0
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.subckt and_gate a=a[2] b=b[0] out=s_csamul_cla16_and2_0
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.subckt and_gate a=a[3] b=b[0] out=s_csamul_cla16_and3_0
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.subckt and_gate a=a[4] b=b[0] out=s_csamul_cla16_and4_0
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.subckt and_gate a=a[5] b=b[0] out=s_csamul_cla16_and5_0
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.subckt and_gate a=a[6] b=b[0] out=s_csamul_cla16_and6_0
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.subckt and_gate a=a[7] b=b[0] out=s_csamul_cla16_and7_0
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.subckt and_gate a=a[8] b=b[0] out=s_csamul_cla16_and8_0
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.subckt and_gate a=a[9] b=b[0] out=s_csamul_cla16_and9_0
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.subckt and_gate a=a[10] b=b[0] out=s_csamul_cla16_and10_0
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.subckt and_gate a=a[11] b=b[0] out=s_csamul_cla16_and11_0
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.subckt and_gate a=a[12] b=b[0] out=s_csamul_cla16_and12_0
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.subckt and_gate a=a[13] b=b[0] out=s_csamul_cla16_and13_0
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.subckt and_gate a=a[14] b=b[0] out=s_csamul_cla16_and14_0
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.subckt nand_gate a=a[15] b=b[0] out=s_csamul_cla16_nand15_0
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.subckt and_gate a=a[0] b=b[1] out=s_csamul_cla16_and0_1
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.subckt ha a=s_csamul_cla16_and0_1 b=s_csamul_cla16_and1_0 ha_xor0=s_csamul_cla16_ha0_1_xor0 ha_and0=s_csamul_cla16_ha0_1_and0
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.subckt and_gate a=a[1] b=b[1] out=s_csamul_cla16_and1_1
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.subckt ha a=s_csamul_cla16_and1_1 b=s_csamul_cla16_and2_0 ha_xor0=s_csamul_cla16_ha1_1_xor0 ha_and0=s_csamul_cla16_ha1_1_and0
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.subckt and_gate a=a[2] b=b[1] out=s_csamul_cla16_and2_1
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.subckt ha a=s_csamul_cla16_and2_1 b=s_csamul_cla16_and3_0 ha_xor0=s_csamul_cla16_ha2_1_xor0 ha_and0=s_csamul_cla16_ha2_1_and0
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.subckt and_gate a=a[3] b=b[1] out=s_csamul_cla16_and3_1
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.subckt ha a=s_csamul_cla16_and3_1 b=s_csamul_cla16_and4_0 ha_xor0=s_csamul_cla16_ha3_1_xor0 ha_and0=s_csamul_cla16_ha3_1_and0
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.subckt and_gate a=a[4] b=b[1] out=s_csamul_cla16_and4_1
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.subckt ha a=s_csamul_cla16_and4_1 b=s_csamul_cla16_and5_0 ha_xor0=s_csamul_cla16_ha4_1_xor0 ha_and0=s_csamul_cla16_ha4_1_and0
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.subckt and_gate a=a[5] b=b[1] out=s_csamul_cla16_and5_1
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.subckt ha a=s_csamul_cla16_and5_1 b=s_csamul_cla16_and6_0 ha_xor0=s_csamul_cla16_ha5_1_xor0 ha_and0=s_csamul_cla16_ha5_1_and0
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.subckt and_gate a=a[6] b=b[1] out=s_csamul_cla16_and6_1
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.subckt ha a=s_csamul_cla16_and6_1 b=s_csamul_cla16_and7_0 ha_xor0=s_csamul_cla16_ha6_1_xor0 ha_and0=s_csamul_cla16_ha6_1_and0
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.subckt and_gate a=a[7] b=b[1] out=s_csamul_cla16_and7_1
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.subckt ha a=s_csamul_cla16_and7_1 b=s_csamul_cla16_and8_0 ha_xor0=s_csamul_cla16_ha7_1_xor0 ha_and0=s_csamul_cla16_ha7_1_and0
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.subckt and_gate a=a[8] b=b[1] out=s_csamul_cla16_and8_1
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.subckt ha a=s_csamul_cla16_and8_1 b=s_csamul_cla16_and9_0 ha_xor0=s_csamul_cla16_ha8_1_xor0 ha_and0=s_csamul_cla16_ha8_1_and0
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.subckt and_gate a=a[9] b=b[1] out=s_csamul_cla16_and9_1
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.subckt ha a=s_csamul_cla16_and9_1 b=s_csamul_cla16_and10_0 ha_xor0=s_csamul_cla16_ha9_1_xor0 ha_and0=s_csamul_cla16_ha9_1_and0
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.subckt and_gate a=a[10] b=b[1] out=s_csamul_cla16_and10_1
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.subckt ha a=s_csamul_cla16_and10_1 b=s_csamul_cla16_and11_0 ha_xor0=s_csamul_cla16_ha10_1_xor0 ha_and0=s_csamul_cla16_ha10_1_and0
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.subckt and_gate a=a[11] b=b[1] out=s_csamul_cla16_and11_1
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.subckt ha a=s_csamul_cla16_and11_1 b=s_csamul_cla16_and12_0 ha_xor0=s_csamul_cla16_ha11_1_xor0 ha_and0=s_csamul_cla16_ha11_1_and0
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.subckt and_gate a=a[12] b=b[1] out=s_csamul_cla16_and12_1
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.subckt ha a=s_csamul_cla16_and12_1 b=s_csamul_cla16_and13_0 ha_xor0=s_csamul_cla16_ha12_1_xor0 ha_and0=s_csamul_cla16_ha12_1_and0
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.subckt and_gate a=a[13] b=b[1] out=s_csamul_cla16_and13_1
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.subckt ha a=s_csamul_cla16_and13_1 b=s_csamul_cla16_and14_0 ha_xor0=s_csamul_cla16_ha13_1_xor0 ha_and0=s_csamul_cla16_ha13_1_and0
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.subckt and_gate a=a[14] b=b[1] out=s_csamul_cla16_and14_1
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.subckt ha a=s_csamul_cla16_and14_1 b=s_csamul_cla16_nand15_0 ha_xor0=s_csamul_cla16_ha14_1_xor0 ha_and0=s_csamul_cla16_ha14_1_and0
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.subckt nand_gate a=a[15] b=b[1] out=s_csamul_cla16_nand15_1
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.subckt ha a=s_csamul_cla16_nand15_1 b=vdd ha_xor0=s_csamul_cla16_ha15_1_xor0 ha_and0=s_csamul_cla16_nand15_1
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.subckt and_gate a=a[0] b=b[2] out=s_csamul_cla16_and0_2
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.subckt fa a=s_csamul_cla16_and0_2 b=s_csamul_cla16_ha1_1_xor0 cin=s_csamul_cla16_ha0_1_and0 fa_xor1=s_csamul_cla16_fa0_2_xor1 fa_or0=s_csamul_cla16_fa0_2_or0
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.subckt and_gate a=a[1] b=b[2] out=s_csamul_cla16_and1_2
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.subckt fa a=s_csamul_cla16_and1_2 b=s_csamul_cla16_ha2_1_xor0 cin=s_csamul_cla16_ha1_1_and0 fa_xor1=s_csamul_cla16_fa1_2_xor1 fa_or0=s_csamul_cla16_fa1_2_or0
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.subckt and_gate a=a[2] b=b[2] out=s_csamul_cla16_and2_2
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.subckt fa a=s_csamul_cla16_and2_2 b=s_csamul_cla16_ha3_1_xor0 cin=s_csamul_cla16_ha2_1_and0 fa_xor1=s_csamul_cla16_fa2_2_xor1 fa_or0=s_csamul_cla16_fa2_2_or0
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.subckt and_gate a=a[3] b=b[2] out=s_csamul_cla16_and3_2
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.subckt fa a=s_csamul_cla16_and3_2 b=s_csamul_cla16_ha4_1_xor0 cin=s_csamul_cla16_ha3_1_and0 fa_xor1=s_csamul_cla16_fa3_2_xor1 fa_or0=s_csamul_cla16_fa3_2_or0
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.subckt and_gate a=a[4] b=b[2] out=s_csamul_cla16_and4_2
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.subckt fa a=s_csamul_cla16_and4_2 b=s_csamul_cla16_ha5_1_xor0 cin=s_csamul_cla16_ha4_1_and0 fa_xor1=s_csamul_cla16_fa4_2_xor1 fa_or0=s_csamul_cla16_fa4_2_or0
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.subckt and_gate a=a[5] b=b[2] out=s_csamul_cla16_and5_2
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.subckt fa a=s_csamul_cla16_and5_2 b=s_csamul_cla16_ha6_1_xor0 cin=s_csamul_cla16_ha5_1_and0 fa_xor1=s_csamul_cla16_fa5_2_xor1 fa_or0=s_csamul_cla16_fa5_2_or0
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.subckt and_gate a=a[6] b=b[2] out=s_csamul_cla16_and6_2
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.subckt fa a=s_csamul_cla16_and6_2 b=s_csamul_cla16_ha7_1_xor0 cin=s_csamul_cla16_ha6_1_and0 fa_xor1=s_csamul_cla16_fa6_2_xor1 fa_or0=s_csamul_cla16_fa6_2_or0
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.subckt and_gate a=a[7] b=b[2] out=s_csamul_cla16_and7_2
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.subckt fa a=s_csamul_cla16_and7_2 b=s_csamul_cla16_ha8_1_xor0 cin=s_csamul_cla16_ha7_1_and0 fa_xor1=s_csamul_cla16_fa7_2_xor1 fa_or0=s_csamul_cla16_fa7_2_or0
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.subckt and_gate a=a[8] b=b[2] out=s_csamul_cla16_and8_2
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.subckt fa a=s_csamul_cla16_and8_2 b=s_csamul_cla16_ha9_1_xor0 cin=s_csamul_cla16_ha8_1_and0 fa_xor1=s_csamul_cla16_fa8_2_xor1 fa_or0=s_csamul_cla16_fa8_2_or0
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.subckt and_gate a=a[9] b=b[2] out=s_csamul_cla16_and9_2
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.subckt fa a=s_csamul_cla16_and9_2 b=s_csamul_cla16_ha10_1_xor0 cin=s_csamul_cla16_ha9_1_and0 fa_xor1=s_csamul_cla16_fa9_2_xor1 fa_or0=s_csamul_cla16_fa9_2_or0
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.subckt and_gate a=a[10] b=b[2] out=s_csamul_cla16_and10_2
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.subckt fa a=s_csamul_cla16_and10_2 b=s_csamul_cla16_ha11_1_xor0 cin=s_csamul_cla16_ha10_1_and0 fa_xor1=s_csamul_cla16_fa10_2_xor1 fa_or0=s_csamul_cla16_fa10_2_or0
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.subckt and_gate a=a[11] b=b[2] out=s_csamul_cla16_and11_2
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.subckt fa a=s_csamul_cla16_and11_2 b=s_csamul_cla16_ha12_1_xor0 cin=s_csamul_cla16_ha11_1_and0 fa_xor1=s_csamul_cla16_fa11_2_xor1 fa_or0=s_csamul_cla16_fa11_2_or0
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.subckt and_gate a=a[12] b=b[2] out=s_csamul_cla16_and12_2
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.subckt fa a=s_csamul_cla16_and12_2 b=s_csamul_cla16_ha13_1_xor0 cin=s_csamul_cla16_ha12_1_and0 fa_xor1=s_csamul_cla16_fa12_2_xor1 fa_or0=s_csamul_cla16_fa12_2_or0
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.subckt and_gate a=a[13] b=b[2] out=s_csamul_cla16_and13_2
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.subckt fa a=s_csamul_cla16_and13_2 b=s_csamul_cla16_ha14_1_xor0 cin=s_csamul_cla16_ha13_1_and0 fa_xor1=s_csamul_cla16_fa13_2_xor1 fa_or0=s_csamul_cla16_fa13_2_or0
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.subckt and_gate a=a[14] b=b[2] out=s_csamul_cla16_and14_2
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.subckt fa a=s_csamul_cla16_and14_2 b=s_csamul_cla16_ha15_1_xor0 cin=s_csamul_cla16_ha14_1_and0 fa_xor1=s_csamul_cla16_fa14_2_xor1 fa_or0=s_csamul_cla16_fa14_2_or0
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.subckt nand_gate a=a[15] b=b[2] out=s_csamul_cla16_nand15_2
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.subckt ha a=s_csamul_cla16_nand15_2 b=s_csamul_cla16_nand15_1 ha_xor0=s_csamul_cla16_ha15_2_xor0 ha_and0=s_csamul_cla16_ha15_2_and0
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.subckt and_gate a=a[0] b=b[3] out=s_csamul_cla16_and0_3
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.subckt fa a=s_csamul_cla16_and0_3 b=s_csamul_cla16_fa1_2_xor1 cin=s_csamul_cla16_fa0_2_or0 fa_xor1=s_csamul_cla16_fa0_3_xor1 fa_or0=s_csamul_cla16_fa0_3_or0
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.subckt and_gate a=a[1] b=b[3] out=s_csamul_cla16_and1_3
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.subckt fa a=s_csamul_cla16_and1_3 b=s_csamul_cla16_fa2_2_xor1 cin=s_csamul_cla16_fa1_2_or0 fa_xor1=s_csamul_cla16_fa1_3_xor1 fa_or0=s_csamul_cla16_fa1_3_or0
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.subckt and_gate a=a[2] b=b[3] out=s_csamul_cla16_and2_3
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.subckt fa a=s_csamul_cla16_and2_3 b=s_csamul_cla16_fa3_2_xor1 cin=s_csamul_cla16_fa2_2_or0 fa_xor1=s_csamul_cla16_fa2_3_xor1 fa_or0=s_csamul_cla16_fa2_3_or0
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.subckt and_gate a=a[3] b=b[3] out=s_csamul_cla16_and3_3
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.subckt fa a=s_csamul_cla16_and3_3 b=s_csamul_cla16_fa4_2_xor1 cin=s_csamul_cla16_fa3_2_or0 fa_xor1=s_csamul_cla16_fa3_3_xor1 fa_or0=s_csamul_cla16_fa3_3_or0
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.subckt and_gate a=a[4] b=b[3] out=s_csamul_cla16_and4_3
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.subckt fa a=s_csamul_cla16_and4_3 b=s_csamul_cla16_fa5_2_xor1 cin=s_csamul_cla16_fa4_2_or0 fa_xor1=s_csamul_cla16_fa4_3_xor1 fa_or0=s_csamul_cla16_fa4_3_or0
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.subckt and_gate a=a[5] b=b[3] out=s_csamul_cla16_and5_3
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.subckt fa a=s_csamul_cla16_and5_3 b=s_csamul_cla16_fa6_2_xor1 cin=s_csamul_cla16_fa5_2_or0 fa_xor1=s_csamul_cla16_fa5_3_xor1 fa_or0=s_csamul_cla16_fa5_3_or0
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.subckt and_gate a=a[6] b=b[3] out=s_csamul_cla16_and6_3
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.subckt fa a=s_csamul_cla16_and6_3 b=s_csamul_cla16_fa7_2_xor1 cin=s_csamul_cla16_fa6_2_or0 fa_xor1=s_csamul_cla16_fa6_3_xor1 fa_or0=s_csamul_cla16_fa6_3_or0
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.subckt and_gate a=a[7] b=b[3] out=s_csamul_cla16_and7_3
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.subckt fa a=s_csamul_cla16_and7_3 b=s_csamul_cla16_fa8_2_xor1 cin=s_csamul_cla16_fa7_2_or0 fa_xor1=s_csamul_cla16_fa7_3_xor1 fa_or0=s_csamul_cla16_fa7_3_or0
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.subckt and_gate a=a[8] b=b[3] out=s_csamul_cla16_and8_3
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.subckt fa a=s_csamul_cla16_and8_3 b=s_csamul_cla16_fa9_2_xor1 cin=s_csamul_cla16_fa8_2_or0 fa_xor1=s_csamul_cla16_fa8_3_xor1 fa_or0=s_csamul_cla16_fa8_3_or0
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.subckt and_gate a=a[9] b=b[3] out=s_csamul_cla16_and9_3
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.subckt fa a=s_csamul_cla16_and9_3 b=s_csamul_cla16_fa10_2_xor1 cin=s_csamul_cla16_fa9_2_or0 fa_xor1=s_csamul_cla16_fa9_3_xor1 fa_or0=s_csamul_cla16_fa9_3_or0
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.subckt and_gate a=a[10] b=b[3] out=s_csamul_cla16_and10_3
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.subckt fa a=s_csamul_cla16_and10_3 b=s_csamul_cla16_fa11_2_xor1 cin=s_csamul_cla16_fa10_2_or0 fa_xor1=s_csamul_cla16_fa10_3_xor1 fa_or0=s_csamul_cla16_fa10_3_or0
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.subckt and_gate a=a[11] b=b[3] out=s_csamul_cla16_and11_3
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.subckt fa a=s_csamul_cla16_and11_3 b=s_csamul_cla16_fa12_2_xor1 cin=s_csamul_cla16_fa11_2_or0 fa_xor1=s_csamul_cla16_fa11_3_xor1 fa_or0=s_csamul_cla16_fa11_3_or0
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.subckt and_gate a=a[12] b=b[3] out=s_csamul_cla16_and12_3
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.subckt fa a=s_csamul_cla16_and12_3 b=s_csamul_cla16_fa13_2_xor1 cin=s_csamul_cla16_fa12_2_or0 fa_xor1=s_csamul_cla16_fa12_3_xor1 fa_or0=s_csamul_cla16_fa12_3_or0
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.subckt and_gate a=a[13] b=b[3] out=s_csamul_cla16_and13_3
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.subckt fa a=s_csamul_cla16_and13_3 b=s_csamul_cla16_fa14_2_xor1 cin=s_csamul_cla16_fa13_2_or0 fa_xor1=s_csamul_cla16_fa13_3_xor1 fa_or0=s_csamul_cla16_fa13_3_or0
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.subckt and_gate a=a[14] b=b[3] out=s_csamul_cla16_and14_3
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.subckt fa a=s_csamul_cla16_and14_3 b=s_csamul_cla16_ha15_2_xor0 cin=s_csamul_cla16_fa14_2_or0 fa_xor1=s_csamul_cla16_fa14_3_xor1 fa_or0=s_csamul_cla16_fa14_3_or0
|
|
.subckt nand_gate a=a[15] b=b[3] out=s_csamul_cla16_nand15_3
|
|
.subckt ha a=s_csamul_cla16_nand15_3 b=s_csamul_cla16_ha15_2_and0 ha_xor0=s_csamul_cla16_ha15_3_xor0 ha_and0=s_csamul_cla16_ha15_3_and0
|
|
.subckt and_gate a=a[0] b=b[4] out=s_csamul_cla16_and0_4
|
|
.subckt fa a=s_csamul_cla16_and0_4 b=s_csamul_cla16_fa1_3_xor1 cin=s_csamul_cla16_fa0_3_or0 fa_xor1=s_csamul_cla16_fa0_4_xor1 fa_or0=s_csamul_cla16_fa0_4_or0
|
|
.subckt and_gate a=a[1] b=b[4] out=s_csamul_cla16_and1_4
|
|
.subckt fa a=s_csamul_cla16_and1_4 b=s_csamul_cla16_fa2_3_xor1 cin=s_csamul_cla16_fa1_3_or0 fa_xor1=s_csamul_cla16_fa1_4_xor1 fa_or0=s_csamul_cla16_fa1_4_or0
|
|
.subckt and_gate a=a[2] b=b[4] out=s_csamul_cla16_and2_4
|
|
.subckt fa a=s_csamul_cla16_and2_4 b=s_csamul_cla16_fa3_3_xor1 cin=s_csamul_cla16_fa2_3_or0 fa_xor1=s_csamul_cla16_fa2_4_xor1 fa_or0=s_csamul_cla16_fa2_4_or0
|
|
.subckt and_gate a=a[3] b=b[4] out=s_csamul_cla16_and3_4
|
|
.subckt fa a=s_csamul_cla16_and3_4 b=s_csamul_cla16_fa4_3_xor1 cin=s_csamul_cla16_fa3_3_or0 fa_xor1=s_csamul_cla16_fa3_4_xor1 fa_or0=s_csamul_cla16_fa3_4_or0
|
|
.subckt and_gate a=a[4] b=b[4] out=s_csamul_cla16_and4_4
|
|
.subckt fa a=s_csamul_cla16_and4_4 b=s_csamul_cla16_fa5_3_xor1 cin=s_csamul_cla16_fa4_3_or0 fa_xor1=s_csamul_cla16_fa4_4_xor1 fa_or0=s_csamul_cla16_fa4_4_or0
|
|
.subckt and_gate a=a[5] b=b[4] out=s_csamul_cla16_and5_4
|
|
.subckt fa a=s_csamul_cla16_and5_4 b=s_csamul_cla16_fa6_3_xor1 cin=s_csamul_cla16_fa5_3_or0 fa_xor1=s_csamul_cla16_fa5_4_xor1 fa_or0=s_csamul_cla16_fa5_4_or0
|
|
.subckt and_gate a=a[6] b=b[4] out=s_csamul_cla16_and6_4
|
|
.subckt fa a=s_csamul_cla16_and6_4 b=s_csamul_cla16_fa7_3_xor1 cin=s_csamul_cla16_fa6_3_or0 fa_xor1=s_csamul_cla16_fa6_4_xor1 fa_or0=s_csamul_cla16_fa6_4_or0
|
|
.subckt and_gate a=a[7] b=b[4] out=s_csamul_cla16_and7_4
|
|
.subckt fa a=s_csamul_cla16_and7_4 b=s_csamul_cla16_fa8_3_xor1 cin=s_csamul_cla16_fa7_3_or0 fa_xor1=s_csamul_cla16_fa7_4_xor1 fa_or0=s_csamul_cla16_fa7_4_or0
|
|
.subckt and_gate a=a[8] b=b[4] out=s_csamul_cla16_and8_4
|
|
.subckt fa a=s_csamul_cla16_and8_4 b=s_csamul_cla16_fa9_3_xor1 cin=s_csamul_cla16_fa8_3_or0 fa_xor1=s_csamul_cla16_fa8_4_xor1 fa_or0=s_csamul_cla16_fa8_4_or0
|
|
.subckt and_gate a=a[9] b=b[4] out=s_csamul_cla16_and9_4
|
|
.subckt fa a=s_csamul_cla16_and9_4 b=s_csamul_cla16_fa10_3_xor1 cin=s_csamul_cla16_fa9_3_or0 fa_xor1=s_csamul_cla16_fa9_4_xor1 fa_or0=s_csamul_cla16_fa9_4_or0
|
|
.subckt and_gate a=a[10] b=b[4] out=s_csamul_cla16_and10_4
|
|
.subckt fa a=s_csamul_cla16_and10_4 b=s_csamul_cla16_fa11_3_xor1 cin=s_csamul_cla16_fa10_3_or0 fa_xor1=s_csamul_cla16_fa10_4_xor1 fa_or0=s_csamul_cla16_fa10_4_or0
|
|
.subckt and_gate a=a[11] b=b[4] out=s_csamul_cla16_and11_4
|
|
.subckt fa a=s_csamul_cla16_and11_4 b=s_csamul_cla16_fa12_3_xor1 cin=s_csamul_cla16_fa11_3_or0 fa_xor1=s_csamul_cla16_fa11_4_xor1 fa_or0=s_csamul_cla16_fa11_4_or0
|
|
.subckt and_gate a=a[12] b=b[4] out=s_csamul_cla16_and12_4
|
|
.subckt fa a=s_csamul_cla16_and12_4 b=s_csamul_cla16_fa13_3_xor1 cin=s_csamul_cla16_fa12_3_or0 fa_xor1=s_csamul_cla16_fa12_4_xor1 fa_or0=s_csamul_cla16_fa12_4_or0
|
|
.subckt and_gate a=a[13] b=b[4] out=s_csamul_cla16_and13_4
|
|
.subckt fa a=s_csamul_cla16_and13_4 b=s_csamul_cla16_fa14_3_xor1 cin=s_csamul_cla16_fa13_3_or0 fa_xor1=s_csamul_cla16_fa13_4_xor1 fa_or0=s_csamul_cla16_fa13_4_or0
|
|
.subckt and_gate a=a[14] b=b[4] out=s_csamul_cla16_and14_4
|
|
.subckt fa a=s_csamul_cla16_and14_4 b=s_csamul_cla16_ha15_3_xor0 cin=s_csamul_cla16_fa14_3_or0 fa_xor1=s_csamul_cla16_fa14_4_xor1 fa_or0=s_csamul_cla16_fa14_4_or0
|
|
.subckt nand_gate a=a[15] b=b[4] out=s_csamul_cla16_nand15_4
|
|
.subckt ha a=s_csamul_cla16_nand15_4 b=s_csamul_cla16_ha15_3_and0 ha_xor0=s_csamul_cla16_ha15_4_xor0 ha_and0=s_csamul_cla16_ha15_4_and0
|
|
.subckt and_gate a=a[0] b=b[5] out=s_csamul_cla16_and0_5
|
|
.subckt fa a=s_csamul_cla16_and0_5 b=s_csamul_cla16_fa1_4_xor1 cin=s_csamul_cla16_fa0_4_or0 fa_xor1=s_csamul_cla16_fa0_5_xor1 fa_or0=s_csamul_cla16_fa0_5_or0
|
|
.subckt and_gate a=a[1] b=b[5] out=s_csamul_cla16_and1_5
|
|
.subckt fa a=s_csamul_cla16_and1_5 b=s_csamul_cla16_fa2_4_xor1 cin=s_csamul_cla16_fa1_4_or0 fa_xor1=s_csamul_cla16_fa1_5_xor1 fa_or0=s_csamul_cla16_fa1_5_or0
|
|
.subckt and_gate a=a[2] b=b[5] out=s_csamul_cla16_and2_5
|
|
.subckt fa a=s_csamul_cla16_and2_5 b=s_csamul_cla16_fa3_4_xor1 cin=s_csamul_cla16_fa2_4_or0 fa_xor1=s_csamul_cla16_fa2_5_xor1 fa_or0=s_csamul_cla16_fa2_5_or0
|
|
.subckt and_gate a=a[3] b=b[5] out=s_csamul_cla16_and3_5
|
|
.subckt fa a=s_csamul_cla16_and3_5 b=s_csamul_cla16_fa4_4_xor1 cin=s_csamul_cla16_fa3_4_or0 fa_xor1=s_csamul_cla16_fa3_5_xor1 fa_or0=s_csamul_cla16_fa3_5_or0
|
|
.subckt and_gate a=a[4] b=b[5] out=s_csamul_cla16_and4_5
|
|
.subckt fa a=s_csamul_cla16_and4_5 b=s_csamul_cla16_fa5_4_xor1 cin=s_csamul_cla16_fa4_4_or0 fa_xor1=s_csamul_cla16_fa4_5_xor1 fa_or0=s_csamul_cla16_fa4_5_or0
|
|
.subckt and_gate a=a[5] b=b[5] out=s_csamul_cla16_and5_5
|
|
.subckt fa a=s_csamul_cla16_and5_5 b=s_csamul_cla16_fa6_4_xor1 cin=s_csamul_cla16_fa5_4_or0 fa_xor1=s_csamul_cla16_fa5_5_xor1 fa_or0=s_csamul_cla16_fa5_5_or0
|
|
.subckt and_gate a=a[6] b=b[5] out=s_csamul_cla16_and6_5
|
|
.subckt fa a=s_csamul_cla16_and6_5 b=s_csamul_cla16_fa7_4_xor1 cin=s_csamul_cla16_fa6_4_or0 fa_xor1=s_csamul_cla16_fa6_5_xor1 fa_or0=s_csamul_cla16_fa6_5_or0
|
|
.subckt and_gate a=a[7] b=b[5] out=s_csamul_cla16_and7_5
|
|
.subckt fa a=s_csamul_cla16_and7_5 b=s_csamul_cla16_fa8_4_xor1 cin=s_csamul_cla16_fa7_4_or0 fa_xor1=s_csamul_cla16_fa7_5_xor1 fa_or0=s_csamul_cla16_fa7_5_or0
|
|
.subckt and_gate a=a[8] b=b[5] out=s_csamul_cla16_and8_5
|
|
.subckt fa a=s_csamul_cla16_and8_5 b=s_csamul_cla16_fa9_4_xor1 cin=s_csamul_cla16_fa8_4_or0 fa_xor1=s_csamul_cla16_fa8_5_xor1 fa_or0=s_csamul_cla16_fa8_5_or0
|
|
.subckt and_gate a=a[9] b=b[5] out=s_csamul_cla16_and9_5
|
|
.subckt fa a=s_csamul_cla16_and9_5 b=s_csamul_cla16_fa10_4_xor1 cin=s_csamul_cla16_fa9_4_or0 fa_xor1=s_csamul_cla16_fa9_5_xor1 fa_or0=s_csamul_cla16_fa9_5_or0
|
|
.subckt and_gate a=a[10] b=b[5] out=s_csamul_cla16_and10_5
|
|
.subckt fa a=s_csamul_cla16_and10_5 b=s_csamul_cla16_fa11_4_xor1 cin=s_csamul_cla16_fa10_4_or0 fa_xor1=s_csamul_cla16_fa10_5_xor1 fa_or0=s_csamul_cla16_fa10_5_or0
|
|
.subckt and_gate a=a[11] b=b[5] out=s_csamul_cla16_and11_5
|
|
.subckt fa a=s_csamul_cla16_and11_5 b=s_csamul_cla16_fa12_4_xor1 cin=s_csamul_cla16_fa11_4_or0 fa_xor1=s_csamul_cla16_fa11_5_xor1 fa_or0=s_csamul_cla16_fa11_5_or0
|
|
.subckt and_gate a=a[12] b=b[5] out=s_csamul_cla16_and12_5
|
|
.subckt fa a=s_csamul_cla16_and12_5 b=s_csamul_cla16_fa13_4_xor1 cin=s_csamul_cla16_fa12_4_or0 fa_xor1=s_csamul_cla16_fa12_5_xor1 fa_or0=s_csamul_cla16_fa12_5_or0
|
|
.subckt and_gate a=a[13] b=b[5] out=s_csamul_cla16_and13_5
|
|
.subckt fa a=s_csamul_cla16_and13_5 b=s_csamul_cla16_fa14_4_xor1 cin=s_csamul_cla16_fa13_4_or0 fa_xor1=s_csamul_cla16_fa13_5_xor1 fa_or0=s_csamul_cla16_fa13_5_or0
|
|
.subckt and_gate a=a[14] b=b[5] out=s_csamul_cla16_and14_5
|
|
.subckt fa a=s_csamul_cla16_and14_5 b=s_csamul_cla16_ha15_4_xor0 cin=s_csamul_cla16_fa14_4_or0 fa_xor1=s_csamul_cla16_fa14_5_xor1 fa_or0=s_csamul_cla16_fa14_5_or0
|
|
.subckt nand_gate a=a[15] b=b[5] out=s_csamul_cla16_nand15_5
|
|
.subckt ha a=s_csamul_cla16_nand15_5 b=s_csamul_cla16_ha15_4_and0 ha_xor0=s_csamul_cla16_ha15_5_xor0 ha_and0=s_csamul_cla16_ha15_5_and0
|
|
.subckt and_gate a=a[0] b=b[6] out=s_csamul_cla16_and0_6
|
|
.subckt fa a=s_csamul_cla16_and0_6 b=s_csamul_cla16_fa1_5_xor1 cin=s_csamul_cla16_fa0_5_or0 fa_xor1=s_csamul_cla16_fa0_6_xor1 fa_or0=s_csamul_cla16_fa0_6_or0
|
|
.subckt and_gate a=a[1] b=b[6] out=s_csamul_cla16_and1_6
|
|
.subckt fa a=s_csamul_cla16_and1_6 b=s_csamul_cla16_fa2_5_xor1 cin=s_csamul_cla16_fa1_5_or0 fa_xor1=s_csamul_cla16_fa1_6_xor1 fa_or0=s_csamul_cla16_fa1_6_or0
|
|
.subckt and_gate a=a[2] b=b[6] out=s_csamul_cla16_and2_6
|
|
.subckt fa a=s_csamul_cla16_and2_6 b=s_csamul_cla16_fa3_5_xor1 cin=s_csamul_cla16_fa2_5_or0 fa_xor1=s_csamul_cla16_fa2_6_xor1 fa_or0=s_csamul_cla16_fa2_6_or0
|
|
.subckt and_gate a=a[3] b=b[6] out=s_csamul_cla16_and3_6
|
|
.subckt fa a=s_csamul_cla16_and3_6 b=s_csamul_cla16_fa4_5_xor1 cin=s_csamul_cla16_fa3_5_or0 fa_xor1=s_csamul_cla16_fa3_6_xor1 fa_or0=s_csamul_cla16_fa3_6_or0
|
|
.subckt and_gate a=a[4] b=b[6] out=s_csamul_cla16_and4_6
|
|
.subckt fa a=s_csamul_cla16_and4_6 b=s_csamul_cla16_fa5_5_xor1 cin=s_csamul_cla16_fa4_5_or0 fa_xor1=s_csamul_cla16_fa4_6_xor1 fa_or0=s_csamul_cla16_fa4_6_or0
|
|
.subckt and_gate a=a[5] b=b[6] out=s_csamul_cla16_and5_6
|
|
.subckt fa a=s_csamul_cla16_and5_6 b=s_csamul_cla16_fa6_5_xor1 cin=s_csamul_cla16_fa5_5_or0 fa_xor1=s_csamul_cla16_fa5_6_xor1 fa_or0=s_csamul_cla16_fa5_6_or0
|
|
.subckt and_gate a=a[6] b=b[6] out=s_csamul_cla16_and6_6
|
|
.subckt fa a=s_csamul_cla16_and6_6 b=s_csamul_cla16_fa7_5_xor1 cin=s_csamul_cla16_fa6_5_or0 fa_xor1=s_csamul_cla16_fa6_6_xor1 fa_or0=s_csamul_cla16_fa6_6_or0
|
|
.subckt and_gate a=a[7] b=b[6] out=s_csamul_cla16_and7_6
|
|
.subckt fa a=s_csamul_cla16_and7_6 b=s_csamul_cla16_fa8_5_xor1 cin=s_csamul_cla16_fa7_5_or0 fa_xor1=s_csamul_cla16_fa7_6_xor1 fa_or0=s_csamul_cla16_fa7_6_or0
|
|
.subckt and_gate a=a[8] b=b[6] out=s_csamul_cla16_and8_6
|
|
.subckt fa a=s_csamul_cla16_and8_6 b=s_csamul_cla16_fa9_5_xor1 cin=s_csamul_cla16_fa8_5_or0 fa_xor1=s_csamul_cla16_fa8_6_xor1 fa_or0=s_csamul_cla16_fa8_6_or0
|
|
.subckt and_gate a=a[9] b=b[6] out=s_csamul_cla16_and9_6
|
|
.subckt fa a=s_csamul_cla16_and9_6 b=s_csamul_cla16_fa10_5_xor1 cin=s_csamul_cla16_fa9_5_or0 fa_xor1=s_csamul_cla16_fa9_6_xor1 fa_or0=s_csamul_cla16_fa9_6_or0
|
|
.subckt and_gate a=a[10] b=b[6] out=s_csamul_cla16_and10_6
|
|
.subckt fa a=s_csamul_cla16_and10_6 b=s_csamul_cla16_fa11_5_xor1 cin=s_csamul_cla16_fa10_5_or0 fa_xor1=s_csamul_cla16_fa10_6_xor1 fa_or0=s_csamul_cla16_fa10_6_or0
|
|
.subckt and_gate a=a[11] b=b[6] out=s_csamul_cla16_and11_6
|
|
.subckt fa a=s_csamul_cla16_and11_6 b=s_csamul_cla16_fa12_5_xor1 cin=s_csamul_cla16_fa11_5_or0 fa_xor1=s_csamul_cla16_fa11_6_xor1 fa_or0=s_csamul_cla16_fa11_6_or0
|
|
.subckt and_gate a=a[12] b=b[6] out=s_csamul_cla16_and12_6
|
|
.subckt fa a=s_csamul_cla16_and12_6 b=s_csamul_cla16_fa13_5_xor1 cin=s_csamul_cla16_fa12_5_or0 fa_xor1=s_csamul_cla16_fa12_6_xor1 fa_or0=s_csamul_cla16_fa12_6_or0
|
|
.subckt and_gate a=a[13] b=b[6] out=s_csamul_cla16_and13_6
|
|
.subckt fa a=s_csamul_cla16_and13_6 b=s_csamul_cla16_fa14_5_xor1 cin=s_csamul_cla16_fa13_5_or0 fa_xor1=s_csamul_cla16_fa13_6_xor1 fa_or0=s_csamul_cla16_fa13_6_or0
|
|
.subckt and_gate a=a[14] b=b[6] out=s_csamul_cla16_and14_6
|
|
.subckt fa a=s_csamul_cla16_and14_6 b=s_csamul_cla16_ha15_5_xor0 cin=s_csamul_cla16_fa14_5_or0 fa_xor1=s_csamul_cla16_fa14_6_xor1 fa_or0=s_csamul_cla16_fa14_6_or0
|
|
.subckt nand_gate a=a[15] b=b[6] out=s_csamul_cla16_nand15_6
|
|
.subckt ha a=s_csamul_cla16_nand15_6 b=s_csamul_cla16_ha15_5_and0 ha_xor0=s_csamul_cla16_ha15_6_xor0 ha_and0=s_csamul_cla16_ha15_6_and0
|
|
.subckt and_gate a=a[0] b=b[7] out=s_csamul_cla16_and0_7
|
|
.subckt fa a=s_csamul_cla16_and0_7 b=s_csamul_cla16_fa1_6_xor1 cin=s_csamul_cla16_fa0_6_or0 fa_xor1=s_csamul_cla16_fa0_7_xor1 fa_or0=s_csamul_cla16_fa0_7_or0
|
|
.subckt and_gate a=a[1] b=b[7] out=s_csamul_cla16_and1_7
|
|
.subckt fa a=s_csamul_cla16_and1_7 b=s_csamul_cla16_fa2_6_xor1 cin=s_csamul_cla16_fa1_6_or0 fa_xor1=s_csamul_cla16_fa1_7_xor1 fa_or0=s_csamul_cla16_fa1_7_or0
|
|
.subckt and_gate a=a[2] b=b[7] out=s_csamul_cla16_and2_7
|
|
.subckt fa a=s_csamul_cla16_and2_7 b=s_csamul_cla16_fa3_6_xor1 cin=s_csamul_cla16_fa2_6_or0 fa_xor1=s_csamul_cla16_fa2_7_xor1 fa_or0=s_csamul_cla16_fa2_7_or0
|
|
.subckt and_gate a=a[3] b=b[7] out=s_csamul_cla16_and3_7
|
|
.subckt fa a=s_csamul_cla16_and3_7 b=s_csamul_cla16_fa4_6_xor1 cin=s_csamul_cla16_fa3_6_or0 fa_xor1=s_csamul_cla16_fa3_7_xor1 fa_or0=s_csamul_cla16_fa3_7_or0
|
|
.subckt and_gate a=a[4] b=b[7] out=s_csamul_cla16_and4_7
|
|
.subckt fa a=s_csamul_cla16_and4_7 b=s_csamul_cla16_fa5_6_xor1 cin=s_csamul_cla16_fa4_6_or0 fa_xor1=s_csamul_cla16_fa4_7_xor1 fa_or0=s_csamul_cla16_fa4_7_or0
|
|
.subckt and_gate a=a[5] b=b[7] out=s_csamul_cla16_and5_7
|
|
.subckt fa a=s_csamul_cla16_and5_7 b=s_csamul_cla16_fa6_6_xor1 cin=s_csamul_cla16_fa5_6_or0 fa_xor1=s_csamul_cla16_fa5_7_xor1 fa_or0=s_csamul_cla16_fa5_7_or0
|
|
.subckt and_gate a=a[6] b=b[7] out=s_csamul_cla16_and6_7
|
|
.subckt fa a=s_csamul_cla16_and6_7 b=s_csamul_cla16_fa7_6_xor1 cin=s_csamul_cla16_fa6_6_or0 fa_xor1=s_csamul_cla16_fa6_7_xor1 fa_or0=s_csamul_cla16_fa6_7_or0
|
|
.subckt and_gate a=a[7] b=b[7] out=s_csamul_cla16_and7_7
|
|
.subckt fa a=s_csamul_cla16_and7_7 b=s_csamul_cla16_fa8_6_xor1 cin=s_csamul_cla16_fa7_6_or0 fa_xor1=s_csamul_cla16_fa7_7_xor1 fa_or0=s_csamul_cla16_fa7_7_or0
|
|
.subckt and_gate a=a[8] b=b[7] out=s_csamul_cla16_and8_7
|
|
.subckt fa a=s_csamul_cla16_and8_7 b=s_csamul_cla16_fa9_6_xor1 cin=s_csamul_cla16_fa8_6_or0 fa_xor1=s_csamul_cla16_fa8_7_xor1 fa_or0=s_csamul_cla16_fa8_7_or0
|
|
.subckt and_gate a=a[9] b=b[7] out=s_csamul_cla16_and9_7
|
|
.subckt fa a=s_csamul_cla16_and9_7 b=s_csamul_cla16_fa10_6_xor1 cin=s_csamul_cla16_fa9_6_or0 fa_xor1=s_csamul_cla16_fa9_7_xor1 fa_or0=s_csamul_cla16_fa9_7_or0
|
|
.subckt and_gate a=a[10] b=b[7] out=s_csamul_cla16_and10_7
|
|
.subckt fa a=s_csamul_cla16_and10_7 b=s_csamul_cla16_fa11_6_xor1 cin=s_csamul_cla16_fa10_6_or0 fa_xor1=s_csamul_cla16_fa10_7_xor1 fa_or0=s_csamul_cla16_fa10_7_or0
|
|
.subckt and_gate a=a[11] b=b[7] out=s_csamul_cla16_and11_7
|
|
.subckt fa a=s_csamul_cla16_and11_7 b=s_csamul_cla16_fa12_6_xor1 cin=s_csamul_cla16_fa11_6_or0 fa_xor1=s_csamul_cla16_fa11_7_xor1 fa_or0=s_csamul_cla16_fa11_7_or0
|
|
.subckt and_gate a=a[12] b=b[7] out=s_csamul_cla16_and12_7
|
|
.subckt fa a=s_csamul_cla16_and12_7 b=s_csamul_cla16_fa13_6_xor1 cin=s_csamul_cla16_fa12_6_or0 fa_xor1=s_csamul_cla16_fa12_7_xor1 fa_or0=s_csamul_cla16_fa12_7_or0
|
|
.subckt and_gate a=a[13] b=b[7] out=s_csamul_cla16_and13_7
|
|
.subckt fa a=s_csamul_cla16_and13_7 b=s_csamul_cla16_fa14_6_xor1 cin=s_csamul_cla16_fa13_6_or0 fa_xor1=s_csamul_cla16_fa13_7_xor1 fa_or0=s_csamul_cla16_fa13_7_or0
|
|
.subckt and_gate a=a[14] b=b[7] out=s_csamul_cla16_and14_7
|
|
.subckt fa a=s_csamul_cla16_and14_7 b=s_csamul_cla16_ha15_6_xor0 cin=s_csamul_cla16_fa14_6_or0 fa_xor1=s_csamul_cla16_fa14_7_xor1 fa_or0=s_csamul_cla16_fa14_7_or0
|
|
.subckt nand_gate a=a[15] b=b[7] out=s_csamul_cla16_nand15_7
|
|
.subckt ha a=s_csamul_cla16_nand15_7 b=s_csamul_cla16_ha15_6_and0 ha_xor0=s_csamul_cla16_ha15_7_xor0 ha_and0=s_csamul_cla16_ha15_7_and0
|
|
.subckt and_gate a=a[0] b=b[8] out=s_csamul_cla16_and0_8
|
|
.subckt fa a=s_csamul_cla16_and0_8 b=s_csamul_cla16_fa1_7_xor1 cin=s_csamul_cla16_fa0_7_or0 fa_xor1=s_csamul_cla16_fa0_8_xor1 fa_or0=s_csamul_cla16_fa0_8_or0
|
|
.subckt and_gate a=a[1] b=b[8] out=s_csamul_cla16_and1_8
|
|
.subckt fa a=s_csamul_cla16_and1_8 b=s_csamul_cla16_fa2_7_xor1 cin=s_csamul_cla16_fa1_7_or0 fa_xor1=s_csamul_cla16_fa1_8_xor1 fa_or0=s_csamul_cla16_fa1_8_or0
|
|
.subckt and_gate a=a[2] b=b[8] out=s_csamul_cla16_and2_8
|
|
.subckt fa a=s_csamul_cla16_and2_8 b=s_csamul_cla16_fa3_7_xor1 cin=s_csamul_cla16_fa2_7_or0 fa_xor1=s_csamul_cla16_fa2_8_xor1 fa_or0=s_csamul_cla16_fa2_8_or0
|
|
.subckt and_gate a=a[3] b=b[8] out=s_csamul_cla16_and3_8
|
|
.subckt fa a=s_csamul_cla16_and3_8 b=s_csamul_cla16_fa4_7_xor1 cin=s_csamul_cla16_fa3_7_or0 fa_xor1=s_csamul_cla16_fa3_8_xor1 fa_or0=s_csamul_cla16_fa3_8_or0
|
|
.subckt and_gate a=a[4] b=b[8] out=s_csamul_cla16_and4_8
|
|
.subckt fa a=s_csamul_cla16_and4_8 b=s_csamul_cla16_fa5_7_xor1 cin=s_csamul_cla16_fa4_7_or0 fa_xor1=s_csamul_cla16_fa4_8_xor1 fa_or0=s_csamul_cla16_fa4_8_or0
|
|
.subckt and_gate a=a[5] b=b[8] out=s_csamul_cla16_and5_8
|
|
.subckt fa a=s_csamul_cla16_and5_8 b=s_csamul_cla16_fa6_7_xor1 cin=s_csamul_cla16_fa5_7_or0 fa_xor1=s_csamul_cla16_fa5_8_xor1 fa_or0=s_csamul_cla16_fa5_8_or0
|
|
.subckt and_gate a=a[6] b=b[8] out=s_csamul_cla16_and6_8
|
|
.subckt fa a=s_csamul_cla16_and6_8 b=s_csamul_cla16_fa7_7_xor1 cin=s_csamul_cla16_fa6_7_or0 fa_xor1=s_csamul_cla16_fa6_8_xor1 fa_or0=s_csamul_cla16_fa6_8_or0
|
|
.subckt and_gate a=a[7] b=b[8] out=s_csamul_cla16_and7_8
|
|
.subckt fa a=s_csamul_cla16_and7_8 b=s_csamul_cla16_fa8_7_xor1 cin=s_csamul_cla16_fa7_7_or0 fa_xor1=s_csamul_cla16_fa7_8_xor1 fa_or0=s_csamul_cla16_fa7_8_or0
|
|
.subckt and_gate a=a[8] b=b[8] out=s_csamul_cla16_and8_8
|
|
.subckt fa a=s_csamul_cla16_and8_8 b=s_csamul_cla16_fa9_7_xor1 cin=s_csamul_cla16_fa8_7_or0 fa_xor1=s_csamul_cla16_fa8_8_xor1 fa_or0=s_csamul_cla16_fa8_8_or0
|
|
.subckt and_gate a=a[9] b=b[8] out=s_csamul_cla16_and9_8
|
|
.subckt fa a=s_csamul_cla16_and9_8 b=s_csamul_cla16_fa10_7_xor1 cin=s_csamul_cla16_fa9_7_or0 fa_xor1=s_csamul_cla16_fa9_8_xor1 fa_or0=s_csamul_cla16_fa9_8_or0
|
|
.subckt and_gate a=a[10] b=b[8] out=s_csamul_cla16_and10_8
|
|
.subckt fa a=s_csamul_cla16_and10_8 b=s_csamul_cla16_fa11_7_xor1 cin=s_csamul_cla16_fa10_7_or0 fa_xor1=s_csamul_cla16_fa10_8_xor1 fa_or0=s_csamul_cla16_fa10_8_or0
|
|
.subckt and_gate a=a[11] b=b[8] out=s_csamul_cla16_and11_8
|
|
.subckt fa a=s_csamul_cla16_and11_8 b=s_csamul_cla16_fa12_7_xor1 cin=s_csamul_cla16_fa11_7_or0 fa_xor1=s_csamul_cla16_fa11_8_xor1 fa_or0=s_csamul_cla16_fa11_8_or0
|
|
.subckt and_gate a=a[12] b=b[8] out=s_csamul_cla16_and12_8
|
|
.subckt fa a=s_csamul_cla16_and12_8 b=s_csamul_cla16_fa13_7_xor1 cin=s_csamul_cla16_fa12_7_or0 fa_xor1=s_csamul_cla16_fa12_8_xor1 fa_or0=s_csamul_cla16_fa12_8_or0
|
|
.subckt and_gate a=a[13] b=b[8] out=s_csamul_cla16_and13_8
|
|
.subckt fa a=s_csamul_cla16_and13_8 b=s_csamul_cla16_fa14_7_xor1 cin=s_csamul_cla16_fa13_7_or0 fa_xor1=s_csamul_cla16_fa13_8_xor1 fa_or0=s_csamul_cla16_fa13_8_or0
|
|
.subckt and_gate a=a[14] b=b[8] out=s_csamul_cla16_and14_8
|
|
.subckt fa a=s_csamul_cla16_and14_8 b=s_csamul_cla16_ha15_7_xor0 cin=s_csamul_cla16_fa14_7_or0 fa_xor1=s_csamul_cla16_fa14_8_xor1 fa_or0=s_csamul_cla16_fa14_8_or0
|
|
.subckt nand_gate a=a[15] b=b[8] out=s_csamul_cla16_nand15_8
|
|
.subckt ha a=s_csamul_cla16_nand15_8 b=s_csamul_cla16_ha15_7_and0 ha_xor0=s_csamul_cla16_ha15_8_xor0 ha_and0=s_csamul_cla16_ha15_8_and0
|
|
.subckt and_gate a=a[0] b=b[9] out=s_csamul_cla16_and0_9
|
|
.subckt fa a=s_csamul_cla16_and0_9 b=s_csamul_cla16_fa1_8_xor1 cin=s_csamul_cla16_fa0_8_or0 fa_xor1=s_csamul_cla16_fa0_9_xor1 fa_or0=s_csamul_cla16_fa0_9_or0
|
|
.subckt and_gate a=a[1] b=b[9] out=s_csamul_cla16_and1_9
|
|
.subckt fa a=s_csamul_cla16_and1_9 b=s_csamul_cla16_fa2_8_xor1 cin=s_csamul_cla16_fa1_8_or0 fa_xor1=s_csamul_cla16_fa1_9_xor1 fa_or0=s_csamul_cla16_fa1_9_or0
|
|
.subckt and_gate a=a[2] b=b[9] out=s_csamul_cla16_and2_9
|
|
.subckt fa a=s_csamul_cla16_and2_9 b=s_csamul_cla16_fa3_8_xor1 cin=s_csamul_cla16_fa2_8_or0 fa_xor1=s_csamul_cla16_fa2_9_xor1 fa_or0=s_csamul_cla16_fa2_9_or0
|
|
.subckt and_gate a=a[3] b=b[9] out=s_csamul_cla16_and3_9
|
|
.subckt fa a=s_csamul_cla16_and3_9 b=s_csamul_cla16_fa4_8_xor1 cin=s_csamul_cla16_fa3_8_or0 fa_xor1=s_csamul_cla16_fa3_9_xor1 fa_or0=s_csamul_cla16_fa3_9_or0
|
|
.subckt and_gate a=a[4] b=b[9] out=s_csamul_cla16_and4_9
|
|
.subckt fa a=s_csamul_cla16_and4_9 b=s_csamul_cla16_fa5_8_xor1 cin=s_csamul_cla16_fa4_8_or0 fa_xor1=s_csamul_cla16_fa4_9_xor1 fa_or0=s_csamul_cla16_fa4_9_or0
|
|
.subckt and_gate a=a[5] b=b[9] out=s_csamul_cla16_and5_9
|
|
.subckt fa a=s_csamul_cla16_and5_9 b=s_csamul_cla16_fa6_8_xor1 cin=s_csamul_cla16_fa5_8_or0 fa_xor1=s_csamul_cla16_fa5_9_xor1 fa_or0=s_csamul_cla16_fa5_9_or0
|
|
.subckt and_gate a=a[6] b=b[9] out=s_csamul_cla16_and6_9
|
|
.subckt fa a=s_csamul_cla16_and6_9 b=s_csamul_cla16_fa7_8_xor1 cin=s_csamul_cla16_fa6_8_or0 fa_xor1=s_csamul_cla16_fa6_9_xor1 fa_or0=s_csamul_cla16_fa6_9_or0
|
|
.subckt and_gate a=a[7] b=b[9] out=s_csamul_cla16_and7_9
|
|
.subckt fa a=s_csamul_cla16_and7_9 b=s_csamul_cla16_fa8_8_xor1 cin=s_csamul_cla16_fa7_8_or0 fa_xor1=s_csamul_cla16_fa7_9_xor1 fa_or0=s_csamul_cla16_fa7_9_or0
|
|
.subckt and_gate a=a[8] b=b[9] out=s_csamul_cla16_and8_9
|
|
.subckt fa a=s_csamul_cla16_and8_9 b=s_csamul_cla16_fa9_8_xor1 cin=s_csamul_cla16_fa8_8_or0 fa_xor1=s_csamul_cla16_fa8_9_xor1 fa_or0=s_csamul_cla16_fa8_9_or0
|
|
.subckt and_gate a=a[9] b=b[9] out=s_csamul_cla16_and9_9
|
|
.subckt fa a=s_csamul_cla16_and9_9 b=s_csamul_cla16_fa10_8_xor1 cin=s_csamul_cla16_fa9_8_or0 fa_xor1=s_csamul_cla16_fa9_9_xor1 fa_or0=s_csamul_cla16_fa9_9_or0
|
|
.subckt and_gate a=a[10] b=b[9] out=s_csamul_cla16_and10_9
|
|
.subckt fa a=s_csamul_cla16_and10_9 b=s_csamul_cla16_fa11_8_xor1 cin=s_csamul_cla16_fa10_8_or0 fa_xor1=s_csamul_cla16_fa10_9_xor1 fa_or0=s_csamul_cla16_fa10_9_or0
|
|
.subckt and_gate a=a[11] b=b[9] out=s_csamul_cla16_and11_9
|
|
.subckt fa a=s_csamul_cla16_and11_9 b=s_csamul_cla16_fa12_8_xor1 cin=s_csamul_cla16_fa11_8_or0 fa_xor1=s_csamul_cla16_fa11_9_xor1 fa_or0=s_csamul_cla16_fa11_9_or0
|
|
.subckt and_gate a=a[12] b=b[9] out=s_csamul_cla16_and12_9
|
|
.subckt fa a=s_csamul_cla16_and12_9 b=s_csamul_cla16_fa13_8_xor1 cin=s_csamul_cla16_fa12_8_or0 fa_xor1=s_csamul_cla16_fa12_9_xor1 fa_or0=s_csamul_cla16_fa12_9_or0
|
|
.subckt and_gate a=a[13] b=b[9] out=s_csamul_cla16_and13_9
|
|
.subckt fa a=s_csamul_cla16_and13_9 b=s_csamul_cla16_fa14_8_xor1 cin=s_csamul_cla16_fa13_8_or0 fa_xor1=s_csamul_cla16_fa13_9_xor1 fa_or0=s_csamul_cla16_fa13_9_or0
|
|
.subckt and_gate a=a[14] b=b[9] out=s_csamul_cla16_and14_9
|
|
.subckt fa a=s_csamul_cla16_and14_9 b=s_csamul_cla16_ha15_8_xor0 cin=s_csamul_cla16_fa14_8_or0 fa_xor1=s_csamul_cla16_fa14_9_xor1 fa_or0=s_csamul_cla16_fa14_9_or0
|
|
.subckt nand_gate a=a[15] b=b[9] out=s_csamul_cla16_nand15_9
|
|
.subckt ha a=s_csamul_cla16_nand15_9 b=s_csamul_cla16_ha15_8_and0 ha_xor0=s_csamul_cla16_ha15_9_xor0 ha_and0=s_csamul_cla16_ha15_9_and0
|
|
.subckt and_gate a=a[0] b=b[10] out=s_csamul_cla16_and0_10
|
|
.subckt fa a=s_csamul_cla16_and0_10 b=s_csamul_cla16_fa1_9_xor1 cin=s_csamul_cla16_fa0_9_or0 fa_xor1=s_csamul_cla16_fa0_10_xor1 fa_or0=s_csamul_cla16_fa0_10_or0
|
|
.subckt and_gate a=a[1] b=b[10] out=s_csamul_cla16_and1_10
|
|
.subckt fa a=s_csamul_cla16_and1_10 b=s_csamul_cla16_fa2_9_xor1 cin=s_csamul_cla16_fa1_9_or0 fa_xor1=s_csamul_cla16_fa1_10_xor1 fa_or0=s_csamul_cla16_fa1_10_or0
|
|
.subckt and_gate a=a[2] b=b[10] out=s_csamul_cla16_and2_10
|
|
.subckt fa a=s_csamul_cla16_and2_10 b=s_csamul_cla16_fa3_9_xor1 cin=s_csamul_cla16_fa2_9_or0 fa_xor1=s_csamul_cla16_fa2_10_xor1 fa_or0=s_csamul_cla16_fa2_10_or0
|
|
.subckt and_gate a=a[3] b=b[10] out=s_csamul_cla16_and3_10
|
|
.subckt fa a=s_csamul_cla16_and3_10 b=s_csamul_cla16_fa4_9_xor1 cin=s_csamul_cla16_fa3_9_or0 fa_xor1=s_csamul_cla16_fa3_10_xor1 fa_or0=s_csamul_cla16_fa3_10_or0
|
|
.subckt and_gate a=a[4] b=b[10] out=s_csamul_cla16_and4_10
|
|
.subckt fa a=s_csamul_cla16_and4_10 b=s_csamul_cla16_fa5_9_xor1 cin=s_csamul_cla16_fa4_9_or0 fa_xor1=s_csamul_cla16_fa4_10_xor1 fa_or0=s_csamul_cla16_fa4_10_or0
|
|
.subckt and_gate a=a[5] b=b[10] out=s_csamul_cla16_and5_10
|
|
.subckt fa a=s_csamul_cla16_and5_10 b=s_csamul_cla16_fa6_9_xor1 cin=s_csamul_cla16_fa5_9_or0 fa_xor1=s_csamul_cla16_fa5_10_xor1 fa_or0=s_csamul_cla16_fa5_10_or0
|
|
.subckt and_gate a=a[6] b=b[10] out=s_csamul_cla16_and6_10
|
|
.subckt fa a=s_csamul_cla16_and6_10 b=s_csamul_cla16_fa7_9_xor1 cin=s_csamul_cla16_fa6_9_or0 fa_xor1=s_csamul_cla16_fa6_10_xor1 fa_or0=s_csamul_cla16_fa6_10_or0
|
|
.subckt and_gate a=a[7] b=b[10] out=s_csamul_cla16_and7_10
|
|
.subckt fa a=s_csamul_cla16_and7_10 b=s_csamul_cla16_fa8_9_xor1 cin=s_csamul_cla16_fa7_9_or0 fa_xor1=s_csamul_cla16_fa7_10_xor1 fa_or0=s_csamul_cla16_fa7_10_or0
|
|
.subckt and_gate a=a[8] b=b[10] out=s_csamul_cla16_and8_10
|
|
.subckt fa a=s_csamul_cla16_and8_10 b=s_csamul_cla16_fa9_9_xor1 cin=s_csamul_cla16_fa8_9_or0 fa_xor1=s_csamul_cla16_fa8_10_xor1 fa_or0=s_csamul_cla16_fa8_10_or0
|
|
.subckt and_gate a=a[9] b=b[10] out=s_csamul_cla16_and9_10
|
|
.subckt fa a=s_csamul_cla16_and9_10 b=s_csamul_cla16_fa10_9_xor1 cin=s_csamul_cla16_fa9_9_or0 fa_xor1=s_csamul_cla16_fa9_10_xor1 fa_or0=s_csamul_cla16_fa9_10_or0
|
|
.subckt and_gate a=a[10] b=b[10] out=s_csamul_cla16_and10_10
|
|
.subckt fa a=s_csamul_cla16_and10_10 b=s_csamul_cla16_fa11_9_xor1 cin=s_csamul_cla16_fa10_9_or0 fa_xor1=s_csamul_cla16_fa10_10_xor1 fa_or0=s_csamul_cla16_fa10_10_or0
|
|
.subckt and_gate a=a[11] b=b[10] out=s_csamul_cla16_and11_10
|
|
.subckt fa a=s_csamul_cla16_and11_10 b=s_csamul_cla16_fa12_9_xor1 cin=s_csamul_cla16_fa11_9_or0 fa_xor1=s_csamul_cla16_fa11_10_xor1 fa_or0=s_csamul_cla16_fa11_10_or0
|
|
.subckt and_gate a=a[12] b=b[10] out=s_csamul_cla16_and12_10
|
|
.subckt fa a=s_csamul_cla16_and12_10 b=s_csamul_cla16_fa13_9_xor1 cin=s_csamul_cla16_fa12_9_or0 fa_xor1=s_csamul_cla16_fa12_10_xor1 fa_or0=s_csamul_cla16_fa12_10_or0
|
|
.subckt and_gate a=a[13] b=b[10] out=s_csamul_cla16_and13_10
|
|
.subckt fa a=s_csamul_cla16_and13_10 b=s_csamul_cla16_fa14_9_xor1 cin=s_csamul_cla16_fa13_9_or0 fa_xor1=s_csamul_cla16_fa13_10_xor1 fa_or0=s_csamul_cla16_fa13_10_or0
|
|
.subckt and_gate a=a[14] b=b[10] out=s_csamul_cla16_and14_10
|
|
.subckt fa a=s_csamul_cla16_and14_10 b=s_csamul_cla16_ha15_9_xor0 cin=s_csamul_cla16_fa14_9_or0 fa_xor1=s_csamul_cla16_fa14_10_xor1 fa_or0=s_csamul_cla16_fa14_10_or0
|
|
.subckt nand_gate a=a[15] b=b[10] out=s_csamul_cla16_nand15_10
|
|
.subckt ha a=s_csamul_cla16_nand15_10 b=s_csamul_cla16_ha15_9_and0 ha_xor0=s_csamul_cla16_ha15_10_xor0 ha_and0=s_csamul_cla16_ha15_10_and0
|
|
.subckt and_gate a=a[0] b=b[11] out=s_csamul_cla16_and0_11
|
|
.subckt fa a=s_csamul_cla16_and0_11 b=s_csamul_cla16_fa1_10_xor1 cin=s_csamul_cla16_fa0_10_or0 fa_xor1=s_csamul_cla16_fa0_11_xor1 fa_or0=s_csamul_cla16_fa0_11_or0
|
|
.subckt and_gate a=a[1] b=b[11] out=s_csamul_cla16_and1_11
|
|
.subckt fa a=s_csamul_cla16_and1_11 b=s_csamul_cla16_fa2_10_xor1 cin=s_csamul_cla16_fa1_10_or0 fa_xor1=s_csamul_cla16_fa1_11_xor1 fa_or0=s_csamul_cla16_fa1_11_or0
|
|
.subckt and_gate a=a[2] b=b[11] out=s_csamul_cla16_and2_11
|
|
.subckt fa a=s_csamul_cla16_and2_11 b=s_csamul_cla16_fa3_10_xor1 cin=s_csamul_cla16_fa2_10_or0 fa_xor1=s_csamul_cla16_fa2_11_xor1 fa_or0=s_csamul_cla16_fa2_11_or0
|
|
.subckt and_gate a=a[3] b=b[11] out=s_csamul_cla16_and3_11
|
|
.subckt fa a=s_csamul_cla16_and3_11 b=s_csamul_cla16_fa4_10_xor1 cin=s_csamul_cla16_fa3_10_or0 fa_xor1=s_csamul_cla16_fa3_11_xor1 fa_or0=s_csamul_cla16_fa3_11_or0
|
|
.subckt and_gate a=a[4] b=b[11] out=s_csamul_cla16_and4_11
|
|
.subckt fa a=s_csamul_cla16_and4_11 b=s_csamul_cla16_fa5_10_xor1 cin=s_csamul_cla16_fa4_10_or0 fa_xor1=s_csamul_cla16_fa4_11_xor1 fa_or0=s_csamul_cla16_fa4_11_or0
|
|
.subckt and_gate a=a[5] b=b[11] out=s_csamul_cla16_and5_11
|
|
.subckt fa a=s_csamul_cla16_and5_11 b=s_csamul_cla16_fa6_10_xor1 cin=s_csamul_cla16_fa5_10_or0 fa_xor1=s_csamul_cla16_fa5_11_xor1 fa_or0=s_csamul_cla16_fa5_11_or0
|
|
.subckt and_gate a=a[6] b=b[11] out=s_csamul_cla16_and6_11
|
|
.subckt fa a=s_csamul_cla16_and6_11 b=s_csamul_cla16_fa7_10_xor1 cin=s_csamul_cla16_fa6_10_or0 fa_xor1=s_csamul_cla16_fa6_11_xor1 fa_or0=s_csamul_cla16_fa6_11_or0
|
|
.subckt and_gate a=a[7] b=b[11] out=s_csamul_cla16_and7_11
|
|
.subckt fa a=s_csamul_cla16_and7_11 b=s_csamul_cla16_fa8_10_xor1 cin=s_csamul_cla16_fa7_10_or0 fa_xor1=s_csamul_cla16_fa7_11_xor1 fa_or0=s_csamul_cla16_fa7_11_or0
|
|
.subckt and_gate a=a[8] b=b[11] out=s_csamul_cla16_and8_11
|
|
.subckt fa a=s_csamul_cla16_and8_11 b=s_csamul_cla16_fa9_10_xor1 cin=s_csamul_cla16_fa8_10_or0 fa_xor1=s_csamul_cla16_fa8_11_xor1 fa_or0=s_csamul_cla16_fa8_11_or0
|
|
.subckt and_gate a=a[9] b=b[11] out=s_csamul_cla16_and9_11
|
|
.subckt fa a=s_csamul_cla16_and9_11 b=s_csamul_cla16_fa10_10_xor1 cin=s_csamul_cla16_fa9_10_or0 fa_xor1=s_csamul_cla16_fa9_11_xor1 fa_or0=s_csamul_cla16_fa9_11_or0
|
|
.subckt and_gate a=a[10] b=b[11] out=s_csamul_cla16_and10_11
|
|
.subckt fa a=s_csamul_cla16_and10_11 b=s_csamul_cla16_fa11_10_xor1 cin=s_csamul_cla16_fa10_10_or0 fa_xor1=s_csamul_cla16_fa10_11_xor1 fa_or0=s_csamul_cla16_fa10_11_or0
|
|
.subckt and_gate a=a[11] b=b[11] out=s_csamul_cla16_and11_11
|
|
.subckt fa a=s_csamul_cla16_and11_11 b=s_csamul_cla16_fa12_10_xor1 cin=s_csamul_cla16_fa11_10_or0 fa_xor1=s_csamul_cla16_fa11_11_xor1 fa_or0=s_csamul_cla16_fa11_11_or0
|
|
.subckt and_gate a=a[12] b=b[11] out=s_csamul_cla16_and12_11
|
|
.subckt fa a=s_csamul_cla16_and12_11 b=s_csamul_cla16_fa13_10_xor1 cin=s_csamul_cla16_fa12_10_or0 fa_xor1=s_csamul_cla16_fa12_11_xor1 fa_or0=s_csamul_cla16_fa12_11_or0
|
|
.subckt and_gate a=a[13] b=b[11] out=s_csamul_cla16_and13_11
|
|
.subckt fa a=s_csamul_cla16_and13_11 b=s_csamul_cla16_fa14_10_xor1 cin=s_csamul_cla16_fa13_10_or0 fa_xor1=s_csamul_cla16_fa13_11_xor1 fa_or0=s_csamul_cla16_fa13_11_or0
|
|
.subckt and_gate a=a[14] b=b[11] out=s_csamul_cla16_and14_11
|
|
.subckt fa a=s_csamul_cla16_and14_11 b=s_csamul_cla16_ha15_10_xor0 cin=s_csamul_cla16_fa14_10_or0 fa_xor1=s_csamul_cla16_fa14_11_xor1 fa_or0=s_csamul_cla16_fa14_11_or0
|
|
.subckt nand_gate a=a[15] b=b[11] out=s_csamul_cla16_nand15_11
|
|
.subckt ha a=s_csamul_cla16_nand15_11 b=s_csamul_cla16_ha15_10_and0 ha_xor0=s_csamul_cla16_ha15_11_xor0 ha_and0=s_csamul_cla16_ha15_11_and0
|
|
.subckt and_gate a=a[0] b=b[12] out=s_csamul_cla16_and0_12
|
|
.subckt fa a=s_csamul_cla16_and0_12 b=s_csamul_cla16_fa1_11_xor1 cin=s_csamul_cla16_fa0_11_or0 fa_xor1=s_csamul_cla16_fa0_12_xor1 fa_or0=s_csamul_cla16_fa0_12_or0
|
|
.subckt and_gate a=a[1] b=b[12] out=s_csamul_cla16_and1_12
|
|
.subckt fa a=s_csamul_cla16_and1_12 b=s_csamul_cla16_fa2_11_xor1 cin=s_csamul_cla16_fa1_11_or0 fa_xor1=s_csamul_cla16_fa1_12_xor1 fa_or0=s_csamul_cla16_fa1_12_or0
|
|
.subckt and_gate a=a[2] b=b[12] out=s_csamul_cla16_and2_12
|
|
.subckt fa a=s_csamul_cla16_and2_12 b=s_csamul_cla16_fa3_11_xor1 cin=s_csamul_cla16_fa2_11_or0 fa_xor1=s_csamul_cla16_fa2_12_xor1 fa_or0=s_csamul_cla16_fa2_12_or0
|
|
.subckt and_gate a=a[3] b=b[12] out=s_csamul_cla16_and3_12
|
|
.subckt fa a=s_csamul_cla16_and3_12 b=s_csamul_cla16_fa4_11_xor1 cin=s_csamul_cla16_fa3_11_or0 fa_xor1=s_csamul_cla16_fa3_12_xor1 fa_or0=s_csamul_cla16_fa3_12_or0
|
|
.subckt and_gate a=a[4] b=b[12] out=s_csamul_cla16_and4_12
|
|
.subckt fa a=s_csamul_cla16_and4_12 b=s_csamul_cla16_fa5_11_xor1 cin=s_csamul_cla16_fa4_11_or0 fa_xor1=s_csamul_cla16_fa4_12_xor1 fa_or0=s_csamul_cla16_fa4_12_or0
|
|
.subckt and_gate a=a[5] b=b[12] out=s_csamul_cla16_and5_12
|
|
.subckt fa a=s_csamul_cla16_and5_12 b=s_csamul_cla16_fa6_11_xor1 cin=s_csamul_cla16_fa5_11_or0 fa_xor1=s_csamul_cla16_fa5_12_xor1 fa_or0=s_csamul_cla16_fa5_12_or0
|
|
.subckt and_gate a=a[6] b=b[12] out=s_csamul_cla16_and6_12
|
|
.subckt fa a=s_csamul_cla16_and6_12 b=s_csamul_cla16_fa7_11_xor1 cin=s_csamul_cla16_fa6_11_or0 fa_xor1=s_csamul_cla16_fa6_12_xor1 fa_or0=s_csamul_cla16_fa6_12_or0
|
|
.subckt and_gate a=a[7] b=b[12] out=s_csamul_cla16_and7_12
|
|
.subckt fa a=s_csamul_cla16_and7_12 b=s_csamul_cla16_fa8_11_xor1 cin=s_csamul_cla16_fa7_11_or0 fa_xor1=s_csamul_cla16_fa7_12_xor1 fa_or0=s_csamul_cla16_fa7_12_or0
|
|
.subckt and_gate a=a[8] b=b[12] out=s_csamul_cla16_and8_12
|
|
.subckt fa a=s_csamul_cla16_and8_12 b=s_csamul_cla16_fa9_11_xor1 cin=s_csamul_cla16_fa8_11_or0 fa_xor1=s_csamul_cla16_fa8_12_xor1 fa_or0=s_csamul_cla16_fa8_12_or0
|
|
.subckt and_gate a=a[9] b=b[12] out=s_csamul_cla16_and9_12
|
|
.subckt fa a=s_csamul_cla16_and9_12 b=s_csamul_cla16_fa10_11_xor1 cin=s_csamul_cla16_fa9_11_or0 fa_xor1=s_csamul_cla16_fa9_12_xor1 fa_or0=s_csamul_cla16_fa9_12_or0
|
|
.subckt and_gate a=a[10] b=b[12] out=s_csamul_cla16_and10_12
|
|
.subckt fa a=s_csamul_cla16_and10_12 b=s_csamul_cla16_fa11_11_xor1 cin=s_csamul_cla16_fa10_11_or0 fa_xor1=s_csamul_cla16_fa10_12_xor1 fa_or0=s_csamul_cla16_fa10_12_or0
|
|
.subckt and_gate a=a[11] b=b[12] out=s_csamul_cla16_and11_12
|
|
.subckt fa a=s_csamul_cla16_and11_12 b=s_csamul_cla16_fa12_11_xor1 cin=s_csamul_cla16_fa11_11_or0 fa_xor1=s_csamul_cla16_fa11_12_xor1 fa_or0=s_csamul_cla16_fa11_12_or0
|
|
.subckt and_gate a=a[12] b=b[12] out=s_csamul_cla16_and12_12
|
|
.subckt fa a=s_csamul_cla16_and12_12 b=s_csamul_cla16_fa13_11_xor1 cin=s_csamul_cla16_fa12_11_or0 fa_xor1=s_csamul_cla16_fa12_12_xor1 fa_or0=s_csamul_cla16_fa12_12_or0
|
|
.subckt and_gate a=a[13] b=b[12] out=s_csamul_cla16_and13_12
|
|
.subckt fa a=s_csamul_cla16_and13_12 b=s_csamul_cla16_fa14_11_xor1 cin=s_csamul_cla16_fa13_11_or0 fa_xor1=s_csamul_cla16_fa13_12_xor1 fa_or0=s_csamul_cla16_fa13_12_or0
|
|
.subckt and_gate a=a[14] b=b[12] out=s_csamul_cla16_and14_12
|
|
.subckt fa a=s_csamul_cla16_and14_12 b=s_csamul_cla16_ha15_11_xor0 cin=s_csamul_cla16_fa14_11_or0 fa_xor1=s_csamul_cla16_fa14_12_xor1 fa_or0=s_csamul_cla16_fa14_12_or0
|
|
.subckt nand_gate a=a[15] b=b[12] out=s_csamul_cla16_nand15_12
|
|
.subckt ha a=s_csamul_cla16_nand15_12 b=s_csamul_cla16_ha15_11_and0 ha_xor0=s_csamul_cla16_ha15_12_xor0 ha_and0=s_csamul_cla16_ha15_12_and0
|
|
.subckt and_gate a=a[0] b=b[13] out=s_csamul_cla16_and0_13
|
|
.subckt fa a=s_csamul_cla16_and0_13 b=s_csamul_cla16_fa1_12_xor1 cin=s_csamul_cla16_fa0_12_or0 fa_xor1=s_csamul_cla16_fa0_13_xor1 fa_or0=s_csamul_cla16_fa0_13_or0
|
|
.subckt and_gate a=a[1] b=b[13] out=s_csamul_cla16_and1_13
|
|
.subckt fa a=s_csamul_cla16_and1_13 b=s_csamul_cla16_fa2_12_xor1 cin=s_csamul_cla16_fa1_12_or0 fa_xor1=s_csamul_cla16_fa1_13_xor1 fa_or0=s_csamul_cla16_fa1_13_or0
|
|
.subckt and_gate a=a[2] b=b[13] out=s_csamul_cla16_and2_13
|
|
.subckt fa a=s_csamul_cla16_and2_13 b=s_csamul_cla16_fa3_12_xor1 cin=s_csamul_cla16_fa2_12_or0 fa_xor1=s_csamul_cla16_fa2_13_xor1 fa_or0=s_csamul_cla16_fa2_13_or0
|
|
.subckt and_gate a=a[3] b=b[13] out=s_csamul_cla16_and3_13
|
|
.subckt fa a=s_csamul_cla16_and3_13 b=s_csamul_cla16_fa4_12_xor1 cin=s_csamul_cla16_fa3_12_or0 fa_xor1=s_csamul_cla16_fa3_13_xor1 fa_or0=s_csamul_cla16_fa3_13_or0
|
|
.subckt and_gate a=a[4] b=b[13] out=s_csamul_cla16_and4_13
|
|
.subckt fa a=s_csamul_cla16_and4_13 b=s_csamul_cla16_fa5_12_xor1 cin=s_csamul_cla16_fa4_12_or0 fa_xor1=s_csamul_cla16_fa4_13_xor1 fa_or0=s_csamul_cla16_fa4_13_or0
|
|
.subckt and_gate a=a[5] b=b[13] out=s_csamul_cla16_and5_13
|
|
.subckt fa a=s_csamul_cla16_and5_13 b=s_csamul_cla16_fa6_12_xor1 cin=s_csamul_cla16_fa5_12_or0 fa_xor1=s_csamul_cla16_fa5_13_xor1 fa_or0=s_csamul_cla16_fa5_13_or0
|
|
.subckt and_gate a=a[6] b=b[13] out=s_csamul_cla16_and6_13
|
|
.subckt fa a=s_csamul_cla16_and6_13 b=s_csamul_cla16_fa7_12_xor1 cin=s_csamul_cla16_fa6_12_or0 fa_xor1=s_csamul_cla16_fa6_13_xor1 fa_or0=s_csamul_cla16_fa6_13_or0
|
|
.subckt and_gate a=a[7] b=b[13] out=s_csamul_cla16_and7_13
|
|
.subckt fa a=s_csamul_cla16_and7_13 b=s_csamul_cla16_fa8_12_xor1 cin=s_csamul_cla16_fa7_12_or0 fa_xor1=s_csamul_cla16_fa7_13_xor1 fa_or0=s_csamul_cla16_fa7_13_or0
|
|
.subckt and_gate a=a[8] b=b[13] out=s_csamul_cla16_and8_13
|
|
.subckt fa a=s_csamul_cla16_and8_13 b=s_csamul_cla16_fa9_12_xor1 cin=s_csamul_cla16_fa8_12_or0 fa_xor1=s_csamul_cla16_fa8_13_xor1 fa_or0=s_csamul_cla16_fa8_13_or0
|
|
.subckt and_gate a=a[9] b=b[13] out=s_csamul_cla16_and9_13
|
|
.subckt fa a=s_csamul_cla16_and9_13 b=s_csamul_cla16_fa10_12_xor1 cin=s_csamul_cla16_fa9_12_or0 fa_xor1=s_csamul_cla16_fa9_13_xor1 fa_or0=s_csamul_cla16_fa9_13_or0
|
|
.subckt and_gate a=a[10] b=b[13] out=s_csamul_cla16_and10_13
|
|
.subckt fa a=s_csamul_cla16_and10_13 b=s_csamul_cla16_fa11_12_xor1 cin=s_csamul_cla16_fa10_12_or0 fa_xor1=s_csamul_cla16_fa10_13_xor1 fa_or0=s_csamul_cla16_fa10_13_or0
|
|
.subckt and_gate a=a[11] b=b[13] out=s_csamul_cla16_and11_13
|
|
.subckt fa a=s_csamul_cla16_and11_13 b=s_csamul_cla16_fa12_12_xor1 cin=s_csamul_cla16_fa11_12_or0 fa_xor1=s_csamul_cla16_fa11_13_xor1 fa_or0=s_csamul_cla16_fa11_13_or0
|
|
.subckt and_gate a=a[12] b=b[13] out=s_csamul_cla16_and12_13
|
|
.subckt fa a=s_csamul_cla16_and12_13 b=s_csamul_cla16_fa13_12_xor1 cin=s_csamul_cla16_fa12_12_or0 fa_xor1=s_csamul_cla16_fa12_13_xor1 fa_or0=s_csamul_cla16_fa12_13_or0
|
|
.subckt and_gate a=a[13] b=b[13] out=s_csamul_cla16_and13_13
|
|
.subckt fa a=s_csamul_cla16_and13_13 b=s_csamul_cla16_fa14_12_xor1 cin=s_csamul_cla16_fa13_12_or0 fa_xor1=s_csamul_cla16_fa13_13_xor1 fa_or0=s_csamul_cla16_fa13_13_or0
|
|
.subckt and_gate a=a[14] b=b[13] out=s_csamul_cla16_and14_13
|
|
.subckt fa a=s_csamul_cla16_and14_13 b=s_csamul_cla16_ha15_12_xor0 cin=s_csamul_cla16_fa14_12_or0 fa_xor1=s_csamul_cla16_fa14_13_xor1 fa_or0=s_csamul_cla16_fa14_13_or0
|
|
.subckt nand_gate a=a[15] b=b[13] out=s_csamul_cla16_nand15_13
|
|
.subckt ha a=s_csamul_cla16_nand15_13 b=s_csamul_cla16_ha15_12_and0 ha_xor0=s_csamul_cla16_ha15_13_xor0 ha_and0=s_csamul_cla16_ha15_13_and0
|
|
.subckt and_gate a=a[0] b=b[14] out=s_csamul_cla16_and0_14
|
|
.subckt fa a=s_csamul_cla16_and0_14 b=s_csamul_cla16_fa1_13_xor1 cin=s_csamul_cla16_fa0_13_or0 fa_xor1=s_csamul_cla16_fa0_14_xor1 fa_or0=s_csamul_cla16_fa0_14_or0
|
|
.subckt and_gate a=a[1] b=b[14] out=s_csamul_cla16_and1_14
|
|
.subckt fa a=s_csamul_cla16_and1_14 b=s_csamul_cla16_fa2_13_xor1 cin=s_csamul_cla16_fa1_13_or0 fa_xor1=s_csamul_cla16_fa1_14_xor1 fa_or0=s_csamul_cla16_fa1_14_or0
|
|
.subckt and_gate a=a[2] b=b[14] out=s_csamul_cla16_and2_14
|
|
.subckt fa a=s_csamul_cla16_and2_14 b=s_csamul_cla16_fa3_13_xor1 cin=s_csamul_cla16_fa2_13_or0 fa_xor1=s_csamul_cla16_fa2_14_xor1 fa_or0=s_csamul_cla16_fa2_14_or0
|
|
.subckt and_gate a=a[3] b=b[14] out=s_csamul_cla16_and3_14
|
|
.subckt fa a=s_csamul_cla16_and3_14 b=s_csamul_cla16_fa4_13_xor1 cin=s_csamul_cla16_fa3_13_or0 fa_xor1=s_csamul_cla16_fa3_14_xor1 fa_or0=s_csamul_cla16_fa3_14_or0
|
|
.subckt and_gate a=a[4] b=b[14] out=s_csamul_cla16_and4_14
|
|
.subckt fa a=s_csamul_cla16_and4_14 b=s_csamul_cla16_fa5_13_xor1 cin=s_csamul_cla16_fa4_13_or0 fa_xor1=s_csamul_cla16_fa4_14_xor1 fa_or0=s_csamul_cla16_fa4_14_or0
|
|
.subckt and_gate a=a[5] b=b[14] out=s_csamul_cla16_and5_14
|
|
.subckt fa a=s_csamul_cla16_and5_14 b=s_csamul_cla16_fa6_13_xor1 cin=s_csamul_cla16_fa5_13_or0 fa_xor1=s_csamul_cla16_fa5_14_xor1 fa_or0=s_csamul_cla16_fa5_14_or0
|
|
.subckt and_gate a=a[6] b=b[14] out=s_csamul_cla16_and6_14
|
|
.subckt fa a=s_csamul_cla16_and6_14 b=s_csamul_cla16_fa7_13_xor1 cin=s_csamul_cla16_fa6_13_or0 fa_xor1=s_csamul_cla16_fa6_14_xor1 fa_or0=s_csamul_cla16_fa6_14_or0
|
|
.subckt and_gate a=a[7] b=b[14] out=s_csamul_cla16_and7_14
|
|
.subckt fa a=s_csamul_cla16_and7_14 b=s_csamul_cla16_fa8_13_xor1 cin=s_csamul_cla16_fa7_13_or0 fa_xor1=s_csamul_cla16_fa7_14_xor1 fa_or0=s_csamul_cla16_fa7_14_or0
|
|
.subckt and_gate a=a[8] b=b[14] out=s_csamul_cla16_and8_14
|
|
.subckt fa a=s_csamul_cla16_and8_14 b=s_csamul_cla16_fa9_13_xor1 cin=s_csamul_cla16_fa8_13_or0 fa_xor1=s_csamul_cla16_fa8_14_xor1 fa_or0=s_csamul_cla16_fa8_14_or0
|
|
.subckt and_gate a=a[9] b=b[14] out=s_csamul_cla16_and9_14
|
|
.subckt fa a=s_csamul_cla16_and9_14 b=s_csamul_cla16_fa10_13_xor1 cin=s_csamul_cla16_fa9_13_or0 fa_xor1=s_csamul_cla16_fa9_14_xor1 fa_or0=s_csamul_cla16_fa9_14_or0
|
|
.subckt and_gate a=a[10] b=b[14] out=s_csamul_cla16_and10_14
|
|
.subckt fa a=s_csamul_cla16_and10_14 b=s_csamul_cla16_fa11_13_xor1 cin=s_csamul_cla16_fa10_13_or0 fa_xor1=s_csamul_cla16_fa10_14_xor1 fa_or0=s_csamul_cla16_fa10_14_or0
|
|
.subckt and_gate a=a[11] b=b[14] out=s_csamul_cla16_and11_14
|
|
.subckt fa a=s_csamul_cla16_and11_14 b=s_csamul_cla16_fa12_13_xor1 cin=s_csamul_cla16_fa11_13_or0 fa_xor1=s_csamul_cla16_fa11_14_xor1 fa_or0=s_csamul_cla16_fa11_14_or0
|
|
.subckt and_gate a=a[12] b=b[14] out=s_csamul_cla16_and12_14
|
|
.subckt fa a=s_csamul_cla16_and12_14 b=s_csamul_cla16_fa13_13_xor1 cin=s_csamul_cla16_fa12_13_or0 fa_xor1=s_csamul_cla16_fa12_14_xor1 fa_or0=s_csamul_cla16_fa12_14_or0
|
|
.subckt and_gate a=a[13] b=b[14] out=s_csamul_cla16_and13_14
|
|
.subckt fa a=s_csamul_cla16_and13_14 b=s_csamul_cla16_fa14_13_xor1 cin=s_csamul_cla16_fa13_13_or0 fa_xor1=s_csamul_cla16_fa13_14_xor1 fa_or0=s_csamul_cla16_fa13_14_or0
|
|
.subckt and_gate a=a[14] b=b[14] out=s_csamul_cla16_and14_14
|
|
.subckt fa a=s_csamul_cla16_and14_14 b=s_csamul_cla16_ha15_13_xor0 cin=s_csamul_cla16_fa14_13_or0 fa_xor1=s_csamul_cla16_fa14_14_xor1 fa_or0=s_csamul_cla16_fa14_14_or0
|
|
.subckt nand_gate a=a[15] b=b[14] out=s_csamul_cla16_nand15_14
|
|
.subckt ha a=s_csamul_cla16_nand15_14 b=s_csamul_cla16_ha15_13_and0 ha_xor0=s_csamul_cla16_ha15_14_xor0 ha_and0=s_csamul_cla16_ha15_14_and0
|
|
.subckt nand_gate a=a[0] b=b[15] out=s_csamul_cla16_nand0_15
|
|
.subckt fa a=s_csamul_cla16_nand0_15 b=s_csamul_cla16_fa1_14_xor1 cin=s_csamul_cla16_fa0_14_or0 fa_xor1=s_csamul_cla16_fa0_15_xor1 fa_or0=s_csamul_cla16_fa0_15_or0
|
|
.subckt nand_gate a=a[1] b=b[15] out=s_csamul_cla16_nand1_15
|
|
.subckt fa a=s_csamul_cla16_nand1_15 b=s_csamul_cla16_fa2_14_xor1 cin=s_csamul_cla16_fa1_14_or0 fa_xor1=s_csamul_cla16_fa1_15_xor1 fa_or0=s_csamul_cla16_fa1_15_or0
|
|
.subckt nand_gate a=a[2] b=b[15] out=s_csamul_cla16_nand2_15
|
|
.subckt fa a=s_csamul_cla16_nand2_15 b=s_csamul_cla16_fa3_14_xor1 cin=s_csamul_cla16_fa2_14_or0 fa_xor1=s_csamul_cla16_fa2_15_xor1 fa_or0=s_csamul_cla16_fa2_15_or0
|
|
.subckt nand_gate a=a[3] b=b[15] out=s_csamul_cla16_nand3_15
|
|
.subckt fa a=s_csamul_cla16_nand3_15 b=s_csamul_cla16_fa4_14_xor1 cin=s_csamul_cla16_fa3_14_or0 fa_xor1=s_csamul_cla16_fa3_15_xor1 fa_or0=s_csamul_cla16_fa3_15_or0
|
|
.subckt nand_gate a=a[4] b=b[15] out=s_csamul_cla16_nand4_15
|
|
.subckt fa a=s_csamul_cla16_nand4_15 b=s_csamul_cla16_fa5_14_xor1 cin=s_csamul_cla16_fa4_14_or0 fa_xor1=s_csamul_cla16_fa4_15_xor1 fa_or0=s_csamul_cla16_fa4_15_or0
|
|
.subckt nand_gate a=a[5] b=b[15] out=s_csamul_cla16_nand5_15
|
|
.subckt fa a=s_csamul_cla16_nand5_15 b=s_csamul_cla16_fa6_14_xor1 cin=s_csamul_cla16_fa5_14_or0 fa_xor1=s_csamul_cla16_fa5_15_xor1 fa_or0=s_csamul_cla16_fa5_15_or0
|
|
.subckt nand_gate a=a[6] b=b[15] out=s_csamul_cla16_nand6_15
|
|
.subckt fa a=s_csamul_cla16_nand6_15 b=s_csamul_cla16_fa7_14_xor1 cin=s_csamul_cla16_fa6_14_or0 fa_xor1=s_csamul_cla16_fa6_15_xor1 fa_or0=s_csamul_cla16_fa6_15_or0
|
|
.subckt nand_gate a=a[7] b=b[15] out=s_csamul_cla16_nand7_15
|
|
.subckt fa a=s_csamul_cla16_nand7_15 b=s_csamul_cla16_fa8_14_xor1 cin=s_csamul_cla16_fa7_14_or0 fa_xor1=s_csamul_cla16_fa7_15_xor1 fa_or0=s_csamul_cla16_fa7_15_or0
|
|
.subckt nand_gate a=a[8] b=b[15] out=s_csamul_cla16_nand8_15
|
|
.subckt fa a=s_csamul_cla16_nand8_15 b=s_csamul_cla16_fa9_14_xor1 cin=s_csamul_cla16_fa8_14_or0 fa_xor1=s_csamul_cla16_fa8_15_xor1 fa_or0=s_csamul_cla16_fa8_15_or0
|
|
.subckt nand_gate a=a[9] b=b[15] out=s_csamul_cla16_nand9_15
|
|
.subckt fa a=s_csamul_cla16_nand9_15 b=s_csamul_cla16_fa10_14_xor1 cin=s_csamul_cla16_fa9_14_or0 fa_xor1=s_csamul_cla16_fa9_15_xor1 fa_or0=s_csamul_cla16_fa9_15_or0
|
|
.subckt nand_gate a=a[10] b=b[15] out=s_csamul_cla16_nand10_15
|
|
.subckt fa a=s_csamul_cla16_nand10_15 b=s_csamul_cla16_fa11_14_xor1 cin=s_csamul_cla16_fa10_14_or0 fa_xor1=s_csamul_cla16_fa10_15_xor1 fa_or0=s_csamul_cla16_fa10_15_or0
|
|
.subckt nand_gate a=a[11] b=b[15] out=s_csamul_cla16_nand11_15
|
|
.subckt fa a=s_csamul_cla16_nand11_15 b=s_csamul_cla16_fa12_14_xor1 cin=s_csamul_cla16_fa11_14_or0 fa_xor1=s_csamul_cla16_fa11_15_xor1 fa_or0=s_csamul_cla16_fa11_15_or0
|
|
.subckt nand_gate a=a[12] b=b[15] out=s_csamul_cla16_nand12_15
|
|
.subckt fa a=s_csamul_cla16_nand12_15 b=s_csamul_cla16_fa13_14_xor1 cin=s_csamul_cla16_fa12_14_or0 fa_xor1=s_csamul_cla16_fa12_15_xor1 fa_or0=s_csamul_cla16_fa12_15_or0
|
|
.subckt nand_gate a=a[13] b=b[15] out=s_csamul_cla16_nand13_15
|
|
.subckt fa a=s_csamul_cla16_nand13_15 b=s_csamul_cla16_fa14_14_xor1 cin=s_csamul_cla16_fa13_14_or0 fa_xor1=s_csamul_cla16_fa13_15_xor1 fa_or0=s_csamul_cla16_fa13_15_or0
|
|
.subckt nand_gate a=a[14] b=b[15] out=s_csamul_cla16_nand14_15
|
|
.subckt fa a=s_csamul_cla16_nand14_15 b=s_csamul_cla16_ha15_14_xor0 cin=s_csamul_cla16_fa14_14_or0 fa_xor1=s_csamul_cla16_fa14_15_xor1 fa_or0=s_csamul_cla16_fa14_15_or0
|
|
.subckt and_gate a=a[15] b=b[15] out=s_csamul_cla16_and15_15
|
|
.subckt ha a=s_csamul_cla16_and15_15 b=s_csamul_cla16_ha15_14_and0 ha_xor0=s_csamul_cla16_ha15_15_xor0 ha_and0=s_csamul_cla16_ha15_15_and0
|
|
.names s_csamul_cla16_fa1_15_xor1 s_csamul_cla16_u_cla16_a[0]
|
|
1 1
|
|
.names s_csamul_cla16_fa2_15_xor1 s_csamul_cla16_u_cla16_a[1]
|
|
1 1
|
|
.names s_csamul_cla16_fa3_15_xor1 s_csamul_cla16_u_cla16_a[2]
|
|
1 1
|
|
.names s_csamul_cla16_fa4_15_xor1 s_csamul_cla16_u_cla16_a[3]
|
|
1 1
|
|
.names s_csamul_cla16_fa5_15_xor1 s_csamul_cla16_u_cla16_a[4]
|
|
1 1
|
|
.names s_csamul_cla16_fa6_15_xor1 s_csamul_cla16_u_cla16_a[5]
|
|
1 1
|
|
.names s_csamul_cla16_fa7_15_xor1 s_csamul_cla16_u_cla16_a[6]
|
|
1 1
|
|
.names s_csamul_cla16_fa8_15_xor1 s_csamul_cla16_u_cla16_a[7]
|
|
1 1
|
|
.names s_csamul_cla16_fa9_15_xor1 s_csamul_cla16_u_cla16_a[8]
|
|
1 1
|
|
.names s_csamul_cla16_fa10_15_xor1 s_csamul_cla16_u_cla16_a[9]
|
|
1 1
|
|
.names s_csamul_cla16_fa11_15_xor1 s_csamul_cla16_u_cla16_a[10]
|
|
1 1
|
|
.names s_csamul_cla16_fa12_15_xor1 s_csamul_cla16_u_cla16_a[11]
|
|
1 1
|
|
.names s_csamul_cla16_fa13_15_xor1 s_csamul_cla16_u_cla16_a[12]
|
|
1 1
|
|
.names s_csamul_cla16_fa14_15_xor1 s_csamul_cla16_u_cla16_a[13]
|
|
1 1
|
|
.names s_csamul_cla16_ha15_15_xor0 s_csamul_cla16_u_cla16_a[14]
|
|
1 1
|
|
.names vdd s_csamul_cla16_u_cla16_a[15]
|
|
1 1
|
|
.names s_csamul_cla16_fa0_15_or0 s_csamul_cla16_u_cla16_b[0]
|
|
1 1
|
|
.names s_csamul_cla16_fa1_15_or0 s_csamul_cla16_u_cla16_b[1]
|
|
1 1
|
|
.names s_csamul_cla16_fa2_15_or0 s_csamul_cla16_u_cla16_b[2]
|
|
1 1
|
|
.names s_csamul_cla16_fa3_15_or0 s_csamul_cla16_u_cla16_b[3]
|
|
1 1
|
|
.names s_csamul_cla16_fa4_15_or0 s_csamul_cla16_u_cla16_b[4]
|
|
1 1
|
|
.names s_csamul_cla16_fa5_15_or0 s_csamul_cla16_u_cla16_b[5]
|
|
1 1
|
|
.names s_csamul_cla16_fa6_15_or0 s_csamul_cla16_u_cla16_b[6]
|
|
1 1
|
|
.names s_csamul_cla16_fa7_15_or0 s_csamul_cla16_u_cla16_b[7]
|
|
1 1
|
|
.names s_csamul_cla16_fa8_15_or0 s_csamul_cla16_u_cla16_b[8]
|
|
1 1
|
|
.names s_csamul_cla16_fa9_15_or0 s_csamul_cla16_u_cla16_b[9]
|
|
1 1
|
|
.names s_csamul_cla16_fa10_15_or0 s_csamul_cla16_u_cla16_b[10]
|
|
1 1
|
|
.names s_csamul_cla16_fa11_15_or0 s_csamul_cla16_u_cla16_b[11]
|
|
1 1
|
|
.names s_csamul_cla16_fa12_15_or0 s_csamul_cla16_u_cla16_b[12]
|
|
1 1
|
|
.names s_csamul_cla16_fa13_15_or0 s_csamul_cla16_u_cla16_b[13]
|
|
1 1
|
|
.names s_csamul_cla16_fa14_15_or0 s_csamul_cla16_u_cla16_b[14]
|
|
1 1
|
|
.names s_csamul_cla16_ha15_15_and0 s_csamul_cla16_u_cla16_b[15]
|
|
1 1
|
|
.subckt u_cla16 a[0]=s_csamul_cla16_u_cla16_a[0] a[1]=s_csamul_cla16_u_cla16_a[1] a[2]=s_csamul_cla16_u_cla16_a[2] a[3]=s_csamul_cla16_u_cla16_a[3] a[4]=s_csamul_cla16_u_cla16_a[4] a[5]=s_csamul_cla16_u_cla16_a[5] a[6]=s_csamul_cla16_u_cla16_a[6] a[7]=s_csamul_cla16_u_cla16_a[7] a[8]=s_csamul_cla16_u_cla16_a[8] a[9]=s_csamul_cla16_u_cla16_a[9] a[10]=s_csamul_cla16_u_cla16_a[10] a[11]=s_csamul_cla16_u_cla16_a[11] a[12]=s_csamul_cla16_u_cla16_a[12] a[13]=s_csamul_cla16_u_cla16_a[13] a[14]=s_csamul_cla16_u_cla16_a[14] a[15]=s_csamul_cla16_u_cla16_a[15] b[0]=s_csamul_cla16_u_cla16_b[0] b[1]=s_csamul_cla16_u_cla16_b[1] b[2]=s_csamul_cla16_u_cla16_b[2] b[3]=s_csamul_cla16_u_cla16_b[3] b[4]=s_csamul_cla16_u_cla16_b[4] b[5]=s_csamul_cla16_u_cla16_b[5] b[6]=s_csamul_cla16_u_cla16_b[6] b[7]=s_csamul_cla16_u_cla16_b[7] b[8]=s_csamul_cla16_u_cla16_b[8] b[9]=s_csamul_cla16_u_cla16_b[9] b[10]=s_csamul_cla16_u_cla16_b[10] b[11]=s_csamul_cla16_u_cla16_b[11] b[12]=s_csamul_cla16_u_cla16_b[12] b[13]=s_csamul_cla16_u_cla16_b[13] b[14]=s_csamul_cla16_u_cla16_b[14] b[15]=s_csamul_cla16_u_cla16_b[15] u_cla16_out[0]=s_csamul_cla16_u_cla16_pg_logic0_xor0 u_cla16_out[1]=s_csamul_cla16_u_cla16_xor1 u_cla16_out[2]=s_csamul_cla16_u_cla16_xor2 u_cla16_out[3]=s_csamul_cla16_u_cla16_xor3 u_cla16_out[4]=s_csamul_cla16_u_cla16_xor4 u_cla16_out[5]=s_csamul_cla16_u_cla16_xor5 u_cla16_out[6]=s_csamul_cla16_u_cla16_xor6 u_cla16_out[7]=s_csamul_cla16_u_cla16_xor7 u_cla16_out[8]=s_csamul_cla16_u_cla16_xor8 u_cla16_out[9]=s_csamul_cla16_u_cla16_xor9 u_cla16_out[10]=s_csamul_cla16_u_cla16_xor10 u_cla16_out[11]=s_csamul_cla16_u_cla16_xor11 u_cla16_out[12]=s_csamul_cla16_u_cla16_xor12 u_cla16_out[13]=s_csamul_cla16_u_cla16_xor13 u_cla16_out[14]=s_csamul_cla16_u_cla16_xor14 u_cla16_out[15]=s_csamul_cla16_u_cla16_xor15 u_cla16_out[16]=s_csamul_cla16_u_cla16_or35
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.names s_csamul_cla16_and0_0 s_csamul_cla16_out[0]
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1 1
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|
.names s_csamul_cla16_ha0_1_xor0 s_csamul_cla16_out[1]
|
|
1 1
|
|
.names s_csamul_cla16_fa0_2_xor1 s_csamul_cla16_out[2]
|
|
1 1
|
|
.names s_csamul_cla16_fa0_3_xor1 s_csamul_cla16_out[3]
|
|
1 1
|
|
.names s_csamul_cla16_fa0_4_xor1 s_csamul_cla16_out[4]
|
|
1 1
|
|
.names s_csamul_cla16_fa0_5_xor1 s_csamul_cla16_out[5]
|
|
1 1
|
|
.names s_csamul_cla16_fa0_6_xor1 s_csamul_cla16_out[6]
|
|
1 1
|
|
.names s_csamul_cla16_fa0_7_xor1 s_csamul_cla16_out[7]
|
|
1 1
|
|
.names s_csamul_cla16_fa0_8_xor1 s_csamul_cla16_out[8]
|
|
1 1
|
|
.names s_csamul_cla16_fa0_9_xor1 s_csamul_cla16_out[9]
|
|
1 1
|
|
.names s_csamul_cla16_fa0_10_xor1 s_csamul_cla16_out[10]
|
|
1 1
|
|
.names s_csamul_cla16_fa0_11_xor1 s_csamul_cla16_out[11]
|
|
1 1
|
|
.names s_csamul_cla16_fa0_12_xor1 s_csamul_cla16_out[12]
|
|
1 1
|
|
.names s_csamul_cla16_fa0_13_xor1 s_csamul_cla16_out[13]
|
|
1 1
|
|
.names s_csamul_cla16_fa0_14_xor1 s_csamul_cla16_out[14]
|
|
1 1
|
|
.names s_csamul_cla16_fa0_15_xor1 s_csamul_cla16_out[15]
|
|
1 1
|
|
.names s_csamul_cla16_u_cla16_pg_logic0_xor0 s_csamul_cla16_out[16]
|
|
1 1
|
|
.names s_csamul_cla16_u_cla16_xor1 s_csamul_cla16_out[17]
|
|
1 1
|
|
.names s_csamul_cla16_u_cla16_xor2 s_csamul_cla16_out[18]
|
|
1 1
|
|
.names s_csamul_cla16_u_cla16_xor3 s_csamul_cla16_out[19]
|
|
1 1
|
|
.names s_csamul_cla16_u_cla16_xor4 s_csamul_cla16_out[20]
|
|
1 1
|
|
.names s_csamul_cla16_u_cla16_xor5 s_csamul_cla16_out[21]
|
|
1 1
|
|
.names s_csamul_cla16_u_cla16_xor6 s_csamul_cla16_out[22]
|
|
1 1
|
|
.names s_csamul_cla16_u_cla16_xor7 s_csamul_cla16_out[23]
|
|
1 1
|
|
.names s_csamul_cla16_u_cla16_xor8 s_csamul_cla16_out[24]
|
|
1 1
|
|
.names s_csamul_cla16_u_cla16_xor9 s_csamul_cla16_out[25]
|
|
1 1
|
|
.names s_csamul_cla16_u_cla16_xor10 s_csamul_cla16_out[26]
|
|
1 1
|
|
.names s_csamul_cla16_u_cla16_xor11 s_csamul_cla16_out[27]
|
|
1 1
|
|
.names s_csamul_cla16_u_cla16_xor12 s_csamul_cla16_out[28]
|
|
1 1
|
|
.names s_csamul_cla16_u_cla16_xor13 s_csamul_cla16_out[29]
|
|
1 1
|
|
.names s_csamul_cla16_u_cla16_xor14 s_csamul_cla16_out[30]
|
|
1 1
|
|
.names s_csamul_cla16_u_cla16_xor15 s_csamul_cla16_out[31]
|
|
1 1
|
|
.end
|
|
|
|
.model u_cla16
|
|
.inputs a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] a[8] a[9] a[10] a[11] a[12] a[13] a[14] a[15] b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9] b[10] b[11] b[12] b[13] b[14] b[15]
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.outputs u_cla16_out[0] u_cla16_out[1] u_cla16_out[2] u_cla16_out[3] u_cla16_out[4] u_cla16_out[5] u_cla16_out[6] u_cla16_out[7] u_cla16_out[8] u_cla16_out[9] u_cla16_out[10] u_cla16_out[11] u_cla16_out[12] u_cla16_out[13] u_cla16_out[14] u_cla16_out[15] u_cla16_out[16]
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.names vdd
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1
|
|
.names gnd
|
|
0
|
|
.subckt pg_logic a=a[0] b=b[0] pg_logic_or0=u_cla16_pg_logic0_or0 pg_logic_and0=u_cla16_pg_logic0_and0 pg_logic_xor0=u_cla16_pg_logic0_xor0
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.subckt pg_logic a=a[1] b=b[1] pg_logic_or0=u_cla16_pg_logic1_or0 pg_logic_and0=u_cla16_pg_logic1_and0 pg_logic_xor0=u_cla16_pg_logic1_xor0
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.subckt xor_gate a=u_cla16_pg_logic1_xor0 b=u_cla16_pg_logic0_and0 out=u_cla16_xor1
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.subckt and_gate a=u_cla16_pg_logic0_and0 b=u_cla16_pg_logic1_or0 out=u_cla16_and0
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.subckt or_gate a=u_cla16_pg_logic1_and0 b=u_cla16_and0 out=u_cla16_or0
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.subckt pg_logic a=a[2] b=b[2] pg_logic_or0=u_cla16_pg_logic2_or0 pg_logic_and0=u_cla16_pg_logic2_and0 pg_logic_xor0=u_cla16_pg_logic2_xor0
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.subckt xor_gate a=u_cla16_pg_logic2_xor0 b=u_cla16_or0 out=u_cla16_xor2
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.subckt and_gate a=u_cla16_pg_logic2_or0 b=u_cla16_pg_logic0_or0 out=u_cla16_and1
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.subckt and_gate a=u_cla16_pg_logic0_and0 b=u_cla16_pg_logic2_or0 out=u_cla16_and2
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.subckt and_gate a=u_cla16_and2 b=u_cla16_pg_logic1_or0 out=u_cla16_and3
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.subckt and_gate a=u_cla16_pg_logic1_and0 b=u_cla16_pg_logic2_or0 out=u_cla16_and4
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.subckt or_gate a=u_cla16_and3 b=u_cla16_and4 out=u_cla16_or1
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.subckt or_gate a=u_cla16_pg_logic2_and0 b=u_cla16_or1 out=u_cla16_or2
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.subckt pg_logic a=a[3] b=b[3] pg_logic_or0=u_cla16_pg_logic3_or0 pg_logic_and0=u_cla16_pg_logic3_and0 pg_logic_xor0=u_cla16_pg_logic3_xor0
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.subckt xor_gate a=u_cla16_pg_logic3_xor0 b=u_cla16_or2 out=u_cla16_xor3
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.subckt and_gate a=u_cla16_pg_logic3_or0 b=u_cla16_pg_logic1_or0 out=u_cla16_and5
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.subckt and_gate a=u_cla16_pg_logic0_and0 b=u_cla16_pg_logic2_or0 out=u_cla16_and6
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.subckt and_gate a=u_cla16_pg_logic3_or0 b=u_cla16_pg_logic1_or0 out=u_cla16_and7
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.subckt and_gate a=u_cla16_and6 b=u_cla16_and7 out=u_cla16_and8
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.subckt and_gate a=u_cla16_pg_logic1_and0 b=u_cla16_pg_logic3_or0 out=u_cla16_and9
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.subckt and_gate a=u_cla16_and9 b=u_cla16_pg_logic2_or0 out=u_cla16_and10
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.subckt and_gate a=u_cla16_pg_logic2_and0 b=u_cla16_pg_logic3_or0 out=u_cla16_and11
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.subckt or_gate a=u_cla16_and8 b=u_cla16_and11 out=u_cla16_or3
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.subckt or_gate a=u_cla16_and10 b=u_cla16_or3 out=u_cla16_or4
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.subckt or_gate a=u_cla16_pg_logic3_and0 b=u_cla16_or4 out=u_cla16_or5
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.subckt pg_logic a=a[4] b=b[4] pg_logic_or0=u_cla16_pg_logic4_or0 pg_logic_and0=u_cla16_pg_logic4_and0 pg_logic_xor0=u_cla16_pg_logic4_xor0
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.subckt xor_gate a=u_cla16_pg_logic4_xor0 b=u_cla16_or5 out=u_cla16_xor4
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.subckt and_gate a=u_cla16_or5 b=u_cla16_pg_logic4_or0 out=u_cla16_and12
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.subckt or_gate a=u_cla16_pg_logic4_and0 b=u_cla16_and12 out=u_cla16_or6
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.subckt pg_logic a=a[5] b=b[5] pg_logic_or0=u_cla16_pg_logic5_or0 pg_logic_and0=u_cla16_pg_logic5_and0 pg_logic_xor0=u_cla16_pg_logic5_xor0
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.subckt xor_gate a=u_cla16_pg_logic5_xor0 b=u_cla16_or6 out=u_cla16_xor5
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.subckt and_gate a=u_cla16_or5 b=u_cla16_pg_logic5_or0 out=u_cla16_and13
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.subckt and_gate a=u_cla16_and13 b=u_cla16_pg_logic4_or0 out=u_cla16_and14
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.subckt and_gate a=u_cla16_pg_logic4_and0 b=u_cla16_pg_logic5_or0 out=u_cla16_and15
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.subckt or_gate a=u_cla16_and14 b=u_cla16_and15 out=u_cla16_or7
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.subckt or_gate a=u_cla16_pg_logic5_and0 b=u_cla16_or7 out=u_cla16_or8
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.subckt pg_logic a=a[6] b=b[6] pg_logic_or0=u_cla16_pg_logic6_or0 pg_logic_and0=u_cla16_pg_logic6_and0 pg_logic_xor0=u_cla16_pg_logic6_xor0
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.subckt xor_gate a=u_cla16_pg_logic6_xor0 b=u_cla16_or8 out=u_cla16_xor6
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.subckt and_gate a=u_cla16_or5 b=u_cla16_pg_logic5_or0 out=u_cla16_and16
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.subckt and_gate a=u_cla16_pg_logic6_or0 b=u_cla16_pg_logic4_or0 out=u_cla16_and17
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.subckt and_gate a=u_cla16_and16 b=u_cla16_and17 out=u_cla16_and18
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.subckt and_gate a=u_cla16_pg_logic4_and0 b=u_cla16_pg_logic6_or0 out=u_cla16_and19
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.subckt and_gate a=u_cla16_and19 b=u_cla16_pg_logic5_or0 out=u_cla16_and20
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.subckt and_gate a=u_cla16_pg_logic5_and0 b=u_cla16_pg_logic6_or0 out=u_cla16_and21
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.subckt or_gate a=u_cla16_and18 b=u_cla16_and20 out=u_cla16_or9
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.subckt or_gate a=u_cla16_or9 b=u_cla16_and21 out=u_cla16_or10
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.subckt or_gate a=u_cla16_pg_logic6_and0 b=u_cla16_or10 out=u_cla16_or11
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.subckt pg_logic a=a[7] b=b[7] pg_logic_or0=u_cla16_pg_logic7_or0 pg_logic_and0=u_cla16_pg_logic7_and0 pg_logic_xor0=u_cla16_pg_logic7_xor0
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.subckt xor_gate a=u_cla16_pg_logic7_xor0 b=u_cla16_or11 out=u_cla16_xor7
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.subckt and_gate a=u_cla16_or5 b=u_cla16_pg_logic6_or0 out=u_cla16_and22
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.subckt and_gate a=u_cla16_pg_logic7_or0 b=u_cla16_pg_logic5_or0 out=u_cla16_and23
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.subckt and_gate a=u_cla16_and22 b=u_cla16_and23 out=u_cla16_and24
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.subckt and_gate a=u_cla16_and24 b=u_cla16_pg_logic4_or0 out=u_cla16_and25
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.subckt and_gate a=u_cla16_pg_logic4_and0 b=u_cla16_pg_logic6_or0 out=u_cla16_and26
|
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.subckt and_gate a=u_cla16_pg_logic7_or0 b=u_cla16_pg_logic5_or0 out=u_cla16_and27
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.subckt and_gate a=u_cla16_and26 b=u_cla16_and27 out=u_cla16_and28
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.subckt and_gate a=u_cla16_pg_logic5_and0 b=u_cla16_pg_logic7_or0 out=u_cla16_and29
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.subckt and_gate a=u_cla16_and29 b=u_cla16_pg_logic6_or0 out=u_cla16_and30
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.subckt and_gate a=u_cla16_pg_logic6_and0 b=u_cla16_pg_logic7_or0 out=u_cla16_and31
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.subckt or_gate a=u_cla16_and25 b=u_cla16_and30 out=u_cla16_or12
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.subckt or_gate a=u_cla16_and28 b=u_cla16_and31 out=u_cla16_or13
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.subckt or_gate a=u_cla16_or12 b=u_cla16_or13 out=u_cla16_or14
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.subckt or_gate a=u_cla16_pg_logic7_and0 b=u_cla16_or14 out=u_cla16_or15
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|
.subckt pg_logic a=a[8] b=b[8] pg_logic_or0=u_cla16_pg_logic8_or0 pg_logic_and0=u_cla16_pg_logic8_and0 pg_logic_xor0=u_cla16_pg_logic8_xor0
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.subckt xor_gate a=u_cla16_pg_logic8_xor0 b=u_cla16_or15 out=u_cla16_xor8
|
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.subckt and_gate a=u_cla16_or15 b=u_cla16_pg_logic8_or0 out=u_cla16_and32
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.subckt or_gate a=u_cla16_pg_logic8_and0 b=u_cla16_and32 out=u_cla16_or16
|
|
.subckt pg_logic a=a[9] b=b[9] pg_logic_or0=u_cla16_pg_logic9_or0 pg_logic_and0=u_cla16_pg_logic9_and0 pg_logic_xor0=u_cla16_pg_logic9_xor0
|
|
.subckt xor_gate a=u_cla16_pg_logic9_xor0 b=u_cla16_or16 out=u_cla16_xor9
|
|
.subckt and_gate a=u_cla16_or15 b=u_cla16_pg_logic9_or0 out=u_cla16_and33
|
|
.subckt and_gate a=u_cla16_and33 b=u_cla16_pg_logic8_or0 out=u_cla16_and34
|
|
.subckt and_gate a=u_cla16_pg_logic8_and0 b=u_cla16_pg_logic9_or0 out=u_cla16_and35
|
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.subckt or_gate a=u_cla16_and34 b=u_cla16_and35 out=u_cla16_or17
|
|
.subckt or_gate a=u_cla16_pg_logic9_and0 b=u_cla16_or17 out=u_cla16_or18
|
|
.subckt pg_logic a=a[10] b=b[10] pg_logic_or0=u_cla16_pg_logic10_or0 pg_logic_and0=u_cla16_pg_logic10_and0 pg_logic_xor0=u_cla16_pg_logic10_xor0
|
|
.subckt xor_gate a=u_cla16_pg_logic10_xor0 b=u_cla16_or18 out=u_cla16_xor10
|
|
.subckt and_gate a=u_cla16_or15 b=u_cla16_pg_logic9_or0 out=u_cla16_and36
|
|
.subckt and_gate a=u_cla16_pg_logic10_or0 b=u_cla16_pg_logic8_or0 out=u_cla16_and37
|
|
.subckt and_gate a=u_cla16_and36 b=u_cla16_and37 out=u_cla16_and38
|
|
.subckt and_gate a=u_cla16_pg_logic8_and0 b=u_cla16_pg_logic10_or0 out=u_cla16_and39
|
|
.subckt and_gate a=u_cla16_and39 b=u_cla16_pg_logic9_or0 out=u_cla16_and40
|
|
.subckt and_gate a=u_cla16_pg_logic9_and0 b=u_cla16_pg_logic10_or0 out=u_cla16_and41
|
|
.subckt or_gate a=u_cla16_and38 b=u_cla16_and40 out=u_cla16_or19
|
|
.subckt or_gate a=u_cla16_or19 b=u_cla16_and41 out=u_cla16_or20
|
|
.subckt or_gate a=u_cla16_pg_logic10_and0 b=u_cla16_or20 out=u_cla16_or21
|
|
.subckt pg_logic a=a[11] b=b[11] pg_logic_or0=u_cla16_pg_logic11_or0 pg_logic_and0=u_cla16_pg_logic11_and0 pg_logic_xor0=u_cla16_pg_logic11_xor0
|
|
.subckt xor_gate a=u_cla16_pg_logic11_xor0 b=u_cla16_or21 out=u_cla16_xor11
|
|
.subckt and_gate a=u_cla16_or15 b=u_cla16_pg_logic10_or0 out=u_cla16_and42
|
|
.subckt and_gate a=u_cla16_pg_logic11_or0 b=u_cla16_pg_logic9_or0 out=u_cla16_and43
|
|
.subckt and_gate a=u_cla16_and42 b=u_cla16_and43 out=u_cla16_and44
|
|
.subckt and_gate a=u_cla16_and44 b=u_cla16_pg_logic8_or0 out=u_cla16_and45
|
|
.subckt and_gate a=u_cla16_pg_logic8_and0 b=u_cla16_pg_logic10_or0 out=u_cla16_and46
|
|
.subckt and_gate a=u_cla16_pg_logic11_or0 b=u_cla16_pg_logic9_or0 out=u_cla16_and47
|
|
.subckt and_gate a=u_cla16_and46 b=u_cla16_and47 out=u_cla16_and48
|
|
.subckt and_gate a=u_cla16_pg_logic9_and0 b=u_cla16_pg_logic11_or0 out=u_cla16_and49
|
|
.subckt and_gate a=u_cla16_and49 b=u_cla16_pg_logic10_or0 out=u_cla16_and50
|
|
.subckt and_gate a=u_cla16_pg_logic10_and0 b=u_cla16_pg_logic11_or0 out=u_cla16_and51
|
|
.subckt or_gate a=u_cla16_and45 b=u_cla16_and50 out=u_cla16_or22
|
|
.subckt or_gate a=u_cla16_and48 b=u_cla16_and51 out=u_cla16_or23
|
|
.subckt or_gate a=u_cla16_or22 b=u_cla16_or23 out=u_cla16_or24
|
|
.subckt or_gate a=u_cla16_pg_logic11_and0 b=u_cla16_or24 out=u_cla16_or25
|
|
.subckt pg_logic a=a[12] b=b[12] pg_logic_or0=u_cla16_pg_logic12_or0 pg_logic_and0=u_cla16_pg_logic12_and0 pg_logic_xor0=u_cla16_pg_logic12_xor0
|
|
.subckt xor_gate a=u_cla16_pg_logic12_xor0 b=u_cla16_or25 out=u_cla16_xor12
|
|
.subckt and_gate a=u_cla16_or25 b=u_cla16_pg_logic12_or0 out=u_cla16_and52
|
|
.subckt or_gate a=u_cla16_pg_logic12_and0 b=u_cla16_and52 out=u_cla16_or26
|
|
.subckt pg_logic a=a[13] b=b[13] pg_logic_or0=u_cla16_pg_logic13_or0 pg_logic_and0=u_cla16_pg_logic13_and0 pg_logic_xor0=u_cla16_pg_logic13_xor0
|
|
.subckt xor_gate a=u_cla16_pg_logic13_xor0 b=u_cla16_or26 out=u_cla16_xor13
|
|
.subckt and_gate a=u_cla16_or25 b=u_cla16_pg_logic13_or0 out=u_cla16_and53
|
|
.subckt and_gate a=u_cla16_and53 b=u_cla16_pg_logic12_or0 out=u_cla16_and54
|
|
.subckt and_gate a=u_cla16_pg_logic12_and0 b=u_cla16_pg_logic13_or0 out=u_cla16_and55
|
|
.subckt or_gate a=u_cla16_and54 b=u_cla16_and55 out=u_cla16_or27
|
|
.subckt or_gate a=u_cla16_pg_logic13_and0 b=u_cla16_or27 out=u_cla16_or28
|
|
.subckt pg_logic a=a[14] b=b[14] pg_logic_or0=u_cla16_pg_logic14_or0 pg_logic_and0=u_cla16_pg_logic14_and0 pg_logic_xor0=u_cla16_pg_logic14_xor0
|
|
.subckt xor_gate a=u_cla16_pg_logic14_xor0 b=u_cla16_or28 out=u_cla16_xor14
|
|
.subckt and_gate a=u_cla16_or25 b=u_cla16_pg_logic13_or0 out=u_cla16_and56
|
|
.subckt and_gate a=u_cla16_pg_logic14_or0 b=u_cla16_pg_logic12_or0 out=u_cla16_and57
|
|
.subckt and_gate a=u_cla16_and56 b=u_cla16_and57 out=u_cla16_and58
|
|
.subckt and_gate a=u_cla16_pg_logic12_and0 b=u_cla16_pg_logic14_or0 out=u_cla16_and59
|
|
.subckt and_gate a=u_cla16_and59 b=u_cla16_pg_logic13_or0 out=u_cla16_and60
|
|
.subckt and_gate a=u_cla16_pg_logic13_and0 b=u_cla16_pg_logic14_or0 out=u_cla16_and61
|
|
.subckt or_gate a=u_cla16_and58 b=u_cla16_and60 out=u_cla16_or29
|
|
.subckt or_gate a=u_cla16_or29 b=u_cla16_and61 out=u_cla16_or30
|
|
.subckt or_gate a=u_cla16_pg_logic14_and0 b=u_cla16_or30 out=u_cla16_or31
|
|
.subckt pg_logic a=a[15] b=b[15] pg_logic_or0=u_cla16_pg_logic15_or0 pg_logic_and0=u_cla16_pg_logic15_and0 pg_logic_xor0=u_cla16_pg_logic15_xor0
|
|
.subckt xor_gate a=u_cla16_pg_logic15_xor0 b=u_cla16_or31 out=u_cla16_xor15
|
|
.subckt and_gate a=u_cla16_or25 b=u_cla16_pg_logic14_or0 out=u_cla16_and62
|
|
.subckt and_gate a=u_cla16_pg_logic15_or0 b=u_cla16_pg_logic13_or0 out=u_cla16_and63
|
|
.subckt and_gate a=u_cla16_and62 b=u_cla16_and63 out=u_cla16_and64
|
|
.subckt and_gate a=u_cla16_and64 b=u_cla16_pg_logic12_or0 out=u_cla16_and65
|
|
.subckt and_gate a=u_cla16_pg_logic12_and0 b=u_cla16_pg_logic14_or0 out=u_cla16_and66
|
|
.subckt and_gate a=u_cla16_pg_logic15_or0 b=u_cla16_pg_logic13_or0 out=u_cla16_and67
|
|
.subckt and_gate a=u_cla16_and66 b=u_cla16_and67 out=u_cla16_and68
|
|
.subckt and_gate a=u_cla16_pg_logic13_and0 b=u_cla16_pg_logic15_or0 out=u_cla16_and69
|
|
.subckt and_gate a=u_cla16_and69 b=u_cla16_pg_logic14_or0 out=u_cla16_and70
|
|
.subckt and_gate a=u_cla16_pg_logic14_and0 b=u_cla16_pg_logic15_or0 out=u_cla16_and71
|
|
.subckt or_gate a=u_cla16_and65 b=u_cla16_and70 out=u_cla16_or32
|
|
.subckt or_gate a=u_cla16_and68 b=u_cla16_and71 out=u_cla16_or33
|
|
.subckt or_gate a=u_cla16_or32 b=u_cla16_or33 out=u_cla16_or34
|
|
.subckt or_gate a=u_cla16_pg_logic15_and0 b=u_cla16_or34 out=u_cla16_or35
|
|
.names u_cla16_pg_logic0_xor0 u_cla16_out[0]
|
|
1 1
|
|
.names u_cla16_xor1 u_cla16_out[1]
|
|
1 1
|
|
.names u_cla16_xor2 u_cla16_out[2]
|
|
1 1
|
|
.names u_cla16_xor3 u_cla16_out[3]
|
|
1 1
|
|
.names u_cla16_xor4 u_cla16_out[4]
|
|
1 1
|
|
.names u_cla16_xor5 u_cla16_out[5]
|
|
1 1
|
|
.names u_cla16_xor6 u_cla16_out[6]
|
|
1 1
|
|
.names u_cla16_xor7 u_cla16_out[7]
|
|
1 1
|
|
.names u_cla16_xor8 u_cla16_out[8]
|
|
1 1
|
|
.names u_cla16_xor9 u_cla16_out[9]
|
|
1 1
|
|
.names u_cla16_xor10 u_cla16_out[10]
|
|
1 1
|
|
.names u_cla16_xor11 u_cla16_out[11]
|
|
1 1
|
|
.names u_cla16_xor12 u_cla16_out[12]
|
|
1 1
|
|
.names u_cla16_xor13 u_cla16_out[13]
|
|
1 1
|
|
.names u_cla16_xor14 u_cla16_out[14]
|
|
1 1
|
|
.names u_cla16_xor15 u_cla16_out[15]
|
|
1 1
|
|
.names u_cla16_or35 u_cla16_out[16]
|
|
1 1
|
|
.end
|
|
|
|
.model pg_logic
|
|
.inputs a b
|
|
.outputs pg_logic_or0 pg_logic_and0 pg_logic_xor0
|
|
.names vdd
|
|
1
|
|
.names gnd
|
|
0
|
|
.subckt or_gate a=a b=b out=pg_logic_or0
|
|
.subckt and_gate a=a b=b out=pg_logic_and0
|
|
.subckt xor_gate a=a b=b out=pg_logic_xor0
|
|
.end
|
|
|
|
.model fa
|
|
.inputs a b cin
|
|
.outputs fa_xor1 fa_or0
|
|
.names vdd
|
|
1
|
|
.names gnd
|
|
0
|
|
.subckt xor_gate a=a b=b out=fa_xor0
|
|
.subckt and_gate a=a b=b out=fa_and0
|
|
.subckt xor_gate a=fa_xor0 b=cin out=fa_xor1
|
|
.subckt and_gate a=fa_xor0 b=cin out=fa_and1
|
|
.subckt or_gate a=fa_and0 b=fa_and1 out=fa_or0
|
|
.end
|
|
|
|
.model ha
|
|
.inputs a b
|
|
.outputs ha_xor0 ha_and0
|
|
.names vdd
|
|
1
|
|
.names gnd
|
|
0
|
|
.subckt xor_gate a=a b=b out=ha_xor0
|
|
.subckt and_gate a=a b=b out=ha_and0
|
|
.end
|
|
|
|
.model or_gate
|
|
.inputs a b
|
|
.outputs out
|
|
.names vdd
|
|
1
|
|
.names gnd
|
|
0
|
|
.names a b out
|
|
1- 1
|
|
-1 1
|
|
.end
|
|
|
|
.model not_gate
|
|
.inputs a
|
|
.outputs out
|
|
.names vdd
|
|
1
|
|
.names gnd
|
|
0
|
|
.names a out
|
|
0 1
|
|
.end
|
|
|
|
.model xor_gate
|
|
.inputs a b
|
|
.outputs out
|
|
.names vdd
|
|
1
|
|
.names gnd
|
|
0
|
|
.names a b out
|
|
01 1
|
|
10 1
|
|
.end
|
|
|
|
.model nand_gate
|
|
.inputs a b
|
|
.outputs out
|
|
.names vdd
|
|
1
|
|
.names gnd
|
|
0
|
|
.names a b out
|
|
0- 1
|
|
-0 1
|
|
.end
|
|
|
|
.model and_gate
|
|
.inputs a b
|
|
.outputs out
|
|
.names vdd
|
|
1
|
|
.names gnd
|
|
0
|
|
.names a b out
|
|
11 1
|
|
.end
|