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<article id="content">
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<header>
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<h1 class="title">Module <code>ariths_gen.wire_components.wires</code></h1>
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</header>
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<section id="section-intro">
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<details class="source">
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<summary>
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<span>Expand source code</span>
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</summary>
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<pre><code class="python">class Wire():
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"""Class representing basic wire used to interconnect components.
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Description of the __init__ method.
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Args:
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name (str): Name of the wire.
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prefix (str, optional): Prefix of the wire. Defaultly the same as its name. Defaults to "".
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value (int, optional): Value the wire carries (0,1). Defaults to 0.
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index (int, optional): Index position of wire (mainly used for indexing within a bus). Defaults to 0.
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parent_bus (object, optional): Bus object of which a Wire is a part of (used mainly for proper generation of wire names). Defaults to None.
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"""
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def __init__(self, name: str, prefix: str = "", value: int = 0, index: int = 0, parent_bus: object = None):
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self.name = name
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self.value = value
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self.index = index
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self.prefix = name if prefix == "" else prefix
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self.parent_bus = parent_bus
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@staticmethod
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def is_const():
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"""Information whether wire carries constant value.
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Returns:
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bool: False, because basic wire doesn't represent a wire with constant value.
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"""
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return False
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""" C CODE GENERATION """
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def get_declaration_c(self):
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"""Wire declaration in C code.
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Returns:
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str: Empty string if C code wire is carrying constant value (constant value is used in situ) or returns C code for declaration and initialization of wire's name.
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||
"""
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if self.is_const():
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return ""
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||
else:
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return f" uint8_t {self.name} = {self.value};\n"
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def get_wire_value_c_flat(self):
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"""Accesses desired bit value from wire represented in C code variable used for flat generation.
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Returns:
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str: C code bitwise shift to get desired bit value from this wire or wire variable's constant bit value 0/1.
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||
"""
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if self.is_const():
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return f"({self.c_const})"
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else:
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# If wire is part of an input bus (where wire names are concatenated from bus prefix and their index position inside the bus in square brackets)
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# then the wire value is obtained from bitwise shifting the required wire from the parent bus ('parent_bus.prefix' is the same value as 'self.prefix')
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if self.name.endswith("["+str(self.index)+"]") and self.parent_bus is not None:
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return f"(({self.prefix} >> {self.index}) & 0x01)"
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else:
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return f"(({self.name} >> 0) & 0x01)"
|
||
|
||
def get_wire_value_c_hier(self):
|
||
"""Accesses desired bit value from wire represented in C code variable used for hierarchical generation.
|
||
|
||
Returns:
|
||
str: C code bitwise shift to get desired bit value position from this wire or wire variable's constant bit value 0/1.
|
||
"""
|
||
if self.is_const():
|
||
return f"({self.c_const})"
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||
else:
|
||
return f"(({self.prefix} >> {self.index}) & 0x01)"
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||
|
||
def return_wire_value_c_flat(self, offset: int = 0):
|
||
"""Retrieves desired bit value from wire represented in C code variable and bitwise shifts it to desired position for storing it within a bus for flat generation.
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||
|
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Args:
|
||
offset (int, optional): Used to shift wire value in order to be stored in proper location inside a bus. Defaults to 0.
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||
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||
Returns:
|
||
str: C code bitwise shift for storing (constant/variable) wire value at desired offset position.
|
||
"""
|
||
if self.is_const():
|
||
return f"({self.c_const}) << {offset};\n"
|
||
else:
|
||
return f"(({self.name} >> 0) & 0x01) << {offset};\n"
|
||
|
||
def return_wire_value_c_hier(self, offset: int = 0):
|
||
"""Retrieves desired bit value from wire represented in C code variable and bitwise shifts it to desired position for storing it within a bus for hierarchical generation.
|
||
|
||
Args:
|
||
offset (int, optional): Used to shift wire value in order to be stored in proper location inside a bus. Defaults to 0.
|
||
|
||
Returns:
|
||
str: C code bitwise shift for storing (constant/variable) wire value at desired offset position.
|
||
"""
|
||
if self.is_const():
|
||
return f"({self.c_const}) << {offset};\n"
|
||
else:
|
||
return f"(({self.prefix} >> {self.index}) & 0x01) << {offset};\n"
|
||
|
||
""" VERILOG CODE GENERATION """
|
||
def get_declaration_v_flat(self):
|
||
"""Wire declaration for flat Verilog code.
|
||
|
||
Returns:
|
||
str: Empty string if Verilog code wire is carrying constant value (constant value is used in situ) or returns Verilog code for declaration and initialization of wire's name.
|
||
"""
|
||
if self.is_const():
|
||
return ""
|
||
else:
|
||
return f" wire {self.name};\n"
|
||
|
||
def get_declaration_v_hier(self):
|
||
"""Wire declaration for hierarchical Verilog code.
|
||
|
||
Returns:
|
||
str: Empty string if Verilog code wire is carrying constant value (constant value is used in situ) or returns Verilog code for declaration and initialization of wire's name.
|
||
"""
|
||
if self.is_const():
|
||
return ""
|
||
else:
|
||
return f" wire [0:0] {self.name};\n"
|
||
|
||
def get_wire_value_v_flat(self):
|
||
"""Accesses bit value from wire represented in Verilog code variable used for flat generation.
|
||
|
||
Returns:
|
||
str: Verilog code to get bit value from this wire or to get constant wire's bit value 0/1.
|
||
"""
|
||
if self.is_const():
|
||
return self.v_const
|
||
else:
|
||
return self.name
|
||
|
||
def get_wire_value_v_hier(self):
|
||
"""Accesses bit value from wire represented in Verilog code variable used for hierarchical generation.
|
||
|
||
Returns:
|
||
str: Verilog code to get bit value from this wire or to get constant wire's bit value 0/1.
|
||
"""
|
||
if self.is_const():
|
||
return self.v_const
|
||
else:
|
||
return f"{self.prefix}[{self.index}]"
|
||
|
||
def return_wire_value_v_flat(self):
|
||
"""Retrieves bit value from wire represented in Verilog code variable for storing it within a bus for flat generation.
|
||
|
||
Returns:
|
||
str: Verilog code for retrieving (constant/variable) wire value (and assign it at desired bus offset position).
|
||
"""
|
||
if self.is_const():
|
||
return f"{self.v_const};\n"
|
||
else:
|
||
return f"{self.name};\n"
|
||
|
||
def return_wire_value_v_hier(self):
|
||
"""Retrieves bit value from bus's wires and stores them in bus's corresponding Verilog variable at proper offset bit position in the bus for hierarchical generation.
|
||
|
||
Returns:
|
||
str: Verilog code for retrieving (constant/variable) wire value used for assigning it into bus represented in Verilog code variable.
|
||
"""
|
||
if self.is_const():
|
||
return f"{self.v_const};\n"
|
||
else:
|
||
return f"{self.prefix}[{self.index}];\n"
|
||
|
||
""" BLIF CODE GENERATION """
|
||
def get_declaration_blif(self, prefix: str = "", offset: int = 0, array: bool = False):
|
||
"""Wire declaration in Blif code.
|
||
|
||
Declares basic wire name if wire is not part of a bus
|
||
or declares wire by an offset of its position within the bus.
|
||
|
||
Args:
|
||
prefix (str, optional): Bus prefix of which this wire is a part off. Defaults to "".
|
||
offset (int, optional): Offset wire location within a bus. Defaults to 0.
|
||
array (bool, optional): Tells whether a basic wire or a wire from within a bus is to be declared. Defaults to False.
|
||
|
||
Returns:
|
||
str: Blif code for declaration of a wire.
|
||
"""
|
||
if array is True:
|
||
return f"{prefix}[{offset}]"
|
||
else:
|
||
return f"{self.name}"
|
||
|
||
def get_assign_blif(self, prefix: str, output: bool = False):
|
||
"""Assignment of wire value to another desired wire in Blif code.
|
||
|
||
This wire's value is either assigned to desired output bus wire (represented by `prefix` name) when `output`=True.
|
||
Otherwise the wire value at desired bus position (represented by `prefix` name) is assigned to this wire when `output`=False.
|
||
|
||
Args:
|
||
prefix (str): Name of the source/destination bus wire to be assigned from/to.
|
||
output (bool, optional): Whether `prefix` represents the destination or the source wire in the assignment. Defaultly it symbolizes the source. Defaults to False.
|
||
|
||
Returns:
|
||
str: Blif code for assignment of one wire to another.
|
||
"""
|
||
if output is True:
|
||
if self.is_const():
|
||
return f".names {self.blif_const} {prefix}\n" + \
|
||
f"1 1\n"
|
||
else:
|
||
return f".names {self.name} {prefix}\n" + \
|
||
f"1 1\n"
|
||
else:
|
||
if self.is_const():
|
||
return "\n"
|
||
else:
|
||
return f".names {prefix} {self.name}\n" + \
|
||
f"1 1\n"
|
||
|
||
def get_wire_value_blif(self):
|
||
"""Accesses bit value from wire represented in Blif code.
|
||
|
||
Used for assignment of specific one bit circuit/gate values to their respective parameters
|
||
in hierarchical Blif subcomponents generation.
|
||
|
||
Returns:
|
||
str: Blif code to get bit value from this wire or to get constant wire's bit value 0/1.
|
||
"""
|
||
if self.is_const():
|
||
return self.blif_const
|
||
elif self.parent_bus is not None and self.parent_bus.N > 1:
|
||
return self.name
|
||
else:
|
||
return self.prefix
|
||
|
||
|
||
# Wires with constant values #
|
||
class ConstantWireValue0(Wire):
|
||
"""Class representing wire carrying constant value 0 used to interconnect components.
|
||
|
||
Description of the __init__ method.
|
||
|
||
Method fills in desired constant wire's attributes regarding its values for individual representations.
|
||
|
||
Args:
|
||
name (str, optional): Custom constant wire name and prefix (used for generation of circuits that use constants as inputs). Defaults to "".
|
||
"""
|
||
def __init__(self, name: str = ""):
|
||
self.name = "constant_value_0" if name == "" else name
|
||
self.prefix = "constant_value_0" if name == "" else name
|
||
self.index = 0
|
||
self.value = 0
|
||
self.parent_bus = None
|
||
|
||
self.c_const = "0x00"
|
||
self.v_const = "1'b0"
|
||
self.blif_const = "gnd"
|
||
# Constant wire id for CGP generation
|
||
self.cgp_const = 0
|
||
|
||
@staticmethod
|
||
def is_const():
|
||
"""Information whether wire carries constant value.
|
||
|
||
Returns:
|
||
bool: True, because constant wire carries a constant value 0.
|
||
"""
|
||
return True
|
||
|
||
|
||
class ConstantWireValue1(Wire):
|
||
"""Class representing wire carrying constant value 1 used to interconnect components.
|
||
|
||
Description of the __init__ method.
|
||
|
||
Method fills in desired constant wire's attributes regarding its values for individual representations.
|
||
|
||
Args:
|
||
name (str, optional): Custom constant wire name and prefix (used for generation of circuits that use constants as inputs). Defaults to "".
|
||
"""
|
||
def __init__(self, name: str = ""):
|
||
self.name = "constant_value_1" if name == "" else name
|
||
self.prefix = "constant_value_1" if name == "" else name
|
||
self.index = 0
|
||
self.value = 1
|
||
self.parent_bus = None
|
||
|
||
self.c_const = "0x01"
|
||
self.v_const = "1'b1"
|
||
self.blif_const = "vdd"
|
||
# Constant wire id for CGP generation
|
||
self.cgp_const = 1
|
||
|
||
@staticmethod
|
||
def is_const():
|
||
"""Information whether wire carries constant value.
|
||
|
||
Returns:
|
||
bool: True, because constant wire carries a constant value 1.
|
||
"""
|
||
return True</code></pre>
|
||
</details>
|
||
</section>
|
||
<section>
|
||
</section>
|
||
<section>
|
||
</section>
|
||
<section>
|
||
</section>
|
||
<section>
|
||
<h2 class="section-title" id="header-classes">Classes</h2>
|
||
<dl>
|
||
<dt id="ariths_gen.wire_components.wires.ConstantWireValue0"><code class="flex name class">
|
||
<span>class <span class="ident">ConstantWireValue0</span></span>
|
||
<span>(</span><span>name: str = '')</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Class representing wire carrying constant value 0 used to interconnect components.</p>
|
||
<p>Description of the <strong>init</strong> method.</p>
|
||
<p>Method fills in desired constant wire's attributes regarding its values for individual representations.</p>
|
||
<h2 id="args">Args</h2>
|
||
<dl>
|
||
<dt><strong><code>name</code></strong> : <code>str</code>, optional</dt>
|
||
<dd>Custom constant wire name and prefix (used for generation of circuits that use constants as inputs). Defaults to "".</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">class ConstantWireValue0(Wire):
|
||
"""Class representing wire carrying constant value 0 used to interconnect components.
|
||
|
||
Description of the __init__ method.
|
||
|
||
Method fills in desired constant wire's attributes regarding its values for individual representations.
|
||
|
||
Args:
|
||
name (str, optional): Custom constant wire name and prefix (used for generation of circuits that use constants as inputs). Defaults to "".
|
||
"""
|
||
def __init__(self, name: str = ""):
|
||
self.name = "constant_value_0" if name == "" else name
|
||
self.prefix = "constant_value_0" if name == "" else name
|
||
self.index = 0
|
||
self.value = 0
|
||
self.parent_bus = None
|
||
|
||
self.c_const = "0x00"
|
||
self.v_const = "1'b0"
|
||
self.blif_const = "gnd"
|
||
# Constant wire id for CGP generation
|
||
self.cgp_const = 0
|
||
|
||
@staticmethod
|
||
def is_const():
|
||
"""Information whether wire carries constant value.
|
||
|
||
Returns:
|
||
bool: True, because constant wire carries a constant value 0.
|
||
"""
|
||
return True</code></pre>
|
||
</details>
|
||
<h3>Ancestors</h3>
|
||
<ul class="hlist">
|
||
<li><a title="ariths_gen.wire_components.wires.Wire" href="#ariths_gen.wire_components.wires.Wire">Wire</a></li>
|
||
</ul>
|
||
<h3>Static methods</h3>
|
||
<dl>
|
||
<dt id="ariths_gen.wire_components.wires.ConstantWireValue0.is_const"><code class="name flex">
|
||
<span>def <span class="ident">is_const</span></span>(<span>)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Information whether wire carries constant value.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>bool</code></dt>
|
||
<dd>True, because constant wire carries a constant value 0.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">@staticmethod
|
||
def is_const():
|
||
"""Information whether wire carries constant value.
|
||
|
||
Returns:
|
||
bool: True, because constant wire carries a constant value 0.
|
||
"""
|
||
return True</code></pre>
|
||
</details>
|
||
</dd>
|
||
</dl>
|
||
<h3>Inherited members</h3>
|
||
<ul class="hlist">
|
||
<li><code><b><a title="ariths_gen.wire_components.wires.Wire" href="#ariths_gen.wire_components.wires.Wire">Wire</a></b></code>:
|
||
<ul class="hlist">
|
||
<li><code><a title="ariths_gen.wire_components.wires.Wire.get_assign_blif" href="#ariths_gen.wire_components.wires.Wire.get_assign_blif">get_assign_blif</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.wires.Wire.get_declaration_blif" href="#ariths_gen.wire_components.wires.Wire.get_declaration_blif">get_declaration_blif</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.wires.Wire.get_declaration_c" href="#ariths_gen.wire_components.wires.Wire.get_declaration_c">get_declaration_c</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.wires.Wire.get_declaration_v_flat" href="#ariths_gen.wire_components.wires.Wire.get_declaration_v_flat">get_declaration_v_flat</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.wires.Wire.get_declaration_v_hier" href="#ariths_gen.wire_components.wires.Wire.get_declaration_v_hier">get_declaration_v_hier</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.wires.Wire.get_wire_value_blif" href="#ariths_gen.wire_components.wires.Wire.get_wire_value_blif">get_wire_value_blif</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.wires.Wire.get_wire_value_c_flat" href="#ariths_gen.wire_components.wires.Wire.get_wire_value_c_flat">get_wire_value_c_flat</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.wires.Wire.get_wire_value_c_hier" href="#ariths_gen.wire_components.wires.Wire.get_wire_value_c_hier">get_wire_value_c_hier</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.wires.Wire.get_wire_value_v_flat" href="#ariths_gen.wire_components.wires.Wire.get_wire_value_v_flat">get_wire_value_v_flat</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.wires.Wire.get_wire_value_v_hier" href="#ariths_gen.wire_components.wires.Wire.get_wire_value_v_hier">get_wire_value_v_hier</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.wires.Wire.return_wire_value_c_flat" href="#ariths_gen.wire_components.wires.Wire.return_wire_value_c_flat">return_wire_value_c_flat</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.wires.Wire.return_wire_value_c_hier" href="#ariths_gen.wire_components.wires.Wire.return_wire_value_c_hier">return_wire_value_c_hier</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.wires.Wire.return_wire_value_v_flat" href="#ariths_gen.wire_components.wires.Wire.return_wire_value_v_flat">return_wire_value_v_flat</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.wires.Wire.return_wire_value_v_hier" href="#ariths_gen.wire_components.wires.Wire.return_wire_value_v_hier">return_wire_value_v_hier</a></code></li>
|
||
</ul>
|
||
</li>
|
||
</ul>
|
||
</dd>
|
||
<dt id="ariths_gen.wire_components.wires.ConstantWireValue1"><code class="flex name class">
|
||
<span>class <span class="ident">ConstantWireValue1</span></span>
|
||
<span>(</span><span>name: str = '')</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Class representing wire carrying constant value 1 used to interconnect components.</p>
|
||
<p>Description of the <strong>init</strong> method.</p>
|
||
<p>Method fills in desired constant wire's attributes regarding its values for individual representations.</p>
|
||
<h2 id="args">Args</h2>
|
||
<dl>
|
||
<dt><strong><code>name</code></strong> : <code>str</code>, optional</dt>
|
||
<dd>Custom constant wire name and prefix (used for generation of circuits that use constants as inputs). Defaults to "".</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">class ConstantWireValue1(Wire):
|
||
"""Class representing wire carrying constant value 1 used to interconnect components.
|
||
|
||
Description of the __init__ method.
|
||
|
||
Method fills in desired constant wire's attributes regarding its values for individual representations.
|
||
|
||
Args:
|
||
name (str, optional): Custom constant wire name and prefix (used for generation of circuits that use constants as inputs). Defaults to "".
|
||
"""
|
||
def __init__(self, name: str = ""):
|
||
self.name = "constant_value_1" if name == "" else name
|
||
self.prefix = "constant_value_1" if name == "" else name
|
||
self.index = 0
|
||
self.value = 1
|
||
self.parent_bus = None
|
||
|
||
self.c_const = "0x01"
|
||
self.v_const = "1'b1"
|
||
self.blif_const = "vdd"
|
||
# Constant wire id for CGP generation
|
||
self.cgp_const = 1
|
||
|
||
@staticmethod
|
||
def is_const():
|
||
"""Information whether wire carries constant value.
|
||
|
||
Returns:
|
||
bool: True, because constant wire carries a constant value 1.
|
||
"""
|
||
return True</code></pre>
|
||
</details>
|
||
<h3>Ancestors</h3>
|
||
<ul class="hlist">
|
||
<li><a title="ariths_gen.wire_components.wires.Wire" href="#ariths_gen.wire_components.wires.Wire">Wire</a></li>
|
||
</ul>
|
||
<h3>Static methods</h3>
|
||
<dl>
|
||
<dt id="ariths_gen.wire_components.wires.ConstantWireValue1.is_const"><code class="name flex">
|
||
<span>def <span class="ident">is_const</span></span>(<span>)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Information whether wire carries constant value.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>bool</code></dt>
|
||
<dd>True, because constant wire carries a constant value 1.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">@staticmethod
|
||
def is_const():
|
||
"""Information whether wire carries constant value.
|
||
|
||
Returns:
|
||
bool: True, because constant wire carries a constant value 1.
|
||
"""
|
||
return True</code></pre>
|
||
</details>
|
||
</dd>
|
||
</dl>
|
||
<h3>Inherited members</h3>
|
||
<ul class="hlist">
|
||
<li><code><b><a title="ariths_gen.wire_components.wires.Wire" href="#ariths_gen.wire_components.wires.Wire">Wire</a></b></code>:
|
||
<ul class="hlist">
|
||
<li><code><a title="ariths_gen.wire_components.wires.Wire.get_assign_blif" href="#ariths_gen.wire_components.wires.Wire.get_assign_blif">get_assign_blif</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.wires.Wire.get_declaration_blif" href="#ariths_gen.wire_components.wires.Wire.get_declaration_blif">get_declaration_blif</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.wires.Wire.get_declaration_c" href="#ariths_gen.wire_components.wires.Wire.get_declaration_c">get_declaration_c</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.wires.Wire.get_declaration_v_flat" href="#ariths_gen.wire_components.wires.Wire.get_declaration_v_flat">get_declaration_v_flat</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.wires.Wire.get_declaration_v_hier" href="#ariths_gen.wire_components.wires.Wire.get_declaration_v_hier">get_declaration_v_hier</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.wires.Wire.get_wire_value_blif" href="#ariths_gen.wire_components.wires.Wire.get_wire_value_blif">get_wire_value_blif</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.wires.Wire.get_wire_value_c_flat" href="#ariths_gen.wire_components.wires.Wire.get_wire_value_c_flat">get_wire_value_c_flat</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.wires.Wire.get_wire_value_c_hier" href="#ariths_gen.wire_components.wires.Wire.get_wire_value_c_hier">get_wire_value_c_hier</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.wires.Wire.get_wire_value_v_flat" href="#ariths_gen.wire_components.wires.Wire.get_wire_value_v_flat">get_wire_value_v_flat</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.wires.Wire.get_wire_value_v_hier" href="#ariths_gen.wire_components.wires.Wire.get_wire_value_v_hier">get_wire_value_v_hier</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.wires.Wire.return_wire_value_c_flat" href="#ariths_gen.wire_components.wires.Wire.return_wire_value_c_flat">return_wire_value_c_flat</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.wires.Wire.return_wire_value_c_hier" href="#ariths_gen.wire_components.wires.Wire.return_wire_value_c_hier">return_wire_value_c_hier</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.wires.Wire.return_wire_value_v_flat" href="#ariths_gen.wire_components.wires.Wire.return_wire_value_v_flat">return_wire_value_v_flat</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.wires.Wire.return_wire_value_v_hier" href="#ariths_gen.wire_components.wires.Wire.return_wire_value_v_hier">return_wire_value_v_hier</a></code></li>
|
||
</ul>
|
||
</li>
|
||
</ul>
|
||
</dd>
|
||
<dt id="ariths_gen.wire_components.wires.Wire"><code class="flex name class">
|
||
<span>class <span class="ident">Wire</span></span>
|
||
<span>(</span><span>name: str, prefix: str = '', value: int = 0, index: int = 0, parent_bus: object = None)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Class representing basic wire used to interconnect components.</p>
|
||
<p>Description of the <strong>init</strong> method.</p>
|
||
<h2 id="args">Args</h2>
|
||
<dl>
|
||
<dt><strong><code>name</code></strong> : <code>str</code></dt>
|
||
<dd>Name of the wire.</dd>
|
||
<dt><strong><code>prefix</code></strong> : <code>str</code>, optional</dt>
|
||
<dd>Prefix of the wire. Defaultly the same as its name. Defaults to "".</dd>
|
||
<dt><strong><code>value</code></strong> : <code>int</code>, optional</dt>
|
||
<dd>Value the wire carries (0,1). Defaults to 0.</dd>
|
||
<dt><strong><code>index</code></strong> : <code>int</code>, optional</dt>
|
||
<dd>Index position of wire (mainly used for indexing within a bus). Defaults to 0.</dd>
|
||
<dt><strong><code>parent_bus</code></strong> : <code>object</code>, optional</dt>
|
||
<dd>Bus object of which a Wire is a part of (used mainly for proper generation of wire names). Defaults to None.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">class Wire():
|
||
"""Class representing basic wire used to interconnect components.
|
||
|
||
Description of the __init__ method.
|
||
|
||
Args:
|
||
name (str): Name of the wire.
|
||
prefix (str, optional): Prefix of the wire. Defaultly the same as its name. Defaults to "".
|
||
value (int, optional): Value the wire carries (0,1). Defaults to 0.
|
||
index (int, optional): Index position of wire (mainly used for indexing within a bus). Defaults to 0.
|
||
parent_bus (object, optional): Bus object of which a Wire is a part of (used mainly for proper generation of wire names). Defaults to None.
|
||
"""
|
||
def __init__(self, name: str, prefix: str = "", value: int = 0, index: int = 0, parent_bus: object = None):
|
||
self.name = name
|
||
self.value = value
|
||
self.index = index
|
||
self.prefix = name if prefix == "" else prefix
|
||
self.parent_bus = parent_bus
|
||
|
||
@staticmethod
|
||
def is_const():
|
||
"""Information whether wire carries constant value.
|
||
|
||
Returns:
|
||
bool: False, because basic wire doesn't represent a wire with constant value.
|
||
"""
|
||
return False
|
||
|
||
""" C CODE GENERATION """
|
||
def get_declaration_c(self):
|
||
"""Wire declaration in C code.
|
||
|
||
Returns:
|
||
str: Empty string if C code wire is carrying constant value (constant value is used in situ) or returns C code for declaration and initialization of wire's name.
|
||
"""
|
||
if self.is_const():
|
||
return ""
|
||
else:
|
||
return f" uint8_t {self.name} = {self.value};\n"
|
||
|
||
def get_wire_value_c_flat(self):
|
||
"""Accesses desired bit value from wire represented in C code variable used for flat generation.
|
||
|
||
Returns:
|
||
str: C code bitwise shift to get desired bit value from this wire or wire variable's constant bit value 0/1.
|
||
"""
|
||
if self.is_const():
|
||
return f"({self.c_const})"
|
||
else:
|
||
# If wire is part of an input bus (where wire names are concatenated from bus prefix and their index position inside the bus in square brackets)
|
||
# then the wire value is obtained from bitwise shifting the required wire from the parent bus ('parent_bus.prefix' is the same value as 'self.prefix')
|
||
if self.name.endswith("["+str(self.index)+"]") and self.parent_bus is not None:
|
||
return f"(({self.prefix} >> {self.index}) & 0x01)"
|
||
else:
|
||
return f"(({self.name} >> 0) & 0x01)"
|
||
|
||
def get_wire_value_c_hier(self):
|
||
"""Accesses desired bit value from wire represented in C code variable used for hierarchical generation.
|
||
|
||
Returns:
|
||
str: C code bitwise shift to get desired bit value position from this wire or wire variable's constant bit value 0/1.
|
||
"""
|
||
if self.is_const():
|
||
return f"({self.c_const})"
|
||
else:
|
||
return f"(({self.prefix} >> {self.index}) & 0x01)"
|
||
|
||
def return_wire_value_c_flat(self, offset: int = 0):
|
||
"""Retrieves desired bit value from wire represented in C code variable and bitwise shifts it to desired position for storing it within a bus for flat generation.
|
||
|
||
Args:
|
||
offset (int, optional): Used to shift wire value in order to be stored in proper location inside a bus. Defaults to 0.
|
||
|
||
Returns:
|
||
str: C code bitwise shift for storing (constant/variable) wire value at desired offset position.
|
||
"""
|
||
if self.is_const():
|
||
return f"({self.c_const}) << {offset};\n"
|
||
else:
|
||
return f"(({self.name} >> 0) & 0x01) << {offset};\n"
|
||
|
||
def return_wire_value_c_hier(self, offset: int = 0):
|
||
"""Retrieves desired bit value from wire represented in C code variable and bitwise shifts it to desired position for storing it within a bus for hierarchical generation.
|
||
|
||
Args:
|
||
offset (int, optional): Used to shift wire value in order to be stored in proper location inside a bus. Defaults to 0.
|
||
|
||
Returns:
|
||
str: C code bitwise shift for storing (constant/variable) wire value at desired offset position.
|
||
"""
|
||
if self.is_const():
|
||
return f"({self.c_const}) << {offset};\n"
|
||
else:
|
||
return f"(({self.prefix} >> {self.index}) & 0x01) << {offset};\n"
|
||
|
||
""" VERILOG CODE GENERATION """
|
||
def get_declaration_v_flat(self):
|
||
"""Wire declaration for flat Verilog code.
|
||
|
||
Returns:
|
||
str: Empty string if Verilog code wire is carrying constant value (constant value is used in situ) or returns Verilog code for declaration and initialization of wire's name.
|
||
"""
|
||
if self.is_const():
|
||
return ""
|
||
else:
|
||
return f" wire {self.name};\n"
|
||
|
||
def get_declaration_v_hier(self):
|
||
"""Wire declaration for hierarchical Verilog code.
|
||
|
||
Returns:
|
||
str: Empty string if Verilog code wire is carrying constant value (constant value is used in situ) or returns Verilog code for declaration and initialization of wire's name.
|
||
"""
|
||
if self.is_const():
|
||
return ""
|
||
else:
|
||
return f" wire [0:0] {self.name};\n"
|
||
|
||
def get_wire_value_v_flat(self):
|
||
"""Accesses bit value from wire represented in Verilog code variable used for flat generation.
|
||
|
||
Returns:
|
||
str: Verilog code to get bit value from this wire or to get constant wire's bit value 0/1.
|
||
"""
|
||
if self.is_const():
|
||
return self.v_const
|
||
else:
|
||
return self.name
|
||
|
||
def get_wire_value_v_hier(self):
|
||
"""Accesses bit value from wire represented in Verilog code variable used for hierarchical generation.
|
||
|
||
Returns:
|
||
str: Verilog code to get bit value from this wire or to get constant wire's bit value 0/1.
|
||
"""
|
||
if self.is_const():
|
||
return self.v_const
|
||
else:
|
||
return f"{self.prefix}[{self.index}]"
|
||
|
||
def return_wire_value_v_flat(self):
|
||
"""Retrieves bit value from wire represented in Verilog code variable for storing it within a bus for flat generation.
|
||
|
||
Returns:
|
||
str: Verilog code for retrieving (constant/variable) wire value (and assign it at desired bus offset position).
|
||
"""
|
||
if self.is_const():
|
||
return f"{self.v_const};\n"
|
||
else:
|
||
return f"{self.name};\n"
|
||
|
||
def return_wire_value_v_hier(self):
|
||
"""Retrieves bit value from bus's wires and stores them in bus's corresponding Verilog variable at proper offset bit position in the bus for hierarchical generation.
|
||
|
||
Returns:
|
||
str: Verilog code for retrieving (constant/variable) wire value used for assigning it into bus represented in Verilog code variable.
|
||
"""
|
||
if self.is_const():
|
||
return f"{self.v_const};\n"
|
||
else:
|
||
return f"{self.prefix}[{self.index}];\n"
|
||
|
||
""" BLIF CODE GENERATION """
|
||
def get_declaration_blif(self, prefix: str = "", offset: int = 0, array: bool = False):
|
||
"""Wire declaration in Blif code.
|
||
|
||
Declares basic wire name if wire is not part of a bus
|
||
or declares wire by an offset of its position within the bus.
|
||
|
||
Args:
|
||
prefix (str, optional): Bus prefix of which this wire is a part off. Defaults to "".
|
||
offset (int, optional): Offset wire location within a bus. Defaults to 0.
|
||
array (bool, optional): Tells whether a basic wire or a wire from within a bus is to be declared. Defaults to False.
|
||
|
||
Returns:
|
||
str: Blif code for declaration of a wire.
|
||
"""
|
||
if array is True:
|
||
return f"{prefix}[{offset}]"
|
||
else:
|
||
return f"{self.name}"
|
||
|
||
def get_assign_blif(self, prefix: str, output: bool = False):
|
||
"""Assignment of wire value to another desired wire in Blif code.
|
||
|
||
This wire's value is either assigned to desired output bus wire (represented by `prefix` name) when `output`=True.
|
||
Otherwise the wire value at desired bus position (represented by `prefix` name) is assigned to this wire when `output`=False.
|
||
|
||
Args:
|
||
prefix (str): Name of the source/destination bus wire to be assigned from/to.
|
||
output (bool, optional): Whether `prefix` represents the destination or the source wire in the assignment. Defaultly it symbolizes the source. Defaults to False.
|
||
|
||
Returns:
|
||
str: Blif code for assignment of one wire to another.
|
||
"""
|
||
if output is True:
|
||
if self.is_const():
|
||
return f".names {self.blif_const} {prefix}\n" + \
|
||
f"1 1\n"
|
||
else:
|
||
return f".names {self.name} {prefix}\n" + \
|
||
f"1 1\n"
|
||
else:
|
||
if self.is_const():
|
||
return "\n"
|
||
else:
|
||
return f".names {prefix} {self.name}\n" + \
|
||
f"1 1\n"
|
||
|
||
def get_wire_value_blif(self):
|
||
"""Accesses bit value from wire represented in Blif code.
|
||
|
||
Used for assignment of specific one bit circuit/gate values to their respective parameters
|
||
in hierarchical Blif subcomponents generation.
|
||
|
||
Returns:
|
||
str: Blif code to get bit value from this wire or to get constant wire's bit value 0/1.
|
||
"""
|
||
if self.is_const():
|
||
return self.blif_const
|
||
elif self.parent_bus is not None and self.parent_bus.N > 1:
|
||
return self.name
|
||
else:
|
||
return self.prefix</code></pre>
|
||
</details>
|
||
<h3>Subclasses</h3>
|
||
<ul class="hlist">
|
||
<li><a title="ariths_gen.wire_components.wires.ConstantWireValue0" href="#ariths_gen.wire_components.wires.ConstantWireValue0">ConstantWireValue0</a></li>
|
||
<li><a title="ariths_gen.wire_components.wires.ConstantWireValue1" href="#ariths_gen.wire_components.wires.ConstantWireValue1">ConstantWireValue1</a></li>
|
||
</ul>
|
||
<h3>Static methods</h3>
|
||
<dl>
|
||
<dt id="ariths_gen.wire_components.wires.Wire.is_const"><code class="name flex">
|
||
<span>def <span class="ident">is_const</span></span>(<span>)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Information whether wire carries constant value.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>bool</code></dt>
|
||
<dd>False, because basic wire doesn't represent a wire with constant value.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">@staticmethod
|
||
def is_const():
|
||
"""Information whether wire carries constant value.
|
||
|
||
Returns:
|
||
bool: False, because basic wire doesn't represent a wire with constant value.
|
||
"""
|
||
return False</code></pre>
|
||
</details>
|
||
</dd>
|
||
</dl>
|
||
<h3>Methods</h3>
|
||
<dl>
|
||
<dt id="ariths_gen.wire_components.wires.Wire.get_assign_blif"><code class="name flex">
|
||
<span>def <span class="ident">get_assign_blif</span></span>(<span>self, prefix: str, output: bool = False)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Assignment of wire value to another desired wire in Blif code.</p>
|
||
<p>This wire's value is either assigned to desired output bus wire (represented by <code>prefix</code> name) when <code>output</code>=True.
|
||
Otherwise the wire value at desired bus position (represented by <code>prefix</code> name) is assigned to this wire when <code>output</code>=False.</p>
|
||
<h2 id="args">Args</h2>
|
||
<dl>
|
||
<dt><strong><code>prefix</code></strong> : <code>str</code></dt>
|
||
<dd>Name of the source/destination bus wire to be assigned from/to.</dd>
|
||
<dt><strong><code>output</code></strong> : <code>bool</code>, optional</dt>
|
||
<dd>Whether <code>prefix</code> represents the destination or the source wire in the assignment. Defaultly it symbolizes the source. Defaults to False.</dd>
|
||
</dl>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Blif code for assignment of one wire to another.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_assign_blif(self, prefix: str, output: bool = False):
|
||
"""Assignment of wire value to another desired wire in Blif code.
|
||
|
||
This wire's value is either assigned to desired output bus wire (represented by `prefix` name) when `output`=True.
|
||
Otherwise the wire value at desired bus position (represented by `prefix` name) is assigned to this wire when `output`=False.
|
||
|
||
Args:
|
||
prefix (str): Name of the source/destination bus wire to be assigned from/to.
|
||
output (bool, optional): Whether `prefix` represents the destination or the source wire in the assignment. Defaultly it symbolizes the source. Defaults to False.
|
||
|
||
Returns:
|
||
str: Blif code for assignment of one wire to another.
|
||
"""
|
||
if output is True:
|
||
if self.is_const():
|
||
return f".names {self.blif_const} {prefix}\n" + \
|
||
f"1 1\n"
|
||
else:
|
||
return f".names {self.name} {prefix}\n" + \
|
||
f"1 1\n"
|
||
else:
|
||
if self.is_const():
|
||
return "\n"
|
||
else:
|
||
return f".names {prefix} {self.name}\n" + \
|
||
f"1 1\n"</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.wire_components.wires.Wire.get_declaration_blif"><code class="name flex">
|
||
<span>def <span class="ident">get_declaration_blif</span></span>(<span>self, prefix: str = '', offset: int = 0, array: bool = False)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Wire declaration in Blif code.</p>
|
||
<p>Declares basic wire name if wire is not part of a bus
|
||
or declares wire by an offset of its position within the bus.</p>
|
||
<h2 id="args">Args</h2>
|
||
<dl>
|
||
<dt><strong><code>prefix</code></strong> : <code>str</code>, optional</dt>
|
||
<dd>Bus prefix of which this wire is a part off. Defaults to "".</dd>
|
||
<dt><strong><code>offset</code></strong> : <code>int</code>, optional</dt>
|
||
<dd>Offset wire location within a bus. Defaults to 0.</dd>
|
||
<dt><strong><code>array</code></strong> : <code>bool</code>, optional</dt>
|
||
<dd>Tells whether a basic wire or a wire from within a bus is to be declared. Defaults to False.</dd>
|
||
</dl>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Blif code for declaration of a wire.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_declaration_blif(self, prefix: str = "", offset: int = 0, array: bool = False):
|
||
"""Wire declaration in Blif code.
|
||
|
||
Declares basic wire name if wire is not part of a bus
|
||
or declares wire by an offset of its position within the bus.
|
||
|
||
Args:
|
||
prefix (str, optional): Bus prefix of which this wire is a part off. Defaults to "".
|
||
offset (int, optional): Offset wire location within a bus. Defaults to 0.
|
||
array (bool, optional): Tells whether a basic wire or a wire from within a bus is to be declared. Defaults to False.
|
||
|
||
Returns:
|
||
str: Blif code for declaration of a wire.
|
||
"""
|
||
if array is True:
|
||
return f"{prefix}[{offset}]"
|
||
else:
|
||
return f"{self.name}"</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.wire_components.wires.Wire.get_declaration_c"><code class="name flex">
|
||
<span>def <span class="ident">get_declaration_c</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Wire declaration in C code.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Empty string if C code wire is carrying constant value (constant value is used in situ) or returns C code for declaration and initialization of wire's name.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_declaration_c(self):
|
||
"""Wire declaration in C code.
|
||
|
||
Returns:
|
||
str: Empty string if C code wire is carrying constant value (constant value is used in situ) or returns C code for declaration and initialization of wire's name.
|
||
"""
|
||
if self.is_const():
|
||
return ""
|
||
else:
|
||
return f" uint8_t {self.name} = {self.value};\n"</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.wire_components.wires.Wire.get_declaration_v_flat"><code class="name flex">
|
||
<span>def <span class="ident">get_declaration_v_flat</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Wire declaration for flat Verilog code.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Empty string if Verilog code wire is carrying constant value (constant value is used in situ) or returns Verilog code for declaration and initialization of wire's name.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_declaration_v_flat(self):
|
||
"""Wire declaration for flat Verilog code.
|
||
|
||
Returns:
|
||
str: Empty string if Verilog code wire is carrying constant value (constant value is used in situ) or returns Verilog code for declaration and initialization of wire's name.
|
||
"""
|
||
if self.is_const():
|
||
return ""
|
||
else:
|
||
return f" wire {self.name};\n"</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.wire_components.wires.Wire.get_declaration_v_hier"><code class="name flex">
|
||
<span>def <span class="ident">get_declaration_v_hier</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Wire declaration for hierarchical Verilog code.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Empty string if Verilog code wire is carrying constant value (constant value is used in situ) or returns Verilog code for declaration and initialization of wire's name.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_declaration_v_hier(self):
|
||
"""Wire declaration for hierarchical Verilog code.
|
||
|
||
Returns:
|
||
str: Empty string if Verilog code wire is carrying constant value (constant value is used in situ) or returns Verilog code for declaration and initialization of wire's name.
|
||
"""
|
||
if self.is_const():
|
||
return ""
|
||
else:
|
||
return f" wire [0:0] {self.name};\n"</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.wire_components.wires.Wire.get_wire_value_blif"><code class="name flex">
|
||
<span>def <span class="ident">get_wire_value_blif</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Accesses bit value from wire represented in Blif code.</p>
|
||
<p>Used for assignment of specific one bit circuit/gate values to their respective parameters
|
||
in hierarchical Blif subcomponents generation.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Blif code to get bit value from this wire or to get constant wire's bit value 0/1.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_wire_value_blif(self):
|
||
"""Accesses bit value from wire represented in Blif code.
|
||
|
||
Used for assignment of specific one bit circuit/gate values to their respective parameters
|
||
in hierarchical Blif subcomponents generation.
|
||
|
||
Returns:
|
||
str: Blif code to get bit value from this wire or to get constant wire's bit value 0/1.
|
||
"""
|
||
if self.is_const():
|
||
return self.blif_const
|
||
elif self.parent_bus is not None and self.parent_bus.N > 1:
|
||
return self.name
|
||
else:
|
||
return self.prefix</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.wire_components.wires.Wire.get_wire_value_c_flat"><code class="name flex">
|
||
<span>def <span class="ident">get_wire_value_c_flat</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Accesses desired bit value from wire represented in C code variable used for flat generation.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>C code bitwise shift to get desired bit value from this wire or wire variable's constant bit value 0/1.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_wire_value_c_flat(self):
|
||
"""Accesses desired bit value from wire represented in C code variable used for flat generation.
|
||
|
||
Returns:
|
||
str: C code bitwise shift to get desired bit value from this wire or wire variable's constant bit value 0/1.
|
||
"""
|
||
if self.is_const():
|
||
return f"({self.c_const})"
|
||
else:
|
||
# If wire is part of an input bus (where wire names are concatenated from bus prefix and their index position inside the bus in square brackets)
|
||
# then the wire value is obtained from bitwise shifting the required wire from the parent bus ('parent_bus.prefix' is the same value as 'self.prefix')
|
||
if self.name.endswith("["+str(self.index)+"]") and self.parent_bus is not None:
|
||
return f"(({self.prefix} >> {self.index}) & 0x01)"
|
||
else:
|
||
return f"(({self.name} >> 0) & 0x01)"</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.wire_components.wires.Wire.get_wire_value_c_hier"><code class="name flex">
|
||
<span>def <span class="ident">get_wire_value_c_hier</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Accesses desired bit value from wire represented in C code variable used for hierarchical generation.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>C code bitwise shift to get desired bit value position from this wire or wire variable's constant bit value 0/1.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_wire_value_c_hier(self):
|
||
"""Accesses desired bit value from wire represented in C code variable used for hierarchical generation.
|
||
|
||
Returns:
|
||
str: C code bitwise shift to get desired bit value position from this wire or wire variable's constant bit value 0/1.
|
||
"""
|
||
if self.is_const():
|
||
return f"({self.c_const})"
|
||
else:
|
||
return f"(({self.prefix} >> {self.index}) & 0x01)"</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.wire_components.wires.Wire.get_wire_value_v_flat"><code class="name flex">
|
||
<span>def <span class="ident">get_wire_value_v_flat</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Accesses bit value from wire represented in Verilog code variable used for flat generation.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Verilog code to get bit value from this wire or to get constant wire's bit value 0/1.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_wire_value_v_flat(self):
|
||
"""Accesses bit value from wire represented in Verilog code variable used for flat generation.
|
||
|
||
Returns:
|
||
str: Verilog code to get bit value from this wire or to get constant wire's bit value 0/1.
|
||
"""
|
||
if self.is_const():
|
||
return self.v_const
|
||
else:
|
||
return self.name</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.wire_components.wires.Wire.get_wire_value_v_hier"><code class="name flex">
|
||
<span>def <span class="ident">get_wire_value_v_hier</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Accesses bit value from wire represented in Verilog code variable used for hierarchical generation.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Verilog code to get bit value from this wire or to get constant wire's bit value 0/1.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_wire_value_v_hier(self):
|
||
"""Accesses bit value from wire represented in Verilog code variable used for hierarchical generation.
|
||
|
||
Returns:
|
||
str: Verilog code to get bit value from this wire or to get constant wire's bit value 0/1.
|
||
"""
|
||
if self.is_const():
|
||
return self.v_const
|
||
else:
|
||
return f"{self.prefix}[{self.index}]"</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.wire_components.wires.Wire.return_wire_value_c_flat"><code class="name flex">
|
||
<span>def <span class="ident">return_wire_value_c_flat</span></span>(<span>self, offset: int = 0)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Retrieves desired bit value from wire represented in C code variable and bitwise shifts it to desired position for storing it within a bus for flat generation.</p>
|
||
<h2 id="args">Args</h2>
|
||
<dl>
|
||
<dt><strong><code>offset</code></strong> : <code>int</code>, optional</dt>
|
||
<dd>Used to shift wire value in order to be stored in proper location inside a bus. Defaults to 0.</dd>
|
||
</dl>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>C code bitwise shift for storing (constant/variable) wire value at desired offset position.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def return_wire_value_c_flat(self, offset: int = 0):
|
||
"""Retrieves desired bit value from wire represented in C code variable and bitwise shifts it to desired position for storing it within a bus for flat generation.
|
||
|
||
Args:
|
||
offset (int, optional): Used to shift wire value in order to be stored in proper location inside a bus. Defaults to 0.
|
||
|
||
Returns:
|
||
str: C code bitwise shift for storing (constant/variable) wire value at desired offset position.
|
||
"""
|
||
if self.is_const():
|
||
return f"({self.c_const}) << {offset};\n"
|
||
else:
|
||
return f"(({self.name} >> 0) & 0x01) << {offset};\n"</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.wire_components.wires.Wire.return_wire_value_c_hier"><code class="name flex">
|
||
<span>def <span class="ident">return_wire_value_c_hier</span></span>(<span>self, offset: int = 0)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Retrieves desired bit value from wire represented in C code variable and bitwise shifts it to desired position for storing it within a bus for hierarchical generation.</p>
|
||
<h2 id="args">Args</h2>
|
||
<dl>
|
||
<dt><strong><code>offset</code></strong> : <code>int</code>, optional</dt>
|
||
<dd>Used to shift wire value in order to be stored in proper location inside a bus. Defaults to 0.</dd>
|
||
</dl>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>C code bitwise shift for storing (constant/variable) wire value at desired offset position.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def return_wire_value_c_hier(self, offset: int = 0):
|
||
"""Retrieves desired bit value from wire represented in C code variable and bitwise shifts it to desired position for storing it within a bus for hierarchical generation.
|
||
|
||
Args:
|
||
offset (int, optional): Used to shift wire value in order to be stored in proper location inside a bus. Defaults to 0.
|
||
|
||
Returns:
|
||
str: C code bitwise shift for storing (constant/variable) wire value at desired offset position.
|
||
"""
|
||
if self.is_const():
|
||
return f"({self.c_const}) << {offset};\n"
|
||
else:
|
||
return f"(({self.prefix} >> {self.index}) & 0x01) << {offset};\n"</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.wire_components.wires.Wire.return_wire_value_v_flat"><code class="name flex">
|
||
<span>def <span class="ident">return_wire_value_v_flat</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Retrieves bit value from wire represented in Verilog code variable for storing it within a bus for flat generation.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Verilog code for retrieving (constant/variable) wire value (and assign it at desired bus offset position).</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def return_wire_value_v_flat(self):
|
||
"""Retrieves bit value from wire represented in Verilog code variable for storing it within a bus for flat generation.
|
||
|
||
Returns:
|
||
str: Verilog code for retrieving (constant/variable) wire value (and assign it at desired bus offset position).
|
||
"""
|
||
if self.is_const():
|
||
return f"{self.v_const};\n"
|
||
else:
|
||
return f"{self.name};\n"</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.wire_components.wires.Wire.return_wire_value_v_hier"><code class="name flex">
|
||
<span>def <span class="ident">return_wire_value_v_hier</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Retrieves bit value from bus's wires and stores them in bus's corresponding Verilog variable at proper offset bit position in the bus for hierarchical generation.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Verilog code for retrieving (constant/variable) wire value used for assigning it into bus represented in Verilog code variable.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def return_wire_value_v_hier(self):
|
||
"""Retrieves bit value from bus's wires and stores them in bus's corresponding Verilog variable at proper offset bit position in the bus for hierarchical generation.
|
||
|
||
Returns:
|
||
str: Verilog code for retrieving (constant/variable) wire value used for assigning it into bus represented in Verilog code variable.
|
||
"""
|
||
if self.is_const():
|
||
return f"{self.v_const};\n"
|
||
else:
|
||
return f"{self.prefix}[{self.index}];\n"</code></pre>
|
||
</details>
|
||
</dd>
|
||
</dl>
|
||
</dd>
|
||
</dl>
|
||
</section>
|
||
</article>
|
||
<nav id="sidebar">
|
||
<h1>Index</h1>
|
||
<div class="toc">
|
||
<ul></ul>
|
||
</div>
|
||
<ul id="index">
|
||
<li><h3>Super-module</h3>
|
||
<ul>
|
||
<li><code><a title="ariths_gen.wire_components" href="index.html">ariths_gen.wire_components</a></code></li>
|
||
</ul>
|
||
</li>
|
||
<li><h3><a href="#header-classes">Classes</a></h3>
|
||
<ul>
|
||
<li>
|
||
<h4><code><a title="ariths_gen.wire_components.wires.ConstantWireValue0" href="#ariths_gen.wire_components.wires.ConstantWireValue0">ConstantWireValue0</a></code></h4>
|
||
<ul class="">
|
||
<li><code><a title="ariths_gen.wire_components.wires.ConstantWireValue0.is_const" href="#ariths_gen.wire_components.wires.ConstantWireValue0.is_const">is_const</a></code></li>
|
||
</ul>
|
||
</li>
|
||
<li>
|
||
<h4><code><a title="ariths_gen.wire_components.wires.ConstantWireValue1" href="#ariths_gen.wire_components.wires.ConstantWireValue1">ConstantWireValue1</a></code></h4>
|
||
<ul class="">
|
||
<li><code><a title="ariths_gen.wire_components.wires.ConstantWireValue1.is_const" href="#ariths_gen.wire_components.wires.ConstantWireValue1.is_const">is_const</a></code></li>
|
||
</ul>
|
||
</li>
|
||
<li>
|
||
<h4><code><a title="ariths_gen.wire_components.wires.Wire" href="#ariths_gen.wire_components.wires.Wire">Wire</a></code></h4>
|
||
<ul class="">
|
||
<li><code><a title="ariths_gen.wire_components.wires.Wire.get_assign_blif" href="#ariths_gen.wire_components.wires.Wire.get_assign_blif">get_assign_blif</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.wires.Wire.get_declaration_blif" href="#ariths_gen.wire_components.wires.Wire.get_declaration_blif">get_declaration_blif</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.wires.Wire.get_declaration_c" href="#ariths_gen.wire_components.wires.Wire.get_declaration_c">get_declaration_c</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.wires.Wire.get_declaration_v_flat" href="#ariths_gen.wire_components.wires.Wire.get_declaration_v_flat">get_declaration_v_flat</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.wires.Wire.get_declaration_v_hier" href="#ariths_gen.wire_components.wires.Wire.get_declaration_v_hier">get_declaration_v_hier</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.wires.Wire.get_wire_value_blif" href="#ariths_gen.wire_components.wires.Wire.get_wire_value_blif">get_wire_value_blif</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.wires.Wire.get_wire_value_c_flat" href="#ariths_gen.wire_components.wires.Wire.get_wire_value_c_flat">get_wire_value_c_flat</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.wires.Wire.get_wire_value_c_hier" href="#ariths_gen.wire_components.wires.Wire.get_wire_value_c_hier">get_wire_value_c_hier</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.wires.Wire.get_wire_value_v_flat" href="#ariths_gen.wire_components.wires.Wire.get_wire_value_v_flat">get_wire_value_v_flat</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.wires.Wire.get_wire_value_v_hier" href="#ariths_gen.wire_components.wires.Wire.get_wire_value_v_hier">get_wire_value_v_hier</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.wires.Wire.is_const" href="#ariths_gen.wire_components.wires.Wire.is_const">is_const</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.wires.Wire.return_wire_value_c_flat" href="#ariths_gen.wire_components.wires.Wire.return_wire_value_c_flat">return_wire_value_c_flat</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.wires.Wire.return_wire_value_c_hier" href="#ariths_gen.wire_components.wires.Wire.return_wire_value_c_hier">return_wire_value_c_hier</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.wires.Wire.return_wire_value_v_flat" href="#ariths_gen.wire_components.wires.Wire.return_wire_value_v_flat">return_wire_value_v_flat</a></code></li>
|
||
<li><code><a title="ariths_gen.wire_components.wires.Wire.return_wire_value_v_hier" href="#ariths_gen.wire_components.wires.Wire.return_wire_value_v_hier">return_wire_value_v_hier</a></code></li>
|
||
</ul>
|
||
</li>
|
||
</ul>
|
||
</li>
|
||
</ul>
|
||
</nav>
|
||
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<p>Generated by <a href="https://pdoc3.github.io/pdoc"><cite>pdoc</cite> 0.9.2</a>.</p>
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