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<article id="content">
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<header>
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<h1 class="title">Module <code>ariths_gen.core.arithmetic_circuits.arithmetic_circuit</code></h1>
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</header>
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<section id="section-intro">
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<details class="source">
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<summary>
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<span>Expand source code</span>
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</summary>
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<pre><code class="python">from ariths_gen.core.logic_gate_circuits.logic_gate_circuit import OneInputLogicGate, TwoInputLogicGate
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from ariths_gen.wire_components import (
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Wire,
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ConstantWireValue0,
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ConstantWireValue1,
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Bus
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)
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class ArithmeticCircuit():
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"""Class represents a general arithmetic circuit and ensures their generation to various representations.
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The __init__ method fills some mandatory attributes concerning arithmetic circuit
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that are later used for generation into various representations.
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"""
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def __init__(self):
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self.components = []
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self.circuit_wires = []
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self.circuit_gates = []
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self.c_data_type = "uint64_t"
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self.N = 1
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def add_component(self, component):
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"""Adds a component into list of circuit's inner subcomponents.
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Args:
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component: Subcomponent to be added into list of components composing described circuit.
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"""
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self.components.append(component)
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def get_previous_component(self, number: int = 1):
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"""Retrieves previously added composite subcomponent from circuit's list of components.
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Args:
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number (int, optional): Offset indicating which lastly added component will be retrieved. Defaults to 1.
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Returns:
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component: Desired previously added composite component.
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"""
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return self.components[-number]
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def get_instance_num(self, cls, count_disabled_gates: bool = True):
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"""Informs how many instances of the same type are already present inside circuit's components list.
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Args:
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cls (type): Class type for which to count the number of instances in the components list.
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count_disabled_gates (bool, optional): Indicates whether logic gates that aren't generated should be also counted. Defaults to True.
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Returns:
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int: Number of instances of the same class type.
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"""
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if issubclass(cls, TwoInputLogicGate) and count_disabled_gates is False:
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return sum(isinstance(c, cls) for c in self.components if isinstance(c, cls) and c.disable_generation is False)
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else:
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return sum(isinstance(c, cls) for c in self.components)
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def get_circuit_gates(self):
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"""Gets a list of all the logic gates in circuit that should be generated.
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Returns:
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list: List of composite logic gates.
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"""
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gates = []
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for c in self.components:
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if isinstance(c, TwoInputLogicGate):
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if c.disable_generation is False:
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gates.append(c)
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else:
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gates.extend((c.get_circuit_gates()))
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return gates
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def get_one_bit_components(self):
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"""Retrieves a list of all the one bit circuits (besides logic gates) present as subcomponents inside the circuit.
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Returns:
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list: List of composite one bit circuits.
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"""
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one_bit_comps = []
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for c in self.components:
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if isinstance(c, TwoInputLogicGate):
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continue
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elif isinstance(getattr(c, 'a'), Wire):
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one_bit_comps.append(c)
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else:
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one_bit_comps.extend(c.get_one_bit_components())
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return one_bit_comps
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def get_multi_bit_components(self):
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"""Retrieves a list of all the multi bit circuits present as subcomponents inside the circuit.
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Returns:
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list: List of composite multi bit circuits.
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"""
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multi_bit_comps = []
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for c in self.components:
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if isinstance(c, TwoInputLogicGate):
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continue
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elif isinstance(getattr(c, 'a'), Wire):
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continue
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else:
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multi_bit_comps.append(c)
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return multi_bit_comps
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@staticmethod
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def get_unique_types(components: list):
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"""Retrieves just the unique representatives of class types present inside the provided components list.
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Args:
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components (list): List of components to be filtered.
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Returns:
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list: List of unique composite class types.
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"""
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return list({type(c): c for c in components}.values())
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def get_component_types(self):
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"""Retrieves a list of all the unique types of subcomponents composing the circuit.
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Returning list consists of only the unique types of logic gates, one bit circuits and multi bit circuits.
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Returns:
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list: List of unique component types describing the circuit.
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"""
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gate_comps = self.get_unique_types(components=self.get_circuit_gates())
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one_bit_comps = self.get_unique_types(components=self.get_one_bit_components())
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multi_bit_comps = self.get_unique_types(components=self.get_multi_bit_components())
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all_components = gate_comps + one_bit_comps + multi_bit_comps
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return all_components
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def get_sum_wire(self):
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"""Get output wire carrying sum value.
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Returns:
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Wire: Return sum wire.
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"""
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return self.out.get_wire(0)
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def get_carry_wire(self):
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"""Get output wire carrying carry out value.
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Returns:
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Wire: Return carry out wire.
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"""
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return self.out.get_wire(1)
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def save_wire_id(self, wire: Wire):
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"""Returns appropriate wire index position within the circuit.
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Constant wire with value 0 has constant index of 0.
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Constant wire with value 1 has constant index of 1.
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Other wires indexes start counting from 2 and up.
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Args:
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wire (Wire): Wire that will be stored at this circuit index position.
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Returns:
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int: Wire's index position within circuit.
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"""
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if wire.is_const():
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return wire.cgp_const
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else:
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return len([w[0] for w in self.circuit_wires if w[0].is_const() is False]) + 2
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def get_cgp_wires(self):
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"""Gets a list of all wires in circuit along with their index position for cgp chromosome generation and stores them inside `self.circuit_wires` list.
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Constant wire with value 0 has constant index of 0.
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Constant wire with value 1 has constant index of 1.
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Other wires indexes start counting from 2 and up.
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"""
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self.circuit_wires = []
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if isinstance(self.a, Bus):
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[self.circuit_wires.append((w, f"{w.name}", self.save_wire_id(wire=w))) for w in self.a.bus]
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[self.circuit_wires.append((w, f"{w.name}", self.save_wire_id(wire=w))) for w in self.b.bus]
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else:
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self.circuit_wires.append((self.a, f"{self.a.name}", self.save_wire_id(wire=self.a)))
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self.circuit_wires.append((self.b, f"{self.b.name}", self.save_wire_id(wire=self.b)))
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if hasattr(self, 'c'):
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self.circuit_wires.append((self.c, f"{self.c.name}", self.save_wire_id(wire=self.c)))
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for gate in self.circuit_gates:
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if not [item for item in self.circuit_wires if gate.a.name == item[1]]:
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self.circuit_wires.append((gate.a, gate.a.name, self.save_wire_id(wire=gate.a)))
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if hasattr(gate, 'b') and not [item for item in self.circuit_wires if gate.b.name == item[1]]:
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self.circuit_wires.append((gate.b, gate.b.name, self.save_wire_id(wire=gate.b)))
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if not [item for item in self.circuit_wires if gate.out.name == item[1]]:
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self.circuit_wires.append((gate.out, gate.out.name, self.save_wire_id(wire=gate.out)))
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def get_circuit_wire_index(self, wire: Wire):
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"""Searches for circuit's wire unique index position within the circuit. Used for cgp chromosome generation.
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Args:
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wire (Wire): Wire to retrieve index position of.
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Returns:
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int: Wire's index position number within the circuit.
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"""
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if wire.is_const():
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return wire.cgp_const
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else:
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for w in self.circuit_wires:
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if wire.name == w[1]:
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return w[2]
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""" C CODE GENERATION """
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# FLAT C #
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@staticmethod
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def get_includes_c():
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"""Generates necessary C library includes for output representation.
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Returns:
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str: C code library includes.
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"""
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return f"#include <stdio.h>\n#include <stdint.h>\n\n"
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def get_prototype_c(self):
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"""Generates C code function header to describe corresponding arithmetic circuit's interface in C code.
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Returns:
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str: Function's name and parameters in C code.
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"""
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return f"{self.c_data_type} {self.prefix}({self.c_data_type} {self.a.prefix}, {self.c_data_type} {self.b.prefix})" + "{" + "\n"
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def get_declaration_c_flat(self):
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"""Generates flat C code declaration of input/output circuit wires.
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Returns:
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str: Flat C code arithmetic circuit's wires declaration.
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"""
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return f"".join([c.get_declaration_c_flat() for c in self.components])
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def get_init_c_flat(self):
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"""Generates flat C code initialization and assignment of corresponding arithmetic circuit's input/output wires.
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Returns:
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str: Flat C code initialization of arithmetic circuit wires.
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"""
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return "".join([c.get_assign_c_flat() if isinstance(c, TwoInputLogicGate) else c.get_init_c_flat() for c in self.components])
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def get_function_out_c_flat(self):
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"""Generates flat C code assignment of corresponding arithmetic circuit's output bus wires.
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Returns:
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str: Flat C code containing output bus wires assignment.
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"""
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return self.out.return_bus_wires_values_c_flat()
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# Generating flat C code representation of circuit
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def get_c_code_flat(self, file_object):
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"""Generates flat C code representation of corresponding arithmetic circuit.
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Args:
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file_object (TextIOWrapper): Destination file object where circuit's representation will be written to.
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"""
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file_object.write(self.get_includes_c())
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file_object.write(self.get_prototype_c())
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file_object.write(self.out.get_declaration_c())
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file_object.write(self.get_declaration_c_flat()+"\n")
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file_object.write(self.get_init_c_flat()+"\n")
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file_object.write(self.get_function_out_c_flat())
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file_object.write(f" return {self.out.prefix}"+";\n}")
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file_object.close()
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# HIERARCHICAL C #
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def get_function_blocks_c(self):
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"""Generates hierarchical C code representation of all subcomponents function blocks present in corresponding arithmetic circuit.
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Returns:
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str: Hierarchical C code of all subcomponents function blocks description.
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"""
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# Retrieve all unique component types composing this circuit
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self.component_types = self.get_component_types()
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return "".join([c.get_function_block_c() for c in self.component_types])
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def get_function_block_c(self):
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"""Generates hierarchical C code representation of corresponding multi-bit arithmetic circuit used as function block in hierarchical circuit description.
|
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Returns:
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str: Hierarchical C code of multi-bit arithmetic circuit's function block description.
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"""
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# Obtain proper circuit name with its bit width
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circuit_prefix = self.__class__(a=Bus("a"), b=Bus("b")).prefix + str(self.N)
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circuit_block = self.__class__(a=Bus(N=self.N, prefix="a"), b=Bus(N=self.N, prefix="b"), prefix=circuit_prefix)
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return f"{circuit_block.get_circuit_c()}\n\n"
|
||
|
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def get_declarations_c_hier(self):
|
||
"""Generates hierarchical C code declaration of input/output circuit wires.
|
||
|
||
Returns:
|
||
str: Hierarchical C code containing unique declaration of arithmetic circuit wires.
|
||
"""
|
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return "".join([c.get_declaration_c_hier() for c in self.components])
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||
|
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def get_declaration_c_hier(self):
|
||
"""Generates hierarchical C code declaration of corresponding subcomponent input/output wires inside the upper component.
|
||
|
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Generates wires used to connect input/output values to/from invocation of the corresponding function block into inner wires present
|
||
inside the upper component from which function block has been invoked.
|
||
|
||
Returns:
|
||
str: Hierarchical C code of subcomponent arithmetic circuit's wires declaration.
|
||
"""
|
||
return f" {self.c_data_type} {self.a.prefix} = 0;\n" + \
|
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f" {self.c_data_type} {self.b.prefix} = 0;\n" + \
|
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f" {self.c_data_type} {self.out.prefix} = 0;\n"
|
||
|
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def get_init_c_hier(self):
|
||
"""Generates hierarchical C code initialization and assignment of corresponding arithmetic circuit's input/output wires.
|
||
|
||
Returns:
|
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str: Hierarchical C code initialization of arithmetic circuit wires.
|
||
"""
|
||
return "".join([c.get_gate_invocation_c() if isinstance(c, TwoInputLogicGate) else c.get_out_invocation_c(circuit_prefix=self.prefix) for c in self.components])
|
||
|
||
def get_out_invocation_c(self, circuit_prefix: str):
|
||
"""Generates hierarchical C code invocation of corresponding arithmetic circuit's generated function block.
|
||
|
||
Assigns input values from other subcomponents into multi-bit input buses used as inputs for function block invocation.
|
||
Assigns output values from invocation of the corresponding function block into inner wires present inside
|
||
the upper component from which function block has been invoked.
|
||
|
||
Args:
|
||
circuit_prefix (str): Prefix name of the upper component from which function block is being invoked.
|
||
|
||
Returns:
|
||
str: Hierarchical C code of subcomponent's C function invocation and output assignment.
|
||
"""
|
||
# Getting name of circuit type for proper C code generation without affecting actual generated composition
|
||
circuit_type = self.prefix.replace(circuit_prefix+"_", "")
|
||
return self.a.return_bus_wires_values_c_hier() + self.b.return_bus_wires_values_c_hier() + \
|
||
f" {self.out.prefix} = {circuit_type}({self.a.prefix}, {self.b.prefix});\n"
|
||
|
||
def get_function_out_c_hier(self):
|
||
"""Generates hierarchical C code assignment of corresponding arithmetic circuit's output bus wires.
|
||
|
||
Returns:
|
||
str: Hierarchical C code containing output bus wires assignment.
|
||
"""
|
||
return self.out.return_bus_wires_values_c_hier()
|
||
|
||
def get_circuit_c(self):
|
||
"""Generates hierarchical C code subcomponent's function block.
|
||
|
||
Returns:
|
||
str: Hierarchical C code of subcomponent's function block.
|
||
"""
|
||
return f"{self.get_prototype_c()}" + \
|
||
f"{self.out.get_declaration_c()}" + \
|
||
f"{self.get_declarations_c_hier()}\n" + \
|
||
f"{self.get_init_c_hier()}\n" + \
|
||
f"{self.get_function_out_c_hier()}" + \
|
||
f" return {self.out.prefix}"+";\n}"
|
||
|
||
# Generating hierarchical C code representation of circuit
|
||
def get_c_code_hier(self, file_object):
|
||
"""Generates hierarchical C code representation of corresponding arithmetic circuit.
|
||
|
||
Args:
|
||
file_object (TextIOWrapper): Destination file object where circuit's representation will be written to.
|
||
"""
|
||
file_object.write(self.get_includes_c())
|
||
file_object.write(self.get_function_blocks_c())
|
||
file_object.write(self.get_circuit_c())
|
||
file_object.close()
|
||
|
||
""" VERILOG CODE GENERATION """
|
||
# FLAT VERILOG #
|
||
def get_prototype_v(self):
|
||
"""Generates Verilog code module header to describe corresponding arithmetic circuit's interface in Verilog code.
|
||
|
||
Returns:
|
||
str: Module's name and parameters in Verilog code.
|
||
"""
|
||
return f"module {self.prefix}(input [{self.N-1}:0] {self.a.prefix}, input [{self.N-1}:0] {self.b.prefix}, output [{self.out.N-1}:0] {self.out.prefix});\n"
|
||
|
||
def get_declaration_v_flat(self):
|
||
"""Generates flat Verilog code declaration of input/output circuit wires.
|
||
|
||
Returns:
|
||
str: Flat Verilog code arithmetic circuit's wires declaration.
|
||
"""
|
||
return f"".join([c.get_declaration_v_flat() for c in self.components])
|
||
|
||
def get_init_v_flat(self):
|
||
"""Generates flat Verilog code initialization and assignment of corresponding arithmetic circuit's input/output buses wires.
|
||
|
||
Returns:
|
||
str: Flat Verilog code initialization of arithmetic circuit wires.
|
||
"""
|
||
return "".join([c.get_assign_v_flat() if isinstance(c, TwoInputLogicGate) else c.get_init_v_flat() for c in self.components])
|
||
|
||
def get_function_out_v_flat(self):
|
||
"""Generates flat Verilog code assignment of corresponding arithmetic circuit's output bus wires.
|
||
|
||
Returns:
|
||
str: Flat Verilog code containing output bus wires assignment.
|
||
"""
|
||
return self.out.return_bus_wires_values_v_flat()
|
||
|
||
# Generating flat Verilog code representation of circuit
|
||
def get_v_code_flat(self, file_object):
|
||
"""Generates flat Verilog code representation of corresponding arithmetic circuit.
|
||
|
||
Args:
|
||
file_object (TextIOWrapper): Destination file object where circuit's representation will be written to.
|
||
"""
|
||
file_object.write(self.get_prototype_v())
|
||
file_object.write(self.get_declaration_v_flat()+"\n")
|
||
file_object.write(self.get_init_v_flat() + "\n")
|
||
file_object.write(self.get_function_out_v_flat())
|
||
file_object.write(f"endmodule")
|
||
file_object.close()
|
||
|
||
# HIERARCHICAL VERILOG #
|
||
def get_function_blocks_v(self):
|
||
"""Generates hierarchical Verilog code representation of all subcomponents function blocks present in corresponding arithmetic circuit.
|
||
|
||
Returns:
|
||
str: Hierarchical Verilog code of all subcomponents function blocks description.
|
||
"""
|
||
# Retrieve all unique component types composing this circuit
|
||
self.component_types = self.get_component_types()
|
||
return "".join([c.get_function_block_v() for c in self.component_types])
|
||
|
||
def get_function_block_v(self):
|
||
"""Generates hierarchical Verilog code representation of corresponding multi-bit arithmetic circuit used as function block in hierarchical circuit description.
|
||
|
||
Returns:
|
||
str: Hierarchical Verilog code of multi-bit arithmetic circuit's function block description.
|
||
"""
|
||
# Obtain proper circuit name with its bit width
|
||
circuit_prefix = self.__class__(a=Bus("a"), b=Bus("b")).prefix + str(self.N)
|
||
circuit_block = self.__class__(a=Bus(N=self.N, prefix="a"), b=Bus(N=self.N, prefix="b"), prefix=circuit_prefix)
|
||
return f"{circuit_block.get_circuit_v()}\n\n"
|
||
|
||
def get_declarations_v_hier(self):
|
||
"""Generates hierarchical Verilog code declaration of input/output circuit wires.
|
||
|
||
Returns:
|
||
str: Hierarchical Verilog code containing unique declaration of arithmetic circuit wires.
|
||
"""
|
||
return "".join([c.get_declaration_v_hier() for c in self.components])
|
||
|
||
def get_declaration_v_hier(self):
|
||
"""Generates hierarchical Verilog code declaration of corresponding subcomponent input/output wires inside the upper component.
|
||
|
||
Generates wires used to connect input/output values to/from invocation of the corresponding function block into inner wires present
|
||
inside the upper component from which function block has been invoked.
|
||
|
||
Returns:
|
||
str: Hierarchical Verilog code of subcomponent arithmetic circuit's wires declaration.
|
||
"""
|
||
return f" wire [{self.a.N-1}:0] {self.a.prefix};\n" + \
|
||
f" wire [{self.b.N-1}:0] {self.b.prefix};\n" + \
|
||
f" wire [{self.out.N-1}:0] {self.out.prefix};\n"
|
||
|
||
def get_init_v_hier(self):
|
||
"""Generates hierarchical Verilog code initialization and assignment of corresponding arithmetic circuit's input/output wires.
|
||
|
||
Returns:
|
||
str: Hierarchical Verilog code initialization of arithmetic circuit wires.
|
||
"""
|
||
return "".join([c.get_gate_invocation_v() if isinstance(c, TwoInputLogicGate) else c.get_out_invocation_v(circuit_prefix=self.prefix) for c in self.components])
|
||
|
||
def get_out_invocation_v(self, circuit_prefix: str):
|
||
"""Generates hierarchical Verilog code invocation of corresponding arithmetic circuit's generated function block.
|
||
|
||
Assigns input values from other subcomponents into multi-bit input buses used as inputs for function block invocation.
|
||
Assigns output values from invocation of the corresponding function block into inner wires present inside
|
||
the upper component from which function block has been invoked.
|
||
|
||
Args:
|
||
circuit_prefix (str): Prefix name of the upper component from which function block is being invoked.
|
||
|
||
Returns:
|
||
str: Hierarchical Verilog code of subcomponent's module invocation and output assignment.
|
||
"""
|
||
# Getting name of circuit type and insitu copying out bus for proper Verilog code generation without affecting actual generated composition
|
||
circuit_type = self.prefix.replace(circuit_prefix+"_", "")
|
||
|
||
# Obtain proper circuit name with its bit width
|
||
circuit_prefix = self.__class__(a=Bus("a"), b=Bus("b")).prefix + str(self.N)
|
||
circuit_block = self.__class__(a=Bus(N=self.N, prefix="a"), b=Bus(N=self.N, prefix="b"), prefix=circuit_prefix)
|
||
return self.a.return_bus_wires_values_v_hier() + self.b.return_bus_wires_values_v_hier() + \
|
||
f" {circuit_type} {circuit_type}_{self.out.prefix}(.{circuit_block.a.prefix}({self.a.prefix}), .{circuit_block.b.prefix}({self.b.prefix}), .{circuit_block.out.prefix}({self.out.prefix}));\n"
|
||
|
||
def get_function_out_v_hier(self):
|
||
"""Generates hierarchical Verilog code assignment of corresponding arithmetic circuit's output bus wires.
|
||
|
||
Returns:
|
||
str: Hierarchical Verilog code containing output bus wires assignment.
|
||
"""
|
||
return self.out.return_bus_wires_values_v_hier()
|
||
|
||
def get_circuit_v(self):
|
||
"""Generates hierarchical Verilog code subcomponent's function block.
|
||
|
||
Returns:
|
||
str: Hierarchical Verilog code of subcomponent's function block.
|
||
"""
|
||
return f"{self.get_prototype_v()}" + \
|
||
f"{self.get_declarations_v_hier()}\n" + \
|
||
f"{self.get_init_v_hier()}\n" + \
|
||
f"{self.get_function_out_v_hier()}" + \
|
||
f"endmodule"
|
||
|
||
# Generating hierarchical Verilog code representation of circuit
|
||
def get_v_code_hier(self, file_object):
|
||
"""Generates hierarchical Verilog code representation of corresponding arithmetic circuit.
|
||
|
||
Args:
|
||
file_object (TextIOWrapper): Destination file object where circuit's representation will be written to.
|
||
"""
|
||
file_object.write(self.get_function_blocks_v())
|
||
file_object.write(self.get_circuit_v())
|
||
file_object.close()
|
||
|
||
""" BLIF CODE GENERATION """
|
||
# FLAT BLIF #
|
||
def get_prototype_blif(self):
|
||
"""Generates Blif code model name of described arithmetic circuit.
|
||
|
||
Returns:
|
||
str: Model's name in Blif code.
|
||
"""
|
||
return f".model {self.prefix}\n"
|
||
|
||
def get_declaration_blif(self):
|
||
"""Generates flat Blif code declaration of input/output circuit wires.
|
||
|
||
Returns:
|
||
str: Flat Blif code containing declaration of circuit's wires.
|
||
"""
|
||
if self.N == 1:
|
||
return f".inputs {self.a.prefix} {self.b.prefix}\n" + \
|
||
f".outputs{self.out.get_wire_declaration_blif()}\n" + \
|
||
f".names vdd\n1\n" + \
|
||
f".names gnd\n0\n"
|
||
else:
|
||
return f".inputs{self.a.get_wire_declaration_blif()}{self.b.get_wire_declaration_blif()}\n" + \
|
||
f".outputs{self.out.get_wire_declaration_blif()}\n" + \
|
||
f".names vdd\n1\n" + \
|
||
f".names gnd\n0\n"
|
||
|
||
def get_function_blif_flat(self):
|
||
"""Generates flat Blif code with invocation of subcomponents logic gates functions via their corresponding truth tables.
|
||
|
||
Returns:
|
||
str: Flat Blif code containing invocation of inner subcomponents logic gates Boolean functions.
|
||
"""
|
||
return "".join(c.get_function_blif_flat() for c in self.components)
|
||
|
||
def get_function_out_blif(self):
|
||
"""Generates flat Blif code assignment of corresponding arithmetic circuit's output bus wires.
|
||
|
||
Returns:
|
||
str: Flat Blif code containing output bus wires assignment.
|
||
"""
|
||
return f"{self.out.get_wire_assign_blif(output=True)}"
|
||
|
||
# Generating flat BLIF code representation of circuit
|
||
def get_blif_code_flat(self, file_object):
|
||
"""Generates flat Blif code representation of corresponding arithmetic circuit.
|
||
|
||
Args:
|
||
file_object (TextIOWrapper): Destination file object where circuit's representation will be written to.
|
||
"""
|
||
file_object.write(self.get_prototype_blif())
|
||
file_object.write(self.get_declaration_blif())
|
||
file_object.write(self.get_function_blif_flat())
|
||
file_object.write(self.get_function_out_blif())
|
||
file_object.write(f".end\n")
|
||
file_object.close()
|
||
|
||
# HIERARCHICAL BLIF #
|
||
def get_invocations_blif_hier(self):
|
||
"""Generates hierarchical Blif code with invocations of subcomponents function blocks.
|
||
|
||
Returns:
|
||
str: Hierarchical Blif code containing invocations of inner subcomponents function blocks.
|
||
"""
|
||
return "".join(c.get_invocation_blif_hier(circuit_prefix=self.prefix) for c in self.components)
|
||
|
||
def get_invocation_blif_hier(self, circuit_prefix: str):
|
||
"""Generates hierarchical Blif code invocation of corresponding arithmetic circuit's generated function block.
|
||
|
||
Used for multi-bit subcomponent's modul invocation.
|
||
|
||
Args:
|
||
circuit_prefix (str): Prefix name of the upper component from which function block is being invoked.
|
||
|
||
Returns:
|
||
str: Hierarchical Blif code of subcomponent's model invocation and output assignment.
|
||
"""
|
||
# Getting name of circuit type for proper Blif code generation without affecting actual generated composition
|
||
circuit_type = self.prefix.replace(circuit_prefix+"_", "")
|
||
return f"{self.a.get_wire_assign_blif(output=True)}" + \
|
||
f"{self.b.get_wire_assign_blif(output=True)}" + \
|
||
f".subckt {circuit_type}" + \
|
||
"".join([f" a[{self.a.bus.index(w)}]={self.a.prefix}[{self.a.bus.index(w)}]" for w in self.a.bus]) + \
|
||
"".join([f" b[{self.b.bus.index(w)}]={self.b.prefix}[{self.b.bus.index(w)}]" for w in self.b.bus]) + \
|
||
"".join([f" {circuit_type}_out[{self.out.bus.index(o)}]={o.name}" for o in self.out.bus]) + "\n"
|
||
|
||
def get_circuit_blif(self):
|
||
"""Generates hierarchical Blif code subcomponent's function block.
|
||
|
||
Returns:
|
||
str: Hierarchical Blif code of subcomponent's function block.
|
||
"""
|
||
return f"{self.get_prototype_blif()}" + \
|
||
f"{self.get_declaration_blif()}" + \
|
||
f"{self.get_invocations_blif_hier()}" + \
|
||
f"{self.get_function_out_blif()}" + \
|
||
f".end\n"
|
||
|
||
def get_function_blocks_blif(self):
|
||
"""Generates hierarchical Blif code representation of all subcomponents function blocks present in corresponding arithmetic circuit.
|
||
|
||
Returns:
|
||
str: Hierarchical Blif code of all subcomponents function blocks description.
|
||
"""
|
||
# Retrieve all unique component types composing this circuit
|
||
# (iterating backwards as opposed to other representations so the top modul is always above its subcomponents)
|
||
self.component_types = self.get_component_types()
|
||
return "\n".join([c.get_function_block_blif() for c in self.component_types[::-1]])
|
||
|
||
def get_function_block_blif(self):
|
||
"""Generates hierarchical Blif code representation of corresponding multi-bit arithmetic circuit used as function block in hierarchical circuit description.
|
||
|
||
Returns:
|
||
str: Hierarchical Blif code of multi-bit arithmetic circuit's function block description.
|
||
"""
|
||
# Obtain proper circuit name with its bit width
|
||
circuit_prefix = self.__class__(a=Bus("a"), b=Bus("b")).prefix + str(self.N)
|
||
circuit_block = self.__class__(a=Bus(N=self.N, prefix="a"), b=Bus(N=self.N, prefix="b"), prefix=circuit_prefix)
|
||
return f"{circuit_block.get_circuit_blif()}"
|
||
|
||
# Generating hierarchical BLIF code representation of circuit
|
||
def get_blif_code_hier(self, file_object):
|
||
"""Generates hierarchical Blif code representation of corresponding arithmetic circuit.
|
||
|
||
Args:
|
||
file_object (TextIOWrapper): Destination file object where circuit's representation will be written to.
|
||
"""
|
||
file_object.write(self.get_circuit_blif()+"\n")
|
||
file_object.write(self.get_function_blocks_blif())
|
||
file_object.close()
|
||
|
||
""" CGP CODE GENERATION """
|
||
# FLAT CGP #
|
||
def get_parameters_cgp(self):
|
||
"""Generates CGP chromosome parameters of corresponding arithmetic circuit.
|
||
|
||
In total seven parameters represent: total inputs, total outputs, number of rows, number of columns (gates),
|
||
number of each gate's inputs, number of each gate's outputs, quality constant value.
|
||
|
||
Returns:
|
||
str: CGP chromosome parameters of described arithmetic circuit.
|
||
"""
|
||
self.circuit_gates = self.get_circuit_gates()
|
||
return f"{{{self.a.N+self.a.N},{self.out.N},1,{len(self.circuit_gates)},2,1,0}}"
|
||
|
||
def get_triplets_cgp(self):
|
||
"""Generates list of logic gate triplets (first input wire, second input wire, logic gate function) using wires unique position indexes within the described circuit.
|
||
|
||
Each triplet represents unique logic gate within the described arithmetic circuit. Besides the contained input wires indexes and gate's inner logic function, an output wire
|
||
with incremented index position is also created and remembered to be appropriately driven as an input to another logic gate or as the circuit's output.
|
||
|
||
Constant wire with value 0 has constant index of 0.
|
||
Constant wire with value 1 has constant index of 1.
|
||
Other wires indexes start counting from 2 and up.
|
||
|
||
Returns:
|
||
str: List of triplets each describing logic function of corresponding two input logic gate and as a whole describe the arithmetic circuit.
|
||
"""
|
||
self.get_cgp_wires()
|
||
return "".join([g.get_triplet_cgp(a_id=self.get_circuit_wire_index(g.a)) if isinstance(g, OneInputLogicGate) else
|
||
g.get_triplet_cgp(a_id=self.get_circuit_wire_index(g.a), b_id=self.get_circuit_wire_index(g.b)) for g in self.circuit_gates])
|
||
|
||
def get_outputs_cgp(self):
|
||
"""Generates list of output wires indexes of described arithmetic circuit from MSB to LSB.
|
||
|
||
Returns:
|
||
str: List of arithmetic circuit's output wire indexes.
|
||
"""
|
||
return "(" + ",".join([str(self.get_circuit_wire_index(o)) for o in self.out.bus[::-1]]) + ")"
|
||
|
||
# Generating flat CGP chromosome representation of circuit
|
||
def get_cgp_code_flat(self, file_object):
|
||
"""Generates flat CGP chromosome representation of corresponding arithmetic circuit.
|
||
|
||
Args:
|
||
file_object (TextIOWrapper): Destination file object where circuit's representation will be written to.
|
||
"""
|
||
file_object.write(self.get_parameters_cgp())
|
||
file_object.write(self.get_triplets_cgp())
|
||
file_object.write(self.get_outputs_cgp())
|
||
file_object.close()</code></pre>
|
||
</details>
|
||
</section>
|
||
<section>
|
||
</section>
|
||
<section>
|
||
</section>
|
||
<section>
|
||
</section>
|
||
<section>
|
||
<h2 class="section-title" id="header-classes">Classes</h2>
|
||
<dl>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit"><code class="flex name class">
|
||
<span>class <span class="ident">ArithmeticCircuit</span></span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Class represents a general arithmetic circuit and ensures their generation to various representations.</p>
|
||
<p>The <strong>init</strong> method fills some mandatory attributes concerning arithmetic circuit
|
||
that are later used for generation into various representations.</p></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">class ArithmeticCircuit():
|
||
"""Class represents a general arithmetic circuit and ensures their generation to various representations.
|
||
|
||
The __init__ method fills some mandatory attributes concerning arithmetic circuit
|
||
that are later used for generation into various representations.
|
||
"""
|
||
def __init__(self):
|
||
self.components = []
|
||
self.circuit_wires = []
|
||
self.circuit_gates = []
|
||
self.c_data_type = "uint64_t"
|
||
self.N = 1
|
||
|
||
def add_component(self, component):
|
||
"""Adds a component into list of circuit's inner subcomponents.
|
||
|
||
Args:
|
||
component: Subcomponent to be added into list of components composing described circuit.
|
||
"""
|
||
self.components.append(component)
|
||
|
||
def get_previous_component(self, number: int = 1):
|
||
"""Retrieves previously added composite subcomponent from circuit's list of components.
|
||
|
||
Args:
|
||
number (int, optional): Offset indicating which lastly added component will be retrieved. Defaults to 1.
|
||
|
||
Returns:
|
||
component: Desired previously added composite component.
|
||
"""
|
||
return self.components[-number]
|
||
|
||
def get_instance_num(self, cls, count_disabled_gates: bool = True):
|
||
"""Informs how many instances of the same type are already present inside circuit's components list.
|
||
|
||
Args:
|
||
cls (type): Class type for which to count the number of instances in the components list.
|
||
count_disabled_gates (bool, optional): Indicates whether logic gates that aren't generated should be also counted. Defaults to True.
|
||
Returns:
|
||
int: Number of instances of the same class type.
|
||
"""
|
||
if issubclass(cls, TwoInputLogicGate) and count_disabled_gates is False:
|
||
return sum(isinstance(c, cls) for c in self.components if isinstance(c, cls) and c.disable_generation is False)
|
||
else:
|
||
return sum(isinstance(c, cls) for c in self.components)
|
||
|
||
def get_circuit_gates(self):
|
||
"""Gets a list of all the logic gates in circuit that should be generated.
|
||
|
||
Returns:
|
||
list: List of composite logic gates.
|
||
"""
|
||
gates = []
|
||
for c in self.components:
|
||
if isinstance(c, TwoInputLogicGate):
|
||
if c.disable_generation is False:
|
||
gates.append(c)
|
||
else:
|
||
gates.extend((c.get_circuit_gates()))
|
||
return gates
|
||
|
||
def get_one_bit_components(self):
|
||
"""Retrieves a list of all the one bit circuits (besides logic gates) present as subcomponents inside the circuit.
|
||
|
||
Returns:
|
||
list: List of composite one bit circuits.
|
||
"""
|
||
one_bit_comps = []
|
||
for c in self.components:
|
||
if isinstance(c, TwoInputLogicGate):
|
||
continue
|
||
elif isinstance(getattr(c, 'a'), Wire):
|
||
one_bit_comps.append(c)
|
||
else:
|
||
one_bit_comps.extend(c.get_one_bit_components())
|
||
|
||
return one_bit_comps
|
||
|
||
def get_multi_bit_components(self):
|
||
"""Retrieves a list of all the multi bit circuits present as subcomponents inside the circuit.
|
||
|
||
Returns:
|
||
list: List of composite multi bit circuits.
|
||
"""
|
||
multi_bit_comps = []
|
||
for c in self.components:
|
||
if isinstance(c, TwoInputLogicGate):
|
||
continue
|
||
elif isinstance(getattr(c, 'a'), Wire):
|
||
continue
|
||
else:
|
||
multi_bit_comps.append(c)
|
||
return multi_bit_comps
|
||
|
||
@staticmethod
|
||
def get_unique_types(components: list):
|
||
"""Retrieves just the unique representatives of class types present inside the provided components list.
|
||
|
||
Args:
|
||
components (list): List of components to be filtered.
|
||
|
||
Returns:
|
||
list: List of unique composite class types.
|
||
"""
|
||
return list({type(c): c for c in components}.values())
|
||
|
||
def get_component_types(self):
|
||
"""Retrieves a list of all the unique types of subcomponents composing the circuit.
|
||
|
||
Returning list consists of only the unique types of logic gates, one bit circuits and multi bit circuits.
|
||
|
||
Returns:
|
||
list: List of unique component types describing the circuit.
|
||
"""
|
||
gate_comps = self.get_unique_types(components=self.get_circuit_gates())
|
||
one_bit_comps = self.get_unique_types(components=self.get_one_bit_components())
|
||
multi_bit_comps = self.get_unique_types(components=self.get_multi_bit_components())
|
||
|
||
all_components = gate_comps + one_bit_comps + multi_bit_comps
|
||
return all_components
|
||
|
||
def get_sum_wire(self):
|
||
"""Get output wire carrying sum value.
|
||
|
||
Returns:
|
||
Wire: Return sum wire.
|
||
"""
|
||
return self.out.get_wire(0)
|
||
|
||
def get_carry_wire(self):
|
||
"""Get output wire carrying carry out value.
|
||
|
||
Returns:
|
||
Wire: Return carry out wire.
|
||
"""
|
||
return self.out.get_wire(1)
|
||
|
||
def save_wire_id(self, wire: Wire):
|
||
"""Returns appropriate wire index position within the circuit.
|
||
|
||
Constant wire with value 0 has constant index of 0.
|
||
Constant wire with value 1 has constant index of 1.
|
||
Other wires indexes start counting from 2 and up.
|
||
|
||
Args:
|
||
wire (Wire): Wire that will be stored at this circuit index position.
|
||
|
||
Returns:
|
||
int: Wire's index position within circuit.
|
||
"""
|
||
if wire.is_const():
|
||
return wire.cgp_const
|
||
else:
|
||
return len([w[0] for w in self.circuit_wires if w[0].is_const() is False]) + 2
|
||
|
||
def get_cgp_wires(self):
|
||
"""Gets a list of all wires in circuit along with their index position for cgp chromosome generation and stores them inside `self.circuit_wires` list.
|
||
|
||
Constant wire with value 0 has constant index of 0.
|
||
Constant wire with value 1 has constant index of 1.
|
||
Other wires indexes start counting from 2 and up.
|
||
"""
|
||
self.circuit_wires = []
|
||
if isinstance(self.a, Bus):
|
||
[self.circuit_wires.append((w, f"{w.name}", self.save_wire_id(wire=w))) for w in self.a.bus]
|
||
[self.circuit_wires.append((w, f"{w.name}", self.save_wire_id(wire=w))) for w in self.b.bus]
|
||
else:
|
||
self.circuit_wires.append((self.a, f"{self.a.name}", self.save_wire_id(wire=self.a)))
|
||
self.circuit_wires.append((self.b, f"{self.b.name}", self.save_wire_id(wire=self.b)))
|
||
if hasattr(self, 'c'):
|
||
self.circuit_wires.append((self.c, f"{self.c.name}", self.save_wire_id(wire=self.c)))
|
||
|
||
for gate in self.circuit_gates:
|
||
if not [item for item in self.circuit_wires if gate.a.name == item[1]]:
|
||
self.circuit_wires.append((gate.a, gate.a.name, self.save_wire_id(wire=gate.a)))
|
||
|
||
if hasattr(gate, 'b') and not [item for item in self.circuit_wires if gate.b.name == item[1]]:
|
||
self.circuit_wires.append((gate.b, gate.b.name, self.save_wire_id(wire=gate.b)))
|
||
|
||
if not [item for item in self.circuit_wires if gate.out.name == item[1]]:
|
||
self.circuit_wires.append((gate.out, gate.out.name, self.save_wire_id(wire=gate.out)))
|
||
|
||
def get_circuit_wire_index(self, wire: Wire):
|
||
"""Searches for circuit's wire unique index position within the circuit. Used for cgp chromosome generation.
|
||
|
||
Args:
|
||
wire (Wire): Wire to retrieve index position of.
|
||
|
||
Returns:
|
||
int: Wire's index position number within the circuit.
|
||
"""
|
||
if wire.is_const():
|
||
return wire.cgp_const
|
||
else:
|
||
for w in self.circuit_wires:
|
||
if wire.name == w[1]:
|
||
return w[2]
|
||
|
||
""" C CODE GENERATION """
|
||
# FLAT C #
|
||
@staticmethod
|
||
def get_includes_c():
|
||
"""Generates necessary C library includes for output representation.
|
||
|
||
Returns:
|
||
str: C code library includes.
|
||
"""
|
||
return f"#include <stdio.h>\n#include <stdint.h>\n\n"
|
||
|
||
def get_prototype_c(self):
|
||
"""Generates C code function header to describe corresponding arithmetic circuit's interface in C code.
|
||
|
||
Returns:
|
||
str: Function's name and parameters in C code.
|
||
"""
|
||
return f"{self.c_data_type} {self.prefix}({self.c_data_type} {self.a.prefix}, {self.c_data_type} {self.b.prefix})" + "{" + "\n"
|
||
|
||
def get_declaration_c_flat(self):
|
||
"""Generates flat C code declaration of input/output circuit wires.
|
||
|
||
Returns:
|
||
str: Flat C code arithmetic circuit's wires declaration.
|
||
"""
|
||
return f"".join([c.get_declaration_c_flat() for c in self.components])
|
||
|
||
def get_init_c_flat(self):
|
||
"""Generates flat C code initialization and assignment of corresponding arithmetic circuit's input/output wires.
|
||
|
||
Returns:
|
||
str: Flat C code initialization of arithmetic circuit wires.
|
||
"""
|
||
return "".join([c.get_assign_c_flat() if isinstance(c, TwoInputLogicGate) else c.get_init_c_flat() for c in self.components])
|
||
|
||
def get_function_out_c_flat(self):
|
||
"""Generates flat C code assignment of corresponding arithmetic circuit's output bus wires.
|
||
|
||
Returns:
|
||
str: Flat C code containing output bus wires assignment.
|
||
"""
|
||
return self.out.return_bus_wires_values_c_flat()
|
||
|
||
# Generating flat C code representation of circuit
|
||
def get_c_code_flat(self, file_object):
|
||
"""Generates flat C code representation of corresponding arithmetic circuit.
|
||
|
||
Args:
|
||
file_object (TextIOWrapper): Destination file object where circuit's representation will be written to.
|
||
"""
|
||
file_object.write(self.get_includes_c())
|
||
file_object.write(self.get_prototype_c())
|
||
file_object.write(self.out.get_declaration_c())
|
||
file_object.write(self.get_declaration_c_flat()+"\n")
|
||
file_object.write(self.get_init_c_flat()+"\n")
|
||
file_object.write(self.get_function_out_c_flat())
|
||
file_object.write(f" return {self.out.prefix}"+";\n}")
|
||
file_object.close()
|
||
|
||
# HIERARCHICAL C #
|
||
def get_function_blocks_c(self):
|
||
"""Generates hierarchical C code representation of all subcomponents function blocks present in corresponding arithmetic circuit.
|
||
|
||
Returns:
|
||
str: Hierarchical C code of all subcomponents function blocks description.
|
||
"""
|
||
# Retrieve all unique component types composing this circuit
|
||
self.component_types = self.get_component_types()
|
||
return "".join([c.get_function_block_c() for c in self.component_types])
|
||
|
||
def get_function_block_c(self):
|
||
"""Generates hierarchical C code representation of corresponding multi-bit arithmetic circuit used as function block in hierarchical circuit description.
|
||
|
||
Returns:
|
||
str: Hierarchical C code of multi-bit arithmetic circuit's function block description.
|
||
"""
|
||
# Obtain proper circuit name with its bit width
|
||
circuit_prefix = self.__class__(a=Bus("a"), b=Bus("b")).prefix + str(self.N)
|
||
circuit_block = self.__class__(a=Bus(N=self.N, prefix="a"), b=Bus(N=self.N, prefix="b"), prefix=circuit_prefix)
|
||
return f"{circuit_block.get_circuit_c()}\n\n"
|
||
|
||
def get_declarations_c_hier(self):
|
||
"""Generates hierarchical C code declaration of input/output circuit wires.
|
||
|
||
Returns:
|
||
str: Hierarchical C code containing unique declaration of arithmetic circuit wires.
|
||
"""
|
||
return "".join([c.get_declaration_c_hier() for c in self.components])
|
||
|
||
def get_declaration_c_hier(self):
|
||
"""Generates hierarchical C code declaration of corresponding subcomponent input/output wires inside the upper component.
|
||
|
||
Generates wires used to connect input/output values to/from invocation of the corresponding function block into inner wires present
|
||
inside the upper component from which function block has been invoked.
|
||
|
||
Returns:
|
||
str: Hierarchical C code of subcomponent arithmetic circuit's wires declaration.
|
||
"""
|
||
return f" {self.c_data_type} {self.a.prefix} = 0;\n" + \
|
||
f" {self.c_data_type} {self.b.prefix} = 0;\n" + \
|
||
f" {self.c_data_type} {self.out.prefix} = 0;\n"
|
||
|
||
def get_init_c_hier(self):
|
||
"""Generates hierarchical C code initialization and assignment of corresponding arithmetic circuit's input/output wires.
|
||
|
||
Returns:
|
||
str: Hierarchical C code initialization of arithmetic circuit wires.
|
||
"""
|
||
return "".join([c.get_gate_invocation_c() if isinstance(c, TwoInputLogicGate) else c.get_out_invocation_c(circuit_prefix=self.prefix) for c in self.components])
|
||
|
||
def get_out_invocation_c(self, circuit_prefix: str):
|
||
"""Generates hierarchical C code invocation of corresponding arithmetic circuit's generated function block.
|
||
|
||
Assigns input values from other subcomponents into multi-bit input buses used as inputs for function block invocation.
|
||
Assigns output values from invocation of the corresponding function block into inner wires present inside
|
||
the upper component from which function block has been invoked.
|
||
|
||
Args:
|
||
circuit_prefix (str): Prefix name of the upper component from which function block is being invoked.
|
||
|
||
Returns:
|
||
str: Hierarchical C code of subcomponent's C function invocation and output assignment.
|
||
"""
|
||
# Getting name of circuit type for proper C code generation without affecting actual generated composition
|
||
circuit_type = self.prefix.replace(circuit_prefix+"_", "")
|
||
return self.a.return_bus_wires_values_c_hier() + self.b.return_bus_wires_values_c_hier() + \
|
||
f" {self.out.prefix} = {circuit_type}({self.a.prefix}, {self.b.prefix});\n"
|
||
|
||
def get_function_out_c_hier(self):
|
||
"""Generates hierarchical C code assignment of corresponding arithmetic circuit's output bus wires.
|
||
|
||
Returns:
|
||
str: Hierarchical C code containing output bus wires assignment.
|
||
"""
|
||
return self.out.return_bus_wires_values_c_hier()
|
||
|
||
def get_circuit_c(self):
|
||
"""Generates hierarchical C code subcomponent's function block.
|
||
|
||
Returns:
|
||
str: Hierarchical C code of subcomponent's function block.
|
||
"""
|
||
return f"{self.get_prototype_c()}" + \
|
||
f"{self.out.get_declaration_c()}" + \
|
||
f"{self.get_declarations_c_hier()}\n" + \
|
||
f"{self.get_init_c_hier()}\n" + \
|
||
f"{self.get_function_out_c_hier()}" + \
|
||
f" return {self.out.prefix}"+";\n}"
|
||
|
||
# Generating hierarchical C code representation of circuit
|
||
def get_c_code_hier(self, file_object):
|
||
"""Generates hierarchical C code representation of corresponding arithmetic circuit.
|
||
|
||
Args:
|
||
file_object (TextIOWrapper): Destination file object where circuit's representation will be written to.
|
||
"""
|
||
file_object.write(self.get_includes_c())
|
||
file_object.write(self.get_function_blocks_c())
|
||
file_object.write(self.get_circuit_c())
|
||
file_object.close()
|
||
|
||
""" VERILOG CODE GENERATION """
|
||
# FLAT VERILOG #
|
||
def get_prototype_v(self):
|
||
"""Generates Verilog code module header to describe corresponding arithmetic circuit's interface in Verilog code.
|
||
|
||
Returns:
|
||
str: Module's name and parameters in Verilog code.
|
||
"""
|
||
return f"module {self.prefix}(input [{self.N-1}:0] {self.a.prefix}, input [{self.N-1}:0] {self.b.prefix}, output [{self.out.N-1}:0] {self.out.prefix});\n"
|
||
|
||
def get_declaration_v_flat(self):
|
||
"""Generates flat Verilog code declaration of input/output circuit wires.
|
||
|
||
Returns:
|
||
str: Flat Verilog code arithmetic circuit's wires declaration.
|
||
"""
|
||
return f"".join([c.get_declaration_v_flat() for c in self.components])
|
||
|
||
def get_init_v_flat(self):
|
||
"""Generates flat Verilog code initialization and assignment of corresponding arithmetic circuit's input/output buses wires.
|
||
|
||
Returns:
|
||
str: Flat Verilog code initialization of arithmetic circuit wires.
|
||
"""
|
||
return "".join([c.get_assign_v_flat() if isinstance(c, TwoInputLogicGate) else c.get_init_v_flat() for c in self.components])
|
||
|
||
def get_function_out_v_flat(self):
|
||
"""Generates flat Verilog code assignment of corresponding arithmetic circuit's output bus wires.
|
||
|
||
Returns:
|
||
str: Flat Verilog code containing output bus wires assignment.
|
||
"""
|
||
return self.out.return_bus_wires_values_v_flat()
|
||
|
||
# Generating flat Verilog code representation of circuit
|
||
def get_v_code_flat(self, file_object):
|
||
"""Generates flat Verilog code representation of corresponding arithmetic circuit.
|
||
|
||
Args:
|
||
file_object (TextIOWrapper): Destination file object where circuit's representation will be written to.
|
||
"""
|
||
file_object.write(self.get_prototype_v())
|
||
file_object.write(self.get_declaration_v_flat()+"\n")
|
||
file_object.write(self.get_init_v_flat() + "\n")
|
||
file_object.write(self.get_function_out_v_flat())
|
||
file_object.write(f"endmodule")
|
||
file_object.close()
|
||
|
||
# HIERARCHICAL VERILOG #
|
||
def get_function_blocks_v(self):
|
||
"""Generates hierarchical Verilog code representation of all subcomponents function blocks present in corresponding arithmetic circuit.
|
||
|
||
Returns:
|
||
str: Hierarchical Verilog code of all subcomponents function blocks description.
|
||
"""
|
||
# Retrieve all unique component types composing this circuit
|
||
self.component_types = self.get_component_types()
|
||
return "".join([c.get_function_block_v() for c in self.component_types])
|
||
|
||
def get_function_block_v(self):
|
||
"""Generates hierarchical Verilog code representation of corresponding multi-bit arithmetic circuit used as function block in hierarchical circuit description.
|
||
|
||
Returns:
|
||
str: Hierarchical Verilog code of multi-bit arithmetic circuit's function block description.
|
||
"""
|
||
# Obtain proper circuit name with its bit width
|
||
circuit_prefix = self.__class__(a=Bus("a"), b=Bus("b")).prefix + str(self.N)
|
||
circuit_block = self.__class__(a=Bus(N=self.N, prefix="a"), b=Bus(N=self.N, prefix="b"), prefix=circuit_prefix)
|
||
return f"{circuit_block.get_circuit_v()}\n\n"
|
||
|
||
def get_declarations_v_hier(self):
|
||
"""Generates hierarchical Verilog code declaration of input/output circuit wires.
|
||
|
||
Returns:
|
||
str: Hierarchical Verilog code containing unique declaration of arithmetic circuit wires.
|
||
"""
|
||
return "".join([c.get_declaration_v_hier() for c in self.components])
|
||
|
||
def get_declaration_v_hier(self):
|
||
"""Generates hierarchical Verilog code declaration of corresponding subcomponent input/output wires inside the upper component.
|
||
|
||
Generates wires used to connect input/output values to/from invocation of the corresponding function block into inner wires present
|
||
inside the upper component from which function block has been invoked.
|
||
|
||
Returns:
|
||
str: Hierarchical Verilog code of subcomponent arithmetic circuit's wires declaration.
|
||
"""
|
||
return f" wire [{self.a.N-1}:0] {self.a.prefix};\n" + \
|
||
f" wire [{self.b.N-1}:0] {self.b.prefix};\n" + \
|
||
f" wire [{self.out.N-1}:0] {self.out.prefix};\n"
|
||
|
||
def get_init_v_hier(self):
|
||
"""Generates hierarchical Verilog code initialization and assignment of corresponding arithmetic circuit's input/output wires.
|
||
|
||
Returns:
|
||
str: Hierarchical Verilog code initialization of arithmetic circuit wires.
|
||
"""
|
||
return "".join([c.get_gate_invocation_v() if isinstance(c, TwoInputLogicGate) else c.get_out_invocation_v(circuit_prefix=self.prefix) for c in self.components])
|
||
|
||
def get_out_invocation_v(self, circuit_prefix: str):
|
||
"""Generates hierarchical Verilog code invocation of corresponding arithmetic circuit's generated function block.
|
||
|
||
Assigns input values from other subcomponents into multi-bit input buses used as inputs for function block invocation.
|
||
Assigns output values from invocation of the corresponding function block into inner wires present inside
|
||
the upper component from which function block has been invoked.
|
||
|
||
Args:
|
||
circuit_prefix (str): Prefix name of the upper component from which function block is being invoked.
|
||
|
||
Returns:
|
||
str: Hierarchical Verilog code of subcomponent's module invocation and output assignment.
|
||
"""
|
||
# Getting name of circuit type and insitu copying out bus for proper Verilog code generation without affecting actual generated composition
|
||
circuit_type = self.prefix.replace(circuit_prefix+"_", "")
|
||
|
||
# Obtain proper circuit name with its bit width
|
||
circuit_prefix = self.__class__(a=Bus("a"), b=Bus("b")).prefix + str(self.N)
|
||
circuit_block = self.__class__(a=Bus(N=self.N, prefix="a"), b=Bus(N=self.N, prefix="b"), prefix=circuit_prefix)
|
||
return self.a.return_bus_wires_values_v_hier() + self.b.return_bus_wires_values_v_hier() + \
|
||
f" {circuit_type} {circuit_type}_{self.out.prefix}(.{circuit_block.a.prefix}({self.a.prefix}), .{circuit_block.b.prefix}({self.b.prefix}), .{circuit_block.out.prefix}({self.out.prefix}));\n"
|
||
|
||
def get_function_out_v_hier(self):
|
||
"""Generates hierarchical Verilog code assignment of corresponding arithmetic circuit's output bus wires.
|
||
|
||
Returns:
|
||
str: Hierarchical Verilog code containing output bus wires assignment.
|
||
"""
|
||
return self.out.return_bus_wires_values_v_hier()
|
||
|
||
def get_circuit_v(self):
|
||
"""Generates hierarchical Verilog code subcomponent's function block.
|
||
|
||
Returns:
|
||
str: Hierarchical Verilog code of subcomponent's function block.
|
||
"""
|
||
return f"{self.get_prototype_v()}" + \
|
||
f"{self.get_declarations_v_hier()}\n" + \
|
||
f"{self.get_init_v_hier()}\n" + \
|
||
f"{self.get_function_out_v_hier()}" + \
|
||
f"endmodule"
|
||
|
||
# Generating hierarchical Verilog code representation of circuit
|
||
def get_v_code_hier(self, file_object):
|
||
"""Generates hierarchical Verilog code representation of corresponding arithmetic circuit.
|
||
|
||
Args:
|
||
file_object (TextIOWrapper): Destination file object where circuit's representation will be written to.
|
||
"""
|
||
file_object.write(self.get_function_blocks_v())
|
||
file_object.write(self.get_circuit_v())
|
||
file_object.close()
|
||
|
||
""" BLIF CODE GENERATION """
|
||
# FLAT BLIF #
|
||
def get_prototype_blif(self):
|
||
"""Generates Blif code model name of described arithmetic circuit.
|
||
|
||
Returns:
|
||
str: Model's name in Blif code.
|
||
"""
|
||
return f".model {self.prefix}\n"
|
||
|
||
def get_declaration_blif(self):
|
||
"""Generates flat Blif code declaration of input/output circuit wires.
|
||
|
||
Returns:
|
||
str: Flat Blif code containing declaration of circuit's wires.
|
||
"""
|
||
if self.N == 1:
|
||
return f".inputs {self.a.prefix} {self.b.prefix}\n" + \
|
||
f".outputs{self.out.get_wire_declaration_blif()}\n" + \
|
||
f".names vdd\n1\n" + \
|
||
f".names gnd\n0\n"
|
||
else:
|
||
return f".inputs{self.a.get_wire_declaration_blif()}{self.b.get_wire_declaration_blif()}\n" + \
|
||
f".outputs{self.out.get_wire_declaration_blif()}\n" + \
|
||
f".names vdd\n1\n" + \
|
||
f".names gnd\n0\n"
|
||
|
||
def get_function_blif_flat(self):
|
||
"""Generates flat Blif code with invocation of subcomponents logic gates functions via their corresponding truth tables.
|
||
|
||
Returns:
|
||
str: Flat Blif code containing invocation of inner subcomponents logic gates Boolean functions.
|
||
"""
|
||
return "".join(c.get_function_blif_flat() for c in self.components)
|
||
|
||
def get_function_out_blif(self):
|
||
"""Generates flat Blif code assignment of corresponding arithmetic circuit's output bus wires.
|
||
|
||
Returns:
|
||
str: Flat Blif code containing output bus wires assignment.
|
||
"""
|
||
return f"{self.out.get_wire_assign_blif(output=True)}"
|
||
|
||
# Generating flat BLIF code representation of circuit
|
||
def get_blif_code_flat(self, file_object):
|
||
"""Generates flat Blif code representation of corresponding arithmetic circuit.
|
||
|
||
Args:
|
||
file_object (TextIOWrapper): Destination file object where circuit's representation will be written to.
|
||
"""
|
||
file_object.write(self.get_prototype_blif())
|
||
file_object.write(self.get_declaration_blif())
|
||
file_object.write(self.get_function_blif_flat())
|
||
file_object.write(self.get_function_out_blif())
|
||
file_object.write(f".end\n")
|
||
file_object.close()
|
||
|
||
# HIERARCHICAL BLIF #
|
||
def get_invocations_blif_hier(self):
|
||
"""Generates hierarchical Blif code with invocations of subcomponents function blocks.
|
||
|
||
Returns:
|
||
str: Hierarchical Blif code containing invocations of inner subcomponents function blocks.
|
||
"""
|
||
return "".join(c.get_invocation_blif_hier(circuit_prefix=self.prefix) for c in self.components)
|
||
|
||
def get_invocation_blif_hier(self, circuit_prefix: str):
|
||
"""Generates hierarchical Blif code invocation of corresponding arithmetic circuit's generated function block.
|
||
|
||
Used for multi-bit subcomponent's modul invocation.
|
||
|
||
Args:
|
||
circuit_prefix (str): Prefix name of the upper component from which function block is being invoked.
|
||
|
||
Returns:
|
||
str: Hierarchical Blif code of subcomponent's model invocation and output assignment.
|
||
"""
|
||
# Getting name of circuit type for proper Blif code generation without affecting actual generated composition
|
||
circuit_type = self.prefix.replace(circuit_prefix+"_", "")
|
||
return f"{self.a.get_wire_assign_blif(output=True)}" + \
|
||
f"{self.b.get_wire_assign_blif(output=True)}" + \
|
||
f".subckt {circuit_type}" + \
|
||
"".join([f" a[{self.a.bus.index(w)}]={self.a.prefix}[{self.a.bus.index(w)}]" for w in self.a.bus]) + \
|
||
"".join([f" b[{self.b.bus.index(w)}]={self.b.prefix}[{self.b.bus.index(w)}]" for w in self.b.bus]) + \
|
||
"".join([f" {circuit_type}_out[{self.out.bus.index(o)}]={o.name}" for o in self.out.bus]) + "\n"
|
||
|
||
def get_circuit_blif(self):
|
||
"""Generates hierarchical Blif code subcomponent's function block.
|
||
|
||
Returns:
|
||
str: Hierarchical Blif code of subcomponent's function block.
|
||
"""
|
||
return f"{self.get_prototype_blif()}" + \
|
||
f"{self.get_declaration_blif()}" + \
|
||
f"{self.get_invocations_blif_hier()}" + \
|
||
f"{self.get_function_out_blif()}" + \
|
||
f".end\n"
|
||
|
||
def get_function_blocks_blif(self):
|
||
"""Generates hierarchical Blif code representation of all subcomponents function blocks present in corresponding arithmetic circuit.
|
||
|
||
Returns:
|
||
str: Hierarchical Blif code of all subcomponents function blocks description.
|
||
"""
|
||
# Retrieve all unique component types composing this circuit
|
||
# (iterating backwards as opposed to other representations so the top modul is always above its subcomponents)
|
||
self.component_types = self.get_component_types()
|
||
return "\n".join([c.get_function_block_blif() for c in self.component_types[::-1]])
|
||
|
||
def get_function_block_blif(self):
|
||
"""Generates hierarchical Blif code representation of corresponding multi-bit arithmetic circuit used as function block in hierarchical circuit description.
|
||
|
||
Returns:
|
||
str: Hierarchical Blif code of multi-bit arithmetic circuit's function block description.
|
||
"""
|
||
# Obtain proper circuit name with its bit width
|
||
circuit_prefix = self.__class__(a=Bus("a"), b=Bus("b")).prefix + str(self.N)
|
||
circuit_block = self.__class__(a=Bus(N=self.N, prefix="a"), b=Bus(N=self.N, prefix="b"), prefix=circuit_prefix)
|
||
return f"{circuit_block.get_circuit_blif()}"
|
||
|
||
# Generating hierarchical BLIF code representation of circuit
|
||
def get_blif_code_hier(self, file_object):
|
||
"""Generates hierarchical Blif code representation of corresponding arithmetic circuit.
|
||
|
||
Args:
|
||
file_object (TextIOWrapper): Destination file object where circuit's representation will be written to.
|
||
"""
|
||
file_object.write(self.get_circuit_blif()+"\n")
|
||
file_object.write(self.get_function_blocks_blif())
|
||
file_object.close()
|
||
|
||
""" CGP CODE GENERATION """
|
||
# FLAT CGP #
|
||
def get_parameters_cgp(self):
|
||
"""Generates CGP chromosome parameters of corresponding arithmetic circuit.
|
||
|
||
In total seven parameters represent: total inputs, total outputs, number of rows, number of columns (gates),
|
||
number of each gate's inputs, number of each gate's outputs, quality constant value.
|
||
|
||
Returns:
|
||
str: CGP chromosome parameters of described arithmetic circuit.
|
||
"""
|
||
self.circuit_gates = self.get_circuit_gates()
|
||
return f"{{{self.a.N+self.a.N},{self.out.N},1,{len(self.circuit_gates)},2,1,0}}"
|
||
|
||
def get_triplets_cgp(self):
|
||
"""Generates list of logic gate triplets (first input wire, second input wire, logic gate function) using wires unique position indexes within the described circuit.
|
||
|
||
Each triplet represents unique logic gate within the described arithmetic circuit. Besides the contained input wires indexes and gate's inner logic function, an output wire
|
||
with incremented index position is also created and remembered to be appropriately driven as an input to another logic gate or as the circuit's output.
|
||
|
||
Constant wire with value 0 has constant index of 0.
|
||
Constant wire with value 1 has constant index of 1.
|
||
Other wires indexes start counting from 2 and up.
|
||
|
||
Returns:
|
||
str: List of triplets each describing logic function of corresponding two input logic gate and as a whole describe the arithmetic circuit.
|
||
"""
|
||
self.get_cgp_wires()
|
||
return "".join([g.get_triplet_cgp(a_id=self.get_circuit_wire_index(g.a)) if isinstance(g, OneInputLogicGate) else
|
||
g.get_triplet_cgp(a_id=self.get_circuit_wire_index(g.a), b_id=self.get_circuit_wire_index(g.b)) for g in self.circuit_gates])
|
||
|
||
def get_outputs_cgp(self):
|
||
"""Generates list of output wires indexes of described arithmetic circuit from MSB to LSB.
|
||
|
||
Returns:
|
||
str: List of arithmetic circuit's output wire indexes.
|
||
"""
|
||
return "(" + ",".join([str(self.get_circuit_wire_index(o)) for o in self.out.bus[::-1]]) + ")"
|
||
|
||
# Generating flat CGP chromosome representation of circuit
|
||
def get_cgp_code_flat(self, file_object):
|
||
"""Generates flat CGP chromosome representation of corresponding arithmetic circuit.
|
||
|
||
Args:
|
||
file_object (TextIOWrapper): Destination file object where circuit's representation will be written to.
|
||
"""
|
||
file_object.write(self.get_parameters_cgp())
|
||
file_object.write(self.get_triplets_cgp())
|
||
file_object.write(self.get_outputs_cgp())
|
||
file_object.close()</code></pre>
|
||
</details>
|
||
<h3>Subclasses</h3>
|
||
<ul class="hlist">
|
||
<li><a title="ariths_gen.core.arithmetic_circuits.multiplier_circuit.MultiplierCircuit" href="multiplier_circuit.html#ariths_gen.core.arithmetic_circuits.multiplier_circuit.MultiplierCircuit">MultiplierCircuit</a></li>
|
||
<li><a title="ariths_gen.core.one_bit_circuits.two_input_one_bit_circuit.TwoInputOneBitCircuit" href="../one_bit_circuits/two_input_one_bit_circuit.html#ariths_gen.core.one_bit_circuits.two_input_one_bit_circuit.TwoInputOneBitCircuit">TwoInputOneBitCircuit</a></li>
|
||
<li><a title="ariths_gen.multi_bit_circuits.adders.carry_lookahead_adder.SignedCarryLookaheadAdder" href="../../multi_bit_circuits/adders/carry_lookahead_adder.html#ariths_gen.multi_bit_circuits.adders.carry_lookahead_adder.SignedCarryLookaheadAdder">SignedCarryLookaheadAdder</a></li>
|
||
<li><a title="ariths_gen.multi_bit_circuits.adders.carry_lookahead_adder.UnsignedCarryLookaheadAdder" href="../../multi_bit_circuits/adders/carry_lookahead_adder.html#ariths_gen.multi_bit_circuits.adders.carry_lookahead_adder.UnsignedCarryLookaheadAdder">UnsignedCarryLookaheadAdder</a></li>
|
||
<li><a title="ariths_gen.multi_bit_circuits.adders.carry_skip_adder.SignedCarrySkipAdder" href="../../multi_bit_circuits/adders/carry_skip_adder.html#ariths_gen.multi_bit_circuits.adders.carry_skip_adder.SignedCarrySkipAdder">SignedCarrySkipAdder</a></li>
|
||
<li><a title="ariths_gen.multi_bit_circuits.adders.carry_skip_adder.UnsignedCarrySkipAdder" href="../../multi_bit_circuits/adders/carry_skip_adder.html#ariths_gen.multi_bit_circuits.adders.carry_skip_adder.UnsignedCarrySkipAdder">UnsignedCarrySkipAdder</a></li>
|
||
<li><a title="ariths_gen.multi_bit_circuits.adders.pg_ripple_carry_adder.SignedPGRippleCarryAdder" href="../../multi_bit_circuits/adders/pg_ripple_carry_adder.html#ariths_gen.multi_bit_circuits.adders.pg_ripple_carry_adder.SignedPGRippleCarryAdder">SignedPGRippleCarryAdder</a></li>
|
||
<li><a title="ariths_gen.multi_bit_circuits.adders.pg_ripple_carry_adder.UnsignedPGRippleCarryAdder" href="../../multi_bit_circuits/adders/pg_ripple_carry_adder.html#ariths_gen.multi_bit_circuits.adders.pg_ripple_carry_adder.UnsignedPGRippleCarryAdder">UnsignedPGRippleCarryAdder</a></li>
|
||
<li><a title="ariths_gen.multi_bit_circuits.adders.ripple_carry_adder.SignedRippleCarryAdder" href="../../multi_bit_circuits/adders/ripple_carry_adder.html#ariths_gen.multi_bit_circuits.adders.ripple_carry_adder.SignedRippleCarryAdder">SignedRippleCarryAdder</a></li>
|
||
<li><a title="ariths_gen.multi_bit_circuits.adders.ripple_carry_adder.UnsignedRippleCarryAdder" href="../../multi_bit_circuits/adders/ripple_carry_adder.html#ariths_gen.multi_bit_circuits.adders.ripple_carry_adder.UnsignedRippleCarryAdder">UnsignedRippleCarryAdder</a></li>
|
||
<li><a title="ariths_gen.multi_bit_circuits.dividers.array_divider.ArrayDivider" href="../../multi_bit_circuits/dividers/array_divider.html#ariths_gen.multi_bit_circuits.dividers.array_divider.ArrayDivider">ArrayDivider</a></li>
|
||
</ul>
|
||
<h3>Static methods</h3>
|
||
<dl>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_includes_c"><code class="name flex">
|
||
<span>def <span class="ident">get_includes_c</span></span>(<span>)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates necessary C library includes for output representation.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>C code library includes.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">@staticmethod
|
||
def get_includes_c():
|
||
"""Generates necessary C library includes for output representation.
|
||
|
||
Returns:
|
||
str: C code library includes.
|
||
"""
|
||
return f"#include <stdio.h>\n#include <stdint.h>\n\n"</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_unique_types"><code class="name flex">
|
||
<span>def <span class="ident">get_unique_types</span></span>(<span>components: list)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Retrieves just the unique representatives of class types present inside the provided components list.</p>
|
||
<h2 id="args">Args</h2>
|
||
<dl>
|
||
<dt><strong><code>components</code></strong> : <code>list</code></dt>
|
||
<dd>List of components to be filtered.</dd>
|
||
</dl>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>list</code></dt>
|
||
<dd>List of unique composite class types.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">@staticmethod
|
||
def get_unique_types(components: list):
|
||
"""Retrieves just the unique representatives of class types present inside the provided components list.
|
||
|
||
Args:
|
||
components (list): List of components to be filtered.
|
||
|
||
Returns:
|
||
list: List of unique composite class types.
|
||
"""
|
||
return list({type(c): c for c in components}.values())</code></pre>
|
||
</details>
|
||
</dd>
|
||
</dl>
|
||
<h3>Methods</h3>
|
||
<dl>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.add_component"><code class="name flex">
|
||
<span>def <span class="ident">add_component</span></span>(<span>self, component)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Adds a component into list of circuit's inner subcomponents.</p>
|
||
<h2 id="args">Args</h2>
|
||
<dl>
|
||
<dt><strong><code>component</code></strong></dt>
|
||
<dd>Subcomponent to be added into list of components composing described circuit.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def add_component(self, component):
|
||
"""Adds a component into list of circuit's inner subcomponents.
|
||
|
||
Args:
|
||
component: Subcomponent to be added into list of components composing described circuit.
|
||
"""
|
||
self.components.append(component)</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_blif_code_flat"><code class="name flex">
|
||
<span>def <span class="ident">get_blif_code_flat</span></span>(<span>self, file_object)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates flat Blif code representation of corresponding arithmetic circuit.</p>
|
||
<h2 id="args">Args</h2>
|
||
<dl>
|
||
<dt><strong><code>file_object</code></strong> : <code>TextIOWrapper</code></dt>
|
||
<dd>Destination file object where circuit's representation will be written to.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_blif_code_flat(self, file_object):
|
||
"""Generates flat Blif code representation of corresponding arithmetic circuit.
|
||
|
||
Args:
|
||
file_object (TextIOWrapper): Destination file object where circuit's representation will be written to.
|
||
"""
|
||
file_object.write(self.get_prototype_blif())
|
||
file_object.write(self.get_declaration_blif())
|
||
file_object.write(self.get_function_blif_flat())
|
||
file_object.write(self.get_function_out_blif())
|
||
file_object.write(f".end\n")
|
||
file_object.close()</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_blif_code_hier"><code class="name flex">
|
||
<span>def <span class="ident">get_blif_code_hier</span></span>(<span>self, file_object)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates hierarchical Blif code representation of corresponding arithmetic circuit.</p>
|
||
<h2 id="args">Args</h2>
|
||
<dl>
|
||
<dt><strong><code>file_object</code></strong> : <code>TextIOWrapper</code></dt>
|
||
<dd>Destination file object where circuit's representation will be written to.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_blif_code_hier(self, file_object):
|
||
"""Generates hierarchical Blif code representation of corresponding arithmetic circuit.
|
||
|
||
Args:
|
||
file_object (TextIOWrapper): Destination file object where circuit's representation will be written to.
|
||
"""
|
||
file_object.write(self.get_circuit_blif()+"\n")
|
||
file_object.write(self.get_function_blocks_blif())
|
||
file_object.close()</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_c_code_flat"><code class="name flex">
|
||
<span>def <span class="ident">get_c_code_flat</span></span>(<span>self, file_object)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates flat C code representation of corresponding arithmetic circuit.</p>
|
||
<h2 id="args">Args</h2>
|
||
<dl>
|
||
<dt><strong><code>file_object</code></strong> : <code>TextIOWrapper</code></dt>
|
||
<dd>Destination file object where circuit's representation will be written to.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_c_code_flat(self, file_object):
|
||
"""Generates flat C code representation of corresponding arithmetic circuit.
|
||
|
||
Args:
|
||
file_object (TextIOWrapper): Destination file object where circuit's representation will be written to.
|
||
"""
|
||
file_object.write(self.get_includes_c())
|
||
file_object.write(self.get_prototype_c())
|
||
file_object.write(self.out.get_declaration_c())
|
||
file_object.write(self.get_declaration_c_flat()+"\n")
|
||
file_object.write(self.get_init_c_flat()+"\n")
|
||
file_object.write(self.get_function_out_c_flat())
|
||
file_object.write(f" return {self.out.prefix}"+";\n}")
|
||
file_object.close()</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_c_code_hier"><code class="name flex">
|
||
<span>def <span class="ident">get_c_code_hier</span></span>(<span>self, file_object)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates hierarchical C code representation of corresponding arithmetic circuit.</p>
|
||
<h2 id="args">Args</h2>
|
||
<dl>
|
||
<dt><strong><code>file_object</code></strong> : <code>TextIOWrapper</code></dt>
|
||
<dd>Destination file object where circuit's representation will be written to.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_c_code_hier(self, file_object):
|
||
"""Generates hierarchical C code representation of corresponding arithmetic circuit.
|
||
|
||
Args:
|
||
file_object (TextIOWrapper): Destination file object where circuit's representation will be written to.
|
||
"""
|
||
file_object.write(self.get_includes_c())
|
||
file_object.write(self.get_function_blocks_c())
|
||
file_object.write(self.get_circuit_c())
|
||
file_object.close()</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_carry_wire"><code class="name flex">
|
||
<span>def <span class="ident">get_carry_wire</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Get output wire carrying carry out value.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>Wire</code></dt>
|
||
<dd>Return carry out wire.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_carry_wire(self):
|
||
"""Get output wire carrying carry out value.
|
||
|
||
Returns:
|
||
Wire: Return carry out wire.
|
||
"""
|
||
return self.out.get_wire(1)</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_cgp_code_flat"><code class="name flex">
|
||
<span>def <span class="ident">get_cgp_code_flat</span></span>(<span>self, file_object)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates flat CGP chromosome representation of corresponding arithmetic circuit.</p>
|
||
<h2 id="args">Args</h2>
|
||
<dl>
|
||
<dt><strong><code>file_object</code></strong> : <code>TextIOWrapper</code></dt>
|
||
<dd>Destination file object where circuit's representation will be written to.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_cgp_code_flat(self, file_object):
|
||
"""Generates flat CGP chromosome representation of corresponding arithmetic circuit.
|
||
|
||
Args:
|
||
file_object (TextIOWrapper): Destination file object where circuit's representation will be written to.
|
||
"""
|
||
file_object.write(self.get_parameters_cgp())
|
||
file_object.write(self.get_triplets_cgp())
|
||
file_object.write(self.get_outputs_cgp())
|
||
file_object.close()</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_cgp_wires"><code class="name flex">
|
||
<span>def <span class="ident">get_cgp_wires</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Gets a list of all wires in circuit along with their index position for cgp chromosome generation and stores them inside <code>self.circuit_wires</code> list.</p>
|
||
<p>Constant wire with value 0 has constant index of 0.
|
||
Constant wire with value 1 has constant index of 1.
|
||
Other wires indexes start counting from 2 and up.</p></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_cgp_wires(self):
|
||
"""Gets a list of all wires in circuit along with their index position for cgp chromosome generation and stores them inside `self.circuit_wires` list.
|
||
|
||
Constant wire with value 0 has constant index of 0.
|
||
Constant wire with value 1 has constant index of 1.
|
||
Other wires indexes start counting from 2 and up.
|
||
"""
|
||
self.circuit_wires = []
|
||
if isinstance(self.a, Bus):
|
||
[self.circuit_wires.append((w, f"{w.name}", self.save_wire_id(wire=w))) for w in self.a.bus]
|
||
[self.circuit_wires.append((w, f"{w.name}", self.save_wire_id(wire=w))) for w in self.b.bus]
|
||
else:
|
||
self.circuit_wires.append((self.a, f"{self.a.name}", self.save_wire_id(wire=self.a)))
|
||
self.circuit_wires.append((self.b, f"{self.b.name}", self.save_wire_id(wire=self.b)))
|
||
if hasattr(self, 'c'):
|
||
self.circuit_wires.append((self.c, f"{self.c.name}", self.save_wire_id(wire=self.c)))
|
||
|
||
for gate in self.circuit_gates:
|
||
if not [item for item in self.circuit_wires if gate.a.name == item[1]]:
|
||
self.circuit_wires.append((gate.a, gate.a.name, self.save_wire_id(wire=gate.a)))
|
||
|
||
if hasattr(gate, 'b') and not [item for item in self.circuit_wires if gate.b.name == item[1]]:
|
||
self.circuit_wires.append((gate.b, gate.b.name, self.save_wire_id(wire=gate.b)))
|
||
|
||
if not [item for item in self.circuit_wires if gate.out.name == item[1]]:
|
||
self.circuit_wires.append((gate.out, gate.out.name, self.save_wire_id(wire=gate.out)))</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_circuit_blif"><code class="name flex">
|
||
<span>def <span class="ident">get_circuit_blif</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates hierarchical Blif code subcomponent's function block.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Hierarchical Blif code of subcomponent's function block.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_circuit_blif(self):
|
||
"""Generates hierarchical Blif code subcomponent's function block.
|
||
|
||
Returns:
|
||
str: Hierarchical Blif code of subcomponent's function block.
|
||
"""
|
||
return f"{self.get_prototype_blif()}" + \
|
||
f"{self.get_declaration_blif()}" + \
|
||
f"{self.get_invocations_blif_hier()}" + \
|
||
f"{self.get_function_out_blif()}" + \
|
||
f".end\n"</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_circuit_c"><code class="name flex">
|
||
<span>def <span class="ident">get_circuit_c</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates hierarchical C code subcomponent's function block.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Hierarchical C code of subcomponent's function block.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_circuit_c(self):
|
||
"""Generates hierarchical C code subcomponent's function block.
|
||
|
||
Returns:
|
||
str: Hierarchical C code of subcomponent's function block.
|
||
"""
|
||
return f"{self.get_prototype_c()}" + \
|
||
f"{self.out.get_declaration_c()}" + \
|
||
f"{self.get_declarations_c_hier()}\n" + \
|
||
f"{self.get_init_c_hier()}\n" + \
|
||
f"{self.get_function_out_c_hier()}" + \
|
||
f" return {self.out.prefix}"+";\n}"</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_circuit_gates"><code class="name flex">
|
||
<span>def <span class="ident">get_circuit_gates</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Gets a list of all the logic gates in circuit that should be generated.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>list</code></dt>
|
||
<dd>List of composite logic gates.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_circuit_gates(self):
|
||
"""Gets a list of all the logic gates in circuit that should be generated.
|
||
|
||
Returns:
|
||
list: List of composite logic gates.
|
||
"""
|
||
gates = []
|
||
for c in self.components:
|
||
if isinstance(c, TwoInputLogicGate):
|
||
if c.disable_generation is False:
|
||
gates.append(c)
|
||
else:
|
||
gates.extend((c.get_circuit_gates()))
|
||
return gates</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_circuit_v"><code class="name flex">
|
||
<span>def <span class="ident">get_circuit_v</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates hierarchical Verilog code subcomponent's function block.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Hierarchical Verilog code of subcomponent's function block.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_circuit_v(self):
|
||
"""Generates hierarchical Verilog code subcomponent's function block.
|
||
|
||
Returns:
|
||
str: Hierarchical Verilog code of subcomponent's function block.
|
||
"""
|
||
return f"{self.get_prototype_v()}" + \
|
||
f"{self.get_declarations_v_hier()}\n" + \
|
||
f"{self.get_init_v_hier()}\n" + \
|
||
f"{self.get_function_out_v_hier()}" + \
|
||
f"endmodule"</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_circuit_wire_index"><code class="name flex">
|
||
<span>def <span class="ident">get_circuit_wire_index</span></span>(<span>self, wire: <a title="ariths_gen.wire_components.wires.Wire" href="../../wire_components/wires.html#ariths_gen.wire_components.wires.Wire">Wire</a>)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Searches for circuit's wire unique index position within the circuit. Used for cgp chromosome generation.</p>
|
||
<h2 id="args">Args</h2>
|
||
<dl>
|
||
<dt><strong><code>wire</code></strong> : <code>Wire</code></dt>
|
||
<dd>Wire to retrieve index position of.</dd>
|
||
</dl>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>int</code></dt>
|
||
<dd>Wire's index position number within the circuit.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_circuit_wire_index(self, wire: Wire):
|
||
"""Searches for circuit's wire unique index position within the circuit. Used for cgp chromosome generation.
|
||
|
||
Args:
|
||
wire (Wire): Wire to retrieve index position of.
|
||
|
||
Returns:
|
||
int: Wire's index position number within the circuit.
|
||
"""
|
||
if wire.is_const():
|
||
return wire.cgp_const
|
||
else:
|
||
for w in self.circuit_wires:
|
||
if wire.name == w[1]:
|
||
return w[2]</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_component_types"><code class="name flex">
|
||
<span>def <span class="ident">get_component_types</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Retrieves a list of all the unique types of subcomponents composing the circuit.</p>
|
||
<p>Returning list consists of only the unique types of logic gates, one bit circuits and multi bit circuits.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>list</code></dt>
|
||
<dd>List of unique component types describing the circuit.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_component_types(self):
|
||
"""Retrieves a list of all the unique types of subcomponents composing the circuit.
|
||
|
||
Returning list consists of only the unique types of logic gates, one bit circuits and multi bit circuits.
|
||
|
||
Returns:
|
||
list: List of unique component types describing the circuit.
|
||
"""
|
||
gate_comps = self.get_unique_types(components=self.get_circuit_gates())
|
||
one_bit_comps = self.get_unique_types(components=self.get_one_bit_components())
|
||
multi_bit_comps = self.get_unique_types(components=self.get_multi_bit_components())
|
||
|
||
all_components = gate_comps + one_bit_comps + multi_bit_comps
|
||
return all_components</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_declaration_blif"><code class="name flex">
|
||
<span>def <span class="ident">get_declaration_blif</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates flat Blif code declaration of input/output circuit wires.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Flat Blif code containing declaration of circuit's wires.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_declaration_blif(self):
|
||
"""Generates flat Blif code declaration of input/output circuit wires.
|
||
|
||
Returns:
|
||
str: Flat Blif code containing declaration of circuit's wires.
|
||
"""
|
||
if self.N == 1:
|
||
return f".inputs {self.a.prefix} {self.b.prefix}\n" + \
|
||
f".outputs{self.out.get_wire_declaration_blif()}\n" + \
|
||
f".names vdd\n1\n" + \
|
||
f".names gnd\n0\n"
|
||
else:
|
||
return f".inputs{self.a.get_wire_declaration_blif()}{self.b.get_wire_declaration_blif()}\n" + \
|
||
f".outputs{self.out.get_wire_declaration_blif()}\n" + \
|
||
f".names vdd\n1\n" + \
|
||
f".names gnd\n0\n"</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_declaration_c_flat"><code class="name flex">
|
||
<span>def <span class="ident">get_declaration_c_flat</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates flat C code declaration of input/output circuit wires.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Flat C code arithmetic circuit's wires declaration.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_declaration_c_flat(self):
|
||
"""Generates flat C code declaration of input/output circuit wires.
|
||
|
||
Returns:
|
||
str: Flat C code arithmetic circuit's wires declaration.
|
||
"""
|
||
return f"".join([c.get_declaration_c_flat() for c in self.components])</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_declaration_c_hier"><code class="name flex">
|
||
<span>def <span class="ident">get_declaration_c_hier</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates hierarchical C code declaration of corresponding subcomponent input/output wires inside the upper component.</p>
|
||
<p>Generates wires used to connect input/output values to/from invocation of the corresponding function block into inner wires present
|
||
inside the upper component from which function block has been invoked.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Hierarchical C code of subcomponent arithmetic circuit's wires declaration.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_declaration_c_hier(self):
|
||
"""Generates hierarchical C code declaration of corresponding subcomponent input/output wires inside the upper component.
|
||
|
||
Generates wires used to connect input/output values to/from invocation of the corresponding function block into inner wires present
|
||
inside the upper component from which function block has been invoked.
|
||
|
||
Returns:
|
||
str: Hierarchical C code of subcomponent arithmetic circuit's wires declaration.
|
||
"""
|
||
return f" {self.c_data_type} {self.a.prefix} = 0;\n" + \
|
||
f" {self.c_data_type} {self.b.prefix} = 0;\n" + \
|
||
f" {self.c_data_type} {self.out.prefix} = 0;\n"</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_declaration_v_flat"><code class="name flex">
|
||
<span>def <span class="ident">get_declaration_v_flat</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates flat Verilog code declaration of input/output circuit wires.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Flat Verilog code arithmetic circuit's wires declaration.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_declaration_v_flat(self):
|
||
"""Generates flat Verilog code declaration of input/output circuit wires.
|
||
|
||
Returns:
|
||
str: Flat Verilog code arithmetic circuit's wires declaration.
|
||
"""
|
||
return f"".join([c.get_declaration_v_flat() for c in self.components])</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_declaration_v_hier"><code class="name flex">
|
||
<span>def <span class="ident">get_declaration_v_hier</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates hierarchical Verilog code declaration of corresponding subcomponent input/output wires inside the upper component.</p>
|
||
<p>Generates wires used to connect input/output values to/from invocation of the corresponding function block into inner wires present
|
||
inside the upper component from which function block has been invoked.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Hierarchical Verilog code of subcomponent arithmetic circuit's wires declaration.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_declaration_v_hier(self):
|
||
"""Generates hierarchical Verilog code declaration of corresponding subcomponent input/output wires inside the upper component.
|
||
|
||
Generates wires used to connect input/output values to/from invocation of the corresponding function block into inner wires present
|
||
inside the upper component from which function block has been invoked.
|
||
|
||
Returns:
|
||
str: Hierarchical Verilog code of subcomponent arithmetic circuit's wires declaration.
|
||
"""
|
||
return f" wire [{self.a.N-1}:0] {self.a.prefix};\n" + \
|
||
f" wire [{self.b.N-1}:0] {self.b.prefix};\n" + \
|
||
f" wire [{self.out.N-1}:0] {self.out.prefix};\n"</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_declarations_c_hier"><code class="name flex">
|
||
<span>def <span class="ident">get_declarations_c_hier</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates hierarchical C code declaration of input/output circuit wires.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Hierarchical C code containing unique declaration of arithmetic circuit wires.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_declarations_c_hier(self):
|
||
"""Generates hierarchical C code declaration of input/output circuit wires.
|
||
|
||
Returns:
|
||
str: Hierarchical C code containing unique declaration of arithmetic circuit wires.
|
||
"""
|
||
return "".join([c.get_declaration_c_hier() for c in self.components])</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_declarations_v_hier"><code class="name flex">
|
||
<span>def <span class="ident">get_declarations_v_hier</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates hierarchical Verilog code declaration of input/output circuit wires.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Hierarchical Verilog code containing unique declaration of arithmetic circuit wires.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_declarations_v_hier(self):
|
||
"""Generates hierarchical Verilog code declaration of input/output circuit wires.
|
||
|
||
Returns:
|
||
str: Hierarchical Verilog code containing unique declaration of arithmetic circuit wires.
|
||
"""
|
||
return "".join([c.get_declaration_v_hier() for c in self.components])</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_function_blif_flat"><code class="name flex">
|
||
<span>def <span class="ident">get_function_blif_flat</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates flat Blif code with invocation of subcomponents logic gates functions via their corresponding truth tables.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Flat Blif code containing invocation of inner subcomponents logic gates Boolean functions.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_function_blif_flat(self):
|
||
"""Generates flat Blif code with invocation of subcomponents logic gates functions via their corresponding truth tables.
|
||
|
||
Returns:
|
||
str: Flat Blif code containing invocation of inner subcomponents logic gates Boolean functions.
|
||
"""
|
||
return "".join(c.get_function_blif_flat() for c in self.components)</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_function_block_blif"><code class="name flex">
|
||
<span>def <span class="ident">get_function_block_blif</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates hierarchical Blif code representation of corresponding multi-bit arithmetic circuit used as function block in hierarchical circuit description.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Hierarchical Blif code of multi-bit arithmetic circuit's function block description.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_function_block_blif(self):
|
||
"""Generates hierarchical Blif code representation of corresponding multi-bit arithmetic circuit used as function block in hierarchical circuit description.
|
||
|
||
Returns:
|
||
str: Hierarchical Blif code of multi-bit arithmetic circuit's function block description.
|
||
"""
|
||
# Obtain proper circuit name with its bit width
|
||
circuit_prefix = self.__class__(a=Bus("a"), b=Bus("b")).prefix + str(self.N)
|
||
circuit_block = self.__class__(a=Bus(N=self.N, prefix="a"), b=Bus(N=self.N, prefix="b"), prefix=circuit_prefix)
|
||
return f"{circuit_block.get_circuit_blif()}"</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_function_block_c"><code class="name flex">
|
||
<span>def <span class="ident">get_function_block_c</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates hierarchical C code representation of corresponding multi-bit arithmetic circuit used as function block in hierarchical circuit description.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Hierarchical C code of multi-bit arithmetic circuit's function block description.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_function_block_c(self):
|
||
"""Generates hierarchical C code representation of corresponding multi-bit arithmetic circuit used as function block in hierarchical circuit description.
|
||
|
||
Returns:
|
||
str: Hierarchical C code of multi-bit arithmetic circuit's function block description.
|
||
"""
|
||
# Obtain proper circuit name with its bit width
|
||
circuit_prefix = self.__class__(a=Bus("a"), b=Bus("b")).prefix + str(self.N)
|
||
circuit_block = self.__class__(a=Bus(N=self.N, prefix="a"), b=Bus(N=self.N, prefix="b"), prefix=circuit_prefix)
|
||
return f"{circuit_block.get_circuit_c()}\n\n"</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_function_block_v"><code class="name flex">
|
||
<span>def <span class="ident">get_function_block_v</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates hierarchical Verilog code representation of corresponding multi-bit arithmetic circuit used as function block in hierarchical circuit description.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Hierarchical Verilog code of multi-bit arithmetic circuit's function block description.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_function_block_v(self):
|
||
"""Generates hierarchical Verilog code representation of corresponding multi-bit arithmetic circuit used as function block in hierarchical circuit description.
|
||
|
||
Returns:
|
||
str: Hierarchical Verilog code of multi-bit arithmetic circuit's function block description.
|
||
"""
|
||
# Obtain proper circuit name with its bit width
|
||
circuit_prefix = self.__class__(a=Bus("a"), b=Bus("b")).prefix + str(self.N)
|
||
circuit_block = self.__class__(a=Bus(N=self.N, prefix="a"), b=Bus(N=self.N, prefix="b"), prefix=circuit_prefix)
|
||
return f"{circuit_block.get_circuit_v()}\n\n"</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_function_blocks_blif"><code class="name flex">
|
||
<span>def <span class="ident">get_function_blocks_blif</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates hierarchical Blif code representation of all subcomponents function blocks present in corresponding arithmetic circuit.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Hierarchical Blif code of all subcomponents function blocks description.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_function_blocks_blif(self):
|
||
"""Generates hierarchical Blif code representation of all subcomponents function blocks present in corresponding arithmetic circuit.
|
||
|
||
Returns:
|
||
str: Hierarchical Blif code of all subcomponents function blocks description.
|
||
"""
|
||
# Retrieve all unique component types composing this circuit
|
||
# (iterating backwards as opposed to other representations so the top modul is always above its subcomponents)
|
||
self.component_types = self.get_component_types()
|
||
return "\n".join([c.get_function_block_blif() for c in self.component_types[::-1]])</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_function_blocks_c"><code class="name flex">
|
||
<span>def <span class="ident">get_function_blocks_c</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates hierarchical C code representation of all subcomponents function blocks present in corresponding arithmetic circuit.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Hierarchical C code of all subcomponents function blocks description.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_function_blocks_c(self):
|
||
"""Generates hierarchical C code representation of all subcomponents function blocks present in corresponding arithmetic circuit.
|
||
|
||
Returns:
|
||
str: Hierarchical C code of all subcomponents function blocks description.
|
||
"""
|
||
# Retrieve all unique component types composing this circuit
|
||
self.component_types = self.get_component_types()
|
||
return "".join([c.get_function_block_c() for c in self.component_types])</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_function_blocks_v"><code class="name flex">
|
||
<span>def <span class="ident">get_function_blocks_v</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates hierarchical Verilog code representation of all subcomponents function blocks present in corresponding arithmetic circuit.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Hierarchical Verilog code of all subcomponents function blocks description.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_function_blocks_v(self):
|
||
"""Generates hierarchical Verilog code representation of all subcomponents function blocks present in corresponding arithmetic circuit.
|
||
|
||
Returns:
|
||
str: Hierarchical Verilog code of all subcomponents function blocks description.
|
||
"""
|
||
# Retrieve all unique component types composing this circuit
|
||
self.component_types = self.get_component_types()
|
||
return "".join([c.get_function_block_v() for c in self.component_types])</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_function_out_blif"><code class="name flex">
|
||
<span>def <span class="ident">get_function_out_blif</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates flat Blif code assignment of corresponding arithmetic circuit's output bus wires.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Flat Blif code containing output bus wires assignment.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_function_out_blif(self):
|
||
"""Generates flat Blif code assignment of corresponding arithmetic circuit's output bus wires.
|
||
|
||
Returns:
|
||
str: Flat Blif code containing output bus wires assignment.
|
||
"""
|
||
return f"{self.out.get_wire_assign_blif(output=True)}"</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_function_out_c_flat"><code class="name flex">
|
||
<span>def <span class="ident">get_function_out_c_flat</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates flat C code assignment of corresponding arithmetic circuit's output bus wires.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Flat C code containing output bus wires assignment.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_function_out_c_flat(self):
|
||
"""Generates flat C code assignment of corresponding arithmetic circuit's output bus wires.
|
||
|
||
Returns:
|
||
str: Flat C code containing output bus wires assignment.
|
||
"""
|
||
return self.out.return_bus_wires_values_c_flat()</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_function_out_c_hier"><code class="name flex">
|
||
<span>def <span class="ident">get_function_out_c_hier</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates hierarchical C code assignment of corresponding arithmetic circuit's output bus wires.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Hierarchical C code containing output bus wires assignment.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_function_out_c_hier(self):
|
||
"""Generates hierarchical C code assignment of corresponding arithmetic circuit's output bus wires.
|
||
|
||
Returns:
|
||
str: Hierarchical C code containing output bus wires assignment.
|
||
"""
|
||
return self.out.return_bus_wires_values_c_hier()</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_function_out_v_flat"><code class="name flex">
|
||
<span>def <span class="ident">get_function_out_v_flat</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates flat Verilog code assignment of corresponding arithmetic circuit's output bus wires.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Flat Verilog code containing output bus wires assignment.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_function_out_v_flat(self):
|
||
"""Generates flat Verilog code assignment of corresponding arithmetic circuit's output bus wires.
|
||
|
||
Returns:
|
||
str: Flat Verilog code containing output bus wires assignment.
|
||
"""
|
||
return self.out.return_bus_wires_values_v_flat()</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_function_out_v_hier"><code class="name flex">
|
||
<span>def <span class="ident">get_function_out_v_hier</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates hierarchical Verilog code assignment of corresponding arithmetic circuit's output bus wires.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Hierarchical Verilog code containing output bus wires assignment.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_function_out_v_hier(self):
|
||
"""Generates hierarchical Verilog code assignment of corresponding arithmetic circuit's output bus wires.
|
||
|
||
Returns:
|
||
str: Hierarchical Verilog code containing output bus wires assignment.
|
||
"""
|
||
return self.out.return_bus_wires_values_v_hier()</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_init_c_flat"><code class="name flex">
|
||
<span>def <span class="ident">get_init_c_flat</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates flat C code initialization and assignment of corresponding arithmetic circuit's input/output wires.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Flat C code initialization of arithmetic circuit wires.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_init_c_flat(self):
|
||
"""Generates flat C code initialization and assignment of corresponding arithmetic circuit's input/output wires.
|
||
|
||
Returns:
|
||
str: Flat C code initialization of arithmetic circuit wires.
|
||
"""
|
||
return "".join([c.get_assign_c_flat() if isinstance(c, TwoInputLogicGate) else c.get_init_c_flat() for c in self.components])</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_init_c_hier"><code class="name flex">
|
||
<span>def <span class="ident">get_init_c_hier</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates hierarchical C code initialization and assignment of corresponding arithmetic circuit's input/output wires.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Hierarchical C code initialization of arithmetic circuit wires.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_init_c_hier(self):
|
||
"""Generates hierarchical C code initialization and assignment of corresponding arithmetic circuit's input/output wires.
|
||
|
||
Returns:
|
||
str: Hierarchical C code initialization of arithmetic circuit wires.
|
||
"""
|
||
return "".join([c.get_gate_invocation_c() if isinstance(c, TwoInputLogicGate) else c.get_out_invocation_c(circuit_prefix=self.prefix) for c in self.components])</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_init_v_flat"><code class="name flex">
|
||
<span>def <span class="ident">get_init_v_flat</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates flat Verilog code initialization and assignment of corresponding arithmetic circuit's input/output buses wires.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Flat Verilog code initialization of arithmetic circuit wires.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_init_v_flat(self):
|
||
"""Generates flat Verilog code initialization and assignment of corresponding arithmetic circuit's input/output buses wires.
|
||
|
||
Returns:
|
||
str: Flat Verilog code initialization of arithmetic circuit wires.
|
||
"""
|
||
return "".join([c.get_assign_v_flat() if isinstance(c, TwoInputLogicGate) else c.get_init_v_flat() for c in self.components])</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_init_v_hier"><code class="name flex">
|
||
<span>def <span class="ident">get_init_v_hier</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates hierarchical Verilog code initialization and assignment of corresponding arithmetic circuit's input/output wires.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Hierarchical Verilog code initialization of arithmetic circuit wires.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_init_v_hier(self):
|
||
"""Generates hierarchical Verilog code initialization and assignment of corresponding arithmetic circuit's input/output wires.
|
||
|
||
Returns:
|
||
str: Hierarchical Verilog code initialization of arithmetic circuit wires.
|
||
"""
|
||
return "".join([c.get_gate_invocation_v() if isinstance(c, TwoInputLogicGate) else c.get_out_invocation_v(circuit_prefix=self.prefix) for c in self.components])</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_instance_num"><code class="name flex">
|
||
<span>def <span class="ident">get_instance_num</span></span>(<span>self, cls, count_disabled_gates: bool = True)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Informs how many instances of the same type are already present inside circuit's components list.</p>
|
||
<h2 id="args">Args</h2>
|
||
<dl>
|
||
<dt><strong><code>cls</code></strong> : <code>type</code></dt>
|
||
<dd>Class type for which to count the number of instances in the components list.</dd>
|
||
<dt><strong><code>count_disabled_gates</code></strong> : <code>bool</code>, optional</dt>
|
||
<dd>Indicates whether logic gates that aren't generated should be also counted. Defaults to True.</dd>
|
||
</dl>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>int</code></dt>
|
||
<dd>Number of instances of the same class type.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_instance_num(self, cls, count_disabled_gates: bool = True):
|
||
"""Informs how many instances of the same type are already present inside circuit's components list.
|
||
|
||
Args:
|
||
cls (type): Class type for which to count the number of instances in the components list.
|
||
count_disabled_gates (bool, optional): Indicates whether logic gates that aren't generated should be also counted. Defaults to True.
|
||
Returns:
|
||
int: Number of instances of the same class type.
|
||
"""
|
||
if issubclass(cls, TwoInputLogicGate) and count_disabled_gates is False:
|
||
return sum(isinstance(c, cls) for c in self.components if isinstance(c, cls) and c.disable_generation is False)
|
||
else:
|
||
return sum(isinstance(c, cls) for c in self.components)</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_invocation_blif_hier"><code class="name flex">
|
||
<span>def <span class="ident">get_invocation_blif_hier</span></span>(<span>self, circuit_prefix: str)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates hierarchical Blif code invocation of corresponding arithmetic circuit's generated function block.</p>
|
||
<p>Used for multi-bit subcomponent's modul invocation.</p>
|
||
<h2 id="args">Args</h2>
|
||
<dl>
|
||
<dt><strong><code>circuit_prefix</code></strong> : <code>str</code></dt>
|
||
<dd>Prefix name of the upper component from which function block is being invoked.</dd>
|
||
</dl>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Hierarchical Blif code of subcomponent's model invocation and output assignment.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_invocation_blif_hier(self, circuit_prefix: str):
|
||
"""Generates hierarchical Blif code invocation of corresponding arithmetic circuit's generated function block.
|
||
|
||
Used for multi-bit subcomponent's modul invocation.
|
||
|
||
Args:
|
||
circuit_prefix (str): Prefix name of the upper component from which function block is being invoked.
|
||
|
||
Returns:
|
||
str: Hierarchical Blif code of subcomponent's model invocation and output assignment.
|
||
"""
|
||
# Getting name of circuit type for proper Blif code generation without affecting actual generated composition
|
||
circuit_type = self.prefix.replace(circuit_prefix+"_", "")
|
||
return f"{self.a.get_wire_assign_blif(output=True)}" + \
|
||
f"{self.b.get_wire_assign_blif(output=True)}" + \
|
||
f".subckt {circuit_type}" + \
|
||
"".join([f" a[{self.a.bus.index(w)}]={self.a.prefix}[{self.a.bus.index(w)}]" for w in self.a.bus]) + \
|
||
"".join([f" b[{self.b.bus.index(w)}]={self.b.prefix}[{self.b.bus.index(w)}]" for w in self.b.bus]) + \
|
||
"".join([f" {circuit_type}_out[{self.out.bus.index(o)}]={o.name}" for o in self.out.bus]) + "\n"</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_invocations_blif_hier"><code class="name flex">
|
||
<span>def <span class="ident">get_invocations_blif_hier</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates hierarchical Blif code with invocations of subcomponents function blocks.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Hierarchical Blif code containing invocations of inner subcomponents function blocks.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_invocations_blif_hier(self):
|
||
"""Generates hierarchical Blif code with invocations of subcomponents function blocks.
|
||
|
||
Returns:
|
||
str: Hierarchical Blif code containing invocations of inner subcomponents function blocks.
|
||
"""
|
||
return "".join(c.get_invocation_blif_hier(circuit_prefix=self.prefix) for c in self.components)</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_multi_bit_components"><code class="name flex">
|
||
<span>def <span class="ident">get_multi_bit_components</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Retrieves a list of all the multi bit circuits present as subcomponents inside the circuit.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>list</code></dt>
|
||
<dd>List of composite multi bit circuits.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_multi_bit_components(self):
|
||
"""Retrieves a list of all the multi bit circuits present as subcomponents inside the circuit.
|
||
|
||
Returns:
|
||
list: List of composite multi bit circuits.
|
||
"""
|
||
multi_bit_comps = []
|
||
for c in self.components:
|
||
if isinstance(c, TwoInputLogicGate):
|
||
continue
|
||
elif isinstance(getattr(c, 'a'), Wire):
|
||
continue
|
||
else:
|
||
multi_bit_comps.append(c)
|
||
return multi_bit_comps</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_one_bit_components"><code class="name flex">
|
||
<span>def <span class="ident">get_one_bit_components</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Retrieves a list of all the one bit circuits (besides logic gates) present as subcomponents inside the circuit.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>list</code></dt>
|
||
<dd>List of composite one bit circuits.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_one_bit_components(self):
|
||
"""Retrieves a list of all the one bit circuits (besides logic gates) present as subcomponents inside the circuit.
|
||
|
||
Returns:
|
||
list: List of composite one bit circuits.
|
||
"""
|
||
one_bit_comps = []
|
||
for c in self.components:
|
||
if isinstance(c, TwoInputLogicGate):
|
||
continue
|
||
elif isinstance(getattr(c, 'a'), Wire):
|
||
one_bit_comps.append(c)
|
||
else:
|
||
one_bit_comps.extend(c.get_one_bit_components())
|
||
|
||
return one_bit_comps</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_out_invocation_c"><code class="name flex">
|
||
<span>def <span class="ident">get_out_invocation_c</span></span>(<span>self, circuit_prefix: str)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates hierarchical C code invocation of corresponding arithmetic circuit's generated function block.</p>
|
||
<p>Assigns input values from other subcomponents into multi-bit input buses used as inputs for function block invocation.
|
||
Assigns output values from invocation of the corresponding function block into inner wires present inside
|
||
the upper component from which function block has been invoked.</p>
|
||
<h2 id="args">Args</h2>
|
||
<dl>
|
||
<dt><strong><code>circuit_prefix</code></strong> : <code>str</code></dt>
|
||
<dd>Prefix name of the upper component from which function block is being invoked.</dd>
|
||
</dl>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Hierarchical C code of subcomponent's C function invocation and output assignment.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_out_invocation_c(self, circuit_prefix: str):
|
||
"""Generates hierarchical C code invocation of corresponding arithmetic circuit's generated function block.
|
||
|
||
Assigns input values from other subcomponents into multi-bit input buses used as inputs for function block invocation.
|
||
Assigns output values from invocation of the corresponding function block into inner wires present inside
|
||
the upper component from which function block has been invoked.
|
||
|
||
Args:
|
||
circuit_prefix (str): Prefix name of the upper component from which function block is being invoked.
|
||
|
||
Returns:
|
||
str: Hierarchical C code of subcomponent's C function invocation and output assignment.
|
||
"""
|
||
# Getting name of circuit type for proper C code generation without affecting actual generated composition
|
||
circuit_type = self.prefix.replace(circuit_prefix+"_", "")
|
||
return self.a.return_bus_wires_values_c_hier() + self.b.return_bus_wires_values_c_hier() + \
|
||
f" {self.out.prefix} = {circuit_type}({self.a.prefix}, {self.b.prefix});\n"</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_out_invocation_v"><code class="name flex">
|
||
<span>def <span class="ident">get_out_invocation_v</span></span>(<span>self, circuit_prefix: str)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates hierarchical Verilog code invocation of corresponding arithmetic circuit's generated function block.</p>
|
||
<p>Assigns input values from other subcomponents into multi-bit input buses used as inputs for function block invocation.
|
||
Assigns output values from invocation of the corresponding function block into inner wires present inside
|
||
the upper component from which function block has been invoked.</p>
|
||
<h2 id="args">Args</h2>
|
||
<dl>
|
||
<dt><strong><code>circuit_prefix</code></strong> : <code>str</code></dt>
|
||
<dd>Prefix name of the upper component from which function block is being invoked.</dd>
|
||
</dl>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Hierarchical Verilog code of subcomponent's module invocation and output assignment.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_out_invocation_v(self, circuit_prefix: str):
|
||
"""Generates hierarchical Verilog code invocation of corresponding arithmetic circuit's generated function block.
|
||
|
||
Assigns input values from other subcomponents into multi-bit input buses used as inputs for function block invocation.
|
||
Assigns output values from invocation of the corresponding function block into inner wires present inside
|
||
the upper component from which function block has been invoked.
|
||
|
||
Args:
|
||
circuit_prefix (str): Prefix name of the upper component from which function block is being invoked.
|
||
|
||
Returns:
|
||
str: Hierarchical Verilog code of subcomponent's module invocation and output assignment.
|
||
"""
|
||
# Getting name of circuit type and insitu copying out bus for proper Verilog code generation without affecting actual generated composition
|
||
circuit_type = self.prefix.replace(circuit_prefix+"_", "")
|
||
|
||
# Obtain proper circuit name with its bit width
|
||
circuit_prefix = self.__class__(a=Bus("a"), b=Bus("b")).prefix + str(self.N)
|
||
circuit_block = self.__class__(a=Bus(N=self.N, prefix="a"), b=Bus(N=self.N, prefix="b"), prefix=circuit_prefix)
|
||
return self.a.return_bus_wires_values_v_hier() + self.b.return_bus_wires_values_v_hier() + \
|
||
f" {circuit_type} {circuit_type}_{self.out.prefix}(.{circuit_block.a.prefix}({self.a.prefix}), .{circuit_block.b.prefix}({self.b.prefix}), .{circuit_block.out.prefix}({self.out.prefix}));\n"</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_outputs_cgp"><code class="name flex">
|
||
<span>def <span class="ident">get_outputs_cgp</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates list of output wires indexes of described arithmetic circuit from MSB to LSB.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>List of arithmetic circuit's output wire indexes.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_outputs_cgp(self):
|
||
"""Generates list of output wires indexes of described arithmetic circuit from MSB to LSB.
|
||
|
||
Returns:
|
||
str: List of arithmetic circuit's output wire indexes.
|
||
"""
|
||
return "(" + ",".join([str(self.get_circuit_wire_index(o)) for o in self.out.bus[::-1]]) + ")"</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_parameters_cgp"><code class="name flex">
|
||
<span>def <span class="ident">get_parameters_cgp</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates CGP chromosome parameters of corresponding arithmetic circuit.</p>
|
||
<p>In total seven parameters represent: total inputs, total outputs, number of rows, number of columns (gates),
|
||
number of each gate's inputs, number of each gate's outputs, quality constant value.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>CGP chromosome parameters of described arithmetic circuit.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_parameters_cgp(self):
|
||
"""Generates CGP chromosome parameters of corresponding arithmetic circuit.
|
||
|
||
In total seven parameters represent: total inputs, total outputs, number of rows, number of columns (gates),
|
||
number of each gate's inputs, number of each gate's outputs, quality constant value.
|
||
|
||
Returns:
|
||
str: CGP chromosome parameters of described arithmetic circuit.
|
||
"""
|
||
self.circuit_gates = self.get_circuit_gates()
|
||
return f"{{{self.a.N+self.a.N},{self.out.N},1,{len(self.circuit_gates)},2,1,0}}"</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_previous_component"><code class="name flex">
|
||
<span>def <span class="ident">get_previous_component</span></span>(<span>self, number: int = 1)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Retrieves previously added composite subcomponent from circuit's list of components.</p>
|
||
<h2 id="args">Args</h2>
|
||
<dl>
|
||
<dt><strong><code>number</code></strong> : <code>int</code>, optional</dt>
|
||
<dd>Offset indicating which lastly added component will be retrieved. Defaults to 1.</dd>
|
||
</dl>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>component</code></dt>
|
||
<dd>Desired previously added composite component.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_previous_component(self, number: int = 1):
|
||
"""Retrieves previously added composite subcomponent from circuit's list of components.
|
||
|
||
Args:
|
||
number (int, optional): Offset indicating which lastly added component will be retrieved. Defaults to 1.
|
||
|
||
Returns:
|
||
component: Desired previously added composite component.
|
||
"""
|
||
return self.components[-number]</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_prototype_blif"><code class="name flex">
|
||
<span>def <span class="ident">get_prototype_blif</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates Blif code model name of described arithmetic circuit.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Model's name in Blif code.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_prototype_blif(self):
|
||
"""Generates Blif code model name of described arithmetic circuit.
|
||
|
||
Returns:
|
||
str: Model's name in Blif code.
|
||
"""
|
||
return f".model {self.prefix}\n"</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_prototype_c"><code class="name flex">
|
||
<span>def <span class="ident">get_prototype_c</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates C code function header to describe corresponding arithmetic circuit's interface in C code.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Function's name and parameters in C code.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_prototype_c(self):
|
||
"""Generates C code function header to describe corresponding arithmetic circuit's interface in C code.
|
||
|
||
Returns:
|
||
str: Function's name and parameters in C code.
|
||
"""
|
||
return f"{self.c_data_type} {self.prefix}({self.c_data_type} {self.a.prefix}, {self.c_data_type} {self.b.prefix})" + "{" + "\n"</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_prototype_v"><code class="name flex">
|
||
<span>def <span class="ident">get_prototype_v</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates Verilog code module header to describe corresponding arithmetic circuit's interface in Verilog code.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>Module's name and parameters in Verilog code.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_prototype_v(self):
|
||
"""Generates Verilog code module header to describe corresponding arithmetic circuit's interface in Verilog code.
|
||
|
||
Returns:
|
||
str: Module's name and parameters in Verilog code.
|
||
"""
|
||
return f"module {self.prefix}(input [{self.N-1}:0] {self.a.prefix}, input [{self.N-1}:0] {self.b.prefix}, output [{self.out.N-1}:0] {self.out.prefix});\n"</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_sum_wire"><code class="name flex">
|
||
<span>def <span class="ident">get_sum_wire</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Get output wire carrying sum value.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>Wire</code></dt>
|
||
<dd>Return sum wire.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_sum_wire(self):
|
||
"""Get output wire carrying sum value.
|
||
|
||
Returns:
|
||
Wire: Return sum wire.
|
||
"""
|
||
return self.out.get_wire(0)</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_triplets_cgp"><code class="name flex">
|
||
<span>def <span class="ident">get_triplets_cgp</span></span>(<span>self)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates list of logic gate triplets (first input wire, second input wire, logic gate function) using wires unique position indexes within the described circuit.</p>
|
||
<p>Each triplet represents unique logic gate within the described arithmetic circuit. Besides the contained input wires indexes and gate's inner logic function, an output wire
|
||
with incremented index position is also created and remembered to be appropriately driven as an input to another logic gate or as the circuit's output.</p>
|
||
<p>Constant wire with value 0 has constant index of 0.
|
||
Constant wire with value 1 has constant index of 1.
|
||
Other wires indexes start counting from 2 and up.</p>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>str</code></dt>
|
||
<dd>List of triplets each describing logic function of corresponding two input logic gate and as a whole describe the arithmetic circuit.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_triplets_cgp(self):
|
||
"""Generates list of logic gate triplets (first input wire, second input wire, logic gate function) using wires unique position indexes within the described circuit.
|
||
|
||
Each triplet represents unique logic gate within the described arithmetic circuit. Besides the contained input wires indexes and gate's inner logic function, an output wire
|
||
with incremented index position is also created and remembered to be appropriately driven as an input to another logic gate or as the circuit's output.
|
||
|
||
Constant wire with value 0 has constant index of 0.
|
||
Constant wire with value 1 has constant index of 1.
|
||
Other wires indexes start counting from 2 and up.
|
||
|
||
Returns:
|
||
str: List of triplets each describing logic function of corresponding two input logic gate and as a whole describe the arithmetic circuit.
|
||
"""
|
||
self.get_cgp_wires()
|
||
return "".join([g.get_triplet_cgp(a_id=self.get_circuit_wire_index(g.a)) if isinstance(g, OneInputLogicGate) else
|
||
g.get_triplet_cgp(a_id=self.get_circuit_wire_index(g.a), b_id=self.get_circuit_wire_index(g.b)) for g in self.circuit_gates])</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_v_code_flat"><code class="name flex">
|
||
<span>def <span class="ident">get_v_code_flat</span></span>(<span>self, file_object)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates flat Verilog code representation of corresponding arithmetic circuit.</p>
|
||
<h2 id="args">Args</h2>
|
||
<dl>
|
||
<dt><strong><code>file_object</code></strong> : <code>TextIOWrapper</code></dt>
|
||
<dd>Destination file object where circuit's representation will be written to.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_v_code_flat(self, file_object):
|
||
"""Generates flat Verilog code representation of corresponding arithmetic circuit.
|
||
|
||
Args:
|
||
file_object (TextIOWrapper): Destination file object where circuit's representation will be written to.
|
||
"""
|
||
file_object.write(self.get_prototype_v())
|
||
file_object.write(self.get_declaration_v_flat()+"\n")
|
||
file_object.write(self.get_init_v_flat() + "\n")
|
||
file_object.write(self.get_function_out_v_flat())
|
||
file_object.write(f"endmodule")
|
||
file_object.close()</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_v_code_hier"><code class="name flex">
|
||
<span>def <span class="ident">get_v_code_hier</span></span>(<span>self, file_object)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Generates hierarchical Verilog code representation of corresponding arithmetic circuit.</p>
|
||
<h2 id="args">Args</h2>
|
||
<dl>
|
||
<dt><strong><code>file_object</code></strong> : <code>TextIOWrapper</code></dt>
|
||
<dd>Destination file object where circuit's representation will be written to.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def get_v_code_hier(self, file_object):
|
||
"""Generates hierarchical Verilog code representation of corresponding arithmetic circuit.
|
||
|
||
Args:
|
||
file_object (TextIOWrapper): Destination file object where circuit's representation will be written to.
|
||
"""
|
||
file_object.write(self.get_function_blocks_v())
|
||
file_object.write(self.get_circuit_v())
|
||
file_object.close()</code></pre>
|
||
</details>
|
||
</dd>
|
||
<dt id="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.save_wire_id"><code class="name flex">
|
||
<span>def <span class="ident">save_wire_id</span></span>(<span>self, wire: <a title="ariths_gen.wire_components.wires.Wire" href="../../wire_components/wires.html#ariths_gen.wire_components.wires.Wire">Wire</a>)</span>
|
||
</code></dt>
|
||
<dd>
|
||
<div class="desc"><p>Returns appropriate wire index position within the circuit.</p>
|
||
<p>Constant wire with value 0 has constant index of 0.
|
||
Constant wire with value 1 has constant index of 1.
|
||
Other wires indexes start counting from 2 and up.</p>
|
||
<h2 id="args">Args</h2>
|
||
<dl>
|
||
<dt><strong><code>wire</code></strong> : <code>Wire</code></dt>
|
||
<dd>Wire that will be stored at this circuit index position.</dd>
|
||
</dl>
|
||
<h2 id="returns">Returns</h2>
|
||
<dl>
|
||
<dt><code>int</code></dt>
|
||
<dd>Wire's index position within circuit.</dd>
|
||
</dl></div>
|
||
<details class="source">
|
||
<summary>
|
||
<span>Expand source code</span>
|
||
</summary>
|
||
<pre><code class="python">def save_wire_id(self, wire: Wire):
|
||
"""Returns appropriate wire index position within the circuit.
|
||
|
||
Constant wire with value 0 has constant index of 0.
|
||
Constant wire with value 1 has constant index of 1.
|
||
Other wires indexes start counting from 2 and up.
|
||
|
||
Args:
|
||
wire (Wire): Wire that will be stored at this circuit index position.
|
||
|
||
Returns:
|
||
int: Wire's index position within circuit.
|
||
"""
|
||
if wire.is_const():
|
||
return wire.cgp_const
|
||
else:
|
||
return len([w[0] for w in self.circuit_wires if w[0].is_const() is False]) + 2</code></pre>
|
||
</details>
|
||
</dd>
|
||
</dl>
|
||
</dd>
|
||
</dl>
|
||
</section>
|
||
</article>
|
||
<nav id="sidebar">
|
||
<h1>Index</h1>
|
||
<div class="toc">
|
||
<ul></ul>
|
||
</div>
|
||
<ul id="index">
|
||
<li><h3>Super-module</h3>
|
||
<ul>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits" href="index.html">ariths_gen.core.arithmetic_circuits</a></code></li>
|
||
</ul>
|
||
</li>
|
||
<li><h3><a href="#header-classes">Classes</a></h3>
|
||
<ul>
|
||
<li>
|
||
<h4><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit">ArithmeticCircuit</a></code></h4>
|
||
<ul class="">
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.add_component" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.add_component">add_component</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_blif_code_flat" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_blif_code_flat">get_blif_code_flat</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_blif_code_hier" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_blif_code_hier">get_blif_code_hier</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_c_code_flat" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_c_code_flat">get_c_code_flat</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_c_code_hier" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_c_code_hier">get_c_code_hier</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_carry_wire" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_carry_wire">get_carry_wire</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_cgp_code_flat" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_cgp_code_flat">get_cgp_code_flat</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_cgp_wires" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_cgp_wires">get_cgp_wires</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_circuit_blif" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_circuit_blif">get_circuit_blif</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_circuit_c" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_circuit_c">get_circuit_c</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_circuit_gates" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_circuit_gates">get_circuit_gates</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_circuit_v" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_circuit_v">get_circuit_v</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_circuit_wire_index" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_circuit_wire_index">get_circuit_wire_index</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_component_types" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_component_types">get_component_types</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_declaration_blif" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_declaration_blif">get_declaration_blif</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_declaration_c_flat" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_declaration_c_flat">get_declaration_c_flat</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_declaration_c_hier" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_declaration_c_hier">get_declaration_c_hier</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_declaration_v_flat" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_declaration_v_flat">get_declaration_v_flat</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_declaration_v_hier" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_declaration_v_hier">get_declaration_v_hier</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_declarations_c_hier" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_declarations_c_hier">get_declarations_c_hier</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_declarations_v_hier" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_declarations_v_hier">get_declarations_v_hier</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_function_blif_flat" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_function_blif_flat">get_function_blif_flat</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_function_block_blif" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_function_block_blif">get_function_block_blif</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_function_block_c" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_function_block_c">get_function_block_c</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_function_block_v" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_function_block_v">get_function_block_v</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_function_blocks_blif" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_function_blocks_blif">get_function_blocks_blif</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_function_blocks_c" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_function_blocks_c">get_function_blocks_c</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_function_blocks_v" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_function_blocks_v">get_function_blocks_v</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_function_out_blif" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_function_out_blif">get_function_out_blif</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_function_out_c_flat" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_function_out_c_flat">get_function_out_c_flat</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_function_out_c_hier" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_function_out_c_hier">get_function_out_c_hier</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_function_out_v_flat" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_function_out_v_flat">get_function_out_v_flat</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_function_out_v_hier" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_function_out_v_hier">get_function_out_v_hier</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_includes_c" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_includes_c">get_includes_c</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_init_c_flat" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_init_c_flat">get_init_c_flat</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_init_c_hier" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_init_c_hier">get_init_c_hier</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_init_v_flat" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_init_v_flat">get_init_v_flat</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_init_v_hier" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_init_v_hier">get_init_v_hier</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_instance_num" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_instance_num">get_instance_num</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_invocation_blif_hier" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_invocation_blif_hier">get_invocation_blif_hier</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_invocations_blif_hier" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_invocations_blif_hier">get_invocations_blif_hier</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_multi_bit_components" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_multi_bit_components">get_multi_bit_components</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_one_bit_components" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_one_bit_components">get_one_bit_components</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_out_invocation_c" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_out_invocation_c">get_out_invocation_c</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_out_invocation_v" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_out_invocation_v">get_out_invocation_v</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_outputs_cgp" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_outputs_cgp">get_outputs_cgp</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_parameters_cgp" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_parameters_cgp">get_parameters_cgp</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_previous_component" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_previous_component">get_previous_component</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_prototype_blif" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_prototype_blif">get_prototype_blif</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_prototype_c" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_prototype_c">get_prototype_c</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_prototype_v" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_prototype_v">get_prototype_v</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_sum_wire" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_sum_wire">get_sum_wire</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_triplets_cgp" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_triplets_cgp">get_triplets_cgp</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_unique_types" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_unique_types">get_unique_types</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_v_code_flat" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_v_code_flat">get_v_code_flat</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_v_code_hier" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.get_v_code_hier">get_v_code_hier</a></code></li>
|
||
<li><code><a title="ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.save_wire_id" href="#ariths_gen.core.arithmetic_circuits.arithmetic_circuit.ArithmeticCircuit.save_wire_id">save_wire_id</a></code></li>
|
||
</ul>
|
||
</li>
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||
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||
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