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https://github.com/ehw-fit/ariths-gen.git
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173 lines
11 KiB
Python
173 lines
11 KiB
Python
from ariths_gen.wire_components import (
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ConstantWireValue0,
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Bus
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)
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from ariths_gen.core.arithmetic_circuits import (
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GeneralCircuit
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)
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from ariths_gen.one_bit_circuits.one_bit_components import (
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PGSumLogic,
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GreyCell,
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BlackCell
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)
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from ariths_gen.one_bit_circuits.logic_gates import (
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XorGate
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)
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class UnsignedSklanskyAdder(GeneralCircuit):
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"""Class representing unsigned Sklansky (or divide-and-conquer) adder (using valency-2 logic gates).
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The Sklansky adder belongs to a type of tree (parallel-prefix) adders.
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Tree adder structure consists of three parts of logic: 1) PG logic generation, 2) Parallel PG logic computation, 3) Final sum and cout computation
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The main difference between each tree adder lies in the implementation of the part 2).
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Along with Kogge-Stone and Brent-Kung it is considered to be a fundamental tree adder architecture.
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Sklansky achieves log2(N) stages by computing intermediate prefixes along with the large group prefixes. This comes at the expense
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of fanouts that double at each level.
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Main building components are GreyCells and BlackCells that appropriately encapsulate the essential logic used for PG computation.
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For further circuit characteristics see the book CMOS VLSI Design.
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The implementation performs the 1) and 3) (sum XORs) parts using one bit three input P/G/Sum logic function blocks.
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The 2) part is then composed according to the parallel-prefix adder characteristics.
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```
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B3 A3 B2 A2 B1 A1 B0 A0
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│ │ │ │ │ │ │ │
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┌─▼──▼─┐ ┌─▼──▼─┐ ┌─▼──▼─┐ ┌─▼──▼─┐
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│ PG │ C3 │ PG │ C2 │ PG │ C1 │ PG │
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│ SUM │◄────┐│ SUM │◄──┐│ SUM │◄──┐│ SUM │◄──0
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│ │ ││ │ ││ │ ││ │
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└─┬──┬┬┘ │└─┬┬┬──┘ │└─┬┬┬──┘ │└─┬┬┬──┘
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│ ││G3P3S3│ │││G2P2S2│ │││G1P1S1│ │││G0P0S0
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│ ┌▼▼──────┴──▼▼▼──────┴──▼▼▼──────┴──▼▼▼──┐
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│ │ Parallel-prefix │
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│ │ PG logic │
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│ └─┬───────┬──────────┬──────────┬────────┘
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│ │S3 │S2 │S1 │S0
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┌─▼───▼───────▼──────────▼──────────▼────────┐
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│ Sum + Cout │
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│ logic │
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└┬────┬───────┬──────────┬──────────┬────────┘
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│ │ │ │ │
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▼ ▼ ▼ ▼ ▼
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Cout S3 S1 S0 S0
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```
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Description of the __init__ method.
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Args:
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a (Bus): First input bus.
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b (Bus): Second input bus.
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prefix (str, optional): Prefix name of unsigned sa. Defaults to "".
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name (str, optional): Name of unsigned sa. Defaults to "u_sa".
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"""
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def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "u_sa", **kwargs):
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self.N = max(a.N, b.N)
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super().__init__(inputs=[a, b], prefix=prefix, name=name, out_N=self.N+1, **kwargs)
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# Bus sign extension in case buses have different lengths
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self.a.bus_extend(N=self.N, prefix=a.prefix)
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self.b.bus_extend(N=self.N, prefix=b.prefix)
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cin = ConstantWireValue0()
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# Lists of list containing all propagate/generate wires
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self.propagate_sig = []
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self.generate_sig = []
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# Cin0 used as a first generate wire for obtaining next carry bits
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self.generate_sig.append([cin])
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# For each bit pair proceed with three stages of PPAs (Generate PG signals, Prefix computation (PG logic), Computation and connection of outputs)
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# NOTE In the implementation below, both the first and third stages are handled by the PG FAs
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for i_wire in range(self.N):
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# 1st + 3rd stage: Generate PG signals + Computation and connection of outputs
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self.add_component(PGSumLogic(self.a.get_wire(i_wire), self.b.get_wire(i_wire), self.generate_sig[i_wire][-1], prefix=self.prefix+"_pg_sum"+str(self.get_instance_num(cls=PGSumLogic))))
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self.generate_sig.append([self.get_previous_component().get_generate_wire()])
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self.propagate_sig.append([self.get_previous_component().get_propagate_wire()])
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self.out.connect(i_wire, self.get_previous_component().get_sum_wire())
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if i_wire == self.N-1:
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self.add_component(GreyCell(self.generate_sig[i_wire+1][-1], self.propagate_sig[i_wire][0], self.generate_sig[i_wire][-1], prefix=self.prefix+"_gc"+str(self.get_instance_num(cls=GreyCell))))
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self.out.connect(self.N, self.get_previous_component().get_generate_wire())
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# 2nd stage: Prefix Computation (PG logic)
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# For all bit indexes expect for the last one, proceed with the parralel prefix PG logic
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else:
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binary_form = bin(i_wire+1)[2:][::-1] # +1 to obtain proper carry bit index (index 0 corresponds to Cin)
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index_stages = len(binary_form)
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prev_stage_int_value = 0
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for stage, value in enumerate(binary_form):
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if value == '1':
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# Grey cell
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if stage == index_stages-1:
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if index_stages == 1: # Bit index with only one stage
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self.add_component(GreyCell(self.generate_sig[i_wire+1][0], self.propagate_sig[i_wire][0], self.generate_sig[i_wire][-1], prefix=self.prefix+"_gc"+str(self.get_instance_num(cls=GreyCell))))
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else: # Bit index contains multiple stages, GC is its last stage
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self.add_component(GreyCell(self.get_previous_component().get_generate_wire(), self.get_previous_component().get_propagate_wire(), self.generate_sig[i_wire-prev_stage_int_value][-1], prefix=self.prefix+"_gc"+str(self.get_instance_num(cls=GreyCell))))
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# Black cell
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else: # If bit index contains more than one stage, every stage except for the last one contains a Black cell
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self.add_component(BlackCell(self.generate_sig[i_wire+1][-1], self.propagate_sig[i_wire][-1], self.generate_sig[i_wire-prev_stage_int_value][stage], self.propagate_sig[i_wire-1-prev_stage_int_value][stage], prefix=self.prefix+"_bc"+str(self.get_instance_num(cls=BlackCell))))
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self.propagate_sig[i_wire].append(self.get_previous_component().get_propagate_wire())
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self.generate_sig[i_wire+1].append(self.get_previous_component().get_generate_wire())
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prev_stage_int_value += 2**stage
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class SignedSklanskyAdder(UnsignedSklanskyAdder, GeneralCircuit):
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"""Class representing signed Sklansky (or divide-and-conquer) adder (using valency-2 logic gates).
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The Sklansky adder belongs to a type of tree (parallel-prefix) adders.
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Tree adder structure consists of three parts of logic: 1) PG logic generation, 2) Parallel PG logic computation, 3) Final sum and cout computation
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The main difference between each tree adder lies in the implementation of the part 2).
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|
|
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Along with Kogge-Stone and Brent-Kung it is considered to be a fundamental tree adder architecture.
|
|
|
|
Sklansky achieves log2(N) stages by computing intermediate prefixes along with the large group prefixes. This comes at the expense
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of fanouts that double at each level.
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|
|
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Main building components are GreyCells and BlackCells that appropriately encapsulate the essential logic used for PG computation.
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For further circuit characteristics see the book CMOS VLSI Design.
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|
|
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The implementation performs the 1) and 3) (sum XORs) parts using one bit three input P/G/Sum logic function blocks.
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The 2) part is then composed according to the parallel-prefix adder characteristics.
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At last XOR gates are used to ensure proper sign extension.
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```
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B3 A3 B2 A2 B1 A1 B0 A0
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│ │ │ │ │ │ │ │
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┌─▼──▼─┐ ┌─▼──▼─┐ ┌─▼──▼─┐ ┌─▼──▼─┐
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│ PG │ C3 │ PG │ C2 │ PG │ C1 │ PG │
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│ SUM │◄────┐│ SUM │◄──┐│ SUM │◄──┐│ SUM │◄──0
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│ │ ││ │ ││ │ ││ │
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└─┬──┬┬┘ │└─┬┬┬──┘ │└─┬┬┬──┘ │└─┬┬┬──┘
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│ ││G3P3S3│ │││G2P2S2│ │││G1P1S1│ │││G0P0S0
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│ ┌▼▼──────┴──▼▼▼──────┴──▼▼▼──────┴──▼▼▼──┐
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│ │ Parallel-prefix │
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│ │ PG logic │
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│ └─┬───────┬──────────┬──────────┬────────┘
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│ │S3 │S2 │S1 │S0
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┌─▼───▼───────▼──────────▼──────────▼────────┐
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│ Sum + Cout │
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│ with sign extension │
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└┬────┬───────┬──────────┬──────────┬────────┘
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│ │ │ │ │
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▼ ▼ ▼ ▼ ▼
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Cout S3 S1 S0 S0
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```
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Description of the __init__ method.
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Args:
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a (Bus): First input bus.
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b (Bus): Second input bus.
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prefix (str, optional): Prefix name of signed sa. Defaults to "".
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name (str, optional): Name of signed sa. Defaults to "s_sa".
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"""
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def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "s_sa", **kwargs):
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super().__init__(a=a, b=b, prefix=prefix, name=name, signed=True, **kwargs)
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# Additional XOR gates to ensure correct sign extension in case of sign addition
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self.add_component(XorGate(self.a.get_wire(self.N-1), self.b.get_wire(self.N-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), parent_component=self))
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self.add_component(XorGate(self.get_previous_component().out, self.get_previous_component(2).get_generate_wire(), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), parent_component=self))
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self.out.connect(self.N, self.get_previous_component().out)
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