ariths-gen/generated_circuits/blif_circuits/hier/u_dadda_rca4.blif

.model u_dadda_rca4
.inputs a[0] a[1] a[2] a[3] b[0] b[1] b[2] b[3]
.outputs u_dadda_rca4_out[0] u_dadda_rca4_out[1] u_dadda_rca4_out[2] u_dadda_rca4_out[3] u_dadda_rca4_out[4] u_dadda_rca4_out[5] u_dadda_rca4_out[6] u_dadda_rca4_out[7]
.names vdd
1
.names gnd
0
.subckt and_gate a=a[3] b=b[0] out=u_dadda_rca4_and_3_0
.subckt and_gate a=a[2] b=b[1] out=u_dadda_rca4_and_2_1
.subckt ha a=u_dadda_rca4_and_3_0 b=u_dadda_rca4_and_2_1 ha_xor0=u_dadda_rca4_ha0_xor0 ha_and0=u_dadda_rca4_ha0_and0
.subckt and_gate a=a[3] b=b[1] out=u_dadda_rca4_and_3_1
.subckt ha a=u_dadda_rca4_ha0_and0 b=u_dadda_rca4_and_3_1 ha_xor0=u_dadda_rca4_ha1_xor0 ha_and0=u_dadda_rca4_ha1_and0
.subckt and_gate a=a[2] b=b[0] out=u_dadda_rca4_and_2_0
.subckt and_gate a=a[1] b=b[1] out=u_dadda_rca4_and_1_1
.subckt ha a=u_dadda_rca4_and_2_0 b=u_dadda_rca4_and_1_1 ha_xor0=u_dadda_rca4_ha2_xor0 ha_and0=u_dadda_rca4_ha2_and0
.subckt and_gate a=a[1] b=b[2] out=u_dadda_rca4_and_1_2
.subckt and_gate a=a[0] b=b[3] out=u_dadda_rca4_and_0_3
.subckt fa a=u_dadda_rca4_ha2_and0 b=u_dadda_rca4_and_1_2 cin=u_dadda_rca4_and_0_3 fa_xor1=u_dadda_rca4_fa0_xor1 fa_or0=u_dadda_rca4_fa0_or0
.subckt and_gate a=a[2] b=b[2] out=u_dadda_rca4_and_2_2
.subckt and_gate a=a[1] b=b[3] out=u_dadda_rca4_and_1_3
.subckt fa a=u_dadda_rca4_fa0_or0 b=u_dadda_rca4_and_2_2 cin=u_dadda_rca4_and_1_3 fa_xor1=u_dadda_rca4_fa1_xor1 fa_or0=u_dadda_rca4_fa1_or0
.subckt and_gate a=a[3] b=b[2] out=u_dadda_rca4_and_3_2
.subckt fa a=u_dadda_rca4_fa1_or0 b=u_dadda_rca4_ha1_and0 cin=u_dadda_rca4_and_3_2 fa_xor1=u_dadda_rca4_fa2_xor1 fa_or0=u_dadda_rca4_fa2_or0
.subckt and_gate a=a[0] b=b[0] out=u_dadda_rca4_and_0_0
.subckt and_gate a=a[1] b=b[0] out=u_dadda_rca4_and_1_0
.subckt and_gate a=a[0] b=b[2] out=u_dadda_rca4_and_0_2
.subckt and_gate a=a[2] b=b[3] out=u_dadda_rca4_and_2_3
.subckt and_gate a=a[0] b=b[1] out=u_dadda_rca4_and_0_1
.subckt and_gate a=a[3] b=b[3] out=u_dadda_rca4_and_3_3
.names u_dadda_rca4_and_1_0 u_dadda_rca4_u_rca6_a[0]
1 1
.names u_dadda_rca4_and_0_2 u_dadda_rca4_u_rca6_a[1]
1 1
.names u_dadda_rca4_ha0_xor0 u_dadda_rca4_u_rca6_a[2]
1 1
.names u_dadda_rca4_ha1_xor0 u_dadda_rca4_u_rca6_a[3]
1 1
.names u_dadda_rca4_and_2_3 u_dadda_rca4_u_rca6_a[4]
1 1
.names u_dadda_rca4_fa2_or0 u_dadda_rca4_u_rca6_a[5]
1 1
.names u_dadda_rca4_and_0_1 u_dadda_rca4_u_rca6_b[0]
1 1
.names u_dadda_rca4_ha2_xor0 u_dadda_rca4_u_rca6_b[1]
1 1
.names u_dadda_rca4_fa0_xor1 u_dadda_rca4_u_rca6_b[2]
1 1
.names u_dadda_rca4_fa1_xor1 u_dadda_rca4_u_rca6_b[3]
1 1
.names u_dadda_rca4_fa2_xor1 u_dadda_rca4_u_rca6_b[4]
1 1
.names u_dadda_rca4_and_3_3 u_dadda_rca4_u_rca6_b[5]
1 1
.subckt u_rca6 a[0]=u_dadda_rca4_u_rca6_a[0] a[1]=u_dadda_rca4_u_rca6_a[1] a[2]=u_dadda_rca4_u_rca6_a[2] a[3]=u_dadda_rca4_u_rca6_a[3] a[4]=u_dadda_rca4_u_rca6_a[4] a[5]=u_dadda_rca4_u_rca6_a[5] b[0]=u_dadda_rca4_u_rca6_b[0] b[1]=u_dadda_rca4_u_rca6_b[1] b[2]=u_dadda_rca4_u_rca6_b[2] b[3]=u_dadda_rca4_u_rca6_b[3] b[4]=u_dadda_rca4_u_rca6_b[4] b[5]=u_dadda_rca4_u_rca6_b[5] u_rca6_out[0]=u_dadda_rca4_u_rca6_ha_xor0 u_rca6_out[1]=u_dadda_rca4_u_rca6_fa1_xor1 u_rca6_out[2]=u_dadda_rca4_u_rca6_fa2_xor1 u_rca6_out[3]=u_dadda_rca4_u_rca6_fa3_xor1 u_rca6_out[4]=u_dadda_rca4_u_rca6_fa4_xor1 u_rca6_out[5]=u_dadda_rca4_u_rca6_fa5_xor1 u_rca6_out[6]=u_dadda_rca4_u_rca6_fa5_or0
.names u_dadda_rca4_and_0_0 u_dadda_rca4_out[0]
1 1
.names u_dadda_rca4_u_rca6_ha_xor0 u_dadda_rca4_out[1]
1 1
.names u_dadda_rca4_u_rca6_fa1_xor1 u_dadda_rca4_out[2]
1 1
.names u_dadda_rca4_u_rca6_fa2_xor1 u_dadda_rca4_out[3]
1 1
.names u_dadda_rca4_u_rca6_fa3_xor1 u_dadda_rca4_out[4]
1 1
.names u_dadda_rca4_u_rca6_fa4_xor1 u_dadda_rca4_out[5]
1 1
.names u_dadda_rca4_u_rca6_fa5_xor1 u_dadda_rca4_out[6]
1 1
.names u_dadda_rca4_u_rca6_fa5_or0 u_dadda_rca4_out[7]
1 1
.end

.model u_rca6
.inputs a[0] a[1] a[2] a[3] a[4] a[5] b[0] b[1] b[2] b[3] b[4] b[5]
.outputs u_rca6_out[0] u_rca6_out[1] u_rca6_out[2] u_rca6_out[3] u_rca6_out[4] u_rca6_out[5] u_rca6_out[6]
.names vdd
1
.names gnd
0
.subckt ha a=a[0] b=b[0] ha_xor0=u_rca6_ha_xor0 ha_and0=u_rca6_ha_and0
.subckt fa a=a[1] b=b[1] cin=u_rca6_ha_and0 fa_xor1=u_rca6_fa1_xor1 fa_or0=u_rca6_fa1_or0
.subckt fa a=a[2] b=b[2] cin=u_rca6_fa1_or0 fa_xor1=u_rca6_fa2_xor1 fa_or0=u_rca6_fa2_or0
.subckt fa a=a[3] b=b[3] cin=u_rca6_fa2_or0 fa_xor1=u_rca6_fa3_xor1 fa_or0=u_rca6_fa3_or0
.subckt fa a=a[4] b=b[4] cin=u_rca6_fa3_or0 fa_xor1=u_rca6_fa4_xor1 fa_or0=u_rca6_fa4_or0
.subckt fa a=a[5] b=b[5] cin=u_rca6_fa4_or0 fa_xor1=u_rca6_fa5_xor1 fa_or0=u_rca6_fa5_or0
.names u_rca6_ha_xor0 u_rca6_out[0]
1 1
.names u_rca6_fa1_xor1 u_rca6_out[1]
1 1
.names u_rca6_fa2_xor1 u_rca6_out[2]
1 1
.names u_rca6_fa3_xor1 u_rca6_out[3]
1 1
.names u_rca6_fa4_xor1 u_rca6_out[4]
1 1
.names u_rca6_fa5_xor1 u_rca6_out[5]
1 1
.names u_rca6_fa5_or0 u_rca6_out[6]
1 1
.end

.model fa
.inputs a b cin
.outputs fa_xor1 fa_or0
.names vdd
1
.names gnd
0
.subckt xor_gate a=a b=b out=fa_xor0
.subckt and_gate a=a b=b out=fa_and0
.subckt xor_gate a=fa_xor0 b=cin out=fa_xor1
.subckt and_gate a=fa_xor0 b=cin out=fa_and1
.subckt or_gate a=fa_and0 b=fa_and1 out=fa_or0
.end

.model ha
.inputs a b
.outputs ha_xor0 ha_and0
.names vdd
1
.names gnd
0
.subckt xor_gate a=a b=b out=ha_xor0
.subckt and_gate a=a b=b out=ha_and0
.end

.model or_gate
.inputs a b
.outputs out
.names vdd
1
.names gnd
0
.names a b out
1- 1
-1 1
.end

.model xor_gate
.inputs a b
.outputs out
.names vdd
1
.names gnd
0
.names a b out
01 1
10 1
.end

.model and_gate
.inputs a b
.outputs out
.names vdd
1
.names gnd
0
.names a b out
11 1
.end