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379 lines
21 KiB
Plaintext
379 lines
21 KiB
Plaintext
.model s_csamul_cla8
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.inputs a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7]
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.outputs s_csamul_cla8_out[0] s_csamul_cla8_out[1] s_csamul_cla8_out[2] s_csamul_cla8_out[3] s_csamul_cla8_out[4] s_csamul_cla8_out[5] s_csamul_cla8_out[6] s_csamul_cla8_out[7] s_csamul_cla8_out[8] s_csamul_cla8_out[9] s_csamul_cla8_out[10] s_csamul_cla8_out[11] s_csamul_cla8_out[12] s_csamul_cla8_out[13] s_csamul_cla8_out[14] s_csamul_cla8_out[15]
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.names vdd
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1
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.names gnd
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0
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.subckt and_gate a=a[0] b=b[0] out=s_csamul_cla8_and0_0
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.subckt and_gate a=a[1] b=b[0] out=s_csamul_cla8_and1_0
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.subckt and_gate a=a[2] b=b[0] out=s_csamul_cla8_and2_0
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.subckt and_gate a=a[3] b=b[0] out=s_csamul_cla8_and3_0
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.subckt and_gate a=a[4] b=b[0] out=s_csamul_cla8_and4_0
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.subckt and_gate a=a[5] b=b[0] out=s_csamul_cla8_and5_0
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.subckt and_gate a=a[6] b=b[0] out=s_csamul_cla8_and6_0
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.subckt nand_gate a=a[7] b=b[0] out=s_csamul_cla8_nand7_0
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.subckt and_gate a=a[0] b=b[1] out=s_csamul_cla8_and0_1
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.subckt ha a=s_csamul_cla8_and0_1 b=s_csamul_cla8_and1_0 ha_xor0=s_csamul_cla8_ha0_1_xor0 ha_and0=s_csamul_cla8_ha0_1_and0
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.subckt and_gate a=a[1] b=b[1] out=s_csamul_cla8_and1_1
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.subckt ha a=s_csamul_cla8_and1_1 b=s_csamul_cla8_and2_0 ha_xor0=s_csamul_cla8_ha1_1_xor0 ha_and0=s_csamul_cla8_ha1_1_and0
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.subckt and_gate a=a[2] b=b[1] out=s_csamul_cla8_and2_1
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.subckt ha a=s_csamul_cla8_and2_1 b=s_csamul_cla8_and3_0 ha_xor0=s_csamul_cla8_ha2_1_xor0 ha_and0=s_csamul_cla8_ha2_1_and0
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.subckt and_gate a=a[3] b=b[1] out=s_csamul_cla8_and3_1
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.subckt ha a=s_csamul_cla8_and3_1 b=s_csamul_cla8_and4_0 ha_xor0=s_csamul_cla8_ha3_1_xor0 ha_and0=s_csamul_cla8_ha3_1_and0
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.subckt and_gate a=a[4] b=b[1] out=s_csamul_cla8_and4_1
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.subckt ha a=s_csamul_cla8_and4_1 b=s_csamul_cla8_and5_0 ha_xor0=s_csamul_cla8_ha4_1_xor0 ha_and0=s_csamul_cla8_ha4_1_and0
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.subckt and_gate a=a[5] b=b[1] out=s_csamul_cla8_and5_1
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.subckt ha a=s_csamul_cla8_and5_1 b=s_csamul_cla8_and6_0 ha_xor0=s_csamul_cla8_ha5_1_xor0 ha_and0=s_csamul_cla8_ha5_1_and0
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.subckt and_gate a=a[6] b=b[1] out=s_csamul_cla8_and6_1
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.subckt ha a=s_csamul_cla8_and6_1 b=s_csamul_cla8_nand7_0 ha_xor0=s_csamul_cla8_ha6_1_xor0 ha_and0=s_csamul_cla8_ha6_1_and0
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.subckt nand_gate a=a[7] b=b[1] out=s_csamul_cla8_nand7_1
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.subckt ha a=s_csamul_cla8_nand7_1 b=vdd ha_xor0=s_csamul_cla8_ha7_1_xor0 ha_and0=s_csamul_cla8_nand7_1
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.subckt and_gate a=a[0] b=b[2] out=s_csamul_cla8_and0_2
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.subckt fa a=s_csamul_cla8_and0_2 b=s_csamul_cla8_ha1_1_xor0 cin=s_csamul_cla8_ha0_1_and0 fa_xor1=s_csamul_cla8_fa0_2_xor1 fa_or0=s_csamul_cla8_fa0_2_or0
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.subckt and_gate a=a[1] b=b[2] out=s_csamul_cla8_and1_2
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.subckt fa a=s_csamul_cla8_and1_2 b=s_csamul_cla8_ha2_1_xor0 cin=s_csamul_cla8_ha1_1_and0 fa_xor1=s_csamul_cla8_fa1_2_xor1 fa_or0=s_csamul_cla8_fa1_2_or0
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.subckt and_gate a=a[2] b=b[2] out=s_csamul_cla8_and2_2
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.subckt fa a=s_csamul_cla8_and2_2 b=s_csamul_cla8_ha3_1_xor0 cin=s_csamul_cla8_ha2_1_and0 fa_xor1=s_csamul_cla8_fa2_2_xor1 fa_or0=s_csamul_cla8_fa2_2_or0
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.subckt and_gate a=a[3] b=b[2] out=s_csamul_cla8_and3_2
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.subckt fa a=s_csamul_cla8_and3_2 b=s_csamul_cla8_ha4_1_xor0 cin=s_csamul_cla8_ha3_1_and0 fa_xor1=s_csamul_cla8_fa3_2_xor1 fa_or0=s_csamul_cla8_fa3_2_or0
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.subckt and_gate a=a[4] b=b[2] out=s_csamul_cla8_and4_2
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.subckt fa a=s_csamul_cla8_and4_2 b=s_csamul_cla8_ha5_1_xor0 cin=s_csamul_cla8_ha4_1_and0 fa_xor1=s_csamul_cla8_fa4_2_xor1 fa_or0=s_csamul_cla8_fa4_2_or0
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.subckt and_gate a=a[5] b=b[2] out=s_csamul_cla8_and5_2
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.subckt fa a=s_csamul_cla8_and5_2 b=s_csamul_cla8_ha6_1_xor0 cin=s_csamul_cla8_ha5_1_and0 fa_xor1=s_csamul_cla8_fa5_2_xor1 fa_or0=s_csamul_cla8_fa5_2_or0
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.subckt and_gate a=a[6] b=b[2] out=s_csamul_cla8_and6_2
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.subckt fa a=s_csamul_cla8_and6_2 b=s_csamul_cla8_ha7_1_xor0 cin=s_csamul_cla8_ha6_1_and0 fa_xor1=s_csamul_cla8_fa6_2_xor1 fa_or0=s_csamul_cla8_fa6_2_or0
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.subckt nand_gate a=a[7] b=b[2] out=s_csamul_cla8_nand7_2
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.subckt ha a=s_csamul_cla8_nand7_2 b=s_csamul_cla8_nand7_1 ha_xor0=s_csamul_cla8_ha7_2_xor0 ha_and0=s_csamul_cla8_ha7_2_and0
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.subckt and_gate a=a[0] b=b[3] out=s_csamul_cla8_and0_3
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.subckt fa a=s_csamul_cla8_and0_3 b=s_csamul_cla8_fa1_2_xor1 cin=s_csamul_cla8_fa0_2_or0 fa_xor1=s_csamul_cla8_fa0_3_xor1 fa_or0=s_csamul_cla8_fa0_3_or0
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.subckt and_gate a=a[1] b=b[3] out=s_csamul_cla8_and1_3
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.subckt fa a=s_csamul_cla8_and1_3 b=s_csamul_cla8_fa2_2_xor1 cin=s_csamul_cla8_fa1_2_or0 fa_xor1=s_csamul_cla8_fa1_3_xor1 fa_or0=s_csamul_cla8_fa1_3_or0
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.subckt and_gate a=a[2] b=b[3] out=s_csamul_cla8_and2_3
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.subckt fa a=s_csamul_cla8_and2_3 b=s_csamul_cla8_fa3_2_xor1 cin=s_csamul_cla8_fa2_2_or0 fa_xor1=s_csamul_cla8_fa2_3_xor1 fa_or0=s_csamul_cla8_fa2_3_or0
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.subckt and_gate a=a[3] b=b[3] out=s_csamul_cla8_and3_3
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.subckt fa a=s_csamul_cla8_and3_3 b=s_csamul_cla8_fa4_2_xor1 cin=s_csamul_cla8_fa3_2_or0 fa_xor1=s_csamul_cla8_fa3_3_xor1 fa_or0=s_csamul_cla8_fa3_3_or0
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.subckt and_gate a=a[4] b=b[3] out=s_csamul_cla8_and4_3
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.subckt fa a=s_csamul_cla8_and4_3 b=s_csamul_cla8_fa5_2_xor1 cin=s_csamul_cla8_fa4_2_or0 fa_xor1=s_csamul_cla8_fa4_3_xor1 fa_or0=s_csamul_cla8_fa4_3_or0
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.subckt and_gate a=a[5] b=b[3] out=s_csamul_cla8_and5_3
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.subckt fa a=s_csamul_cla8_and5_3 b=s_csamul_cla8_fa6_2_xor1 cin=s_csamul_cla8_fa5_2_or0 fa_xor1=s_csamul_cla8_fa5_3_xor1 fa_or0=s_csamul_cla8_fa5_3_or0
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.subckt and_gate a=a[6] b=b[3] out=s_csamul_cla8_and6_3
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.subckt fa a=s_csamul_cla8_and6_3 b=s_csamul_cla8_ha7_2_xor0 cin=s_csamul_cla8_fa6_2_or0 fa_xor1=s_csamul_cla8_fa6_3_xor1 fa_or0=s_csamul_cla8_fa6_3_or0
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.subckt nand_gate a=a[7] b=b[3] out=s_csamul_cla8_nand7_3
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.subckt ha a=s_csamul_cla8_nand7_3 b=s_csamul_cla8_ha7_2_and0 ha_xor0=s_csamul_cla8_ha7_3_xor0 ha_and0=s_csamul_cla8_ha7_3_and0
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.subckt and_gate a=a[0] b=b[4] out=s_csamul_cla8_and0_4
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.subckt fa a=s_csamul_cla8_and0_4 b=s_csamul_cla8_fa1_3_xor1 cin=s_csamul_cla8_fa0_3_or0 fa_xor1=s_csamul_cla8_fa0_4_xor1 fa_or0=s_csamul_cla8_fa0_4_or0
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.subckt and_gate a=a[1] b=b[4] out=s_csamul_cla8_and1_4
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.subckt fa a=s_csamul_cla8_and1_4 b=s_csamul_cla8_fa2_3_xor1 cin=s_csamul_cla8_fa1_3_or0 fa_xor1=s_csamul_cla8_fa1_4_xor1 fa_or0=s_csamul_cla8_fa1_4_or0
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.subckt and_gate a=a[2] b=b[4] out=s_csamul_cla8_and2_4
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.subckt fa a=s_csamul_cla8_and2_4 b=s_csamul_cla8_fa3_3_xor1 cin=s_csamul_cla8_fa2_3_or0 fa_xor1=s_csamul_cla8_fa2_4_xor1 fa_or0=s_csamul_cla8_fa2_4_or0
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.subckt and_gate a=a[3] b=b[4] out=s_csamul_cla8_and3_4
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.subckt fa a=s_csamul_cla8_and3_4 b=s_csamul_cla8_fa4_3_xor1 cin=s_csamul_cla8_fa3_3_or0 fa_xor1=s_csamul_cla8_fa3_4_xor1 fa_or0=s_csamul_cla8_fa3_4_or0
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.subckt and_gate a=a[4] b=b[4] out=s_csamul_cla8_and4_4
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.subckt fa a=s_csamul_cla8_and4_4 b=s_csamul_cla8_fa5_3_xor1 cin=s_csamul_cla8_fa4_3_or0 fa_xor1=s_csamul_cla8_fa4_4_xor1 fa_or0=s_csamul_cla8_fa4_4_or0
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.subckt and_gate a=a[5] b=b[4] out=s_csamul_cla8_and5_4
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.subckt fa a=s_csamul_cla8_and5_4 b=s_csamul_cla8_fa6_3_xor1 cin=s_csamul_cla8_fa5_3_or0 fa_xor1=s_csamul_cla8_fa5_4_xor1 fa_or0=s_csamul_cla8_fa5_4_or0
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.subckt and_gate a=a[6] b=b[4] out=s_csamul_cla8_and6_4
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.subckt fa a=s_csamul_cla8_and6_4 b=s_csamul_cla8_ha7_3_xor0 cin=s_csamul_cla8_fa6_3_or0 fa_xor1=s_csamul_cla8_fa6_4_xor1 fa_or0=s_csamul_cla8_fa6_4_or0
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.subckt nand_gate a=a[7] b=b[4] out=s_csamul_cla8_nand7_4
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.subckt ha a=s_csamul_cla8_nand7_4 b=s_csamul_cla8_ha7_3_and0 ha_xor0=s_csamul_cla8_ha7_4_xor0 ha_and0=s_csamul_cla8_ha7_4_and0
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.subckt and_gate a=a[0] b=b[5] out=s_csamul_cla8_and0_5
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.subckt fa a=s_csamul_cla8_and0_5 b=s_csamul_cla8_fa1_4_xor1 cin=s_csamul_cla8_fa0_4_or0 fa_xor1=s_csamul_cla8_fa0_5_xor1 fa_or0=s_csamul_cla8_fa0_5_or0
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.subckt and_gate a=a[1] b=b[5] out=s_csamul_cla8_and1_5
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.subckt fa a=s_csamul_cla8_and1_5 b=s_csamul_cla8_fa2_4_xor1 cin=s_csamul_cla8_fa1_4_or0 fa_xor1=s_csamul_cla8_fa1_5_xor1 fa_or0=s_csamul_cla8_fa1_5_or0
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.subckt and_gate a=a[2] b=b[5] out=s_csamul_cla8_and2_5
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.subckt fa a=s_csamul_cla8_and2_5 b=s_csamul_cla8_fa3_4_xor1 cin=s_csamul_cla8_fa2_4_or0 fa_xor1=s_csamul_cla8_fa2_5_xor1 fa_or0=s_csamul_cla8_fa2_5_or0
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.subckt and_gate a=a[3] b=b[5] out=s_csamul_cla8_and3_5
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.subckt fa a=s_csamul_cla8_and3_5 b=s_csamul_cla8_fa4_4_xor1 cin=s_csamul_cla8_fa3_4_or0 fa_xor1=s_csamul_cla8_fa3_5_xor1 fa_or0=s_csamul_cla8_fa3_5_or0
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.subckt and_gate a=a[4] b=b[5] out=s_csamul_cla8_and4_5
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.subckt fa a=s_csamul_cla8_and4_5 b=s_csamul_cla8_fa5_4_xor1 cin=s_csamul_cla8_fa4_4_or0 fa_xor1=s_csamul_cla8_fa4_5_xor1 fa_or0=s_csamul_cla8_fa4_5_or0
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.subckt and_gate a=a[5] b=b[5] out=s_csamul_cla8_and5_5
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.subckt fa a=s_csamul_cla8_and5_5 b=s_csamul_cla8_fa6_4_xor1 cin=s_csamul_cla8_fa5_4_or0 fa_xor1=s_csamul_cla8_fa5_5_xor1 fa_or0=s_csamul_cla8_fa5_5_or0
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.subckt and_gate a=a[6] b=b[5] out=s_csamul_cla8_and6_5
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.subckt fa a=s_csamul_cla8_and6_5 b=s_csamul_cla8_ha7_4_xor0 cin=s_csamul_cla8_fa6_4_or0 fa_xor1=s_csamul_cla8_fa6_5_xor1 fa_or0=s_csamul_cla8_fa6_5_or0
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.subckt nand_gate a=a[7] b=b[5] out=s_csamul_cla8_nand7_5
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.subckt ha a=s_csamul_cla8_nand7_5 b=s_csamul_cla8_ha7_4_and0 ha_xor0=s_csamul_cla8_ha7_5_xor0 ha_and0=s_csamul_cla8_ha7_5_and0
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.subckt and_gate a=a[0] b=b[6] out=s_csamul_cla8_and0_6
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.subckt fa a=s_csamul_cla8_and0_6 b=s_csamul_cla8_fa1_5_xor1 cin=s_csamul_cla8_fa0_5_or0 fa_xor1=s_csamul_cla8_fa0_6_xor1 fa_or0=s_csamul_cla8_fa0_6_or0
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.subckt and_gate a=a[1] b=b[6] out=s_csamul_cla8_and1_6
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.subckt fa a=s_csamul_cla8_and1_6 b=s_csamul_cla8_fa2_5_xor1 cin=s_csamul_cla8_fa1_5_or0 fa_xor1=s_csamul_cla8_fa1_6_xor1 fa_or0=s_csamul_cla8_fa1_6_or0
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.subckt and_gate a=a[2] b=b[6] out=s_csamul_cla8_and2_6
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.subckt fa a=s_csamul_cla8_and2_6 b=s_csamul_cla8_fa3_5_xor1 cin=s_csamul_cla8_fa2_5_or0 fa_xor1=s_csamul_cla8_fa2_6_xor1 fa_or0=s_csamul_cla8_fa2_6_or0
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.subckt and_gate a=a[3] b=b[6] out=s_csamul_cla8_and3_6
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.subckt fa a=s_csamul_cla8_and3_6 b=s_csamul_cla8_fa4_5_xor1 cin=s_csamul_cla8_fa3_5_or0 fa_xor1=s_csamul_cla8_fa3_6_xor1 fa_or0=s_csamul_cla8_fa3_6_or0
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.subckt and_gate a=a[4] b=b[6] out=s_csamul_cla8_and4_6
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.subckt fa a=s_csamul_cla8_and4_6 b=s_csamul_cla8_fa5_5_xor1 cin=s_csamul_cla8_fa4_5_or0 fa_xor1=s_csamul_cla8_fa4_6_xor1 fa_or0=s_csamul_cla8_fa4_6_or0
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.subckt and_gate a=a[5] b=b[6] out=s_csamul_cla8_and5_6
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.subckt fa a=s_csamul_cla8_and5_6 b=s_csamul_cla8_fa6_5_xor1 cin=s_csamul_cla8_fa5_5_or0 fa_xor1=s_csamul_cla8_fa5_6_xor1 fa_or0=s_csamul_cla8_fa5_6_or0
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.subckt and_gate a=a[6] b=b[6] out=s_csamul_cla8_and6_6
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.subckt fa a=s_csamul_cla8_and6_6 b=s_csamul_cla8_ha7_5_xor0 cin=s_csamul_cla8_fa6_5_or0 fa_xor1=s_csamul_cla8_fa6_6_xor1 fa_or0=s_csamul_cla8_fa6_6_or0
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.subckt nand_gate a=a[7] b=b[6] out=s_csamul_cla8_nand7_6
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.subckt ha a=s_csamul_cla8_nand7_6 b=s_csamul_cla8_ha7_5_and0 ha_xor0=s_csamul_cla8_ha7_6_xor0 ha_and0=s_csamul_cla8_ha7_6_and0
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.subckt nand_gate a=a[0] b=b[7] out=s_csamul_cla8_nand0_7
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.subckt fa a=s_csamul_cla8_nand0_7 b=s_csamul_cla8_fa1_6_xor1 cin=s_csamul_cla8_fa0_6_or0 fa_xor1=s_csamul_cla8_fa0_7_xor1 fa_or0=s_csamul_cla8_fa0_7_or0
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.subckt nand_gate a=a[1] b=b[7] out=s_csamul_cla8_nand1_7
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.subckt fa a=s_csamul_cla8_nand1_7 b=s_csamul_cla8_fa2_6_xor1 cin=s_csamul_cla8_fa1_6_or0 fa_xor1=s_csamul_cla8_fa1_7_xor1 fa_or0=s_csamul_cla8_fa1_7_or0
|
|
.subckt nand_gate a=a[2] b=b[7] out=s_csamul_cla8_nand2_7
|
|
.subckt fa a=s_csamul_cla8_nand2_7 b=s_csamul_cla8_fa3_6_xor1 cin=s_csamul_cla8_fa2_6_or0 fa_xor1=s_csamul_cla8_fa2_7_xor1 fa_or0=s_csamul_cla8_fa2_7_or0
|
|
.subckt nand_gate a=a[3] b=b[7] out=s_csamul_cla8_nand3_7
|
|
.subckt fa a=s_csamul_cla8_nand3_7 b=s_csamul_cla8_fa4_6_xor1 cin=s_csamul_cla8_fa3_6_or0 fa_xor1=s_csamul_cla8_fa3_7_xor1 fa_or0=s_csamul_cla8_fa3_7_or0
|
|
.subckt nand_gate a=a[4] b=b[7] out=s_csamul_cla8_nand4_7
|
|
.subckt fa a=s_csamul_cla8_nand4_7 b=s_csamul_cla8_fa5_6_xor1 cin=s_csamul_cla8_fa4_6_or0 fa_xor1=s_csamul_cla8_fa4_7_xor1 fa_or0=s_csamul_cla8_fa4_7_or0
|
|
.subckt nand_gate a=a[5] b=b[7] out=s_csamul_cla8_nand5_7
|
|
.subckt fa a=s_csamul_cla8_nand5_7 b=s_csamul_cla8_fa6_6_xor1 cin=s_csamul_cla8_fa5_6_or0 fa_xor1=s_csamul_cla8_fa5_7_xor1 fa_or0=s_csamul_cla8_fa5_7_or0
|
|
.subckt nand_gate a=a[6] b=b[7] out=s_csamul_cla8_nand6_7
|
|
.subckt fa a=s_csamul_cla8_nand6_7 b=s_csamul_cla8_ha7_6_xor0 cin=s_csamul_cla8_fa6_6_or0 fa_xor1=s_csamul_cla8_fa6_7_xor1 fa_or0=s_csamul_cla8_fa6_7_or0
|
|
.subckt and_gate a=a[7] b=b[7] out=s_csamul_cla8_and7_7
|
|
.subckt ha a=s_csamul_cla8_and7_7 b=s_csamul_cla8_ha7_6_and0 ha_xor0=s_csamul_cla8_ha7_7_xor0 ha_and0=s_csamul_cla8_ha7_7_and0
|
|
.names s_csamul_cla8_fa1_7_xor1 s_csamul_cla8_u_cla8_a[0]
|
|
1 1
|
|
.names s_csamul_cla8_fa2_7_xor1 s_csamul_cla8_u_cla8_a[1]
|
|
1 1
|
|
.names s_csamul_cla8_fa3_7_xor1 s_csamul_cla8_u_cla8_a[2]
|
|
1 1
|
|
.names s_csamul_cla8_fa4_7_xor1 s_csamul_cla8_u_cla8_a[3]
|
|
1 1
|
|
.names s_csamul_cla8_fa5_7_xor1 s_csamul_cla8_u_cla8_a[4]
|
|
1 1
|
|
.names s_csamul_cla8_fa6_7_xor1 s_csamul_cla8_u_cla8_a[5]
|
|
1 1
|
|
.names s_csamul_cla8_ha7_7_xor0 s_csamul_cla8_u_cla8_a[6]
|
|
1 1
|
|
.names vdd s_csamul_cla8_u_cla8_a[7]
|
|
1 1
|
|
.names s_csamul_cla8_fa0_7_or0 s_csamul_cla8_u_cla8_b[0]
|
|
1 1
|
|
.names s_csamul_cla8_fa1_7_or0 s_csamul_cla8_u_cla8_b[1]
|
|
1 1
|
|
.names s_csamul_cla8_fa2_7_or0 s_csamul_cla8_u_cla8_b[2]
|
|
1 1
|
|
.names s_csamul_cla8_fa3_7_or0 s_csamul_cla8_u_cla8_b[3]
|
|
1 1
|
|
.names s_csamul_cla8_fa4_7_or0 s_csamul_cla8_u_cla8_b[4]
|
|
1 1
|
|
.names s_csamul_cla8_fa5_7_or0 s_csamul_cla8_u_cla8_b[5]
|
|
1 1
|
|
.names s_csamul_cla8_fa6_7_or0 s_csamul_cla8_u_cla8_b[6]
|
|
1 1
|
|
.names s_csamul_cla8_ha7_7_and0 s_csamul_cla8_u_cla8_b[7]
|
|
1 1
|
|
.subckt u_cla8 a[0]=s_csamul_cla8_u_cla8_a[0] a[1]=s_csamul_cla8_u_cla8_a[1] a[2]=s_csamul_cla8_u_cla8_a[2] a[3]=s_csamul_cla8_u_cla8_a[3] a[4]=s_csamul_cla8_u_cla8_a[4] a[5]=s_csamul_cla8_u_cla8_a[5] a[6]=s_csamul_cla8_u_cla8_a[6] a[7]=s_csamul_cla8_u_cla8_a[7] b[0]=s_csamul_cla8_u_cla8_b[0] b[1]=s_csamul_cla8_u_cla8_b[1] b[2]=s_csamul_cla8_u_cla8_b[2] b[3]=s_csamul_cla8_u_cla8_b[3] b[4]=s_csamul_cla8_u_cla8_b[4] b[5]=s_csamul_cla8_u_cla8_b[5] b[6]=s_csamul_cla8_u_cla8_b[6] b[7]=s_csamul_cla8_u_cla8_b[7] u_cla8_out[0]=s_csamul_cla8_u_cla8_pg_logic0_xor0 u_cla8_out[1]=s_csamul_cla8_u_cla8_xor1 u_cla8_out[2]=s_csamul_cla8_u_cla8_xor2 u_cla8_out[3]=s_csamul_cla8_u_cla8_xor3 u_cla8_out[4]=s_csamul_cla8_u_cla8_xor4 u_cla8_out[5]=s_csamul_cla8_u_cla8_xor5 u_cla8_out[6]=s_csamul_cla8_u_cla8_xor6 u_cla8_out[7]=s_csamul_cla8_u_cla8_xor7 u_cla8_out[8]=s_csamul_cla8_u_cla8_or15
|
|
.names s_csamul_cla8_and0_0 s_csamul_cla8_out[0]
|
|
1 1
|
|
.names s_csamul_cla8_ha0_1_xor0 s_csamul_cla8_out[1]
|
|
1 1
|
|
.names s_csamul_cla8_fa0_2_xor1 s_csamul_cla8_out[2]
|
|
1 1
|
|
.names s_csamul_cla8_fa0_3_xor1 s_csamul_cla8_out[3]
|
|
1 1
|
|
.names s_csamul_cla8_fa0_4_xor1 s_csamul_cla8_out[4]
|
|
1 1
|
|
.names s_csamul_cla8_fa0_5_xor1 s_csamul_cla8_out[5]
|
|
1 1
|
|
.names s_csamul_cla8_fa0_6_xor1 s_csamul_cla8_out[6]
|
|
1 1
|
|
.names s_csamul_cla8_fa0_7_xor1 s_csamul_cla8_out[7]
|
|
1 1
|
|
.names s_csamul_cla8_u_cla8_pg_logic0_xor0 s_csamul_cla8_out[8]
|
|
1 1
|
|
.names s_csamul_cla8_u_cla8_xor1 s_csamul_cla8_out[9]
|
|
1 1
|
|
.names s_csamul_cla8_u_cla8_xor2 s_csamul_cla8_out[10]
|
|
1 1
|
|
.names s_csamul_cla8_u_cla8_xor3 s_csamul_cla8_out[11]
|
|
1 1
|
|
.names s_csamul_cla8_u_cla8_xor4 s_csamul_cla8_out[12]
|
|
1 1
|
|
.names s_csamul_cla8_u_cla8_xor5 s_csamul_cla8_out[13]
|
|
1 1
|
|
.names s_csamul_cla8_u_cla8_xor6 s_csamul_cla8_out[14]
|
|
1 1
|
|
.names s_csamul_cla8_u_cla8_xor7 s_csamul_cla8_out[15]
|
|
1 1
|
|
.end
|
|
|
|
.model u_cla8
|
|
.inputs a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7]
|
|
.outputs u_cla8_out[0] u_cla8_out[1] u_cla8_out[2] u_cla8_out[3] u_cla8_out[4] u_cla8_out[5] u_cla8_out[6] u_cla8_out[7] u_cla8_out[8]
|
|
.names vdd
|
|
1
|
|
.names gnd
|
|
0
|
|
.subckt pg_logic a=a[0] b=b[0] pg_logic_or0=u_cla8_pg_logic0_or0 pg_logic_and0=u_cla8_pg_logic0_and0 pg_logic_xor0=u_cla8_pg_logic0_xor0
|
|
.subckt pg_logic a=a[1] b=b[1] pg_logic_or0=u_cla8_pg_logic1_or0 pg_logic_and0=u_cla8_pg_logic1_and0 pg_logic_xor0=u_cla8_pg_logic1_xor0
|
|
.subckt xor_gate a=u_cla8_pg_logic1_xor0 b=u_cla8_pg_logic0_and0 out=u_cla8_xor1
|
|
.subckt and_gate a=u_cla8_pg_logic0_and0 b=u_cla8_pg_logic1_or0 out=u_cla8_and0
|
|
.subckt or_gate a=u_cla8_pg_logic1_and0 b=u_cla8_and0 out=u_cla8_or0
|
|
.subckt pg_logic a=a[2] b=b[2] pg_logic_or0=u_cla8_pg_logic2_or0 pg_logic_and0=u_cla8_pg_logic2_and0 pg_logic_xor0=u_cla8_pg_logic2_xor0
|
|
.subckt xor_gate a=u_cla8_pg_logic2_xor0 b=u_cla8_or0 out=u_cla8_xor2
|
|
.subckt and_gate a=u_cla8_pg_logic2_or0 b=u_cla8_pg_logic0_or0 out=u_cla8_and1
|
|
.subckt and_gate a=u_cla8_pg_logic0_and0 b=u_cla8_pg_logic2_or0 out=u_cla8_and2
|
|
.subckt and_gate a=u_cla8_and2 b=u_cla8_pg_logic1_or0 out=u_cla8_and3
|
|
.subckt and_gate a=u_cla8_pg_logic1_and0 b=u_cla8_pg_logic2_or0 out=u_cla8_and4
|
|
.subckt or_gate a=u_cla8_and3 b=u_cla8_and4 out=u_cla8_or1
|
|
.subckt or_gate a=u_cla8_pg_logic2_and0 b=u_cla8_or1 out=u_cla8_or2
|
|
.subckt pg_logic a=a[3] b=b[3] pg_logic_or0=u_cla8_pg_logic3_or0 pg_logic_and0=u_cla8_pg_logic3_and0 pg_logic_xor0=u_cla8_pg_logic3_xor0
|
|
.subckt xor_gate a=u_cla8_pg_logic3_xor0 b=u_cla8_or2 out=u_cla8_xor3
|
|
.subckt and_gate a=u_cla8_pg_logic3_or0 b=u_cla8_pg_logic1_or0 out=u_cla8_and5
|
|
.subckt and_gate a=u_cla8_pg_logic0_and0 b=u_cla8_pg_logic2_or0 out=u_cla8_and6
|
|
.subckt and_gate a=u_cla8_pg_logic3_or0 b=u_cla8_pg_logic1_or0 out=u_cla8_and7
|
|
.subckt and_gate a=u_cla8_and6 b=u_cla8_and7 out=u_cla8_and8
|
|
.subckt and_gate a=u_cla8_pg_logic1_and0 b=u_cla8_pg_logic3_or0 out=u_cla8_and9
|
|
.subckt and_gate a=u_cla8_and9 b=u_cla8_pg_logic2_or0 out=u_cla8_and10
|
|
.subckt and_gate a=u_cla8_pg_logic2_and0 b=u_cla8_pg_logic3_or0 out=u_cla8_and11
|
|
.subckt or_gate a=u_cla8_and8 b=u_cla8_and11 out=u_cla8_or3
|
|
.subckt or_gate a=u_cla8_and10 b=u_cla8_or3 out=u_cla8_or4
|
|
.subckt or_gate a=u_cla8_pg_logic3_and0 b=u_cla8_or4 out=u_cla8_or5
|
|
.subckt pg_logic a=a[4] b=b[4] pg_logic_or0=u_cla8_pg_logic4_or0 pg_logic_and0=u_cla8_pg_logic4_and0 pg_logic_xor0=u_cla8_pg_logic4_xor0
|
|
.subckt xor_gate a=u_cla8_pg_logic4_xor0 b=u_cla8_or5 out=u_cla8_xor4
|
|
.subckt and_gate a=u_cla8_or5 b=u_cla8_pg_logic4_or0 out=u_cla8_and12
|
|
.subckt or_gate a=u_cla8_pg_logic4_and0 b=u_cla8_and12 out=u_cla8_or6
|
|
.subckt pg_logic a=a[5] b=b[5] pg_logic_or0=u_cla8_pg_logic5_or0 pg_logic_and0=u_cla8_pg_logic5_and0 pg_logic_xor0=u_cla8_pg_logic5_xor0
|
|
.subckt xor_gate a=u_cla8_pg_logic5_xor0 b=u_cla8_or6 out=u_cla8_xor5
|
|
.subckt and_gate a=u_cla8_or5 b=u_cla8_pg_logic5_or0 out=u_cla8_and13
|
|
.subckt and_gate a=u_cla8_and13 b=u_cla8_pg_logic4_or0 out=u_cla8_and14
|
|
.subckt and_gate a=u_cla8_pg_logic4_and0 b=u_cla8_pg_logic5_or0 out=u_cla8_and15
|
|
.subckt or_gate a=u_cla8_and14 b=u_cla8_and15 out=u_cla8_or7
|
|
.subckt or_gate a=u_cla8_pg_logic5_and0 b=u_cla8_or7 out=u_cla8_or8
|
|
.subckt pg_logic a=a[6] b=b[6] pg_logic_or0=u_cla8_pg_logic6_or0 pg_logic_and0=u_cla8_pg_logic6_and0 pg_logic_xor0=u_cla8_pg_logic6_xor0
|
|
.subckt xor_gate a=u_cla8_pg_logic6_xor0 b=u_cla8_or8 out=u_cla8_xor6
|
|
.subckt and_gate a=u_cla8_or5 b=u_cla8_pg_logic5_or0 out=u_cla8_and16
|
|
.subckt and_gate a=u_cla8_pg_logic6_or0 b=u_cla8_pg_logic4_or0 out=u_cla8_and17
|
|
.subckt and_gate a=u_cla8_and16 b=u_cla8_and17 out=u_cla8_and18
|
|
.subckt and_gate a=u_cla8_pg_logic4_and0 b=u_cla8_pg_logic6_or0 out=u_cla8_and19
|
|
.subckt and_gate a=u_cla8_and19 b=u_cla8_pg_logic5_or0 out=u_cla8_and20
|
|
.subckt and_gate a=u_cla8_pg_logic5_and0 b=u_cla8_pg_logic6_or0 out=u_cla8_and21
|
|
.subckt or_gate a=u_cla8_and18 b=u_cla8_and20 out=u_cla8_or9
|
|
.subckt or_gate a=u_cla8_or9 b=u_cla8_and21 out=u_cla8_or10
|
|
.subckt or_gate a=u_cla8_pg_logic6_and0 b=u_cla8_or10 out=u_cla8_or11
|
|
.subckt pg_logic a=a[7] b=b[7] pg_logic_or0=u_cla8_pg_logic7_or0 pg_logic_and0=u_cla8_pg_logic7_and0 pg_logic_xor0=u_cla8_pg_logic7_xor0
|
|
.subckt xor_gate a=u_cla8_pg_logic7_xor0 b=u_cla8_or11 out=u_cla8_xor7
|
|
.subckt and_gate a=u_cla8_or5 b=u_cla8_pg_logic6_or0 out=u_cla8_and22
|
|
.subckt and_gate a=u_cla8_pg_logic7_or0 b=u_cla8_pg_logic5_or0 out=u_cla8_and23
|
|
.subckt and_gate a=u_cla8_and22 b=u_cla8_and23 out=u_cla8_and24
|
|
.subckt and_gate a=u_cla8_and24 b=u_cla8_pg_logic4_or0 out=u_cla8_and25
|
|
.subckt and_gate a=u_cla8_pg_logic4_and0 b=u_cla8_pg_logic6_or0 out=u_cla8_and26
|
|
.subckt and_gate a=u_cla8_pg_logic7_or0 b=u_cla8_pg_logic5_or0 out=u_cla8_and27
|
|
.subckt and_gate a=u_cla8_and26 b=u_cla8_and27 out=u_cla8_and28
|
|
.subckt and_gate a=u_cla8_pg_logic5_and0 b=u_cla8_pg_logic7_or0 out=u_cla8_and29
|
|
.subckt and_gate a=u_cla8_and29 b=u_cla8_pg_logic6_or0 out=u_cla8_and30
|
|
.subckt and_gate a=u_cla8_pg_logic6_and0 b=u_cla8_pg_logic7_or0 out=u_cla8_and31
|
|
.subckt or_gate a=u_cla8_and25 b=u_cla8_and30 out=u_cla8_or12
|
|
.subckt or_gate a=u_cla8_and28 b=u_cla8_and31 out=u_cla8_or13
|
|
.subckt or_gate a=u_cla8_or12 b=u_cla8_or13 out=u_cla8_or14
|
|
.subckt or_gate a=u_cla8_pg_logic7_and0 b=u_cla8_or14 out=u_cla8_or15
|
|
.names u_cla8_pg_logic0_xor0 u_cla8_out[0]
|
|
1 1
|
|
.names u_cla8_xor1 u_cla8_out[1]
|
|
1 1
|
|
.names u_cla8_xor2 u_cla8_out[2]
|
|
1 1
|
|
.names u_cla8_xor3 u_cla8_out[3]
|
|
1 1
|
|
.names u_cla8_xor4 u_cla8_out[4]
|
|
1 1
|
|
.names u_cla8_xor5 u_cla8_out[5]
|
|
1 1
|
|
.names u_cla8_xor6 u_cla8_out[6]
|
|
1 1
|
|
.names u_cla8_xor7 u_cla8_out[7]
|
|
1 1
|
|
.names u_cla8_or15 u_cla8_out[8]
|
|
1 1
|
|
.end
|
|
|
|
.model pg_logic
|
|
.inputs a b
|
|
.outputs pg_logic_or0 pg_logic_and0 pg_logic_xor0
|
|
.names vdd
|
|
1
|
|
.names gnd
|
|
0
|
|
.subckt or_gate a=a b=b out=pg_logic_or0
|
|
.subckt and_gate a=a b=b out=pg_logic_and0
|
|
.subckt xor_gate a=a b=b out=pg_logic_xor0
|
|
.end
|
|
|
|
.model fa
|
|
.inputs a b cin
|
|
.outputs fa_xor1 fa_or0
|
|
.names vdd
|
|
1
|
|
.names gnd
|
|
0
|
|
.subckt xor_gate a=a b=b out=fa_xor0
|
|
.subckt and_gate a=a b=b out=fa_and0
|
|
.subckt xor_gate a=fa_xor0 b=cin out=fa_xor1
|
|
.subckt and_gate a=fa_xor0 b=cin out=fa_and1
|
|
.subckt or_gate a=fa_and0 b=fa_and1 out=fa_or0
|
|
.end
|
|
|
|
.model ha
|
|
.inputs a b
|
|
.outputs ha_xor0 ha_and0
|
|
.names vdd
|
|
1
|
|
.names gnd
|
|
0
|
|
.subckt xor_gate a=a b=b out=ha_xor0
|
|
.subckt and_gate a=a b=b out=ha_and0
|
|
.end
|
|
|
|
.model or_gate
|
|
.inputs a b
|
|
.outputs out
|
|
.names vdd
|
|
1
|
|
.names gnd
|
|
0
|
|
.names a b out
|
|
1- 1
|
|
-1 1
|
|
.end
|
|
|
|
.model not_gate
|
|
.inputs a
|
|
.outputs out
|
|
.names vdd
|
|
1
|
|
.names gnd
|
|
0
|
|
.names a out
|
|
0 1
|
|
.end
|
|
|
|
.model xor_gate
|
|
.inputs a b
|
|
.outputs out
|
|
.names vdd
|
|
1
|
|
.names gnd
|
|
0
|
|
.names a b out
|
|
01 1
|
|
10 1
|
|
.end
|
|
|
|
.model nand_gate
|
|
.inputs a b
|
|
.outputs out
|
|
.names vdd
|
|
1
|
|
.names gnd
|
|
0
|
|
.names a b out
|
|
0- 1
|
|
-0 1
|
|
.end
|
|
|
|
.model and_gate
|
|
.inputs a b
|
|
.outputs out
|
|
.names vdd
|
|
1
|
|
.names gnd
|
|
0
|
|
.names a b out
|
|
11 1
|
|
.end
|