ariths-gen/generated_circuits/blif_circuits/hier/arrdiv8.blif

.model arrdiv8
.inputs a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7]
.outputs arrdiv8_out[0] arrdiv8_out[1] arrdiv8_out[2] arrdiv8_out[3] arrdiv8_out[4] arrdiv8_out[5] arrdiv8_out[6] arrdiv8_out[7]
.names vdd
1
.names gnd
0
.subckt fs a=a[7] b=b[0] bin=gnd fs_xor1=arrdiv8_fs0_xor0 fs_or0=arrdiv8_fs0_and0
.subckt fs a=gnd b=b[1] bin=arrdiv8_fs0_and0 fs_xor1=arrdiv8_fs1_xor1 fs_or0=arrdiv8_fs1_or0
.subckt fs a=gnd b=b[2] bin=arrdiv8_fs1_or0 fs_xor1=arrdiv8_fs2_xor1 fs_or0=arrdiv8_fs2_or0
.subckt fs a=gnd b=b[3] bin=arrdiv8_fs2_or0 fs_xor1=arrdiv8_fs3_xor1 fs_or0=arrdiv8_fs3_or0
.subckt fs a=gnd b=b[4] bin=arrdiv8_fs3_or0 fs_xor1=arrdiv8_fs4_xor1 fs_or0=arrdiv8_fs4_or0
.subckt fs a=gnd b=b[5] bin=arrdiv8_fs4_or0 fs_xor1=arrdiv8_fs5_xor1 fs_or0=arrdiv8_fs5_or0
.subckt fs a=gnd b=b[6] bin=arrdiv8_fs5_or0 fs_xor1=arrdiv8_fs6_xor1 fs_or0=arrdiv8_fs6_or0
.subckt fs a=gnd b=b[7] bin=arrdiv8_fs6_or0 fs_xor1=arrdiv8_fs7_xor1 fs_or0=arrdiv8_fs7_or0
.subckt mux2to1 d0=arrdiv8_fs0_xor0 d1=a[7] sel=arrdiv8_fs7_or0 mux2to1_xor0=arrdiv8_mux2to10_xor0
.subckt mux2to1 d0=arrdiv8_fs1_xor1 d1=gnd sel=arrdiv8_fs7_or0 mux2to1_xor0=arrdiv8_mux2to11_and1
.subckt mux2to1 d0=arrdiv8_fs2_xor1 d1=gnd sel=arrdiv8_fs7_or0 mux2to1_xor0=arrdiv8_mux2to12_and1
.subckt mux2to1 d0=arrdiv8_fs3_xor1 d1=gnd sel=arrdiv8_fs7_or0 mux2to1_xor0=arrdiv8_mux2to13_and1
.subckt mux2to1 d0=arrdiv8_fs4_xor1 d1=gnd sel=arrdiv8_fs7_or0 mux2to1_xor0=arrdiv8_mux2to14_and1
.subckt mux2to1 d0=arrdiv8_fs5_xor1 d1=gnd sel=arrdiv8_fs7_or0 mux2to1_xor0=arrdiv8_mux2to15_and1
.subckt mux2to1 d0=arrdiv8_fs6_xor1 d1=gnd sel=arrdiv8_fs7_or0 mux2to1_xor0=arrdiv8_mux2to16_and1
.subckt not_gate a=arrdiv8_fs7_or0 out=arrdiv8_not0
.subckt fs a=a[6] b=b[0] bin=gnd fs_xor1=arrdiv8_fs8_xor0 fs_or0=arrdiv8_fs8_and0
.subckt fs a=arrdiv8_mux2to10_xor0 b=b[1] bin=arrdiv8_fs8_and0 fs_xor1=arrdiv8_fs9_xor1 fs_or0=arrdiv8_fs9_or0
.subckt fs a=arrdiv8_mux2to11_and1 b=b[2] bin=arrdiv8_fs9_or0 fs_xor1=arrdiv8_fs10_xor1 fs_or0=arrdiv8_fs10_or0
.subckt fs a=arrdiv8_mux2to12_and1 b=b[3] bin=arrdiv8_fs10_or0 fs_xor1=arrdiv8_fs11_xor1 fs_or0=arrdiv8_fs11_or0
.subckt fs a=arrdiv8_mux2to13_and1 b=b[4] bin=arrdiv8_fs11_or0 fs_xor1=arrdiv8_fs12_xor1 fs_or0=arrdiv8_fs12_or0
.subckt fs a=arrdiv8_mux2to14_and1 b=b[5] bin=arrdiv8_fs12_or0 fs_xor1=arrdiv8_fs13_xor1 fs_or0=arrdiv8_fs13_or0
.subckt fs a=arrdiv8_mux2to15_and1 b=b[6] bin=arrdiv8_fs13_or0 fs_xor1=arrdiv8_fs14_xor1 fs_or0=arrdiv8_fs14_or0
.subckt fs a=arrdiv8_mux2to16_and1 b=b[7] bin=arrdiv8_fs14_or0 fs_xor1=arrdiv8_fs15_xor1 fs_or0=arrdiv8_fs15_or0
.subckt mux2to1 d0=arrdiv8_fs8_xor0 d1=a[6] sel=arrdiv8_fs15_or0 mux2to1_xor0=arrdiv8_mux2to17_xor0
.subckt mux2to1 d0=arrdiv8_fs9_xor1 d1=arrdiv8_mux2to10_xor0 sel=arrdiv8_fs15_or0 mux2to1_xor0=arrdiv8_mux2to18_xor0
.subckt mux2to1 d0=arrdiv8_fs10_xor1 d1=arrdiv8_mux2to11_and1 sel=arrdiv8_fs15_or0 mux2to1_xor0=arrdiv8_mux2to19_xor0
.subckt mux2to1 d0=arrdiv8_fs11_xor1 d1=arrdiv8_mux2to12_and1 sel=arrdiv8_fs15_or0 mux2to1_xor0=arrdiv8_mux2to110_xor0
.subckt mux2to1 d0=arrdiv8_fs12_xor1 d1=arrdiv8_mux2to13_and1 sel=arrdiv8_fs15_or0 mux2to1_xor0=arrdiv8_mux2to111_xor0
.subckt mux2to1 d0=arrdiv8_fs13_xor1 d1=arrdiv8_mux2to14_and1 sel=arrdiv8_fs15_or0 mux2to1_xor0=arrdiv8_mux2to112_xor0
.subckt mux2to1 d0=arrdiv8_fs14_xor1 d1=arrdiv8_mux2to15_and1 sel=arrdiv8_fs15_or0 mux2to1_xor0=arrdiv8_mux2to113_xor0
.subckt not_gate a=arrdiv8_fs15_or0 out=arrdiv8_not1
.subckt fs a=a[5] b=b[0] bin=gnd fs_xor1=arrdiv8_fs16_xor0 fs_or0=arrdiv8_fs16_and0
.subckt fs a=arrdiv8_mux2to17_xor0 b=b[1] bin=arrdiv8_fs16_and0 fs_xor1=arrdiv8_fs17_xor1 fs_or0=arrdiv8_fs17_or0
.subckt fs a=arrdiv8_mux2to18_xor0 b=b[2] bin=arrdiv8_fs17_or0 fs_xor1=arrdiv8_fs18_xor1 fs_or0=arrdiv8_fs18_or0
.subckt fs a=arrdiv8_mux2to19_xor0 b=b[3] bin=arrdiv8_fs18_or0 fs_xor1=arrdiv8_fs19_xor1 fs_or0=arrdiv8_fs19_or0
.subckt fs a=arrdiv8_mux2to110_xor0 b=b[4] bin=arrdiv8_fs19_or0 fs_xor1=arrdiv8_fs20_xor1 fs_or0=arrdiv8_fs20_or0
.subckt fs a=arrdiv8_mux2to111_xor0 b=b[5] bin=arrdiv8_fs20_or0 fs_xor1=arrdiv8_fs21_xor1 fs_or0=arrdiv8_fs21_or0
.subckt fs a=arrdiv8_mux2to112_xor0 b=b[6] bin=arrdiv8_fs21_or0 fs_xor1=arrdiv8_fs22_xor1 fs_or0=arrdiv8_fs22_or0
.subckt fs a=arrdiv8_mux2to113_xor0 b=b[7] bin=arrdiv8_fs22_or0 fs_xor1=arrdiv8_fs23_xor1 fs_or0=arrdiv8_fs23_or0
.subckt mux2to1 d0=arrdiv8_fs16_xor0 d1=a[5] sel=arrdiv8_fs23_or0 mux2to1_xor0=arrdiv8_mux2to114_xor0
.subckt mux2to1 d0=arrdiv8_fs17_xor1 d1=arrdiv8_mux2to17_xor0 sel=arrdiv8_fs23_or0 mux2to1_xor0=arrdiv8_mux2to115_xor0
.subckt mux2to1 d0=arrdiv8_fs18_xor1 d1=arrdiv8_mux2to18_xor0 sel=arrdiv8_fs23_or0 mux2to1_xor0=arrdiv8_mux2to116_xor0
.subckt mux2to1 d0=arrdiv8_fs19_xor1 d1=arrdiv8_mux2to19_xor0 sel=arrdiv8_fs23_or0 mux2to1_xor0=arrdiv8_mux2to117_xor0
.subckt mux2to1 d0=arrdiv8_fs20_xor1 d1=arrdiv8_mux2to110_xor0 sel=arrdiv8_fs23_or0 mux2to1_xor0=arrdiv8_mux2to118_xor0
.subckt mux2to1 d0=arrdiv8_fs21_xor1 d1=arrdiv8_mux2to111_xor0 sel=arrdiv8_fs23_or0 mux2to1_xor0=arrdiv8_mux2to119_xor0
.subckt mux2to1 d0=arrdiv8_fs22_xor1 d1=arrdiv8_mux2to112_xor0 sel=arrdiv8_fs23_or0 mux2to1_xor0=arrdiv8_mux2to120_xor0
.subckt not_gate a=arrdiv8_fs23_or0 out=arrdiv8_not2
.subckt fs a=a[4] b=b[0] bin=gnd fs_xor1=arrdiv8_fs24_xor0 fs_or0=arrdiv8_fs24_and0
.subckt fs a=arrdiv8_mux2to114_xor0 b=b[1] bin=arrdiv8_fs24_and0 fs_xor1=arrdiv8_fs25_xor1 fs_or0=arrdiv8_fs25_or0
.subckt fs a=arrdiv8_mux2to115_xor0 b=b[2] bin=arrdiv8_fs25_or0 fs_xor1=arrdiv8_fs26_xor1 fs_or0=arrdiv8_fs26_or0
.subckt fs a=arrdiv8_mux2to116_xor0 b=b[3] bin=arrdiv8_fs26_or0 fs_xor1=arrdiv8_fs27_xor1 fs_or0=arrdiv8_fs27_or0
.subckt fs a=arrdiv8_mux2to117_xor0 b=b[4] bin=arrdiv8_fs27_or0 fs_xor1=arrdiv8_fs28_xor1 fs_or0=arrdiv8_fs28_or0
.subckt fs a=arrdiv8_mux2to118_xor0 b=b[5] bin=arrdiv8_fs28_or0 fs_xor1=arrdiv8_fs29_xor1 fs_or0=arrdiv8_fs29_or0
.subckt fs a=arrdiv8_mux2to119_xor0 b=b[6] bin=arrdiv8_fs29_or0 fs_xor1=arrdiv8_fs30_xor1 fs_or0=arrdiv8_fs30_or0
.subckt fs a=arrdiv8_mux2to120_xor0 b=b[7] bin=arrdiv8_fs30_or0 fs_xor1=arrdiv8_fs31_xor1 fs_or0=arrdiv8_fs31_or0
.subckt mux2to1 d0=arrdiv8_fs24_xor0 d1=a[4] sel=arrdiv8_fs31_or0 mux2to1_xor0=arrdiv8_mux2to121_xor0
.subckt mux2to1 d0=arrdiv8_fs25_xor1 d1=arrdiv8_mux2to114_xor0 sel=arrdiv8_fs31_or0 mux2to1_xor0=arrdiv8_mux2to122_xor0
.subckt mux2to1 d0=arrdiv8_fs26_xor1 d1=arrdiv8_mux2to115_xor0 sel=arrdiv8_fs31_or0 mux2to1_xor0=arrdiv8_mux2to123_xor0
.subckt mux2to1 d0=arrdiv8_fs27_xor1 d1=arrdiv8_mux2to116_xor0 sel=arrdiv8_fs31_or0 mux2to1_xor0=arrdiv8_mux2to124_xor0
.subckt mux2to1 d0=arrdiv8_fs28_xor1 d1=arrdiv8_mux2to117_xor0 sel=arrdiv8_fs31_or0 mux2to1_xor0=arrdiv8_mux2to125_xor0
.subckt mux2to1 d0=arrdiv8_fs29_xor1 d1=arrdiv8_mux2to118_xor0 sel=arrdiv8_fs31_or0 mux2to1_xor0=arrdiv8_mux2to126_xor0
.subckt mux2to1 d0=arrdiv8_fs30_xor1 d1=arrdiv8_mux2to119_xor0 sel=arrdiv8_fs31_or0 mux2to1_xor0=arrdiv8_mux2to127_xor0
.subckt not_gate a=arrdiv8_fs31_or0 out=arrdiv8_not3
.subckt fs a=a[3] b=b[0] bin=gnd fs_xor1=arrdiv8_fs32_xor0 fs_or0=arrdiv8_fs32_and0
.subckt fs a=arrdiv8_mux2to121_xor0 b=b[1] bin=arrdiv8_fs32_and0 fs_xor1=arrdiv8_fs33_xor1 fs_or0=arrdiv8_fs33_or0
.subckt fs a=arrdiv8_mux2to122_xor0 b=b[2] bin=arrdiv8_fs33_or0 fs_xor1=arrdiv8_fs34_xor1 fs_or0=arrdiv8_fs34_or0
.subckt fs a=arrdiv8_mux2to123_xor0 b=b[3] bin=arrdiv8_fs34_or0 fs_xor1=arrdiv8_fs35_xor1 fs_or0=arrdiv8_fs35_or0
.subckt fs a=arrdiv8_mux2to124_xor0 b=b[4] bin=arrdiv8_fs35_or0 fs_xor1=arrdiv8_fs36_xor1 fs_or0=arrdiv8_fs36_or0
.subckt fs a=arrdiv8_mux2to125_xor0 b=b[5] bin=arrdiv8_fs36_or0 fs_xor1=arrdiv8_fs37_xor1 fs_or0=arrdiv8_fs37_or0
.subckt fs a=arrdiv8_mux2to126_xor0 b=b[6] bin=arrdiv8_fs37_or0 fs_xor1=arrdiv8_fs38_xor1 fs_or0=arrdiv8_fs38_or0
.subckt fs a=arrdiv8_mux2to127_xor0 b=b[7] bin=arrdiv8_fs38_or0 fs_xor1=arrdiv8_fs39_xor1 fs_or0=arrdiv8_fs39_or0
.subckt mux2to1 d0=arrdiv8_fs32_xor0 d1=a[3] sel=arrdiv8_fs39_or0 mux2to1_xor0=arrdiv8_mux2to128_xor0
.subckt mux2to1 d0=arrdiv8_fs33_xor1 d1=arrdiv8_mux2to121_xor0 sel=arrdiv8_fs39_or0 mux2to1_xor0=arrdiv8_mux2to129_xor0
.subckt mux2to1 d0=arrdiv8_fs34_xor1 d1=arrdiv8_mux2to122_xor0 sel=arrdiv8_fs39_or0 mux2to1_xor0=arrdiv8_mux2to130_xor0
.subckt mux2to1 d0=arrdiv8_fs35_xor1 d1=arrdiv8_mux2to123_xor0 sel=arrdiv8_fs39_or0 mux2to1_xor0=arrdiv8_mux2to131_xor0
.subckt mux2to1 d0=arrdiv8_fs36_xor1 d1=arrdiv8_mux2to124_xor0 sel=arrdiv8_fs39_or0 mux2to1_xor0=arrdiv8_mux2to132_xor0
.subckt mux2to1 d0=arrdiv8_fs37_xor1 d1=arrdiv8_mux2to125_xor0 sel=arrdiv8_fs39_or0 mux2to1_xor0=arrdiv8_mux2to133_xor0
.subckt mux2to1 d0=arrdiv8_fs38_xor1 d1=arrdiv8_mux2to126_xor0 sel=arrdiv8_fs39_or0 mux2to1_xor0=arrdiv8_mux2to134_xor0
.subckt not_gate a=arrdiv8_fs39_or0 out=arrdiv8_not4
.subckt fs a=a[2] b=b[0] bin=gnd fs_xor1=arrdiv8_fs40_xor0 fs_or0=arrdiv8_fs40_and0
.subckt fs a=arrdiv8_mux2to128_xor0 b=b[1] bin=arrdiv8_fs40_and0 fs_xor1=arrdiv8_fs41_xor1 fs_or0=arrdiv8_fs41_or0
.subckt fs a=arrdiv8_mux2to129_xor0 b=b[2] bin=arrdiv8_fs41_or0 fs_xor1=arrdiv8_fs42_xor1 fs_or0=arrdiv8_fs42_or0
.subckt fs a=arrdiv8_mux2to130_xor0 b=b[3] bin=arrdiv8_fs42_or0 fs_xor1=arrdiv8_fs43_xor1 fs_or0=arrdiv8_fs43_or0
.subckt fs a=arrdiv8_mux2to131_xor0 b=b[4] bin=arrdiv8_fs43_or0 fs_xor1=arrdiv8_fs44_xor1 fs_or0=arrdiv8_fs44_or0
.subckt fs a=arrdiv8_mux2to132_xor0 b=b[5] bin=arrdiv8_fs44_or0 fs_xor1=arrdiv8_fs45_xor1 fs_or0=arrdiv8_fs45_or0
.subckt fs a=arrdiv8_mux2to133_xor0 b=b[6] bin=arrdiv8_fs45_or0 fs_xor1=arrdiv8_fs46_xor1 fs_or0=arrdiv8_fs46_or0
.subckt fs a=arrdiv8_mux2to134_xor0 b=b[7] bin=arrdiv8_fs46_or0 fs_xor1=arrdiv8_fs47_xor1 fs_or0=arrdiv8_fs47_or0
.subckt mux2to1 d0=arrdiv8_fs40_xor0 d1=a[2] sel=arrdiv8_fs47_or0 mux2to1_xor0=arrdiv8_mux2to135_xor0
.subckt mux2to1 d0=arrdiv8_fs41_xor1 d1=arrdiv8_mux2to128_xor0 sel=arrdiv8_fs47_or0 mux2to1_xor0=arrdiv8_mux2to136_xor0
.subckt mux2to1 d0=arrdiv8_fs42_xor1 d1=arrdiv8_mux2to129_xor0 sel=arrdiv8_fs47_or0 mux2to1_xor0=arrdiv8_mux2to137_xor0
.subckt mux2to1 d0=arrdiv8_fs43_xor1 d1=arrdiv8_mux2to130_xor0 sel=arrdiv8_fs47_or0 mux2to1_xor0=arrdiv8_mux2to138_xor0
.subckt mux2to1 d0=arrdiv8_fs44_xor1 d1=arrdiv8_mux2to131_xor0 sel=arrdiv8_fs47_or0 mux2to1_xor0=arrdiv8_mux2to139_xor0
.subckt mux2to1 d0=arrdiv8_fs45_xor1 d1=arrdiv8_mux2to132_xor0 sel=arrdiv8_fs47_or0 mux2to1_xor0=arrdiv8_mux2to140_xor0
.subckt mux2to1 d0=arrdiv8_fs46_xor1 d1=arrdiv8_mux2to133_xor0 sel=arrdiv8_fs47_or0 mux2to1_xor0=arrdiv8_mux2to141_xor0
.subckt not_gate a=arrdiv8_fs47_or0 out=arrdiv8_not5
.subckt fs a=a[1] b=b[0] bin=gnd fs_xor1=arrdiv8_fs48_xor0 fs_or0=arrdiv8_fs48_and0
.subckt fs a=arrdiv8_mux2to135_xor0 b=b[1] bin=arrdiv8_fs48_and0 fs_xor1=arrdiv8_fs49_xor1 fs_or0=arrdiv8_fs49_or0
.subckt fs a=arrdiv8_mux2to136_xor0 b=b[2] bin=arrdiv8_fs49_or0 fs_xor1=arrdiv8_fs50_xor1 fs_or0=arrdiv8_fs50_or0
.subckt fs a=arrdiv8_mux2to137_xor0 b=b[3] bin=arrdiv8_fs50_or0 fs_xor1=arrdiv8_fs51_xor1 fs_or0=arrdiv8_fs51_or0
.subckt fs a=arrdiv8_mux2to138_xor0 b=b[4] bin=arrdiv8_fs51_or0 fs_xor1=arrdiv8_fs52_xor1 fs_or0=arrdiv8_fs52_or0
.subckt fs a=arrdiv8_mux2to139_xor0 b=b[5] bin=arrdiv8_fs52_or0 fs_xor1=arrdiv8_fs53_xor1 fs_or0=arrdiv8_fs53_or0
.subckt fs a=arrdiv8_mux2to140_xor0 b=b[6] bin=arrdiv8_fs53_or0 fs_xor1=arrdiv8_fs54_xor1 fs_or0=arrdiv8_fs54_or0
.subckt fs a=arrdiv8_mux2to141_xor0 b=b[7] bin=arrdiv8_fs54_or0 fs_xor1=arrdiv8_fs55_xor1 fs_or0=arrdiv8_fs55_or0
.subckt mux2to1 d0=arrdiv8_fs48_xor0 d1=a[1] sel=arrdiv8_fs55_or0 mux2to1_xor0=arrdiv8_mux2to142_xor0
.subckt mux2to1 d0=arrdiv8_fs49_xor1 d1=arrdiv8_mux2to135_xor0 sel=arrdiv8_fs55_or0 mux2to1_xor0=arrdiv8_mux2to143_xor0
.subckt mux2to1 d0=arrdiv8_fs50_xor1 d1=arrdiv8_mux2to136_xor0 sel=arrdiv8_fs55_or0 mux2to1_xor0=arrdiv8_mux2to144_xor0
.subckt mux2to1 d0=arrdiv8_fs51_xor1 d1=arrdiv8_mux2to137_xor0 sel=arrdiv8_fs55_or0 mux2to1_xor0=arrdiv8_mux2to145_xor0
.subckt mux2to1 d0=arrdiv8_fs52_xor1 d1=arrdiv8_mux2to138_xor0 sel=arrdiv8_fs55_or0 mux2to1_xor0=arrdiv8_mux2to146_xor0
.subckt mux2to1 d0=arrdiv8_fs53_xor1 d1=arrdiv8_mux2to139_xor0 sel=arrdiv8_fs55_or0 mux2to1_xor0=arrdiv8_mux2to147_xor0
.subckt mux2to1 d0=arrdiv8_fs54_xor1 d1=arrdiv8_mux2to140_xor0 sel=arrdiv8_fs55_or0 mux2to1_xor0=arrdiv8_mux2to148_xor0
.subckt not_gate a=arrdiv8_fs55_or0 out=arrdiv8_not6
.subckt fs a=a[0] b=b[0] bin=gnd fs_xor1=arrdiv8_fs56_xor0 fs_or0=arrdiv8_fs56_and0
.subckt fs a=arrdiv8_mux2to142_xor0 b=b[1] bin=arrdiv8_fs56_and0 fs_xor1=arrdiv8_fs57_xor1 fs_or0=arrdiv8_fs57_or0
.subckt fs a=arrdiv8_mux2to143_xor0 b=b[2] bin=arrdiv8_fs57_or0 fs_xor1=arrdiv8_fs58_xor1 fs_or0=arrdiv8_fs58_or0
.subckt fs a=arrdiv8_mux2to144_xor0 b=b[3] bin=arrdiv8_fs58_or0 fs_xor1=arrdiv8_fs59_xor1 fs_or0=arrdiv8_fs59_or0
.subckt fs a=arrdiv8_mux2to145_xor0 b=b[4] bin=arrdiv8_fs59_or0 fs_xor1=arrdiv8_fs60_xor1 fs_or0=arrdiv8_fs60_or0
.subckt fs a=arrdiv8_mux2to146_xor0 b=b[5] bin=arrdiv8_fs60_or0 fs_xor1=arrdiv8_fs61_xor1 fs_or0=arrdiv8_fs61_or0
.subckt fs a=arrdiv8_mux2to147_xor0 b=b[6] bin=arrdiv8_fs61_or0 fs_xor1=arrdiv8_fs62_xor1 fs_or0=arrdiv8_fs62_or0
.subckt fs a=arrdiv8_mux2to148_xor0 b=b[7] bin=arrdiv8_fs62_or0 fs_xor1=arrdiv8_fs63_xor1 fs_or0=arrdiv8_fs63_or0
.subckt not_gate a=arrdiv8_fs63_or0 out=arrdiv8_not7
.names arrdiv8_not7 arrdiv8_out[0]
1 1
.names arrdiv8_not6 arrdiv8_out[1]
1 1
.names arrdiv8_not5 arrdiv8_out[2]
1 1
.names arrdiv8_not4 arrdiv8_out[3]
1 1
.names arrdiv8_not3 arrdiv8_out[4]
1 1
.names arrdiv8_not2 arrdiv8_out[5]
1 1
.names arrdiv8_not1 arrdiv8_out[6]
1 1
.names arrdiv8_not0 arrdiv8_out[7]
1 1
.end

.model mux2to1
.inputs d0 d1 sel
.outputs mux2to1_xor0
.names vdd
1
.names gnd
0
.subckt and_gate a=d1 b=sel out=mux2to1_and0
.subckt not_gate a=sel out=mux2to1_not0
.subckt and_gate a=d0 b=mux2to1_not0 out=mux2to1_and1
.subckt xor_gate a=mux2to1_and0 b=mux2to1_and1 out=mux2to1_xor0
.end

.model fs
.inputs a b bin
.outputs fs_xor1 fs_or0
.names vdd
1
.names gnd
0
.subckt xor_gate a=a b=b out=fs_xor0
.subckt not_gate a=a out=fs_not0
.subckt and_gate a=fs_not0 b=b out=fs_and0
.subckt xor_gate a=bin b=fs_xor0 out=fs_xor1
.subckt not_gate a=fs_xor0 out=fs_not1
.subckt and_gate a=fs_not1 b=bin out=fs_and1
.subckt or_gate a=fs_and1 b=fs_and0 out=fs_or0
.end

.model or_gate
.inputs a b
.outputs out
.names vdd
1
.names gnd
0
.names a b out
1- 1
-1 1
.end

.model and_gate
.inputs a b
.outputs out
.names vdd
1
.names gnd
0
.names a b out
11 1
.end

.model not_gate
.inputs a
.outputs out
.names vdd
1
.names gnd
0
.names a out
0 1
.end

.model xor_gate
.inputs a b
.outputs out
.names vdd
1
.names gnd
0
.names a b out
01 1
10 1
.end