ariths-gen/generated_circuits/blif_circuits/hierarchical/h_u_cla24.blif

.model h_u_cla24
.inputs a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] a[8] a[9] a[10] a[11] a[12] a[13] a[14] a[15] a[16] a[17] a[18] a[19] a[20] a[21] a[22] a[23] b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9] b[10] b[11] b[12] b[13] b[14] b[15] b[16] b[17] b[18] b[19] b[20] b[21] b[22] b[23]
.outputs h_u_cla24_out[0] h_u_cla24_out[1] h_u_cla24_out[2] h_u_cla24_out[3] h_u_cla24_out[4] h_u_cla24_out[5] h_u_cla24_out[6] h_u_cla24_out[7] h_u_cla24_out[8] h_u_cla24_out[9] h_u_cla24_out[10] h_u_cla24_out[11] h_u_cla24_out[12] h_u_cla24_out[13] h_u_cla24_out[14] h_u_cla24_out[15] h_u_cla24_out[16] h_u_cla24_out[17] h_u_cla24_out[18] h_u_cla24_out[19] h_u_cla24_out[20] h_u_cla24_out[21] h_u_cla24_out[22] h_u_cla24_out[23] h_u_cla24_out[24]
.names vdd
1
.names gnd
0
.subckt pg_logic a=a[0] b=b[0] pg_logic_or0=h_u_cla24_pg_logic0_or0 pg_logic_and0=h_u_cla24_pg_logic0_and0 pg_logic_xor0=h_u_cla24_pg_logic0_xor0
.subckt pg_logic a=a[1] b=b[1] pg_logic_or0=h_u_cla24_pg_logic1_or0 pg_logic_and0=h_u_cla24_pg_logic1_and0 pg_logic_xor0=h_u_cla24_pg_logic1_xor0
.subckt xor_gate a=h_u_cla24_pg_logic1_xor0 b=h_u_cla24_pg_logic0_and0 out=h_u_cla24_xor1
.subckt and_gate a=h_u_cla24_pg_logic0_and0 b=h_u_cla24_pg_logic1_or0 out=h_u_cla24_and0
.subckt or_gate a=h_u_cla24_pg_logic1_and0 b=h_u_cla24_and0 out=h_u_cla24_or0
.subckt pg_logic a=a[2] b=b[2] pg_logic_or0=h_u_cla24_pg_logic2_or0 pg_logic_and0=h_u_cla24_pg_logic2_and0 pg_logic_xor0=h_u_cla24_pg_logic2_xor0
.subckt xor_gate a=h_u_cla24_pg_logic2_xor0 b=h_u_cla24_or0 out=h_u_cla24_xor2
.subckt and_gate a=h_u_cla24_pg_logic2_or0 b=h_u_cla24_pg_logic0_or0 out=h_u_cla24_and1
.subckt and_gate a=h_u_cla24_pg_logic0_and0 b=h_u_cla24_pg_logic2_or0 out=h_u_cla24_and2
.subckt and_gate a=h_u_cla24_and2 b=h_u_cla24_pg_logic1_or0 out=h_u_cla24_and3
.subckt and_gate a=h_u_cla24_pg_logic1_and0 b=h_u_cla24_pg_logic2_or0 out=h_u_cla24_and4
.subckt or_gate a=h_u_cla24_and3 b=h_u_cla24_and4 out=h_u_cla24_or1
.subckt or_gate a=h_u_cla24_pg_logic2_and0 b=h_u_cla24_or1 out=h_u_cla24_or2
.subckt pg_logic a=a[3] b=b[3] pg_logic_or0=h_u_cla24_pg_logic3_or0 pg_logic_and0=h_u_cla24_pg_logic3_and0 pg_logic_xor0=h_u_cla24_pg_logic3_xor0
.subckt xor_gate a=h_u_cla24_pg_logic3_xor0 b=h_u_cla24_or2 out=h_u_cla24_xor3
.subckt and_gate a=h_u_cla24_pg_logic3_or0 b=h_u_cla24_pg_logic1_or0 out=h_u_cla24_and5
.subckt and_gate a=h_u_cla24_pg_logic0_and0 b=h_u_cla24_pg_logic2_or0 out=h_u_cla24_and6
.subckt and_gate a=h_u_cla24_pg_logic3_or0 b=h_u_cla24_pg_logic1_or0 out=h_u_cla24_and7
.subckt and_gate a=h_u_cla24_and6 b=h_u_cla24_and7 out=h_u_cla24_and8
.subckt and_gate a=h_u_cla24_pg_logic1_and0 b=h_u_cla24_pg_logic3_or0 out=h_u_cla24_and9
.subckt and_gate a=h_u_cla24_and9 b=h_u_cla24_pg_logic2_or0 out=h_u_cla24_and10
.subckt and_gate a=h_u_cla24_pg_logic2_and0 b=h_u_cla24_pg_logic3_or0 out=h_u_cla24_and11
.subckt or_gate a=h_u_cla24_and8 b=h_u_cla24_and11 out=h_u_cla24_or3
.subckt or_gate a=h_u_cla24_and10 b=h_u_cla24_or3 out=h_u_cla24_or4
.subckt or_gate a=h_u_cla24_pg_logic3_and0 b=h_u_cla24_or4 out=h_u_cla24_or5
.subckt pg_logic a=a[4] b=b[4] pg_logic_or0=h_u_cla24_pg_logic4_or0 pg_logic_and0=h_u_cla24_pg_logic4_and0 pg_logic_xor0=h_u_cla24_pg_logic4_xor0
.subckt xor_gate a=h_u_cla24_pg_logic4_xor0 b=h_u_cla24_or5 out=h_u_cla24_xor4
.subckt and_gate a=h_u_cla24_or5 b=h_u_cla24_pg_logic4_or0 out=h_u_cla24_and12
.subckt or_gate a=h_u_cla24_pg_logic4_and0 b=h_u_cla24_and12 out=h_u_cla24_or6
.subckt pg_logic a=a[5] b=b[5] pg_logic_or0=h_u_cla24_pg_logic5_or0 pg_logic_and0=h_u_cla24_pg_logic5_and0 pg_logic_xor0=h_u_cla24_pg_logic5_xor0
.subckt xor_gate a=h_u_cla24_pg_logic5_xor0 b=h_u_cla24_or6 out=h_u_cla24_xor5
.subckt and_gate a=h_u_cla24_or5 b=h_u_cla24_pg_logic5_or0 out=h_u_cla24_and13
.subckt and_gate a=h_u_cla24_and13 b=h_u_cla24_pg_logic4_or0 out=h_u_cla24_and14
.subckt and_gate a=h_u_cla24_pg_logic4_and0 b=h_u_cla24_pg_logic5_or0 out=h_u_cla24_and15
.subckt or_gate a=h_u_cla24_and14 b=h_u_cla24_and15 out=h_u_cla24_or7
.subckt or_gate a=h_u_cla24_pg_logic5_and0 b=h_u_cla24_or7 out=h_u_cla24_or8
.subckt pg_logic a=a[6] b=b[6] pg_logic_or0=h_u_cla24_pg_logic6_or0 pg_logic_and0=h_u_cla24_pg_logic6_and0 pg_logic_xor0=h_u_cla24_pg_logic6_xor0
.subckt xor_gate a=h_u_cla24_pg_logic6_xor0 b=h_u_cla24_or8 out=h_u_cla24_xor6
.subckt and_gate a=h_u_cla24_or5 b=h_u_cla24_pg_logic5_or0 out=h_u_cla24_and16
.subckt and_gate a=h_u_cla24_pg_logic6_or0 b=h_u_cla24_pg_logic4_or0 out=h_u_cla24_and17
.subckt and_gate a=h_u_cla24_and16 b=h_u_cla24_and17 out=h_u_cla24_and18
.subckt and_gate a=h_u_cla24_pg_logic4_and0 b=h_u_cla24_pg_logic6_or0 out=h_u_cla24_and19
.subckt and_gate a=h_u_cla24_and19 b=h_u_cla24_pg_logic5_or0 out=h_u_cla24_and20
.subckt and_gate a=h_u_cla24_pg_logic5_and0 b=h_u_cla24_pg_logic6_or0 out=h_u_cla24_and21
.subckt or_gate a=h_u_cla24_and18 b=h_u_cla24_and20 out=h_u_cla24_or9
.subckt or_gate a=h_u_cla24_or9 b=h_u_cla24_and21 out=h_u_cla24_or10
.subckt or_gate a=h_u_cla24_pg_logic6_and0 b=h_u_cla24_or10 out=h_u_cla24_or11
.subckt pg_logic a=a[7] b=b[7] pg_logic_or0=h_u_cla24_pg_logic7_or0 pg_logic_and0=h_u_cla24_pg_logic7_and0 pg_logic_xor0=h_u_cla24_pg_logic7_xor0
.subckt xor_gate a=h_u_cla24_pg_logic7_xor0 b=h_u_cla24_or11 out=h_u_cla24_xor7
.subckt and_gate a=h_u_cla24_or5 b=h_u_cla24_pg_logic6_or0 out=h_u_cla24_and22
.subckt and_gate a=h_u_cla24_pg_logic7_or0 b=h_u_cla24_pg_logic5_or0 out=h_u_cla24_and23
.subckt and_gate a=h_u_cla24_and22 b=h_u_cla24_and23 out=h_u_cla24_and24
.subckt and_gate a=h_u_cla24_and24 b=h_u_cla24_pg_logic4_or0 out=h_u_cla24_and25
.subckt and_gate a=h_u_cla24_pg_logic4_and0 b=h_u_cla24_pg_logic6_or0 out=h_u_cla24_and26
.subckt and_gate a=h_u_cla24_pg_logic7_or0 b=h_u_cla24_pg_logic5_or0 out=h_u_cla24_and27
.subckt and_gate a=h_u_cla24_and26 b=h_u_cla24_and27 out=h_u_cla24_and28
.subckt and_gate a=h_u_cla24_pg_logic5_and0 b=h_u_cla24_pg_logic7_or0 out=h_u_cla24_and29
.subckt and_gate a=h_u_cla24_and29 b=h_u_cla24_pg_logic6_or0 out=h_u_cla24_and30
.subckt and_gate a=h_u_cla24_pg_logic6_and0 b=h_u_cla24_pg_logic7_or0 out=h_u_cla24_and31
.subckt or_gate a=h_u_cla24_and25 b=h_u_cla24_and30 out=h_u_cla24_or12
.subckt or_gate a=h_u_cla24_and28 b=h_u_cla24_and31 out=h_u_cla24_or13
.subckt or_gate a=h_u_cla24_or12 b=h_u_cla24_or13 out=h_u_cla24_or14
.subckt or_gate a=h_u_cla24_pg_logic7_and0 b=h_u_cla24_or14 out=h_u_cla24_or15
.subckt pg_logic a=a[8] b=b[8] pg_logic_or0=h_u_cla24_pg_logic8_or0 pg_logic_and0=h_u_cla24_pg_logic8_and0 pg_logic_xor0=h_u_cla24_pg_logic8_xor0
.subckt xor_gate a=h_u_cla24_pg_logic8_xor0 b=h_u_cla24_or15 out=h_u_cla24_xor8
.subckt and_gate a=h_u_cla24_or15 b=h_u_cla24_pg_logic8_or0 out=h_u_cla24_and32
.subckt or_gate a=h_u_cla24_pg_logic8_and0 b=h_u_cla24_and32 out=h_u_cla24_or16
.subckt pg_logic a=a[9] b=b[9] pg_logic_or0=h_u_cla24_pg_logic9_or0 pg_logic_and0=h_u_cla24_pg_logic9_and0 pg_logic_xor0=h_u_cla24_pg_logic9_xor0
.subckt xor_gate a=h_u_cla24_pg_logic9_xor0 b=h_u_cla24_or16 out=h_u_cla24_xor9
.subckt and_gate a=h_u_cla24_or15 b=h_u_cla24_pg_logic9_or0 out=h_u_cla24_and33
.subckt and_gate a=h_u_cla24_and33 b=h_u_cla24_pg_logic8_or0 out=h_u_cla24_and34
.subckt and_gate a=h_u_cla24_pg_logic8_and0 b=h_u_cla24_pg_logic9_or0 out=h_u_cla24_and35
.subckt or_gate a=h_u_cla24_and34 b=h_u_cla24_and35 out=h_u_cla24_or17
.subckt or_gate a=h_u_cla24_pg_logic9_and0 b=h_u_cla24_or17 out=h_u_cla24_or18
.subckt pg_logic a=a[10] b=b[10] pg_logic_or0=h_u_cla24_pg_logic10_or0 pg_logic_and0=h_u_cla24_pg_logic10_and0 pg_logic_xor0=h_u_cla24_pg_logic10_xor0
.subckt xor_gate a=h_u_cla24_pg_logic10_xor0 b=h_u_cla24_or18 out=h_u_cla24_xor10
.subckt and_gate a=h_u_cla24_or15 b=h_u_cla24_pg_logic9_or0 out=h_u_cla24_and36
.subckt and_gate a=h_u_cla24_pg_logic10_or0 b=h_u_cla24_pg_logic8_or0 out=h_u_cla24_and37
.subckt and_gate a=h_u_cla24_and36 b=h_u_cla24_and37 out=h_u_cla24_and38
.subckt and_gate a=h_u_cla24_pg_logic8_and0 b=h_u_cla24_pg_logic10_or0 out=h_u_cla24_and39
.subckt and_gate a=h_u_cla24_and39 b=h_u_cla24_pg_logic9_or0 out=h_u_cla24_and40
.subckt and_gate a=h_u_cla24_pg_logic9_and0 b=h_u_cla24_pg_logic10_or0 out=h_u_cla24_and41
.subckt or_gate a=h_u_cla24_and38 b=h_u_cla24_and40 out=h_u_cla24_or19
.subckt or_gate a=h_u_cla24_or19 b=h_u_cla24_and41 out=h_u_cla24_or20
.subckt or_gate a=h_u_cla24_pg_logic10_and0 b=h_u_cla24_or20 out=h_u_cla24_or21
.subckt pg_logic a=a[11] b=b[11] pg_logic_or0=h_u_cla24_pg_logic11_or0 pg_logic_and0=h_u_cla24_pg_logic11_and0 pg_logic_xor0=h_u_cla24_pg_logic11_xor0
.subckt xor_gate a=h_u_cla24_pg_logic11_xor0 b=h_u_cla24_or21 out=h_u_cla24_xor11
.subckt and_gate a=h_u_cla24_or15 b=h_u_cla24_pg_logic10_or0 out=h_u_cla24_and42
.subckt and_gate a=h_u_cla24_pg_logic11_or0 b=h_u_cla24_pg_logic9_or0 out=h_u_cla24_and43
.subckt and_gate a=h_u_cla24_and42 b=h_u_cla24_and43 out=h_u_cla24_and44
.subckt and_gate a=h_u_cla24_and44 b=h_u_cla24_pg_logic8_or0 out=h_u_cla24_and45
.subckt and_gate a=h_u_cla24_pg_logic8_and0 b=h_u_cla24_pg_logic10_or0 out=h_u_cla24_and46
.subckt and_gate a=h_u_cla24_pg_logic11_or0 b=h_u_cla24_pg_logic9_or0 out=h_u_cla24_and47
.subckt and_gate a=h_u_cla24_and46 b=h_u_cla24_and47 out=h_u_cla24_and48
.subckt and_gate a=h_u_cla24_pg_logic9_and0 b=h_u_cla24_pg_logic11_or0 out=h_u_cla24_and49
.subckt and_gate a=h_u_cla24_and49 b=h_u_cla24_pg_logic10_or0 out=h_u_cla24_and50
.subckt and_gate a=h_u_cla24_pg_logic10_and0 b=h_u_cla24_pg_logic11_or0 out=h_u_cla24_and51
.subckt or_gate a=h_u_cla24_and45 b=h_u_cla24_and50 out=h_u_cla24_or22
.subckt or_gate a=h_u_cla24_and48 b=h_u_cla24_and51 out=h_u_cla24_or23
.subckt or_gate a=h_u_cla24_or22 b=h_u_cla24_or23 out=h_u_cla24_or24
.subckt or_gate a=h_u_cla24_pg_logic11_and0 b=h_u_cla24_or24 out=h_u_cla24_or25
.subckt pg_logic a=a[12] b=b[12] pg_logic_or0=h_u_cla24_pg_logic12_or0 pg_logic_and0=h_u_cla24_pg_logic12_and0 pg_logic_xor0=h_u_cla24_pg_logic12_xor0
.subckt xor_gate a=h_u_cla24_pg_logic12_xor0 b=h_u_cla24_or25 out=h_u_cla24_xor12
.subckt and_gate a=h_u_cla24_or25 b=h_u_cla24_pg_logic12_or0 out=h_u_cla24_and52
.subckt or_gate a=h_u_cla24_pg_logic12_and0 b=h_u_cla24_and52 out=h_u_cla24_or26
.subckt pg_logic a=a[13] b=b[13] pg_logic_or0=h_u_cla24_pg_logic13_or0 pg_logic_and0=h_u_cla24_pg_logic13_and0 pg_logic_xor0=h_u_cla24_pg_logic13_xor0
.subckt xor_gate a=h_u_cla24_pg_logic13_xor0 b=h_u_cla24_or26 out=h_u_cla24_xor13
.subckt and_gate a=h_u_cla24_or25 b=h_u_cla24_pg_logic13_or0 out=h_u_cla24_and53
.subckt and_gate a=h_u_cla24_and53 b=h_u_cla24_pg_logic12_or0 out=h_u_cla24_and54
.subckt and_gate a=h_u_cla24_pg_logic12_and0 b=h_u_cla24_pg_logic13_or0 out=h_u_cla24_and55
.subckt or_gate a=h_u_cla24_and54 b=h_u_cla24_and55 out=h_u_cla24_or27
.subckt or_gate a=h_u_cla24_pg_logic13_and0 b=h_u_cla24_or27 out=h_u_cla24_or28
.subckt pg_logic a=a[14] b=b[14] pg_logic_or0=h_u_cla24_pg_logic14_or0 pg_logic_and0=h_u_cla24_pg_logic14_and0 pg_logic_xor0=h_u_cla24_pg_logic14_xor0
.subckt xor_gate a=h_u_cla24_pg_logic14_xor0 b=h_u_cla24_or28 out=h_u_cla24_xor14
.subckt and_gate a=h_u_cla24_or25 b=h_u_cla24_pg_logic13_or0 out=h_u_cla24_and56
.subckt and_gate a=h_u_cla24_pg_logic14_or0 b=h_u_cla24_pg_logic12_or0 out=h_u_cla24_and57
.subckt and_gate a=h_u_cla24_and56 b=h_u_cla24_and57 out=h_u_cla24_and58
.subckt and_gate a=h_u_cla24_pg_logic12_and0 b=h_u_cla24_pg_logic14_or0 out=h_u_cla24_and59
.subckt and_gate a=h_u_cla24_and59 b=h_u_cla24_pg_logic13_or0 out=h_u_cla24_and60
.subckt and_gate a=h_u_cla24_pg_logic13_and0 b=h_u_cla24_pg_logic14_or0 out=h_u_cla24_and61
.subckt or_gate a=h_u_cla24_and58 b=h_u_cla24_and60 out=h_u_cla24_or29
.subckt or_gate a=h_u_cla24_or29 b=h_u_cla24_and61 out=h_u_cla24_or30
.subckt or_gate a=h_u_cla24_pg_logic14_and0 b=h_u_cla24_or30 out=h_u_cla24_or31
.subckt pg_logic a=a[15] b=b[15] pg_logic_or0=h_u_cla24_pg_logic15_or0 pg_logic_and0=h_u_cla24_pg_logic15_and0 pg_logic_xor0=h_u_cla24_pg_logic15_xor0
.subckt xor_gate a=h_u_cla24_pg_logic15_xor0 b=h_u_cla24_or31 out=h_u_cla24_xor15
.subckt and_gate a=h_u_cla24_or25 b=h_u_cla24_pg_logic14_or0 out=h_u_cla24_and62
.subckt and_gate a=h_u_cla24_pg_logic15_or0 b=h_u_cla24_pg_logic13_or0 out=h_u_cla24_and63
.subckt and_gate a=h_u_cla24_and62 b=h_u_cla24_and63 out=h_u_cla24_and64
.subckt and_gate a=h_u_cla24_and64 b=h_u_cla24_pg_logic12_or0 out=h_u_cla24_and65
.subckt and_gate a=h_u_cla24_pg_logic12_and0 b=h_u_cla24_pg_logic14_or0 out=h_u_cla24_and66
.subckt and_gate a=h_u_cla24_pg_logic15_or0 b=h_u_cla24_pg_logic13_or0 out=h_u_cla24_and67
.subckt and_gate a=h_u_cla24_and66 b=h_u_cla24_and67 out=h_u_cla24_and68
.subckt and_gate a=h_u_cla24_pg_logic13_and0 b=h_u_cla24_pg_logic15_or0 out=h_u_cla24_and69
.subckt and_gate a=h_u_cla24_and69 b=h_u_cla24_pg_logic14_or0 out=h_u_cla24_and70
.subckt and_gate a=h_u_cla24_pg_logic14_and0 b=h_u_cla24_pg_logic15_or0 out=h_u_cla24_and71
.subckt or_gate a=h_u_cla24_and65 b=h_u_cla24_and70 out=h_u_cla24_or32
.subckt or_gate a=h_u_cla24_and68 b=h_u_cla24_and71 out=h_u_cla24_or33
.subckt or_gate a=h_u_cla24_or32 b=h_u_cla24_or33 out=h_u_cla24_or34
.subckt or_gate a=h_u_cla24_pg_logic15_and0 b=h_u_cla24_or34 out=h_u_cla24_or35
.subckt pg_logic a=a[16] b=b[16] pg_logic_or0=h_u_cla24_pg_logic16_or0 pg_logic_and0=h_u_cla24_pg_logic16_and0 pg_logic_xor0=h_u_cla24_pg_logic16_xor0
.subckt xor_gate a=h_u_cla24_pg_logic16_xor0 b=h_u_cla24_or35 out=h_u_cla24_xor16
.subckt and_gate a=h_u_cla24_or35 b=h_u_cla24_pg_logic16_or0 out=h_u_cla24_and72
.subckt or_gate a=h_u_cla24_pg_logic16_and0 b=h_u_cla24_and72 out=h_u_cla24_or36
.subckt pg_logic a=a[17] b=b[17] pg_logic_or0=h_u_cla24_pg_logic17_or0 pg_logic_and0=h_u_cla24_pg_logic17_and0 pg_logic_xor0=h_u_cla24_pg_logic17_xor0
.subckt xor_gate a=h_u_cla24_pg_logic17_xor0 b=h_u_cla24_or36 out=h_u_cla24_xor17
.subckt and_gate a=h_u_cla24_or35 b=h_u_cla24_pg_logic17_or0 out=h_u_cla24_and73
.subckt and_gate a=h_u_cla24_and73 b=h_u_cla24_pg_logic16_or0 out=h_u_cla24_and74
.subckt and_gate a=h_u_cla24_pg_logic16_and0 b=h_u_cla24_pg_logic17_or0 out=h_u_cla24_and75
.subckt or_gate a=h_u_cla24_and74 b=h_u_cla24_and75 out=h_u_cla24_or37
.subckt or_gate a=h_u_cla24_pg_logic17_and0 b=h_u_cla24_or37 out=h_u_cla24_or38
.subckt pg_logic a=a[18] b=b[18] pg_logic_or0=h_u_cla24_pg_logic18_or0 pg_logic_and0=h_u_cla24_pg_logic18_and0 pg_logic_xor0=h_u_cla24_pg_logic18_xor0
.subckt xor_gate a=h_u_cla24_pg_logic18_xor0 b=h_u_cla24_or38 out=h_u_cla24_xor18
.subckt and_gate a=h_u_cla24_or35 b=h_u_cla24_pg_logic17_or0 out=h_u_cla24_and76
.subckt and_gate a=h_u_cla24_pg_logic18_or0 b=h_u_cla24_pg_logic16_or0 out=h_u_cla24_and77
.subckt and_gate a=h_u_cla24_and76 b=h_u_cla24_and77 out=h_u_cla24_and78
.subckt and_gate a=h_u_cla24_pg_logic16_and0 b=h_u_cla24_pg_logic18_or0 out=h_u_cla24_and79
.subckt and_gate a=h_u_cla24_and79 b=h_u_cla24_pg_logic17_or0 out=h_u_cla24_and80
.subckt and_gate a=h_u_cla24_pg_logic17_and0 b=h_u_cla24_pg_logic18_or0 out=h_u_cla24_and81
.subckt or_gate a=h_u_cla24_and78 b=h_u_cla24_and80 out=h_u_cla24_or39
.subckt or_gate a=h_u_cla24_or39 b=h_u_cla24_and81 out=h_u_cla24_or40
.subckt or_gate a=h_u_cla24_pg_logic18_and0 b=h_u_cla24_or40 out=h_u_cla24_or41
.subckt pg_logic a=a[19] b=b[19] pg_logic_or0=h_u_cla24_pg_logic19_or0 pg_logic_and0=h_u_cla24_pg_logic19_and0 pg_logic_xor0=h_u_cla24_pg_logic19_xor0
.subckt xor_gate a=h_u_cla24_pg_logic19_xor0 b=h_u_cla24_or41 out=h_u_cla24_xor19
.subckt and_gate a=h_u_cla24_or35 b=h_u_cla24_pg_logic18_or0 out=h_u_cla24_and82
.subckt and_gate a=h_u_cla24_pg_logic19_or0 b=h_u_cla24_pg_logic17_or0 out=h_u_cla24_and83
.subckt and_gate a=h_u_cla24_and82 b=h_u_cla24_and83 out=h_u_cla24_and84
.subckt and_gate a=h_u_cla24_and84 b=h_u_cla24_pg_logic16_or0 out=h_u_cla24_and85
.subckt and_gate a=h_u_cla24_pg_logic16_and0 b=h_u_cla24_pg_logic18_or0 out=h_u_cla24_and86
.subckt and_gate a=h_u_cla24_pg_logic19_or0 b=h_u_cla24_pg_logic17_or0 out=h_u_cla24_and87
.subckt and_gate a=h_u_cla24_and86 b=h_u_cla24_and87 out=h_u_cla24_and88
.subckt and_gate a=h_u_cla24_pg_logic17_and0 b=h_u_cla24_pg_logic19_or0 out=h_u_cla24_and89
.subckt and_gate a=h_u_cla24_and89 b=h_u_cla24_pg_logic18_or0 out=h_u_cla24_and90
.subckt and_gate a=h_u_cla24_pg_logic18_and0 b=h_u_cla24_pg_logic19_or0 out=h_u_cla24_and91
.subckt or_gate a=h_u_cla24_and85 b=h_u_cla24_and90 out=h_u_cla24_or42
.subckt or_gate a=h_u_cla24_and88 b=h_u_cla24_and91 out=h_u_cla24_or43
.subckt or_gate a=h_u_cla24_or42 b=h_u_cla24_or43 out=h_u_cla24_or44
.subckt or_gate a=h_u_cla24_pg_logic19_and0 b=h_u_cla24_or44 out=h_u_cla24_or45
.subckt pg_logic a=a[20] b=b[20] pg_logic_or0=h_u_cla24_pg_logic20_or0 pg_logic_and0=h_u_cla24_pg_logic20_and0 pg_logic_xor0=h_u_cla24_pg_logic20_xor0
.subckt xor_gate a=h_u_cla24_pg_logic20_xor0 b=h_u_cla24_or45 out=h_u_cla24_xor20
.subckt and_gate a=h_u_cla24_or45 b=h_u_cla24_pg_logic20_or0 out=h_u_cla24_and92
.subckt or_gate a=h_u_cla24_pg_logic20_and0 b=h_u_cla24_and92 out=h_u_cla24_or46
.subckt pg_logic a=a[21] b=b[21] pg_logic_or0=h_u_cla24_pg_logic21_or0 pg_logic_and0=h_u_cla24_pg_logic21_and0 pg_logic_xor0=h_u_cla24_pg_logic21_xor0
.subckt xor_gate a=h_u_cla24_pg_logic21_xor0 b=h_u_cla24_or46 out=h_u_cla24_xor21
.subckt and_gate a=h_u_cla24_or45 b=h_u_cla24_pg_logic21_or0 out=h_u_cla24_and93
.subckt and_gate a=h_u_cla24_and93 b=h_u_cla24_pg_logic20_or0 out=h_u_cla24_and94
.subckt and_gate a=h_u_cla24_pg_logic20_and0 b=h_u_cla24_pg_logic21_or0 out=h_u_cla24_and95
.subckt or_gate a=h_u_cla24_and94 b=h_u_cla24_and95 out=h_u_cla24_or47
.subckt or_gate a=h_u_cla24_pg_logic21_and0 b=h_u_cla24_or47 out=h_u_cla24_or48
.subckt pg_logic a=a[22] b=b[22] pg_logic_or0=h_u_cla24_pg_logic22_or0 pg_logic_and0=h_u_cla24_pg_logic22_and0 pg_logic_xor0=h_u_cla24_pg_logic22_xor0
.subckt xor_gate a=h_u_cla24_pg_logic22_xor0 b=h_u_cla24_or48 out=h_u_cla24_xor22
.subckt and_gate a=h_u_cla24_or45 b=h_u_cla24_pg_logic21_or0 out=h_u_cla24_and96
.subckt and_gate a=h_u_cla24_pg_logic22_or0 b=h_u_cla24_pg_logic20_or0 out=h_u_cla24_and97
.subckt and_gate a=h_u_cla24_and96 b=h_u_cla24_and97 out=h_u_cla24_and98
.subckt and_gate a=h_u_cla24_pg_logic20_and0 b=h_u_cla24_pg_logic22_or0 out=h_u_cla24_and99
.subckt and_gate a=h_u_cla24_and99 b=h_u_cla24_pg_logic21_or0 out=h_u_cla24_and100
.subckt and_gate a=h_u_cla24_pg_logic21_and0 b=h_u_cla24_pg_logic22_or0 out=h_u_cla24_and101
.subckt or_gate a=h_u_cla24_and98 b=h_u_cla24_and100 out=h_u_cla24_or49
.subckt or_gate a=h_u_cla24_or49 b=h_u_cla24_and101 out=h_u_cla24_or50
.subckt or_gate a=h_u_cla24_pg_logic22_and0 b=h_u_cla24_or50 out=h_u_cla24_or51
.subckt pg_logic a=a[23] b=b[23] pg_logic_or0=h_u_cla24_pg_logic23_or0 pg_logic_and0=h_u_cla24_pg_logic23_and0 pg_logic_xor0=h_u_cla24_pg_logic23_xor0
.subckt xor_gate a=h_u_cla24_pg_logic23_xor0 b=h_u_cla24_or51 out=h_u_cla24_xor23
.subckt and_gate a=h_u_cla24_or45 b=h_u_cla24_pg_logic22_or0 out=h_u_cla24_and102
.subckt and_gate a=h_u_cla24_pg_logic23_or0 b=h_u_cla24_pg_logic21_or0 out=h_u_cla24_and103
.subckt and_gate a=h_u_cla24_and102 b=h_u_cla24_and103 out=h_u_cla24_and104
.subckt and_gate a=h_u_cla24_and104 b=h_u_cla24_pg_logic20_or0 out=h_u_cla24_and105
.subckt and_gate a=h_u_cla24_pg_logic20_and0 b=h_u_cla24_pg_logic22_or0 out=h_u_cla24_and106
.subckt and_gate a=h_u_cla24_pg_logic23_or0 b=h_u_cla24_pg_logic21_or0 out=h_u_cla24_and107
.subckt and_gate a=h_u_cla24_and106 b=h_u_cla24_and107 out=h_u_cla24_and108
.subckt and_gate a=h_u_cla24_pg_logic21_and0 b=h_u_cla24_pg_logic23_or0 out=h_u_cla24_and109
.subckt and_gate a=h_u_cla24_and109 b=h_u_cla24_pg_logic22_or0 out=h_u_cla24_and110
.subckt and_gate a=h_u_cla24_pg_logic22_and0 b=h_u_cla24_pg_logic23_or0 out=h_u_cla24_and111
.subckt or_gate a=h_u_cla24_and105 b=h_u_cla24_and110 out=h_u_cla24_or52
.subckt or_gate a=h_u_cla24_and108 b=h_u_cla24_and111 out=h_u_cla24_or53
.subckt or_gate a=h_u_cla24_or52 b=h_u_cla24_or53 out=h_u_cla24_or54
.subckt or_gate a=h_u_cla24_pg_logic23_and0 b=h_u_cla24_or54 out=h_u_cla24_or55
.names h_u_cla24_pg_logic0_xor0 h_u_cla24_out[0]
1 1
.names h_u_cla24_xor1 h_u_cla24_out[1]
1 1
.names h_u_cla24_xor2 h_u_cla24_out[2]
1 1
.names h_u_cla24_xor3 h_u_cla24_out[3]
1 1
.names h_u_cla24_xor4 h_u_cla24_out[4]
1 1
.names h_u_cla24_xor5 h_u_cla24_out[5]
1 1
.names h_u_cla24_xor6 h_u_cla24_out[6]
1 1
.names h_u_cla24_xor7 h_u_cla24_out[7]
1 1
.names h_u_cla24_xor8 h_u_cla24_out[8]
1 1
.names h_u_cla24_xor9 h_u_cla24_out[9]
1 1
.names h_u_cla24_xor10 h_u_cla24_out[10]
1 1
.names h_u_cla24_xor11 h_u_cla24_out[11]
1 1
.names h_u_cla24_xor12 h_u_cla24_out[12]
1 1
.names h_u_cla24_xor13 h_u_cla24_out[13]
1 1
.names h_u_cla24_xor14 h_u_cla24_out[14]
1 1
.names h_u_cla24_xor15 h_u_cla24_out[15]
1 1
.names h_u_cla24_xor16 h_u_cla24_out[16]
1 1
.names h_u_cla24_xor17 h_u_cla24_out[17]
1 1
.names h_u_cla24_xor18 h_u_cla24_out[18]
1 1
.names h_u_cla24_xor19 h_u_cla24_out[19]
1 1
.names h_u_cla24_xor20 h_u_cla24_out[20]
1 1
.names h_u_cla24_xor21 h_u_cla24_out[21]
1 1
.names h_u_cla24_xor22 h_u_cla24_out[22]
1 1
.names h_u_cla24_xor23 h_u_cla24_out[23]
1 1
.names h_u_cla24_or55 h_u_cla24_out[24]
1 1
.end

.model pg_logic
.inputs a b
.outputs pg_logic_or0 pg_logic_and0 pg_logic_xor0
.names vdd
1
.names gnd
0
.subckt or_gate a=a b=b out=pg_logic_or0
.subckt and_gate a=a b=b out=pg_logic_and0
.subckt xor_gate a=a b=b out=pg_logic_xor0
.end

.model xor_gate
.inputs a b
.outputs out
.names vdd
1
.names gnd
0
.names a b out
01 1
10 1
.end

.model and_gate
.inputs a b
.outputs out
.names vdd
1
.names gnd
0
.names a b out
11 1
.end

.model or_gate
.inputs a b
.outputs out
.names vdd
1
.names gnd
0
.names a b out
1- 1
-1 1
.end