ariths-gen/generated_circuits/blif_circuits/flat/f_u_cla12.blif

.model f_u_cla12
.inputs a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] a[8] a[9] a[10] a[11] b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9] b[10] b[11]
.outputs f_u_cla12_out[0] f_u_cla12_out[1] f_u_cla12_out[2] f_u_cla12_out[3] f_u_cla12_out[4] f_u_cla12_out[5] f_u_cla12_out[6] f_u_cla12_out[7] f_u_cla12_out[8] f_u_cla12_out[9] f_u_cla12_out[10] f_u_cla12_out[11] f_u_cla12_out[12]
.names vdd
1
.names gnd
0
.names a[0] b[0] f_u_cla12_pg_logic0_or0
1- 1
-1 1
.names a[0] b[0] f_u_cla12_pg_logic0_and0
11 1
.names a[0] b[0] f_u_cla12_pg_logic0_xor0
01 1
10 1
.names a[1] b[1] f_u_cla12_pg_logic1_or0
1- 1
-1 1
.names a[1] b[1] f_u_cla12_pg_logic1_and0
11 1
.names a[1] b[1] f_u_cla12_pg_logic1_xor0
01 1
10 1
.names f_u_cla12_pg_logic1_xor0 f_u_cla12_pg_logic0_and0 f_u_cla12_xor1
01 1
10 1
.names f_u_cla12_pg_logic0_and0 f_u_cla12_pg_logic1_or0 f_u_cla12_and0
11 1
.names f_u_cla12_pg_logic1_and0 f_u_cla12_and0 f_u_cla12_or0
1- 1
-1 1
.names a[2] b[2] f_u_cla12_pg_logic2_or0
1- 1
-1 1
.names a[2] b[2] f_u_cla12_pg_logic2_and0
11 1
.names a[2] b[2] f_u_cla12_pg_logic2_xor0
01 1
10 1
.names f_u_cla12_pg_logic2_xor0 f_u_cla12_or0 f_u_cla12_xor2
01 1
10 1
.names f_u_cla12_pg_logic2_or0 f_u_cla12_pg_logic0_or0 f_u_cla12_and1
11 1
.names f_u_cla12_pg_logic0_and0 f_u_cla12_pg_logic2_or0 f_u_cla12_and2
11 1
.names f_u_cla12_and2 f_u_cla12_pg_logic1_or0 f_u_cla12_and3
11 1
.names f_u_cla12_pg_logic1_and0 f_u_cla12_pg_logic2_or0 f_u_cla12_and4
11 1
.names f_u_cla12_and3 f_u_cla12_and4 f_u_cla12_or1
1- 1
-1 1
.names f_u_cla12_pg_logic2_and0 f_u_cla12_or1 f_u_cla12_or2
1- 1
-1 1
.names a[3] b[3] f_u_cla12_pg_logic3_or0
1- 1
-1 1
.names a[3] b[3] f_u_cla12_pg_logic3_and0
11 1
.names a[3] b[3] f_u_cla12_pg_logic3_xor0
01 1
10 1
.names f_u_cla12_pg_logic3_xor0 f_u_cla12_or2 f_u_cla12_xor3
01 1
10 1
.names f_u_cla12_pg_logic3_or0 f_u_cla12_pg_logic1_or0 f_u_cla12_and5
11 1
.names f_u_cla12_pg_logic0_and0 f_u_cla12_pg_logic2_or0 f_u_cla12_and6
11 1
.names f_u_cla12_pg_logic3_or0 f_u_cla12_pg_logic1_or0 f_u_cla12_and7
11 1
.names f_u_cla12_and6 f_u_cla12_and7 f_u_cla12_and8
11 1
.names f_u_cla12_pg_logic1_and0 f_u_cla12_pg_logic3_or0 f_u_cla12_and9
11 1
.names f_u_cla12_and9 f_u_cla12_pg_logic2_or0 f_u_cla12_and10
11 1
.names f_u_cla12_pg_logic2_and0 f_u_cla12_pg_logic3_or0 f_u_cla12_and11
11 1
.names f_u_cla12_and8 f_u_cla12_and11 f_u_cla12_or3
1- 1
-1 1
.names f_u_cla12_and10 f_u_cla12_or3 f_u_cla12_or4
1- 1
-1 1
.names f_u_cla12_pg_logic3_and0 f_u_cla12_or4 f_u_cla12_or5
1- 1
-1 1
.names a[4] b[4] f_u_cla12_pg_logic4_or0
1- 1
-1 1
.names a[4] b[4] f_u_cla12_pg_logic4_and0
11 1
.names a[4] b[4] f_u_cla12_pg_logic4_xor0
01 1
10 1
.names f_u_cla12_pg_logic4_xor0 f_u_cla12_or5 f_u_cla12_xor4
01 1
10 1
.names f_u_cla12_or5 f_u_cla12_pg_logic4_or0 f_u_cla12_and12
11 1
.names f_u_cla12_pg_logic4_and0 f_u_cla12_and12 f_u_cla12_or6
1- 1
-1 1
.names a[5] b[5] f_u_cla12_pg_logic5_or0
1- 1
-1 1
.names a[5] b[5] f_u_cla12_pg_logic5_and0
11 1
.names a[5] b[5] f_u_cla12_pg_logic5_xor0
01 1
10 1
.names f_u_cla12_pg_logic5_xor0 f_u_cla12_or6 f_u_cla12_xor5
01 1
10 1
.names f_u_cla12_or5 f_u_cla12_pg_logic5_or0 f_u_cla12_and13
11 1
.names f_u_cla12_and13 f_u_cla12_pg_logic4_or0 f_u_cla12_and14
11 1
.names f_u_cla12_pg_logic4_and0 f_u_cla12_pg_logic5_or0 f_u_cla12_and15
11 1
.names f_u_cla12_and14 f_u_cla12_and15 f_u_cla12_or7
1- 1
-1 1
.names f_u_cla12_pg_logic5_and0 f_u_cla12_or7 f_u_cla12_or8
1- 1
-1 1
.names a[6] b[6] f_u_cla12_pg_logic6_or0
1- 1
-1 1
.names a[6] b[6] f_u_cla12_pg_logic6_and0
11 1
.names a[6] b[6] f_u_cla12_pg_logic6_xor0
01 1
10 1
.names f_u_cla12_pg_logic6_xor0 f_u_cla12_or8 f_u_cla12_xor6
01 1
10 1
.names f_u_cla12_or5 f_u_cla12_pg_logic5_or0 f_u_cla12_and16
11 1
.names f_u_cla12_pg_logic6_or0 f_u_cla12_pg_logic4_or0 f_u_cla12_and17
11 1
.names f_u_cla12_and16 f_u_cla12_and17 f_u_cla12_and18
11 1
.names f_u_cla12_pg_logic4_and0 f_u_cla12_pg_logic6_or0 f_u_cla12_and19
11 1
.names f_u_cla12_and19 f_u_cla12_pg_logic5_or0 f_u_cla12_and20
11 1
.names f_u_cla12_pg_logic5_and0 f_u_cla12_pg_logic6_or0 f_u_cla12_and21
11 1
.names f_u_cla12_and18 f_u_cla12_and20 f_u_cla12_or9
1- 1
-1 1
.names f_u_cla12_or9 f_u_cla12_and21 f_u_cla12_or10
1- 1
-1 1
.names f_u_cla12_pg_logic6_and0 f_u_cla12_or10 f_u_cla12_or11
1- 1
-1 1
.names a[7] b[7] f_u_cla12_pg_logic7_or0
1- 1
-1 1
.names a[7] b[7] f_u_cla12_pg_logic7_and0
11 1
.names a[7] b[7] f_u_cla12_pg_logic7_xor0
01 1
10 1
.names f_u_cla12_pg_logic7_xor0 f_u_cla12_or11 f_u_cla12_xor7
01 1
10 1
.names f_u_cla12_or5 f_u_cla12_pg_logic6_or0 f_u_cla12_and22
11 1
.names f_u_cla12_pg_logic7_or0 f_u_cla12_pg_logic5_or0 f_u_cla12_and23
11 1
.names f_u_cla12_and22 f_u_cla12_and23 f_u_cla12_and24
11 1
.names f_u_cla12_and24 f_u_cla12_pg_logic4_or0 f_u_cla12_and25
11 1
.names f_u_cla12_pg_logic4_and0 f_u_cla12_pg_logic6_or0 f_u_cla12_and26
11 1
.names f_u_cla12_pg_logic7_or0 f_u_cla12_pg_logic5_or0 f_u_cla12_and27
11 1
.names f_u_cla12_and26 f_u_cla12_and27 f_u_cla12_and28
11 1
.names f_u_cla12_pg_logic5_and0 f_u_cla12_pg_logic7_or0 f_u_cla12_and29
11 1
.names f_u_cla12_and29 f_u_cla12_pg_logic6_or0 f_u_cla12_and30
11 1
.names f_u_cla12_pg_logic6_and0 f_u_cla12_pg_logic7_or0 f_u_cla12_and31
11 1
.names f_u_cla12_and25 f_u_cla12_and30 f_u_cla12_or12
1- 1
-1 1
.names f_u_cla12_and28 f_u_cla12_and31 f_u_cla12_or13
1- 1
-1 1
.names f_u_cla12_or12 f_u_cla12_or13 f_u_cla12_or14
1- 1
-1 1
.names f_u_cla12_pg_logic7_and0 f_u_cla12_or14 f_u_cla12_or15
1- 1
-1 1
.names a[8] b[8] f_u_cla12_pg_logic8_or0
1- 1
-1 1
.names a[8] b[8] f_u_cla12_pg_logic8_and0
11 1
.names a[8] b[8] f_u_cla12_pg_logic8_xor0
01 1
10 1
.names f_u_cla12_pg_logic8_xor0 f_u_cla12_or15 f_u_cla12_xor8
01 1
10 1
.names f_u_cla12_or15 f_u_cla12_pg_logic8_or0 f_u_cla12_and32
11 1
.names f_u_cla12_pg_logic8_and0 f_u_cla12_and32 f_u_cla12_or16
1- 1
-1 1
.names a[9] b[9] f_u_cla12_pg_logic9_or0
1- 1
-1 1
.names a[9] b[9] f_u_cla12_pg_logic9_and0
11 1
.names a[9] b[9] f_u_cla12_pg_logic9_xor0
01 1
10 1
.names f_u_cla12_pg_logic9_xor0 f_u_cla12_or16 f_u_cla12_xor9
01 1
10 1
.names f_u_cla12_or15 f_u_cla12_pg_logic9_or0 f_u_cla12_and33
11 1
.names f_u_cla12_and33 f_u_cla12_pg_logic8_or0 f_u_cla12_and34
11 1
.names f_u_cla12_pg_logic8_and0 f_u_cla12_pg_logic9_or0 f_u_cla12_and35
11 1
.names f_u_cla12_and34 f_u_cla12_and35 f_u_cla12_or17
1- 1
-1 1
.names f_u_cla12_pg_logic9_and0 f_u_cla12_or17 f_u_cla12_or18
1- 1
-1 1
.names a[10] b[10] f_u_cla12_pg_logic10_or0
1- 1
-1 1
.names a[10] b[10] f_u_cla12_pg_logic10_and0
11 1
.names a[10] b[10] f_u_cla12_pg_logic10_xor0
01 1
10 1
.names f_u_cla12_pg_logic10_xor0 f_u_cla12_or18 f_u_cla12_xor10
01 1
10 1
.names f_u_cla12_or15 f_u_cla12_pg_logic9_or0 f_u_cla12_and36
11 1
.names f_u_cla12_pg_logic10_or0 f_u_cla12_pg_logic8_or0 f_u_cla12_and37
11 1
.names f_u_cla12_and36 f_u_cla12_and37 f_u_cla12_and38
11 1
.names f_u_cla12_pg_logic8_and0 f_u_cla12_pg_logic10_or0 f_u_cla12_and39
11 1
.names f_u_cla12_and39 f_u_cla12_pg_logic9_or0 f_u_cla12_and40
11 1
.names f_u_cla12_pg_logic9_and0 f_u_cla12_pg_logic10_or0 f_u_cla12_and41
11 1
.names f_u_cla12_and38 f_u_cla12_and40 f_u_cla12_or19
1- 1
-1 1
.names f_u_cla12_or19 f_u_cla12_and41 f_u_cla12_or20
1- 1
-1 1
.names f_u_cla12_pg_logic10_and0 f_u_cla12_or20 f_u_cla12_or21
1- 1
-1 1
.names a[11] b[11] f_u_cla12_pg_logic11_or0
1- 1
-1 1
.names a[11] b[11] f_u_cla12_pg_logic11_and0
11 1
.names a[11] b[11] f_u_cla12_pg_logic11_xor0
01 1
10 1
.names f_u_cla12_pg_logic11_xor0 f_u_cla12_or21 f_u_cla12_xor11
01 1
10 1
.names f_u_cla12_or15 f_u_cla12_pg_logic10_or0 f_u_cla12_and42
11 1
.names f_u_cla12_pg_logic11_or0 f_u_cla12_pg_logic9_or0 f_u_cla12_and43
11 1
.names f_u_cla12_and42 f_u_cla12_and43 f_u_cla12_and44
11 1
.names f_u_cla12_and44 f_u_cla12_pg_logic8_or0 f_u_cla12_and45
11 1
.names f_u_cla12_pg_logic8_and0 f_u_cla12_pg_logic10_or0 f_u_cla12_and46
11 1
.names f_u_cla12_pg_logic11_or0 f_u_cla12_pg_logic9_or0 f_u_cla12_and47
11 1
.names f_u_cla12_and46 f_u_cla12_and47 f_u_cla12_and48
11 1
.names f_u_cla12_pg_logic9_and0 f_u_cla12_pg_logic11_or0 f_u_cla12_and49
11 1
.names f_u_cla12_and49 f_u_cla12_pg_logic10_or0 f_u_cla12_and50
11 1
.names f_u_cla12_pg_logic10_and0 f_u_cla12_pg_logic11_or0 f_u_cla12_and51
11 1
.names f_u_cla12_and45 f_u_cla12_and50 f_u_cla12_or22
1- 1
-1 1
.names f_u_cla12_and48 f_u_cla12_and51 f_u_cla12_or23
1- 1
-1 1
.names f_u_cla12_or22 f_u_cla12_or23 f_u_cla12_or24
1- 1
-1 1
.names f_u_cla12_pg_logic11_and0 f_u_cla12_or24 f_u_cla12_or25
1- 1
-1 1
.names f_u_cla12_pg_logic0_xor0 f_u_cla12_out[0]
1 1
.names f_u_cla12_xor1 f_u_cla12_out[1]
1 1
.names f_u_cla12_xor2 f_u_cla12_out[2]
1 1
.names f_u_cla12_xor3 f_u_cla12_out[3]
1 1
.names f_u_cla12_xor4 f_u_cla12_out[4]
1 1
.names f_u_cla12_xor5 f_u_cla12_out[5]
1 1
.names f_u_cla12_xor6 f_u_cla12_out[6]
1 1
.names f_u_cla12_xor7 f_u_cla12_out[7]
1 1
.names f_u_cla12_xor8 f_u_cla12_out[8]
1 1
.names f_u_cla12_xor9 f_u_cla12_out[9]
1 1
.names f_u_cla12_xor10 f_u_cla12_out[10]
1 1
.names f_u_cla12_xor11 f_u_cla12_out[11]
1 1
.names f_u_cla12_or25 f_u_cla12_out[12]
1 1
.end