honzastor 0f66c5a2e9 Fixed proper connections in submodules instantiation in hierarchical Verilog generation. Sample generated circuits were also accordingly updated.

2021-04-23 11:49:24 +02:00

..

__init__.py

Generated sample circuits for various representations. Updated C code circuits testing simulations and did some cleanup.

2021-04-23 02:44:14 +02:00

buses.py

Fixed proper connections in submodules instantiation in hierarchical Verilog generation. Sample generated circuits were also accordingly updated.

2021-04-23 11:49:24 +02:00

wires.py

Optimized circuits generation, refactored code, fixed cla, added new csa, array divider circuits and create yosys equivalence check script. TBD: Documentation and sample generated circuits.

2021-04-21 11:33:07 +02:00