mirror of
https://github.com/ehw-fit/ariths-gen.git
synced 2025-04-21 22:31:22 +01:00
226 lines
10 KiB
Plaintext
226 lines
10 KiB
Plaintext
.model u_CSAwallace_cla4
|
|
.inputs a[0] a[1] a[2] a[3] b[0] b[1] b[2] b[3]
|
|
.outputs u_CSAwallace_cla4_out[0] u_CSAwallace_cla4_out[1] u_CSAwallace_cla4_out[2] u_CSAwallace_cla4_out[3] u_CSAwallace_cla4_out[4] u_CSAwallace_cla4_out[5] u_CSAwallace_cla4_out[6] u_CSAwallace_cla4_out[7]
|
|
.names vdd
|
|
1
|
|
.names gnd
|
|
0
|
|
.names a[0] b[0] u_CSAwallace_cla4_and_0_0
|
|
11 1
|
|
.names a[1] b[0] u_CSAwallace_cla4_and_1_0
|
|
11 1
|
|
.names a[2] b[0] u_CSAwallace_cla4_and_2_0
|
|
11 1
|
|
.names a[3] b[0] u_CSAwallace_cla4_and_3_0
|
|
11 1
|
|
.names a[0] b[1] u_CSAwallace_cla4_and_0_1
|
|
11 1
|
|
.names a[1] b[1] u_CSAwallace_cla4_and_1_1
|
|
11 1
|
|
.names a[2] b[1] u_CSAwallace_cla4_and_2_1
|
|
11 1
|
|
.names a[3] b[1] u_CSAwallace_cla4_and_3_1
|
|
11 1
|
|
.names a[0] b[2] u_CSAwallace_cla4_and_0_2
|
|
11 1
|
|
.names a[1] b[2] u_CSAwallace_cla4_and_1_2
|
|
11 1
|
|
.names a[2] b[2] u_CSAwallace_cla4_and_2_2
|
|
11 1
|
|
.names a[3] b[2] u_CSAwallace_cla4_and_3_2
|
|
11 1
|
|
.names a[0] b[3] u_CSAwallace_cla4_and_0_3
|
|
11 1
|
|
.names a[1] b[3] u_CSAwallace_cla4_and_1_3
|
|
11 1
|
|
.names a[2] b[3] u_CSAwallace_cla4_and_2_3
|
|
11 1
|
|
.names a[3] b[3] u_CSAwallace_cla4_and_3_3
|
|
11 1
|
|
.names u_CSAwallace_cla4_and_1_0 u_CSAwallace_cla4_and_0_1 u_CSAwallace_cla4_csa0_csa_component_fa1_xor0
|
|
01 1
|
|
10 1
|
|
.names u_CSAwallace_cla4_and_1_0 u_CSAwallace_cla4_and_0_1 u_CSAwallace_cla4_csa0_csa_component_fa1_and0
|
|
11 1
|
|
.names u_CSAwallace_cla4_and_2_0 u_CSAwallace_cla4_and_1_1 u_CSAwallace_cla4_csa0_csa_component_fa2_xor0
|
|
01 1
|
|
10 1
|
|
.names u_CSAwallace_cla4_and_2_0 u_CSAwallace_cla4_and_1_1 u_CSAwallace_cla4_csa0_csa_component_fa2_and0
|
|
11 1
|
|
.names u_CSAwallace_cla4_csa0_csa_component_fa2_xor0 u_CSAwallace_cla4_and_0_2 u_CSAwallace_cla4_csa0_csa_component_fa2_xor1
|
|
01 1
|
|
10 1
|
|
.names u_CSAwallace_cla4_csa0_csa_component_fa2_xor0 u_CSAwallace_cla4_and_0_2 u_CSAwallace_cla4_csa0_csa_component_fa2_and1
|
|
11 1
|
|
.names u_CSAwallace_cla4_csa0_csa_component_fa2_and0 u_CSAwallace_cla4_csa0_csa_component_fa2_and1 u_CSAwallace_cla4_csa0_csa_component_fa2_or0
|
|
1- 1
|
|
-1 1
|
|
.names u_CSAwallace_cla4_and_3_0 u_CSAwallace_cla4_and_2_1 u_CSAwallace_cla4_csa0_csa_component_fa3_xor0
|
|
01 1
|
|
10 1
|
|
.names u_CSAwallace_cla4_and_3_0 u_CSAwallace_cla4_and_2_1 u_CSAwallace_cla4_csa0_csa_component_fa3_and0
|
|
11 1
|
|
.names u_CSAwallace_cla4_csa0_csa_component_fa3_xor0 u_CSAwallace_cla4_and_1_2 u_CSAwallace_cla4_csa0_csa_component_fa3_xor1
|
|
01 1
|
|
10 1
|
|
.names u_CSAwallace_cla4_csa0_csa_component_fa3_xor0 u_CSAwallace_cla4_and_1_2 u_CSAwallace_cla4_csa0_csa_component_fa3_and1
|
|
11 1
|
|
.names u_CSAwallace_cla4_csa0_csa_component_fa3_and0 u_CSAwallace_cla4_csa0_csa_component_fa3_and1 u_CSAwallace_cla4_csa0_csa_component_fa3_or0
|
|
1- 1
|
|
-1 1
|
|
.names u_CSAwallace_cla4_and_3_1 u_CSAwallace_cla4_and_2_2 u_CSAwallace_cla4_csa0_csa_component_fa4_xor1
|
|
01 1
|
|
10 1
|
|
.names u_CSAwallace_cla4_and_3_1 u_CSAwallace_cla4_and_2_2 u_CSAwallace_cla4_csa0_csa_component_fa4_and1
|
|
11 1
|
|
.names u_CSAwallace_cla4_csa0_csa_component_fa2_xor1 u_CSAwallace_cla4_csa0_csa_component_fa1_and0 u_CSAwallace_cla4_csa1_csa_component_fa2_xor0
|
|
01 1
|
|
10 1
|
|
.names u_CSAwallace_cla4_csa0_csa_component_fa2_xor1 u_CSAwallace_cla4_csa0_csa_component_fa1_and0 u_CSAwallace_cla4_csa1_csa_component_fa2_and0
|
|
11 1
|
|
.names u_CSAwallace_cla4_csa0_csa_component_fa3_xor1 u_CSAwallace_cla4_csa0_csa_component_fa2_or0 u_CSAwallace_cla4_csa1_csa_component_fa3_xor0
|
|
01 1
|
|
10 1
|
|
.names u_CSAwallace_cla4_csa0_csa_component_fa3_xor1 u_CSAwallace_cla4_csa0_csa_component_fa2_or0 u_CSAwallace_cla4_csa1_csa_component_fa3_and0
|
|
11 1
|
|
.names u_CSAwallace_cla4_csa1_csa_component_fa3_xor0 u_CSAwallace_cla4_and_0_3 u_CSAwallace_cla4_csa1_csa_component_fa3_xor1
|
|
01 1
|
|
10 1
|
|
.names u_CSAwallace_cla4_csa1_csa_component_fa3_xor0 u_CSAwallace_cla4_and_0_3 u_CSAwallace_cla4_csa1_csa_component_fa3_and1
|
|
11 1
|
|
.names u_CSAwallace_cla4_csa1_csa_component_fa3_and0 u_CSAwallace_cla4_csa1_csa_component_fa3_and1 u_CSAwallace_cla4_csa1_csa_component_fa3_or0
|
|
1- 1
|
|
-1 1
|
|
.names u_CSAwallace_cla4_csa0_csa_component_fa4_xor1 u_CSAwallace_cla4_csa0_csa_component_fa3_or0 u_CSAwallace_cla4_csa1_csa_component_fa4_xor0
|
|
01 1
|
|
10 1
|
|
.names u_CSAwallace_cla4_csa0_csa_component_fa4_xor1 u_CSAwallace_cla4_csa0_csa_component_fa3_or0 u_CSAwallace_cla4_csa1_csa_component_fa4_and0
|
|
11 1
|
|
.names u_CSAwallace_cla4_csa1_csa_component_fa4_xor0 u_CSAwallace_cla4_and_1_3 u_CSAwallace_cla4_csa1_csa_component_fa4_xor1
|
|
01 1
|
|
10 1
|
|
.names u_CSAwallace_cla4_csa1_csa_component_fa4_xor0 u_CSAwallace_cla4_and_1_3 u_CSAwallace_cla4_csa1_csa_component_fa4_and1
|
|
11 1
|
|
.names u_CSAwallace_cla4_csa1_csa_component_fa4_and0 u_CSAwallace_cla4_csa1_csa_component_fa4_and1 u_CSAwallace_cla4_csa1_csa_component_fa4_or0
|
|
1- 1
|
|
-1 1
|
|
.names u_CSAwallace_cla4_and_3_2 u_CSAwallace_cla4_csa0_csa_component_fa4_and1 u_CSAwallace_cla4_csa1_csa_component_fa5_xor0
|
|
01 1
|
|
10 1
|
|
.names u_CSAwallace_cla4_and_3_2 u_CSAwallace_cla4_csa0_csa_component_fa4_and1 u_CSAwallace_cla4_csa1_csa_component_fa5_and0
|
|
11 1
|
|
.names u_CSAwallace_cla4_csa1_csa_component_fa5_xor0 u_CSAwallace_cla4_and_2_3 u_CSAwallace_cla4_csa1_csa_component_fa5_xor1
|
|
01 1
|
|
10 1
|
|
.names u_CSAwallace_cla4_csa1_csa_component_fa5_xor0 u_CSAwallace_cla4_and_2_3 u_CSAwallace_cla4_csa1_csa_component_fa5_and1
|
|
11 1
|
|
.names u_CSAwallace_cla4_csa1_csa_component_fa5_and0 u_CSAwallace_cla4_csa1_csa_component_fa5_and1 u_CSAwallace_cla4_csa1_csa_component_fa5_or0
|
|
1- 1
|
|
-1 1
|
|
.names u_CSAwallace_cla4_csa1_csa_component_fa2_xor0 u_CSAwallace_cla4_and_0_0 u_CSAwallace_cla4_u_cla8_and0
|
|
11 1
|
|
.names u_CSAwallace_cla4_csa1_csa_component_fa3_xor1 u_CSAwallace_cla4_csa1_csa_component_fa2_and0 u_CSAwallace_cla4_u_cla8_pg_logic3_or0
|
|
1- 1
|
|
-1 1
|
|
.names u_CSAwallace_cla4_csa1_csa_component_fa3_xor1 u_CSAwallace_cla4_csa1_csa_component_fa2_and0 u_CSAwallace_cla4_u_cla8_pg_logic3_and0
|
|
11 1
|
|
.names u_CSAwallace_cla4_csa1_csa_component_fa3_xor1 u_CSAwallace_cla4_csa1_csa_component_fa2_and0 u_CSAwallace_cla4_u_cla8_pg_logic3_xor0
|
|
01 1
|
|
10 1
|
|
.names u_CSAwallace_cla4_u_cla8_pg_logic3_or0 u_CSAwallace_cla4_csa0_csa_component_fa1_xor0 u_CSAwallace_cla4_u_cla8_and1
|
|
11 1
|
|
.names u_CSAwallace_cla4_u_cla8_pg_logic3_or0 u_CSAwallace_cla4_csa0_csa_component_fa1_xor0 u_CSAwallace_cla4_u_cla8_and2
|
|
11 1
|
|
.names u_CSAwallace_cla4_csa1_csa_component_fa4_xor1 u_CSAwallace_cla4_csa1_csa_component_fa3_or0 u_CSAwallace_cla4_u_cla8_pg_logic4_or0
|
|
1- 1
|
|
-1 1
|
|
.names u_CSAwallace_cla4_csa1_csa_component_fa4_xor1 u_CSAwallace_cla4_csa1_csa_component_fa3_or0 u_CSAwallace_cla4_u_cla8_pg_logic4_and0
|
|
11 1
|
|
.names u_CSAwallace_cla4_csa1_csa_component_fa4_xor1 u_CSAwallace_cla4_csa1_csa_component_fa3_or0 u_CSAwallace_cla4_u_cla8_pg_logic4_xor0
|
|
01 1
|
|
10 1
|
|
.names u_CSAwallace_cla4_u_cla8_pg_logic4_xor0 u_CSAwallace_cla4_u_cla8_pg_logic3_and0 u_CSAwallace_cla4_u_cla8_xor4
|
|
01 1
|
|
10 1
|
|
.names u_CSAwallace_cla4_u_cla8_pg_logic3_and0 u_CSAwallace_cla4_u_cla8_pg_logic4_or0 u_CSAwallace_cla4_u_cla8_and3
|
|
11 1
|
|
.names u_CSAwallace_cla4_u_cla8_pg_logic4_and0 u_CSAwallace_cla4_u_cla8_and3 u_CSAwallace_cla4_u_cla8_or0
|
|
1- 1
|
|
-1 1
|
|
.names u_CSAwallace_cla4_csa1_csa_component_fa5_xor1 u_CSAwallace_cla4_csa1_csa_component_fa4_or0 u_CSAwallace_cla4_u_cla8_pg_logic5_or0
|
|
1- 1
|
|
-1 1
|
|
.names u_CSAwallace_cla4_csa1_csa_component_fa5_xor1 u_CSAwallace_cla4_csa1_csa_component_fa4_or0 u_CSAwallace_cla4_u_cla8_pg_logic5_and0
|
|
11 1
|
|
.names u_CSAwallace_cla4_csa1_csa_component_fa5_xor1 u_CSAwallace_cla4_csa1_csa_component_fa4_or0 u_CSAwallace_cla4_u_cla8_pg_logic5_xor0
|
|
01 1
|
|
10 1
|
|
.names u_CSAwallace_cla4_u_cla8_pg_logic5_xor0 u_CSAwallace_cla4_u_cla8_or0 u_CSAwallace_cla4_u_cla8_xor5
|
|
01 1
|
|
10 1
|
|
.names u_CSAwallace_cla4_u_cla8_pg_logic3_and0 u_CSAwallace_cla4_u_cla8_pg_logic5_or0 u_CSAwallace_cla4_u_cla8_and4
|
|
11 1
|
|
.names u_CSAwallace_cla4_u_cla8_and4 u_CSAwallace_cla4_u_cla8_pg_logic4_or0 u_CSAwallace_cla4_u_cla8_and5
|
|
11 1
|
|
.names u_CSAwallace_cla4_u_cla8_pg_logic4_and0 u_CSAwallace_cla4_u_cla8_pg_logic5_or0 u_CSAwallace_cla4_u_cla8_and6
|
|
11 1
|
|
.names u_CSAwallace_cla4_u_cla8_and5 u_CSAwallace_cla4_u_cla8_and6 u_CSAwallace_cla4_u_cla8_or1
|
|
1- 1
|
|
-1 1
|
|
.names u_CSAwallace_cla4_u_cla8_pg_logic5_and0 u_CSAwallace_cla4_u_cla8_or1 u_CSAwallace_cla4_u_cla8_or2
|
|
1- 1
|
|
-1 1
|
|
.names u_CSAwallace_cla4_and_3_3 u_CSAwallace_cla4_csa1_csa_component_fa5_or0 u_CSAwallace_cla4_u_cla8_pg_logic6_or0
|
|
1- 1
|
|
-1 1
|
|
.names u_CSAwallace_cla4_and_3_3 u_CSAwallace_cla4_csa1_csa_component_fa5_or0 u_CSAwallace_cla4_u_cla8_pg_logic6_and0
|
|
11 1
|
|
.names u_CSAwallace_cla4_and_3_3 u_CSAwallace_cla4_csa1_csa_component_fa5_or0 u_CSAwallace_cla4_u_cla8_pg_logic6_xor0
|
|
01 1
|
|
10 1
|
|
.names u_CSAwallace_cla4_u_cla8_pg_logic6_xor0 u_CSAwallace_cla4_u_cla8_or2 u_CSAwallace_cla4_u_cla8_xor6
|
|
01 1
|
|
10 1
|
|
.names u_CSAwallace_cla4_u_cla8_pg_logic3_and0 u_CSAwallace_cla4_u_cla8_pg_logic5_or0 u_CSAwallace_cla4_u_cla8_and7
|
|
11 1
|
|
.names u_CSAwallace_cla4_u_cla8_pg_logic6_or0 u_CSAwallace_cla4_u_cla8_pg_logic4_or0 u_CSAwallace_cla4_u_cla8_and8
|
|
11 1
|
|
.names u_CSAwallace_cla4_u_cla8_and7 u_CSAwallace_cla4_u_cla8_and8 u_CSAwallace_cla4_u_cla8_and9
|
|
11 1
|
|
.names u_CSAwallace_cla4_u_cla8_pg_logic4_and0 u_CSAwallace_cla4_u_cla8_pg_logic6_or0 u_CSAwallace_cla4_u_cla8_and10
|
|
11 1
|
|
.names u_CSAwallace_cla4_u_cla8_and10 u_CSAwallace_cla4_u_cla8_pg_logic5_or0 u_CSAwallace_cla4_u_cla8_and11
|
|
11 1
|
|
.names u_CSAwallace_cla4_u_cla8_pg_logic5_and0 u_CSAwallace_cla4_u_cla8_pg_logic6_or0 u_CSAwallace_cla4_u_cla8_and12
|
|
11 1
|
|
.names u_CSAwallace_cla4_u_cla8_and9 u_CSAwallace_cla4_u_cla8_and11 u_CSAwallace_cla4_u_cla8_or3
|
|
1- 1
|
|
-1 1
|
|
.names u_CSAwallace_cla4_u_cla8_or3 u_CSAwallace_cla4_u_cla8_and12 u_CSAwallace_cla4_u_cla8_or4
|
|
1- 1
|
|
-1 1
|
|
.names u_CSAwallace_cla4_u_cla8_pg_logic6_and0 u_CSAwallace_cla4_u_cla8_or4 u_CSAwallace_cla4_u_cla8_or5
|
|
1- 1
|
|
-1 1
|
|
.names u_CSAwallace_cla4_u_cla8_pg_logic3_and0 u_CSAwallace_cla4_u_cla8_pg_logic6_or0 u_CSAwallace_cla4_u_cla8_and13
|
|
11 1
|
|
.names u_CSAwallace_cla4_u_cla8_pg_logic4_and0 u_CSAwallace_cla4_u_cla8_pg_logic6_or0 u_CSAwallace_cla4_u_cla8_and14
|
|
11 1
|
|
.names u_CSAwallace_cla4_and_0_0 u_CSAwallace_cla4_out[0]
|
|
1 1
|
|
.names u_CSAwallace_cla4_csa0_csa_component_fa1_xor0 u_CSAwallace_cla4_out[1]
|
|
1 1
|
|
.names u_CSAwallace_cla4_csa1_csa_component_fa2_xor0 u_CSAwallace_cla4_out[2]
|
|
1 1
|
|
.names u_CSAwallace_cla4_u_cla8_pg_logic3_xor0 u_CSAwallace_cla4_out[3]
|
|
1 1
|
|
.names u_CSAwallace_cla4_u_cla8_xor4 u_CSAwallace_cla4_out[4]
|
|
1 1
|
|
.names u_CSAwallace_cla4_u_cla8_xor5 u_CSAwallace_cla4_out[5]
|
|
1 1
|
|
.names u_CSAwallace_cla4_u_cla8_xor6 u_CSAwallace_cla4_out[6]
|
|
1 1
|
|
.names u_CSAwallace_cla4_u_cla8_or5 u_CSAwallace_cla4_out[7]
|
|
1 1
|
|
.end
|