mirror of
https://github.com/ehw-fit/ariths-gen.git
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217 lines
8.8 KiB
Plaintext
217 lines
8.8 KiB
Plaintext
.model s_cska24
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.inputs a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] a[8] a[9] a[10] a[11] a[12] a[13] a[14] a[15] a[16] a[17] a[18] a[19] a[20] a[21] a[22] a[23] b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9] b[10] b[11] b[12] b[13] b[14] b[15] b[16] b[17] b[18] b[19] b[20] b[21] b[22] b[23]
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.outputs s_cska24_out[0] s_cska24_out[1] s_cska24_out[2] s_cska24_out[3] s_cska24_out[4] s_cska24_out[5] s_cska24_out[6] s_cska24_out[7] s_cska24_out[8] s_cska24_out[9] s_cska24_out[10] s_cska24_out[11] s_cska24_out[12] s_cska24_out[13] s_cska24_out[14] s_cska24_out[15] s_cska24_out[16] s_cska24_out[17] s_cska24_out[18] s_cska24_out[19] s_cska24_out[20] s_cska24_out[21] s_cska24_out[22] s_cska24_out[23] s_cska24_out[24]
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.names vdd
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1
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.names gnd
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0
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.subckt xor_gate a=a[0] b=b[0] out=s_cska24_xor0
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.subckt ha a=a[0] b=b[0] ha_xor0=s_cska24_ha0_xor0 ha_and0=s_cska24_ha0_and0
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.subckt xor_gate a=a[1] b=b[1] out=s_cska24_xor1
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.subckt fa a=a[1] b=b[1] cin=s_cska24_ha0_and0 fa_xor1=s_cska24_fa0_xor1 fa_or0=s_cska24_fa0_or0
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.subckt xor_gate a=a[2] b=b[2] out=s_cska24_xor2
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.subckt fa a=a[2] b=b[2] cin=s_cska24_fa0_or0 fa_xor1=s_cska24_fa1_xor1 fa_or0=s_cska24_fa1_or0
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.subckt xor_gate a=a[3] b=b[3] out=s_cska24_xor3
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.subckt fa a=a[3] b=b[3] cin=s_cska24_fa1_or0 fa_xor1=s_cska24_fa2_xor1 fa_or0=s_cska24_fa2_or0
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.subckt and_gate a=s_cska24_xor0 b=s_cska24_xor2 out=s_cska24_and_propagate00
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.subckt and_gate a=s_cska24_xor1 b=s_cska24_xor3 out=s_cska24_and_propagate01
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.subckt and_gate a=s_cska24_and_propagate00 b=s_cska24_and_propagate01 out=s_cska24_and_propagate02
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.subckt mux2to1 d0=s_cska24_fa2_or0 d1=gnd sel=s_cska24_and_propagate02 mux2to1_xor0=s_cska24_mux2to10_and1
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.subckt xor_gate a=a[4] b=b[4] out=s_cska24_xor4
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.subckt fa a=a[4] b=b[4] cin=s_cska24_mux2to10_and1 fa_xor1=s_cska24_fa3_xor1 fa_or0=s_cska24_fa3_or0
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.subckt xor_gate a=a[5] b=b[5] out=s_cska24_xor5
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.subckt fa a=a[5] b=b[5] cin=s_cska24_fa3_or0 fa_xor1=s_cska24_fa4_xor1 fa_or0=s_cska24_fa4_or0
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.subckt xor_gate a=a[6] b=b[6] out=s_cska24_xor6
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.subckt fa a=a[6] b=b[6] cin=s_cska24_fa4_or0 fa_xor1=s_cska24_fa5_xor1 fa_or0=s_cska24_fa5_or0
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.subckt xor_gate a=a[7] b=b[7] out=s_cska24_xor7
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.subckt fa a=a[7] b=b[7] cin=s_cska24_fa5_or0 fa_xor1=s_cska24_fa6_xor1 fa_or0=s_cska24_fa6_or0
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.subckt and_gate a=s_cska24_xor4 b=s_cska24_xor6 out=s_cska24_and_propagate13
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.subckt and_gate a=s_cska24_xor5 b=s_cska24_xor7 out=s_cska24_and_propagate14
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.subckt and_gate a=s_cska24_and_propagate13 b=s_cska24_and_propagate14 out=s_cska24_and_propagate15
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.subckt mux2to1 d0=s_cska24_fa6_or0 d1=s_cska24_mux2to10_and1 sel=s_cska24_and_propagate15 mux2to1_xor0=s_cska24_mux2to11_xor0
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.subckt xor_gate a=a[8] b=b[8] out=s_cska24_xor8
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.subckt fa a=a[8] b=b[8] cin=s_cska24_mux2to11_xor0 fa_xor1=s_cska24_fa7_xor1 fa_or0=s_cska24_fa7_or0
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.subckt xor_gate a=a[9] b=b[9] out=s_cska24_xor9
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.subckt fa a=a[9] b=b[9] cin=s_cska24_fa7_or0 fa_xor1=s_cska24_fa8_xor1 fa_or0=s_cska24_fa8_or0
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.subckt xor_gate a=a[10] b=b[10] out=s_cska24_xor10
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.subckt fa a=a[10] b=b[10] cin=s_cska24_fa8_or0 fa_xor1=s_cska24_fa9_xor1 fa_or0=s_cska24_fa9_or0
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.subckt xor_gate a=a[11] b=b[11] out=s_cska24_xor11
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.subckt fa a=a[11] b=b[11] cin=s_cska24_fa9_or0 fa_xor1=s_cska24_fa10_xor1 fa_or0=s_cska24_fa10_or0
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.subckt and_gate a=s_cska24_xor8 b=s_cska24_xor10 out=s_cska24_and_propagate26
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.subckt and_gate a=s_cska24_xor9 b=s_cska24_xor11 out=s_cska24_and_propagate27
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.subckt and_gate a=s_cska24_and_propagate26 b=s_cska24_and_propagate27 out=s_cska24_and_propagate28
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.subckt mux2to1 d0=s_cska24_fa10_or0 d1=s_cska24_mux2to11_xor0 sel=s_cska24_and_propagate28 mux2to1_xor0=s_cska24_mux2to12_xor0
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.subckt xor_gate a=a[12] b=b[12] out=s_cska24_xor12
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.subckt fa a=a[12] b=b[12] cin=s_cska24_mux2to12_xor0 fa_xor1=s_cska24_fa11_xor1 fa_or0=s_cska24_fa11_or0
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.subckt xor_gate a=a[13] b=b[13] out=s_cska24_xor13
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.subckt fa a=a[13] b=b[13] cin=s_cska24_fa11_or0 fa_xor1=s_cska24_fa12_xor1 fa_or0=s_cska24_fa12_or0
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.subckt xor_gate a=a[14] b=b[14] out=s_cska24_xor14
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.subckt fa a=a[14] b=b[14] cin=s_cska24_fa12_or0 fa_xor1=s_cska24_fa13_xor1 fa_or0=s_cska24_fa13_or0
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.subckt xor_gate a=a[15] b=b[15] out=s_cska24_xor15
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.subckt fa a=a[15] b=b[15] cin=s_cska24_fa13_or0 fa_xor1=s_cska24_fa14_xor1 fa_or0=s_cska24_fa14_or0
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.subckt and_gate a=s_cska24_xor12 b=s_cska24_xor14 out=s_cska24_and_propagate39
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.subckt and_gate a=s_cska24_xor13 b=s_cska24_xor15 out=s_cska24_and_propagate310
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.subckt and_gate a=s_cska24_and_propagate39 b=s_cska24_and_propagate310 out=s_cska24_and_propagate311
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.subckt mux2to1 d0=s_cska24_fa14_or0 d1=s_cska24_mux2to12_xor0 sel=s_cska24_and_propagate311 mux2to1_xor0=s_cska24_mux2to13_xor0
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.subckt xor_gate a=a[16] b=b[16] out=s_cska24_xor16
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.subckt fa a=a[16] b=b[16] cin=s_cska24_mux2to13_xor0 fa_xor1=s_cska24_fa15_xor1 fa_or0=s_cska24_fa15_or0
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.subckt xor_gate a=a[17] b=b[17] out=s_cska24_xor17
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.subckt fa a=a[17] b=b[17] cin=s_cska24_fa15_or0 fa_xor1=s_cska24_fa16_xor1 fa_or0=s_cska24_fa16_or0
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.subckt xor_gate a=a[18] b=b[18] out=s_cska24_xor18
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.subckt fa a=a[18] b=b[18] cin=s_cska24_fa16_or0 fa_xor1=s_cska24_fa17_xor1 fa_or0=s_cska24_fa17_or0
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.subckt xor_gate a=a[19] b=b[19] out=s_cska24_xor19
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.subckt fa a=a[19] b=b[19] cin=s_cska24_fa17_or0 fa_xor1=s_cska24_fa18_xor1 fa_or0=s_cska24_fa18_or0
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.subckt and_gate a=s_cska24_xor16 b=s_cska24_xor18 out=s_cska24_and_propagate412
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.subckt and_gate a=s_cska24_xor17 b=s_cska24_xor19 out=s_cska24_and_propagate413
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.subckt and_gate a=s_cska24_and_propagate412 b=s_cska24_and_propagate413 out=s_cska24_and_propagate414
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.subckt mux2to1 d0=s_cska24_fa18_or0 d1=s_cska24_mux2to13_xor0 sel=s_cska24_and_propagate414 mux2to1_xor0=s_cska24_mux2to14_xor0
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.subckt xor_gate a=a[20] b=b[20] out=s_cska24_xor20
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.subckt fa a=a[20] b=b[20] cin=s_cska24_mux2to14_xor0 fa_xor1=s_cska24_fa19_xor1 fa_or0=s_cska24_fa19_or0
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.subckt xor_gate a=a[21] b=b[21] out=s_cska24_xor21
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.subckt fa a=a[21] b=b[21] cin=s_cska24_fa19_or0 fa_xor1=s_cska24_fa20_xor1 fa_or0=s_cska24_fa20_or0
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.subckt xor_gate a=a[22] b=b[22] out=s_cska24_xor22
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.subckt fa a=a[22] b=b[22] cin=s_cska24_fa20_or0 fa_xor1=s_cska24_fa21_xor1 fa_or0=s_cska24_fa21_or0
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.subckt xor_gate a=a[23] b=b[23] out=s_cska24_xor23
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.subckt fa a=a[23] b=b[23] cin=s_cska24_fa21_or0 fa_xor1=s_cska24_fa22_xor1 fa_or0=s_cska24_fa22_or0
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.subckt and_gate a=s_cska24_xor20 b=s_cska24_xor22 out=s_cska24_and_propagate515
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.subckt and_gate a=s_cska24_xor21 b=s_cska24_xor23 out=s_cska24_and_propagate516
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.subckt and_gate a=s_cska24_and_propagate515 b=s_cska24_and_propagate516 out=s_cska24_and_propagate517
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.subckt mux2to1 d0=s_cska24_fa22_or0 d1=s_cska24_mux2to14_xor0 sel=s_cska24_and_propagate517 mux2to1_xor0=s_cska24_mux2to15_xor0
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.subckt xor_gate a=a[23] b=b[23] out=s_cska24_xor24
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.subckt xor_gate a=s_cska24_xor24 b=s_cska24_mux2to15_xor0 out=s_cska24_xor25
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.names s_cska24_ha0_xor0 s_cska24_out[0]
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1 1
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.names s_cska24_fa0_xor1 s_cska24_out[1]
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1 1
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.names s_cska24_fa1_xor1 s_cska24_out[2]
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1 1
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.names s_cska24_fa2_xor1 s_cska24_out[3]
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1 1
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.names s_cska24_fa3_xor1 s_cska24_out[4]
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1 1
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.names s_cska24_fa4_xor1 s_cska24_out[5]
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1 1
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.names s_cska24_fa5_xor1 s_cska24_out[6]
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1 1
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.names s_cska24_fa6_xor1 s_cska24_out[7]
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1 1
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.names s_cska24_fa7_xor1 s_cska24_out[8]
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1 1
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.names s_cska24_fa8_xor1 s_cska24_out[9]
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1 1
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.names s_cska24_fa9_xor1 s_cska24_out[10]
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1 1
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.names s_cska24_fa10_xor1 s_cska24_out[11]
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1 1
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.names s_cska24_fa11_xor1 s_cska24_out[12]
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1 1
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.names s_cska24_fa12_xor1 s_cska24_out[13]
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1 1
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.names s_cska24_fa13_xor1 s_cska24_out[14]
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1 1
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.names s_cska24_fa14_xor1 s_cska24_out[15]
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1 1
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.names s_cska24_fa15_xor1 s_cska24_out[16]
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1 1
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.names s_cska24_fa16_xor1 s_cska24_out[17]
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1 1
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.names s_cska24_fa17_xor1 s_cska24_out[18]
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1 1
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.names s_cska24_fa18_xor1 s_cska24_out[19]
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1 1
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.names s_cska24_fa19_xor1 s_cska24_out[20]
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1 1
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.names s_cska24_fa20_xor1 s_cska24_out[21]
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1 1
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.names s_cska24_fa21_xor1 s_cska24_out[22]
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1 1
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.names s_cska24_fa22_xor1 s_cska24_out[23]
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1 1
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.names s_cska24_xor25 s_cska24_out[24]
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1 1
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.end
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.model mux2to1
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.inputs d0 d1 sel
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.outputs mux2to1_xor0
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.names vdd
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1
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.names gnd
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0
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.subckt and_gate a=d1 b=sel out=mux2to1_and0
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.subckt not_gate a=sel out=mux2to1_not0
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.subckt and_gate a=d0 b=mux2to1_not0 out=mux2to1_and1
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.subckt xor_gate a=mux2to1_and0 b=mux2to1_and1 out=mux2to1_xor0
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.end
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.model fa
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.inputs a b cin
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.outputs fa_xor1 fa_or0
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.names vdd
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1
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.names gnd
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0
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.subckt xor_gate a=a b=b out=fa_xor0
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.subckt and_gate a=a b=b out=fa_and0
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.subckt xor_gate a=fa_xor0 b=cin out=fa_xor1
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.subckt and_gate a=fa_xor0 b=cin out=fa_and1
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.subckt or_gate a=fa_and0 b=fa_and1 out=fa_or0
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.end
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.model ha
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.inputs a b
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.outputs ha_xor0 ha_and0
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.names vdd
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1
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.names gnd
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0
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.subckt xor_gate a=a b=b out=ha_xor0
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.subckt and_gate a=a b=b out=ha_and0
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.end
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.model not_gate
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.inputs a
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.outputs out
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.names vdd
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1
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.names gnd
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0
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.names a out
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0 1
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.end
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.model or_gate
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.inputs a b
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.outputs out
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.names vdd
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1
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.names gnd
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0
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.names a b out
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1- 1
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-1 1
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.end
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.model and_gate
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.inputs a b
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.outputs out
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.names vdd
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1
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.names gnd
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0
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.names a b out
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11 1
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.end
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.model xor_gate
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.inputs a b
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.outputs out
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.names vdd
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1
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.names gnd
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0
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.names a b out
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01 1
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10 1
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.end
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