ariths-gen/generated_circuits/blif_circuits/flat/u_cla16.blif

.model u_cla16
.inputs a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] a[8] a[9] a[10] a[11] a[12] a[13] a[14] a[15] b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9] b[10] b[11] b[12] b[13] b[14] b[15]
.outputs u_cla16_out[0] u_cla16_out[1] u_cla16_out[2] u_cla16_out[3] u_cla16_out[4] u_cla16_out[5] u_cla16_out[6] u_cla16_out[7] u_cla16_out[8] u_cla16_out[9] u_cla16_out[10] u_cla16_out[11] u_cla16_out[12] u_cla16_out[13] u_cla16_out[14] u_cla16_out[15] u_cla16_out[16]
.names vdd
1
.names gnd
0
.names a[0] b[0] u_cla16_pg_logic0_or0
1- 1
-1 1
.names a[0] b[0] u_cla16_pg_logic0_and0
11 1
.names a[0] b[0] u_cla16_pg_logic0_xor0
01 1
10 1
.names a[1] b[1] u_cla16_pg_logic1_or0
1- 1
-1 1
.names a[1] b[1] u_cla16_pg_logic1_and0
11 1
.names a[1] b[1] u_cla16_pg_logic1_xor0
01 1
10 1
.names u_cla16_pg_logic1_xor0 u_cla16_pg_logic0_and0 u_cla16_xor1
01 1
10 1
.names u_cla16_pg_logic0_and0 u_cla16_pg_logic1_or0 u_cla16_and0
11 1
.names u_cla16_pg_logic1_and0 u_cla16_and0 u_cla16_or0
1- 1
-1 1
.names a[2] b[2] u_cla16_pg_logic2_or0
1- 1
-1 1
.names a[2] b[2] u_cla16_pg_logic2_and0
11 1
.names a[2] b[2] u_cla16_pg_logic2_xor0
01 1
10 1
.names u_cla16_pg_logic2_xor0 u_cla16_or0 u_cla16_xor2
01 1
10 1
.names u_cla16_pg_logic2_or0 u_cla16_pg_logic0_or0 u_cla16_and1
11 1
.names u_cla16_pg_logic0_and0 u_cla16_pg_logic2_or0 u_cla16_and2
11 1
.names u_cla16_and2 u_cla16_pg_logic1_or0 u_cla16_and3
11 1
.names u_cla16_pg_logic1_and0 u_cla16_pg_logic2_or0 u_cla16_and4
11 1
.names u_cla16_and3 u_cla16_and4 u_cla16_or1
1- 1
-1 1
.names u_cla16_pg_logic2_and0 u_cla16_or1 u_cla16_or2
1- 1
-1 1
.names a[3] b[3] u_cla16_pg_logic3_or0
1- 1
-1 1
.names a[3] b[3] u_cla16_pg_logic3_and0
11 1
.names a[3] b[3] u_cla16_pg_logic3_xor0
01 1
10 1
.names u_cla16_pg_logic3_xor0 u_cla16_or2 u_cla16_xor3
01 1
10 1
.names u_cla16_pg_logic3_or0 u_cla16_pg_logic1_or0 u_cla16_and5
11 1
.names u_cla16_pg_logic0_and0 u_cla16_pg_logic2_or0 u_cla16_and6
11 1
.names u_cla16_pg_logic3_or0 u_cla16_pg_logic1_or0 u_cla16_and7
11 1
.names u_cla16_and6 u_cla16_and7 u_cla16_and8
11 1
.names u_cla16_pg_logic1_and0 u_cla16_pg_logic3_or0 u_cla16_and9
11 1
.names u_cla16_and9 u_cla16_pg_logic2_or0 u_cla16_and10
11 1
.names u_cla16_pg_logic2_and0 u_cla16_pg_logic3_or0 u_cla16_and11
11 1
.names u_cla16_and8 u_cla16_and11 u_cla16_or3
1- 1
-1 1
.names u_cla16_and10 u_cla16_or3 u_cla16_or4
1- 1
-1 1
.names u_cla16_pg_logic3_and0 u_cla16_or4 u_cla16_or5
1- 1
-1 1
.names a[4] b[4] u_cla16_pg_logic4_or0
1- 1
-1 1
.names a[4] b[4] u_cla16_pg_logic4_and0
11 1
.names a[4] b[4] u_cla16_pg_logic4_xor0
01 1
10 1
.names u_cla16_pg_logic4_xor0 u_cla16_or5 u_cla16_xor4
01 1
10 1
.names u_cla16_or5 u_cla16_pg_logic4_or0 u_cla16_and12
11 1
.names u_cla16_pg_logic4_and0 u_cla16_and12 u_cla16_or6
1- 1
-1 1
.names a[5] b[5] u_cla16_pg_logic5_or0
1- 1
-1 1
.names a[5] b[5] u_cla16_pg_logic5_and0
11 1
.names a[5] b[5] u_cla16_pg_logic5_xor0
01 1
10 1
.names u_cla16_pg_logic5_xor0 u_cla16_or6 u_cla16_xor5
01 1
10 1
.names u_cla16_or5 u_cla16_pg_logic5_or0 u_cla16_and13
11 1
.names u_cla16_and13 u_cla16_pg_logic4_or0 u_cla16_and14
11 1
.names u_cla16_pg_logic4_and0 u_cla16_pg_logic5_or0 u_cla16_and15
11 1
.names u_cla16_and14 u_cla16_and15 u_cla16_or7
1- 1
-1 1
.names u_cla16_pg_logic5_and0 u_cla16_or7 u_cla16_or8
1- 1
-1 1
.names a[6] b[6] u_cla16_pg_logic6_or0
1- 1
-1 1
.names a[6] b[6] u_cla16_pg_logic6_and0
11 1
.names a[6] b[6] u_cla16_pg_logic6_xor0
01 1
10 1
.names u_cla16_pg_logic6_xor0 u_cla16_or8 u_cla16_xor6
01 1
10 1
.names u_cla16_or5 u_cla16_pg_logic5_or0 u_cla16_and16
11 1
.names u_cla16_pg_logic6_or0 u_cla16_pg_logic4_or0 u_cla16_and17
11 1
.names u_cla16_and16 u_cla16_and17 u_cla16_and18
11 1
.names u_cla16_pg_logic4_and0 u_cla16_pg_logic6_or0 u_cla16_and19
11 1
.names u_cla16_and19 u_cla16_pg_logic5_or0 u_cla16_and20
11 1
.names u_cla16_pg_logic5_and0 u_cla16_pg_logic6_or0 u_cla16_and21
11 1
.names u_cla16_and18 u_cla16_and20 u_cla16_or9
1- 1
-1 1
.names u_cla16_or9 u_cla16_and21 u_cla16_or10
1- 1
-1 1
.names u_cla16_pg_logic6_and0 u_cla16_or10 u_cla16_or11
1- 1
-1 1
.names a[7] b[7] u_cla16_pg_logic7_or0
1- 1
-1 1
.names a[7] b[7] u_cla16_pg_logic7_and0
11 1
.names a[7] b[7] u_cla16_pg_logic7_xor0
01 1
10 1
.names u_cla16_pg_logic7_xor0 u_cla16_or11 u_cla16_xor7
01 1
10 1
.names u_cla16_or5 u_cla16_pg_logic6_or0 u_cla16_and22
11 1
.names u_cla16_pg_logic7_or0 u_cla16_pg_logic5_or0 u_cla16_and23
11 1
.names u_cla16_and22 u_cla16_and23 u_cla16_and24
11 1
.names u_cla16_and24 u_cla16_pg_logic4_or0 u_cla16_and25
11 1
.names u_cla16_pg_logic4_and0 u_cla16_pg_logic6_or0 u_cla16_and26
11 1
.names u_cla16_pg_logic7_or0 u_cla16_pg_logic5_or0 u_cla16_and27
11 1
.names u_cla16_and26 u_cla16_and27 u_cla16_and28
11 1
.names u_cla16_pg_logic5_and0 u_cla16_pg_logic7_or0 u_cla16_and29
11 1
.names u_cla16_and29 u_cla16_pg_logic6_or0 u_cla16_and30
11 1
.names u_cla16_pg_logic6_and0 u_cla16_pg_logic7_or0 u_cla16_and31
11 1
.names u_cla16_and25 u_cla16_and30 u_cla16_or12
1- 1
-1 1
.names u_cla16_and28 u_cla16_and31 u_cla16_or13
1- 1
-1 1
.names u_cla16_or12 u_cla16_or13 u_cla16_or14
1- 1
-1 1
.names u_cla16_pg_logic7_and0 u_cla16_or14 u_cla16_or15
1- 1
-1 1
.names a[8] b[8] u_cla16_pg_logic8_or0
1- 1
-1 1
.names a[8] b[8] u_cla16_pg_logic8_and0
11 1
.names a[8] b[8] u_cla16_pg_logic8_xor0
01 1
10 1
.names u_cla16_pg_logic8_xor0 u_cla16_or15 u_cla16_xor8
01 1
10 1
.names u_cla16_or15 u_cla16_pg_logic8_or0 u_cla16_and32
11 1
.names u_cla16_pg_logic8_and0 u_cla16_and32 u_cla16_or16
1- 1
-1 1
.names a[9] b[9] u_cla16_pg_logic9_or0
1- 1
-1 1
.names a[9] b[9] u_cla16_pg_logic9_and0
11 1
.names a[9] b[9] u_cla16_pg_logic9_xor0
01 1
10 1
.names u_cla16_pg_logic9_xor0 u_cla16_or16 u_cla16_xor9
01 1
10 1
.names u_cla16_or15 u_cla16_pg_logic9_or0 u_cla16_and33
11 1
.names u_cla16_and33 u_cla16_pg_logic8_or0 u_cla16_and34
11 1
.names u_cla16_pg_logic8_and0 u_cla16_pg_logic9_or0 u_cla16_and35
11 1
.names u_cla16_and34 u_cla16_and35 u_cla16_or17
1- 1
-1 1
.names u_cla16_pg_logic9_and0 u_cla16_or17 u_cla16_or18
1- 1
-1 1
.names a[10] b[10] u_cla16_pg_logic10_or0
1- 1
-1 1
.names a[10] b[10] u_cla16_pg_logic10_and0
11 1
.names a[10] b[10] u_cla16_pg_logic10_xor0
01 1
10 1
.names u_cla16_pg_logic10_xor0 u_cla16_or18 u_cla16_xor10
01 1
10 1
.names u_cla16_or15 u_cla16_pg_logic9_or0 u_cla16_and36
11 1
.names u_cla16_pg_logic10_or0 u_cla16_pg_logic8_or0 u_cla16_and37
11 1
.names u_cla16_and36 u_cla16_and37 u_cla16_and38
11 1
.names u_cla16_pg_logic8_and0 u_cla16_pg_logic10_or0 u_cla16_and39
11 1
.names u_cla16_and39 u_cla16_pg_logic9_or0 u_cla16_and40
11 1
.names u_cla16_pg_logic9_and0 u_cla16_pg_logic10_or0 u_cla16_and41
11 1
.names u_cla16_and38 u_cla16_and40 u_cla16_or19
1- 1
-1 1
.names u_cla16_or19 u_cla16_and41 u_cla16_or20
1- 1
-1 1
.names u_cla16_pg_logic10_and0 u_cla16_or20 u_cla16_or21
1- 1
-1 1
.names a[11] b[11] u_cla16_pg_logic11_or0
1- 1
-1 1
.names a[11] b[11] u_cla16_pg_logic11_and0
11 1
.names a[11] b[11] u_cla16_pg_logic11_xor0
01 1
10 1
.names u_cla16_pg_logic11_xor0 u_cla16_or21 u_cla16_xor11
01 1
10 1
.names u_cla16_or15 u_cla16_pg_logic10_or0 u_cla16_and42
11 1
.names u_cla16_pg_logic11_or0 u_cla16_pg_logic9_or0 u_cla16_and43
11 1
.names u_cla16_and42 u_cla16_and43 u_cla16_and44
11 1
.names u_cla16_and44 u_cla16_pg_logic8_or0 u_cla16_and45
11 1
.names u_cla16_pg_logic8_and0 u_cla16_pg_logic10_or0 u_cla16_and46
11 1
.names u_cla16_pg_logic11_or0 u_cla16_pg_logic9_or0 u_cla16_and47
11 1
.names u_cla16_and46 u_cla16_and47 u_cla16_and48
11 1
.names u_cla16_pg_logic9_and0 u_cla16_pg_logic11_or0 u_cla16_and49
11 1
.names u_cla16_and49 u_cla16_pg_logic10_or0 u_cla16_and50
11 1
.names u_cla16_pg_logic10_and0 u_cla16_pg_logic11_or0 u_cla16_and51
11 1
.names u_cla16_and45 u_cla16_and50 u_cla16_or22
1- 1
-1 1
.names u_cla16_and48 u_cla16_and51 u_cla16_or23
1- 1
-1 1
.names u_cla16_or22 u_cla16_or23 u_cla16_or24
1- 1
-1 1
.names u_cla16_pg_logic11_and0 u_cla16_or24 u_cla16_or25
1- 1
-1 1
.names a[12] b[12] u_cla16_pg_logic12_or0
1- 1
-1 1
.names a[12] b[12] u_cla16_pg_logic12_and0
11 1
.names a[12] b[12] u_cla16_pg_logic12_xor0
01 1
10 1
.names u_cla16_pg_logic12_xor0 u_cla16_or25 u_cla16_xor12
01 1
10 1
.names u_cla16_or25 u_cla16_pg_logic12_or0 u_cla16_and52
11 1
.names u_cla16_pg_logic12_and0 u_cla16_and52 u_cla16_or26
1- 1
-1 1
.names a[13] b[13] u_cla16_pg_logic13_or0
1- 1
-1 1
.names a[13] b[13] u_cla16_pg_logic13_and0
11 1
.names a[13] b[13] u_cla16_pg_logic13_xor0
01 1
10 1
.names u_cla16_pg_logic13_xor0 u_cla16_or26 u_cla16_xor13
01 1
10 1
.names u_cla16_or25 u_cla16_pg_logic13_or0 u_cla16_and53
11 1
.names u_cla16_and53 u_cla16_pg_logic12_or0 u_cla16_and54
11 1
.names u_cla16_pg_logic12_and0 u_cla16_pg_logic13_or0 u_cla16_and55
11 1
.names u_cla16_and54 u_cla16_and55 u_cla16_or27
1- 1
-1 1
.names u_cla16_pg_logic13_and0 u_cla16_or27 u_cla16_or28
1- 1
-1 1
.names a[14] b[14] u_cla16_pg_logic14_or0
1- 1
-1 1
.names a[14] b[14] u_cla16_pg_logic14_and0
11 1
.names a[14] b[14] u_cla16_pg_logic14_xor0
01 1
10 1
.names u_cla16_pg_logic14_xor0 u_cla16_or28 u_cla16_xor14
01 1
10 1
.names u_cla16_or25 u_cla16_pg_logic13_or0 u_cla16_and56
11 1
.names u_cla16_pg_logic14_or0 u_cla16_pg_logic12_or0 u_cla16_and57
11 1
.names u_cla16_and56 u_cla16_and57 u_cla16_and58
11 1
.names u_cla16_pg_logic12_and0 u_cla16_pg_logic14_or0 u_cla16_and59
11 1
.names u_cla16_and59 u_cla16_pg_logic13_or0 u_cla16_and60
11 1
.names u_cla16_pg_logic13_and0 u_cla16_pg_logic14_or0 u_cla16_and61
11 1
.names u_cla16_and58 u_cla16_and60 u_cla16_or29
1- 1
-1 1
.names u_cla16_or29 u_cla16_and61 u_cla16_or30
1- 1
-1 1
.names u_cla16_pg_logic14_and0 u_cla16_or30 u_cla16_or31
1- 1
-1 1
.names a[15] b[15] u_cla16_pg_logic15_or0
1- 1
-1 1
.names a[15] b[15] u_cla16_pg_logic15_and0
11 1
.names a[15] b[15] u_cla16_pg_logic15_xor0
01 1
10 1
.names u_cla16_pg_logic15_xor0 u_cla16_or31 u_cla16_xor15
01 1
10 1
.names u_cla16_or25 u_cla16_pg_logic14_or0 u_cla16_and62
11 1
.names u_cla16_pg_logic15_or0 u_cla16_pg_logic13_or0 u_cla16_and63
11 1
.names u_cla16_and62 u_cla16_and63 u_cla16_and64
11 1
.names u_cla16_and64 u_cla16_pg_logic12_or0 u_cla16_and65
11 1
.names u_cla16_pg_logic12_and0 u_cla16_pg_logic14_or0 u_cla16_and66
11 1
.names u_cla16_pg_logic15_or0 u_cla16_pg_logic13_or0 u_cla16_and67
11 1
.names u_cla16_and66 u_cla16_and67 u_cla16_and68
11 1
.names u_cla16_pg_logic13_and0 u_cla16_pg_logic15_or0 u_cla16_and69
11 1
.names u_cla16_and69 u_cla16_pg_logic14_or0 u_cla16_and70
11 1
.names u_cla16_pg_logic14_and0 u_cla16_pg_logic15_or0 u_cla16_and71
11 1
.names u_cla16_and65 u_cla16_and70 u_cla16_or32
1- 1
-1 1
.names u_cla16_and68 u_cla16_and71 u_cla16_or33
1- 1
-1 1
.names u_cla16_or32 u_cla16_or33 u_cla16_or34
1- 1
-1 1
.names u_cla16_pg_logic15_and0 u_cla16_or34 u_cla16_or35
1- 1
-1 1
.names u_cla16_pg_logic0_xor0 u_cla16_out[0]
1 1
.names u_cla16_xor1 u_cla16_out[1]
1 1
.names u_cla16_xor2 u_cla16_out[2]
1 1
.names u_cla16_xor3 u_cla16_out[3]
1 1
.names u_cla16_xor4 u_cla16_out[4]
1 1
.names u_cla16_xor5 u_cla16_out[5]
1 1
.names u_cla16_xor6 u_cla16_out[6]
1 1
.names u_cla16_xor7 u_cla16_out[7]
1 1
.names u_cla16_xor8 u_cla16_out[8]
1 1
.names u_cla16_xor9 u_cla16_out[9]
1 1
.names u_cla16_xor10 u_cla16_out[10]
1 1
.names u_cla16_xor11 u_cla16_out[11]
1 1
.names u_cla16_xor12 u_cla16_out[12]
1 1
.names u_cla16_xor13 u_cla16_out[13]
1 1
.names u_cla16_xor14 u_cla16_out[14]
1 1
.names u_cla16_xor15 u_cla16_out[15]
1 1
.names u_cla16_or35 u_cla16_out[16]
1 1
.end