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https://github.com/ehw-fit/ariths-gen.git
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96 lines
3.4 KiB
Plaintext
96 lines
3.4 KiB
Plaintext
.model u_pg_rca8
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.inputs a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7]
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.outputs u_pg_rca8_out[0] u_pg_rca8_out[1] u_pg_rca8_out[2] u_pg_rca8_out[3] u_pg_rca8_out[4] u_pg_rca8_out[5] u_pg_rca8_out[6] u_pg_rca8_out[7] u_pg_rca8_out[8]
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.names vdd
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1
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.names gnd
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0
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.subckt pg_fa a=a[0] b=b[0] cin=gnd pg_fa_xor0=u_pg_rca8_pg_fa0_xor0 pg_fa_and0=u_pg_rca8_pg_fa0_and0
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.subckt pg_fa a=a[1] b=b[1] cin=u_pg_rca8_pg_fa0_and0 pg_fa_xor0=u_pg_rca8_pg_fa1_xor0 pg_fa_and0=u_pg_rca8_pg_fa1_and0 pg_fa_xor1=u_pg_rca8_pg_fa1_xor1
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.subckt and_gate a=u_pg_rca8_pg_fa0_and0 b=u_pg_rca8_pg_fa1_xor0 out=u_pg_rca8_and1
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.subckt or_gate a=u_pg_rca8_and1 b=u_pg_rca8_pg_fa1_and0 out=u_pg_rca8_or1
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.subckt pg_fa a=a[2] b=b[2] cin=u_pg_rca8_or1 pg_fa_xor0=u_pg_rca8_pg_fa2_xor0 pg_fa_and0=u_pg_rca8_pg_fa2_and0 pg_fa_xor1=u_pg_rca8_pg_fa2_xor1
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.subckt and_gate a=u_pg_rca8_or1 b=u_pg_rca8_pg_fa2_xor0 out=u_pg_rca8_and2
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.subckt or_gate a=u_pg_rca8_and2 b=u_pg_rca8_pg_fa2_and0 out=u_pg_rca8_or2
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.subckt pg_fa a=a[3] b=b[3] cin=u_pg_rca8_or2 pg_fa_xor0=u_pg_rca8_pg_fa3_xor0 pg_fa_and0=u_pg_rca8_pg_fa3_and0 pg_fa_xor1=u_pg_rca8_pg_fa3_xor1
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.subckt and_gate a=u_pg_rca8_or2 b=u_pg_rca8_pg_fa3_xor0 out=u_pg_rca8_and3
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.subckt or_gate a=u_pg_rca8_and3 b=u_pg_rca8_pg_fa3_and0 out=u_pg_rca8_or3
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.subckt pg_fa a=a[4] b=b[4] cin=u_pg_rca8_or3 pg_fa_xor0=u_pg_rca8_pg_fa4_xor0 pg_fa_and0=u_pg_rca8_pg_fa4_and0 pg_fa_xor1=u_pg_rca8_pg_fa4_xor1
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.subckt and_gate a=u_pg_rca8_or3 b=u_pg_rca8_pg_fa4_xor0 out=u_pg_rca8_and4
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.subckt or_gate a=u_pg_rca8_and4 b=u_pg_rca8_pg_fa4_and0 out=u_pg_rca8_or4
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.subckt pg_fa a=a[5] b=b[5] cin=u_pg_rca8_or4 pg_fa_xor0=u_pg_rca8_pg_fa5_xor0 pg_fa_and0=u_pg_rca8_pg_fa5_and0 pg_fa_xor1=u_pg_rca8_pg_fa5_xor1
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.subckt and_gate a=u_pg_rca8_or4 b=u_pg_rca8_pg_fa5_xor0 out=u_pg_rca8_and5
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.subckt or_gate a=u_pg_rca8_and5 b=u_pg_rca8_pg_fa5_and0 out=u_pg_rca8_or5
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.subckt pg_fa a=a[6] b=b[6] cin=u_pg_rca8_or5 pg_fa_xor0=u_pg_rca8_pg_fa6_xor0 pg_fa_and0=u_pg_rca8_pg_fa6_and0 pg_fa_xor1=u_pg_rca8_pg_fa6_xor1
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.subckt and_gate a=u_pg_rca8_or5 b=u_pg_rca8_pg_fa6_xor0 out=u_pg_rca8_and6
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.subckt or_gate a=u_pg_rca8_and6 b=u_pg_rca8_pg_fa6_and0 out=u_pg_rca8_or6
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.subckt pg_fa a=a[7] b=b[7] cin=u_pg_rca8_or6 pg_fa_xor0=u_pg_rca8_pg_fa7_xor0 pg_fa_and0=u_pg_rca8_pg_fa7_and0 pg_fa_xor1=u_pg_rca8_pg_fa7_xor1
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.subckt and_gate a=u_pg_rca8_or6 b=u_pg_rca8_pg_fa7_xor0 out=u_pg_rca8_and7
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.subckt or_gate a=u_pg_rca8_and7 b=u_pg_rca8_pg_fa7_and0 out=u_pg_rca8_or7
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.names u_pg_rca8_pg_fa0_xor0 u_pg_rca8_out[0]
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1 1
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.names u_pg_rca8_pg_fa1_xor1 u_pg_rca8_out[1]
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1 1
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.names u_pg_rca8_pg_fa2_xor1 u_pg_rca8_out[2]
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1 1
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.names u_pg_rca8_pg_fa3_xor1 u_pg_rca8_out[3]
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1 1
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.names u_pg_rca8_pg_fa4_xor1 u_pg_rca8_out[4]
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1 1
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.names u_pg_rca8_pg_fa5_xor1 u_pg_rca8_out[5]
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1 1
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.names u_pg_rca8_pg_fa6_xor1 u_pg_rca8_out[6]
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1 1
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.names u_pg_rca8_pg_fa7_xor1 u_pg_rca8_out[7]
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1 1
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.names u_pg_rca8_or7 u_pg_rca8_out[8]
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1 1
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.end
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.model pg_fa
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.inputs a b cin
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.outputs pg_fa_xor0 pg_fa_and0 pg_fa_xor1
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.names vdd
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1
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.names gnd
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0
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.subckt xor_gate a=a b=b out=pg_fa_xor0
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.subckt and_gate a=a b=b out=pg_fa_and0
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.subckt xor_gate a=pg_fa_xor0 b=cin out=pg_fa_xor1
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.end
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.model or_gate
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.inputs a b
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.outputs out
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.names vdd
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1
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.names gnd
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0
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.names a b out
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1- 1
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-1 1
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.end
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.model and_gate
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.inputs a b
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.outputs out
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.names vdd
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1
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.names gnd
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0
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.names a b out
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11 1
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.end
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.model xor_gate
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.inputs a b
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.outputs out
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.names vdd
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1
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.names gnd
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0
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.names a b out
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01 1
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10 1
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.end
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