.model h_u_cla12
.inputs  a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] a[8] a[9] a[10] a[11] b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9] b[10] b[11]
.outputs out[0] out[1] out[2] out[3] out[4] out[5] out[6] out[7] out[8] out[9] out[10] out[11] out[12]
.names a[0] a_0
1 1
.names a[1] a_1
1 1
.names a[2] a_2
1 1
.names a[3] a_3
1 1
.names a[4] a_4
1 1
.names a[5] a_5
1 1
.names a[6] a_6
1 1
.names a[7] a_7
1 1
.names a[8] a_8
1 1
.names a[9] a_9
1 1
.names a[10] a_10
1 1
.names a[11] a_11
1 1
.names b[0] b_0
1 1
.names b[1] b_1
1 1
.names b[2] b_2
1 1
.names b[3] b_3
1 1
.names b[4] b_4
1 1
.names b[5] b_5
1 1
.names b[6] b_6
1 1
.names b[7] b_7
1 1
.names b[8] b_8
1 1
.names b[9] b_9
1 1
.names b[10] b_10
1 1
.names b[11] b_11
1 1
.names a_0 constant_wire_value_0_a_0
1 1
.names b_0 constant_wire_value_0_b_0
1 1
.subckt constant_wire_value_0 a=constant_wire_value_0_a_0 b=constant_wire_value_0_b_0 constant_wire_0=constant_wire_0
.names a_0 h_u_cla12_pg_logic0_a_0
1 1
.names b_0 h_u_cla12_pg_logic0_b_0
1 1
.subckt pg_logic a=h_u_cla12_pg_logic0_a_0 b=h_u_cla12_pg_logic0_b_0 pg_logic_y0=h_u_cla12_pg_logic0_y0 pg_logic_y1=h_u_cla12_pg_logic0_y1 pg_logic_y2=h_u_cla12_pg_logic0_y2
.names h_u_cla12_pg_logic0_y2 h_u_cla12_xor0_h_u_cla12_pg_logic0_y2
1 1
.names constant_wire_0 h_u_cla12_xor0_constant_wire_0
1 1
.subckt xor_gate _a=h_u_cla12_xor0_h_u_cla12_pg_logic0_y2 _b=h_u_cla12_xor0_constant_wire_0 _y0=h_u_cla12_xor0_y0
.names h_u_cla12_pg_logic0_y0 h_u_cla12_and0_h_u_cla12_pg_logic0_y0
1 1
.names constant_wire_0 h_u_cla12_and0_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and0_h_u_cla12_pg_logic0_y0 _b=h_u_cla12_and0_constant_wire_0 _y0=h_u_cla12_and0_y0
.names h_u_cla12_pg_logic0_y1 h_u_cla12_or0_h_u_cla12_pg_logic0_y1
1 1
.names h_u_cla12_and0_y0 h_u_cla12_or0_h_u_cla12_and0_y0
1 1
.subckt or_gate _a=h_u_cla12_or0_h_u_cla12_pg_logic0_y1 _b=h_u_cla12_or0_h_u_cla12_and0_y0 _y0=h_u_cla12_or0_y0
.names a_1 h_u_cla12_pg_logic1_a_1
1 1
.names b_1 h_u_cla12_pg_logic1_b_1
1 1
.subckt pg_logic a=h_u_cla12_pg_logic1_a_1 b=h_u_cla12_pg_logic1_b_1 pg_logic_y0=h_u_cla12_pg_logic1_y0 pg_logic_y1=h_u_cla12_pg_logic1_y1 pg_logic_y2=h_u_cla12_pg_logic1_y2
.names h_u_cla12_pg_logic1_y2 h_u_cla12_xor1_h_u_cla12_pg_logic1_y2
1 1
.names h_u_cla12_or0_y0 h_u_cla12_xor1_h_u_cla12_or0_y0
1 1
.subckt xor_gate _a=h_u_cla12_xor1_h_u_cla12_pg_logic1_y2 _b=h_u_cla12_xor1_h_u_cla12_or0_y0 _y0=h_u_cla12_xor1_y0
.names h_u_cla12_pg_logic0_y0 h_u_cla12_and1_h_u_cla12_pg_logic0_y0
1 1
.names constant_wire_0 h_u_cla12_and1_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and1_h_u_cla12_pg_logic0_y0 _b=h_u_cla12_and1_constant_wire_0 _y0=h_u_cla12_and1_y0
.names h_u_cla12_pg_logic1_y0 h_u_cla12_and2_h_u_cla12_pg_logic1_y0
1 1
.names constant_wire_0 h_u_cla12_and2_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and2_h_u_cla12_pg_logic1_y0 _b=h_u_cla12_and2_constant_wire_0 _y0=h_u_cla12_and2_y0
.names h_u_cla12_and2_y0 h_u_cla12_and3_h_u_cla12_and2_y0
1 1
.names h_u_cla12_and1_y0 h_u_cla12_and3_h_u_cla12_and1_y0
1 1
.subckt and_gate _a=h_u_cla12_and3_h_u_cla12_and2_y0 _b=h_u_cla12_and3_h_u_cla12_and1_y0 _y0=h_u_cla12_and3_y0
.names h_u_cla12_pg_logic1_y0 h_u_cla12_and4_h_u_cla12_pg_logic1_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and4_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and4_h_u_cla12_pg_logic1_y0 _b=h_u_cla12_and4_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and4_y0
.names h_u_cla12_and4_y0 h_u_cla12_or1_h_u_cla12_and4_y0
1 1
.names h_u_cla12_and3_y0 h_u_cla12_or1_h_u_cla12_and3_y0
1 1
.subckt or_gate _a=h_u_cla12_or1_h_u_cla12_and4_y0 _b=h_u_cla12_or1_h_u_cla12_and3_y0 _y0=h_u_cla12_or1_y0
.names h_u_cla12_pg_logic1_y1 h_u_cla12_or2_h_u_cla12_pg_logic1_y1
1 1
.names h_u_cla12_or1_y0 h_u_cla12_or2_h_u_cla12_or1_y0
1 1
.subckt or_gate _a=h_u_cla12_or2_h_u_cla12_pg_logic1_y1 _b=h_u_cla12_or2_h_u_cla12_or1_y0 _y0=h_u_cla12_or2_y0
.names a_2 h_u_cla12_pg_logic2_a_2
1 1
.names b_2 h_u_cla12_pg_logic2_b_2
1 1
.subckt pg_logic a=h_u_cla12_pg_logic2_a_2 b=h_u_cla12_pg_logic2_b_2 pg_logic_y0=h_u_cla12_pg_logic2_y0 pg_logic_y1=h_u_cla12_pg_logic2_y1 pg_logic_y2=h_u_cla12_pg_logic2_y2
.names h_u_cla12_pg_logic2_y2 h_u_cla12_xor2_h_u_cla12_pg_logic2_y2
1 1
.names h_u_cla12_or2_y0 h_u_cla12_xor2_h_u_cla12_or2_y0
1 1
.subckt xor_gate _a=h_u_cla12_xor2_h_u_cla12_pg_logic2_y2 _b=h_u_cla12_xor2_h_u_cla12_or2_y0 _y0=h_u_cla12_xor2_y0
.names h_u_cla12_pg_logic0_y0 h_u_cla12_and5_h_u_cla12_pg_logic0_y0
1 1
.names constant_wire_0 h_u_cla12_and5_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and5_h_u_cla12_pg_logic0_y0 _b=h_u_cla12_and5_constant_wire_0 _y0=h_u_cla12_and5_y0
.names h_u_cla12_pg_logic1_y0 h_u_cla12_and6_h_u_cla12_pg_logic1_y0
1 1
.names constant_wire_0 h_u_cla12_and6_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and6_h_u_cla12_pg_logic1_y0 _b=h_u_cla12_and6_constant_wire_0 _y0=h_u_cla12_and6_y0
.names h_u_cla12_and6_y0 h_u_cla12_and7_h_u_cla12_and6_y0
1 1
.names h_u_cla12_and5_y0 h_u_cla12_and7_h_u_cla12_and5_y0
1 1
.subckt and_gate _a=h_u_cla12_and7_h_u_cla12_and6_y0 _b=h_u_cla12_and7_h_u_cla12_and5_y0 _y0=h_u_cla12_and7_y0
.names h_u_cla12_pg_logic2_y0 h_u_cla12_and8_h_u_cla12_pg_logic2_y0
1 1
.names constant_wire_0 h_u_cla12_and8_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and8_h_u_cla12_pg_logic2_y0 _b=h_u_cla12_and8_constant_wire_0 _y0=h_u_cla12_and8_y0
.names h_u_cla12_and8_y0 h_u_cla12_and9_h_u_cla12_and8_y0
1 1
.names h_u_cla12_and7_y0 h_u_cla12_and9_h_u_cla12_and7_y0
1 1
.subckt and_gate _a=h_u_cla12_and9_h_u_cla12_and8_y0 _b=h_u_cla12_and9_h_u_cla12_and7_y0 _y0=h_u_cla12_and9_y0
.names h_u_cla12_pg_logic1_y0 h_u_cla12_and10_h_u_cla12_pg_logic1_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and10_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and10_h_u_cla12_pg_logic1_y0 _b=h_u_cla12_and10_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and10_y0
.names h_u_cla12_pg_logic2_y0 h_u_cla12_and11_h_u_cla12_pg_logic2_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and11_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and11_h_u_cla12_pg_logic2_y0 _b=h_u_cla12_and11_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and11_y0
.names h_u_cla12_and11_y0 h_u_cla12_and12_h_u_cla12_and11_y0
1 1
.names h_u_cla12_and10_y0 h_u_cla12_and12_h_u_cla12_and10_y0
1 1
.subckt and_gate _a=h_u_cla12_and12_h_u_cla12_and11_y0 _b=h_u_cla12_and12_h_u_cla12_and10_y0 _y0=h_u_cla12_and12_y0
.names h_u_cla12_pg_logic2_y0 h_u_cla12_and13_h_u_cla12_pg_logic2_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and13_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and13_h_u_cla12_pg_logic2_y0 _b=h_u_cla12_and13_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and13_y0
.names h_u_cla12_and13_y0 h_u_cla12_or3_h_u_cla12_and13_y0
1 1
.names h_u_cla12_and9_y0 h_u_cla12_or3_h_u_cla12_and9_y0
1 1
.subckt or_gate _a=h_u_cla12_or3_h_u_cla12_and13_y0 _b=h_u_cla12_or3_h_u_cla12_and9_y0 _y0=h_u_cla12_or3_y0
.names h_u_cla12_or3_y0 h_u_cla12_or4_h_u_cla12_or3_y0
1 1
.names h_u_cla12_and12_y0 h_u_cla12_or4_h_u_cla12_and12_y0
1 1
.subckt or_gate _a=h_u_cla12_or4_h_u_cla12_or3_y0 _b=h_u_cla12_or4_h_u_cla12_and12_y0 _y0=h_u_cla12_or4_y0
.names h_u_cla12_pg_logic2_y1 h_u_cla12_or5_h_u_cla12_pg_logic2_y1
1 1
.names h_u_cla12_or4_y0 h_u_cla12_or5_h_u_cla12_or4_y0
1 1
.subckt or_gate _a=h_u_cla12_or5_h_u_cla12_pg_logic2_y1 _b=h_u_cla12_or5_h_u_cla12_or4_y0 _y0=h_u_cla12_or5_y0
.names a_3 h_u_cla12_pg_logic3_a_3
1 1
.names b_3 h_u_cla12_pg_logic3_b_3
1 1
.subckt pg_logic a=h_u_cla12_pg_logic3_a_3 b=h_u_cla12_pg_logic3_b_3 pg_logic_y0=h_u_cla12_pg_logic3_y0 pg_logic_y1=h_u_cla12_pg_logic3_y1 pg_logic_y2=h_u_cla12_pg_logic3_y2
.names h_u_cla12_pg_logic3_y2 h_u_cla12_xor3_h_u_cla12_pg_logic3_y2
1 1
.names h_u_cla12_or5_y0 h_u_cla12_xor3_h_u_cla12_or5_y0
1 1
.subckt xor_gate _a=h_u_cla12_xor3_h_u_cla12_pg_logic3_y2 _b=h_u_cla12_xor3_h_u_cla12_or5_y0 _y0=h_u_cla12_xor3_y0
.names h_u_cla12_pg_logic0_y0 h_u_cla12_and14_h_u_cla12_pg_logic0_y0
1 1
.names constant_wire_0 h_u_cla12_and14_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and14_h_u_cla12_pg_logic0_y0 _b=h_u_cla12_and14_constant_wire_0 _y0=h_u_cla12_and14_y0
.names h_u_cla12_pg_logic1_y0 h_u_cla12_and15_h_u_cla12_pg_logic1_y0
1 1
.names constant_wire_0 h_u_cla12_and15_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and15_h_u_cla12_pg_logic1_y0 _b=h_u_cla12_and15_constant_wire_0 _y0=h_u_cla12_and15_y0
.names h_u_cla12_and15_y0 h_u_cla12_and16_h_u_cla12_and15_y0
1 1
.names h_u_cla12_and14_y0 h_u_cla12_and16_h_u_cla12_and14_y0
1 1
.subckt and_gate _a=h_u_cla12_and16_h_u_cla12_and15_y0 _b=h_u_cla12_and16_h_u_cla12_and14_y0 _y0=h_u_cla12_and16_y0
.names h_u_cla12_pg_logic2_y0 h_u_cla12_and17_h_u_cla12_pg_logic2_y0
1 1
.names constant_wire_0 h_u_cla12_and17_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and17_h_u_cla12_pg_logic2_y0 _b=h_u_cla12_and17_constant_wire_0 _y0=h_u_cla12_and17_y0
.names h_u_cla12_and17_y0 h_u_cla12_and18_h_u_cla12_and17_y0
1 1
.names h_u_cla12_and16_y0 h_u_cla12_and18_h_u_cla12_and16_y0
1 1
.subckt and_gate _a=h_u_cla12_and18_h_u_cla12_and17_y0 _b=h_u_cla12_and18_h_u_cla12_and16_y0 _y0=h_u_cla12_and18_y0
.names h_u_cla12_pg_logic3_y0 h_u_cla12_and19_h_u_cla12_pg_logic3_y0
1 1
.names constant_wire_0 h_u_cla12_and19_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and19_h_u_cla12_pg_logic3_y0 _b=h_u_cla12_and19_constant_wire_0 _y0=h_u_cla12_and19_y0
.names h_u_cla12_and19_y0 h_u_cla12_and20_h_u_cla12_and19_y0
1 1
.names h_u_cla12_and18_y0 h_u_cla12_and20_h_u_cla12_and18_y0
1 1
.subckt and_gate _a=h_u_cla12_and20_h_u_cla12_and19_y0 _b=h_u_cla12_and20_h_u_cla12_and18_y0 _y0=h_u_cla12_and20_y0
.names h_u_cla12_pg_logic1_y0 h_u_cla12_and21_h_u_cla12_pg_logic1_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and21_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and21_h_u_cla12_pg_logic1_y0 _b=h_u_cla12_and21_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and21_y0
.names h_u_cla12_pg_logic2_y0 h_u_cla12_and22_h_u_cla12_pg_logic2_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and22_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and22_h_u_cla12_pg_logic2_y0 _b=h_u_cla12_and22_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and22_y0
.names h_u_cla12_and22_y0 h_u_cla12_and23_h_u_cla12_and22_y0
1 1
.names h_u_cla12_and21_y0 h_u_cla12_and23_h_u_cla12_and21_y0
1 1
.subckt and_gate _a=h_u_cla12_and23_h_u_cla12_and22_y0 _b=h_u_cla12_and23_h_u_cla12_and21_y0 _y0=h_u_cla12_and23_y0
.names h_u_cla12_pg_logic3_y0 h_u_cla12_and24_h_u_cla12_pg_logic3_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and24_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and24_h_u_cla12_pg_logic3_y0 _b=h_u_cla12_and24_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and24_y0
.names h_u_cla12_and24_y0 h_u_cla12_and25_h_u_cla12_and24_y0
1 1
.names h_u_cla12_and23_y0 h_u_cla12_and25_h_u_cla12_and23_y0
1 1
.subckt and_gate _a=h_u_cla12_and25_h_u_cla12_and24_y0 _b=h_u_cla12_and25_h_u_cla12_and23_y0 _y0=h_u_cla12_and25_y0
.names h_u_cla12_pg_logic2_y0 h_u_cla12_and26_h_u_cla12_pg_logic2_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and26_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and26_h_u_cla12_pg_logic2_y0 _b=h_u_cla12_and26_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and26_y0
.names h_u_cla12_pg_logic3_y0 h_u_cla12_and27_h_u_cla12_pg_logic3_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and27_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and27_h_u_cla12_pg_logic3_y0 _b=h_u_cla12_and27_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and27_y0
.names h_u_cla12_and27_y0 h_u_cla12_and28_h_u_cla12_and27_y0
1 1
.names h_u_cla12_and26_y0 h_u_cla12_and28_h_u_cla12_and26_y0
1 1
.subckt and_gate _a=h_u_cla12_and28_h_u_cla12_and27_y0 _b=h_u_cla12_and28_h_u_cla12_and26_y0 _y0=h_u_cla12_and28_y0
.names h_u_cla12_pg_logic3_y0 h_u_cla12_and29_h_u_cla12_pg_logic3_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and29_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and29_h_u_cla12_pg_logic3_y0 _b=h_u_cla12_and29_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and29_y0
.names h_u_cla12_and29_y0 h_u_cla12_or6_h_u_cla12_and29_y0
1 1
.names h_u_cla12_and20_y0 h_u_cla12_or6_h_u_cla12_and20_y0
1 1
.subckt or_gate _a=h_u_cla12_or6_h_u_cla12_and29_y0 _b=h_u_cla12_or6_h_u_cla12_and20_y0 _y0=h_u_cla12_or6_y0
.names h_u_cla12_or6_y0 h_u_cla12_or7_h_u_cla12_or6_y0
1 1
.names h_u_cla12_and25_y0 h_u_cla12_or7_h_u_cla12_and25_y0
1 1
.subckt or_gate _a=h_u_cla12_or7_h_u_cla12_or6_y0 _b=h_u_cla12_or7_h_u_cla12_and25_y0 _y0=h_u_cla12_or7_y0
.names h_u_cla12_or7_y0 h_u_cla12_or8_h_u_cla12_or7_y0
1 1
.names h_u_cla12_and28_y0 h_u_cla12_or8_h_u_cla12_and28_y0
1 1
.subckt or_gate _a=h_u_cla12_or8_h_u_cla12_or7_y0 _b=h_u_cla12_or8_h_u_cla12_and28_y0 _y0=h_u_cla12_or8_y0
.names h_u_cla12_pg_logic3_y1 h_u_cla12_or9_h_u_cla12_pg_logic3_y1
1 1
.names h_u_cla12_or8_y0 h_u_cla12_or9_h_u_cla12_or8_y0
1 1
.subckt or_gate _a=h_u_cla12_or9_h_u_cla12_pg_logic3_y1 _b=h_u_cla12_or9_h_u_cla12_or8_y0 _y0=h_u_cla12_or9_y0
.names a_4 h_u_cla12_pg_logic4_a_4
1 1
.names b_4 h_u_cla12_pg_logic4_b_4
1 1
.subckt pg_logic a=h_u_cla12_pg_logic4_a_4 b=h_u_cla12_pg_logic4_b_4 pg_logic_y0=h_u_cla12_pg_logic4_y0 pg_logic_y1=h_u_cla12_pg_logic4_y1 pg_logic_y2=h_u_cla12_pg_logic4_y2
.names h_u_cla12_pg_logic4_y2 h_u_cla12_xor4_h_u_cla12_pg_logic4_y2
1 1
.names h_u_cla12_or9_y0 h_u_cla12_xor4_h_u_cla12_or9_y0
1 1
.subckt xor_gate _a=h_u_cla12_xor4_h_u_cla12_pg_logic4_y2 _b=h_u_cla12_xor4_h_u_cla12_or9_y0 _y0=h_u_cla12_xor4_y0
.names h_u_cla12_pg_logic0_y0 h_u_cla12_and30_h_u_cla12_pg_logic0_y0
1 1
.names constant_wire_0 h_u_cla12_and30_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and30_h_u_cla12_pg_logic0_y0 _b=h_u_cla12_and30_constant_wire_0 _y0=h_u_cla12_and30_y0
.names h_u_cla12_pg_logic1_y0 h_u_cla12_and31_h_u_cla12_pg_logic1_y0
1 1
.names constant_wire_0 h_u_cla12_and31_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and31_h_u_cla12_pg_logic1_y0 _b=h_u_cla12_and31_constant_wire_0 _y0=h_u_cla12_and31_y0
.names h_u_cla12_and31_y0 h_u_cla12_and32_h_u_cla12_and31_y0
1 1
.names h_u_cla12_and30_y0 h_u_cla12_and32_h_u_cla12_and30_y0
1 1
.subckt and_gate _a=h_u_cla12_and32_h_u_cla12_and31_y0 _b=h_u_cla12_and32_h_u_cla12_and30_y0 _y0=h_u_cla12_and32_y0
.names h_u_cla12_pg_logic2_y0 h_u_cla12_and33_h_u_cla12_pg_logic2_y0
1 1
.names constant_wire_0 h_u_cla12_and33_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and33_h_u_cla12_pg_logic2_y0 _b=h_u_cla12_and33_constant_wire_0 _y0=h_u_cla12_and33_y0
.names h_u_cla12_and33_y0 h_u_cla12_and34_h_u_cla12_and33_y0
1 1
.names h_u_cla12_and32_y0 h_u_cla12_and34_h_u_cla12_and32_y0
1 1
.subckt and_gate _a=h_u_cla12_and34_h_u_cla12_and33_y0 _b=h_u_cla12_and34_h_u_cla12_and32_y0 _y0=h_u_cla12_and34_y0
.names h_u_cla12_pg_logic3_y0 h_u_cla12_and35_h_u_cla12_pg_logic3_y0
1 1
.names constant_wire_0 h_u_cla12_and35_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and35_h_u_cla12_pg_logic3_y0 _b=h_u_cla12_and35_constant_wire_0 _y0=h_u_cla12_and35_y0
.names h_u_cla12_and35_y0 h_u_cla12_and36_h_u_cla12_and35_y0
1 1
.names h_u_cla12_and34_y0 h_u_cla12_and36_h_u_cla12_and34_y0
1 1
.subckt and_gate _a=h_u_cla12_and36_h_u_cla12_and35_y0 _b=h_u_cla12_and36_h_u_cla12_and34_y0 _y0=h_u_cla12_and36_y0
.names h_u_cla12_pg_logic4_y0 h_u_cla12_and37_h_u_cla12_pg_logic4_y0
1 1
.names constant_wire_0 h_u_cla12_and37_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and37_h_u_cla12_pg_logic4_y0 _b=h_u_cla12_and37_constant_wire_0 _y0=h_u_cla12_and37_y0
.names h_u_cla12_and37_y0 h_u_cla12_and38_h_u_cla12_and37_y0
1 1
.names h_u_cla12_and36_y0 h_u_cla12_and38_h_u_cla12_and36_y0
1 1
.subckt and_gate _a=h_u_cla12_and38_h_u_cla12_and37_y0 _b=h_u_cla12_and38_h_u_cla12_and36_y0 _y0=h_u_cla12_and38_y0
.names h_u_cla12_pg_logic1_y0 h_u_cla12_and39_h_u_cla12_pg_logic1_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and39_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and39_h_u_cla12_pg_logic1_y0 _b=h_u_cla12_and39_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and39_y0
.names h_u_cla12_pg_logic2_y0 h_u_cla12_and40_h_u_cla12_pg_logic2_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and40_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and40_h_u_cla12_pg_logic2_y0 _b=h_u_cla12_and40_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and40_y0
.names h_u_cla12_and40_y0 h_u_cla12_and41_h_u_cla12_and40_y0
1 1
.names h_u_cla12_and39_y0 h_u_cla12_and41_h_u_cla12_and39_y0
1 1
.subckt and_gate _a=h_u_cla12_and41_h_u_cla12_and40_y0 _b=h_u_cla12_and41_h_u_cla12_and39_y0 _y0=h_u_cla12_and41_y0
.names h_u_cla12_pg_logic3_y0 h_u_cla12_and42_h_u_cla12_pg_logic3_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and42_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and42_h_u_cla12_pg_logic3_y0 _b=h_u_cla12_and42_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and42_y0
.names h_u_cla12_and42_y0 h_u_cla12_and43_h_u_cla12_and42_y0
1 1
.names h_u_cla12_and41_y0 h_u_cla12_and43_h_u_cla12_and41_y0
1 1
.subckt and_gate _a=h_u_cla12_and43_h_u_cla12_and42_y0 _b=h_u_cla12_and43_h_u_cla12_and41_y0 _y0=h_u_cla12_and43_y0
.names h_u_cla12_pg_logic4_y0 h_u_cla12_and44_h_u_cla12_pg_logic4_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and44_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and44_h_u_cla12_pg_logic4_y0 _b=h_u_cla12_and44_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and44_y0
.names h_u_cla12_and44_y0 h_u_cla12_and45_h_u_cla12_and44_y0
1 1
.names h_u_cla12_and43_y0 h_u_cla12_and45_h_u_cla12_and43_y0
1 1
.subckt and_gate _a=h_u_cla12_and45_h_u_cla12_and44_y0 _b=h_u_cla12_and45_h_u_cla12_and43_y0 _y0=h_u_cla12_and45_y0
.names h_u_cla12_pg_logic2_y0 h_u_cla12_and46_h_u_cla12_pg_logic2_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and46_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and46_h_u_cla12_pg_logic2_y0 _b=h_u_cla12_and46_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and46_y0
.names h_u_cla12_pg_logic3_y0 h_u_cla12_and47_h_u_cla12_pg_logic3_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and47_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and47_h_u_cla12_pg_logic3_y0 _b=h_u_cla12_and47_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and47_y0
.names h_u_cla12_and47_y0 h_u_cla12_and48_h_u_cla12_and47_y0
1 1
.names h_u_cla12_and46_y0 h_u_cla12_and48_h_u_cla12_and46_y0
1 1
.subckt and_gate _a=h_u_cla12_and48_h_u_cla12_and47_y0 _b=h_u_cla12_and48_h_u_cla12_and46_y0 _y0=h_u_cla12_and48_y0
.names h_u_cla12_pg_logic4_y0 h_u_cla12_and49_h_u_cla12_pg_logic4_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and49_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and49_h_u_cla12_pg_logic4_y0 _b=h_u_cla12_and49_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and49_y0
.names h_u_cla12_and49_y0 h_u_cla12_and50_h_u_cla12_and49_y0
1 1
.names h_u_cla12_and48_y0 h_u_cla12_and50_h_u_cla12_and48_y0
1 1
.subckt and_gate _a=h_u_cla12_and50_h_u_cla12_and49_y0 _b=h_u_cla12_and50_h_u_cla12_and48_y0 _y0=h_u_cla12_and50_y0
.names h_u_cla12_pg_logic3_y0 h_u_cla12_and51_h_u_cla12_pg_logic3_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and51_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and51_h_u_cla12_pg_logic3_y0 _b=h_u_cla12_and51_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and51_y0
.names h_u_cla12_pg_logic4_y0 h_u_cla12_and52_h_u_cla12_pg_logic4_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and52_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and52_h_u_cla12_pg_logic4_y0 _b=h_u_cla12_and52_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and52_y0
.names h_u_cla12_and52_y0 h_u_cla12_and53_h_u_cla12_and52_y0
1 1
.names h_u_cla12_and51_y0 h_u_cla12_and53_h_u_cla12_and51_y0
1 1
.subckt and_gate _a=h_u_cla12_and53_h_u_cla12_and52_y0 _b=h_u_cla12_and53_h_u_cla12_and51_y0 _y0=h_u_cla12_and53_y0
.names h_u_cla12_pg_logic4_y0 h_u_cla12_and54_h_u_cla12_pg_logic4_y0
1 1
.names h_u_cla12_pg_logic3_y1 h_u_cla12_and54_h_u_cla12_pg_logic3_y1
1 1
.subckt and_gate _a=h_u_cla12_and54_h_u_cla12_pg_logic4_y0 _b=h_u_cla12_and54_h_u_cla12_pg_logic3_y1 _y0=h_u_cla12_and54_y0
.names h_u_cla12_and54_y0 h_u_cla12_or10_h_u_cla12_and54_y0
1 1
.names h_u_cla12_and38_y0 h_u_cla12_or10_h_u_cla12_and38_y0
1 1
.subckt or_gate _a=h_u_cla12_or10_h_u_cla12_and54_y0 _b=h_u_cla12_or10_h_u_cla12_and38_y0 _y0=h_u_cla12_or10_y0
.names h_u_cla12_or10_y0 h_u_cla12_or11_h_u_cla12_or10_y0
1 1
.names h_u_cla12_and45_y0 h_u_cla12_or11_h_u_cla12_and45_y0
1 1
.subckt or_gate _a=h_u_cla12_or11_h_u_cla12_or10_y0 _b=h_u_cla12_or11_h_u_cla12_and45_y0 _y0=h_u_cla12_or11_y0
.names h_u_cla12_or11_y0 h_u_cla12_or12_h_u_cla12_or11_y0
1 1
.names h_u_cla12_and50_y0 h_u_cla12_or12_h_u_cla12_and50_y0
1 1
.subckt or_gate _a=h_u_cla12_or12_h_u_cla12_or11_y0 _b=h_u_cla12_or12_h_u_cla12_and50_y0 _y0=h_u_cla12_or12_y0
.names h_u_cla12_or12_y0 h_u_cla12_or13_h_u_cla12_or12_y0
1 1
.names h_u_cla12_and53_y0 h_u_cla12_or13_h_u_cla12_and53_y0
1 1
.subckt or_gate _a=h_u_cla12_or13_h_u_cla12_or12_y0 _b=h_u_cla12_or13_h_u_cla12_and53_y0 _y0=h_u_cla12_or13_y0
.names h_u_cla12_pg_logic4_y1 h_u_cla12_or14_h_u_cla12_pg_logic4_y1
1 1
.names h_u_cla12_or13_y0 h_u_cla12_or14_h_u_cla12_or13_y0
1 1
.subckt or_gate _a=h_u_cla12_or14_h_u_cla12_pg_logic4_y1 _b=h_u_cla12_or14_h_u_cla12_or13_y0 _y0=h_u_cla12_or14_y0
.names a_5 h_u_cla12_pg_logic5_a_5
1 1
.names b_5 h_u_cla12_pg_logic5_b_5
1 1
.subckt pg_logic a=h_u_cla12_pg_logic5_a_5 b=h_u_cla12_pg_logic5_b_5 pg_logic_y0=h_u_cla12_pg_logic5_y0 pg_logic_y1=h_u_cla12_pg_logic5_y1 pg_logic_y2=h_u_cla12_pg_logic5_y2
.names h_u_cla12_pg_logic5_y2 h_u_cla12_xor5_h_u_cla12_pg_logic5_y2
1 1
.names h_u_cla12_or14_y0 h_u_cla12_xor5_h_u_cla12_or14_y0
1 1
.subckt xor_gate _a=h_u_cla12_xor5_h_u_cla12_pg_logic5_y2 _b=h_u_cla12_xor5_h_u_cla12_or14_y0 _y0=h_u_cla12_xor5_y0
.names h_u_cla12_pg_logic0_y0 h_u_cla12_and55_h_u_cla12_pg_logic0_y0
1 1
.names constant_wire_0 h_u_cla12_and55_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and55_h_u_cla12_pg_logic0_y0 _b=h_u_cla12_and55_constant_wire_0 _y0=h_u_cla12_and55_y0
.names h_u_cla12_pg_logic1_y0 h_u_cla12_and56_h_u_cla12_pg_logic1_y0
1 1
.names constant_wire_0 h_u_cla12_and56_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and56_h_u_cla12_pg_logic1_y0 _b=h_u_cla12_and56_constant_wire_0 _y0=h_u_cla12_and56_y0
.names h_u_cla12_and56_y0 h_u_cla12_and57_h_u_cla12_and56_y0
1 1
.names h_u_cla12_and55_y0 h_u_cla12_and57_h_u_cla12_and55_y0
1 1
.subckt and_gate _a=h_u_cla12_and57_h_u_cla12_and56_y0 _b=h_u_cla12_and57_h_u_cla12_and55_y0 _y0=h_u_cla12_and57_y0
.names h_u_cla12_pg_logic2_y0 h_u_cla12_and58_h_u_cla12_pg_logic2_y0
1 1
.names constant_wire_0 h_u_cla12_and58_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and58_h_u_cla12_pg_logic2_y0 _b=h_u_cla12_and58_constant_wire_0 _y0=h_u_cla12_and58_y0
.names h_u_cla12_and58_y0 h_u_cla12_and59_h_u_cla12_and58_y0
1 1
.names h_u_cla12_and57_y0 h_u_cla12_and59_h_u_cla12_and57_y0
1 1
.subckt and_gate _a=h_u_cla12_and59_h_u_cla12_and58_y0 _b=h_u_cla12_and59_h_u_cla12_and57_y0 _y0=h_u_cla12_and59_y0
.names h_u_cla12_pg_logic3_y0 h_u_cla12_and60_h_u_cla12_pg_logic3_y0
1 1
.names constant_wire_0 h_u_cla12_and60_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and60_h_u_cla12_pg_logic3_y0 _b=h_u_cla12_and60_constant_wire_0 _y0=h_u_cla12_and60_y0
.names h_u_cla12_and60_y0 h_u_cla12_and61_h_u_cla12_and60_y0
1 1
.names h_u_cla12_and59_y0 h_u_cla12_and61_h_u_cla12_and59_y0
1 1
.subckt and_gate _a=h_u_cla12_and61_h_u_cla12_and60_y0 _b=h_u_cla12_and61_h_u_cla12_and59_y0 _y0=h_u_cla12_and61_y0
.names h_u_cla12_pg_logic4_y0 h_u_cla12_and62_h_u_cla12_pg_logic4_y0
1 1
.names constant_wire_0 h_u_cla12_and62_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and62_h_u_cla12_pg_logic4_y0 _b=h_u_cla12_and62_constant_wire_0 _y0=h_u_cla12_and62_y0
.names h_u_cla12_and62_y0 h_u_cla12_and63_h_u_cla12_and62_y0
1 1
.names h_u_cla12_and61_y0 h_u_cla12_and63_h_u_cla12_and61_y0
1 1
.subckt and_gate _a=h_u_cla12_and63_h_u_cla12_and62_y0 _b=h_u_cla12_and63_h_u_cla12_and61_y0 _y0=h_u_cla12_and63_y0
.names h_u_cla12_pg_logic5_y0 h_u_cla12_and64_h_u_cla12_pg_logic5_y0
1 1
.names constant_wire_0 h_u_cla12_and64_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and64_h_u_cla12_pg_logic5_y0 _b=h_u_cla12_and64_constant_wire_0 _y0=h_u_cla12_and64_y0
.names h_u_cla12_and64_y0 h_u_cla12_and65_h_u_cla12_and64_y0
1 1
.names h_u_cla12_and63_y0 h_u_cla12_and65_h_u_cla12_and63_y0
1 1
.subckt and_gate _a=h_u_cla12_and65_h_u_cla12_and64_y0 _b=h_u_cla12_and65_h_u_cla12_and63_y0 _y0=h_u_cla12_and65_y0
.names h_u_cla12_pg_logic1_y0 h_u_cla12_and66_h_u_cla12_pg_logic1_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and66_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and66_h_u_cla12_pg_logic1_y0 _b=h_u_cla12_and66_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and66_y0
.names h_u_cla12_pg_logic2_y0 h_u_cla12_and67_h_u_cla12_pg_logic2_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and67_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and67_h_u_cla12_pg_logic2_y0 _b=h_u_cla12_and67_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and67_y0
.names h_u_cla12_and67_y0 h_u_cla12_and68_h_u_cla12_and67_y0
1 1
.names h_u_cla12_and66_y0 h_u_cla12_and68_h_u_cla12_and66_y0
1 1
.subckt and_gate _a=h_u_cla12_and68_h_u_cla12_and67_y0 _b=h_u_cla12_and68_h_u_cla12_and66_y0 _y0=h_u_cla12_and68_y0
.names h_u_cla12_pg_logic3_y0 h_u_cla12_and69_h_u_cla12_pg_logic3_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and69_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and69_h_u_cla12_pg_logic3_y0 _b=h_u_cla12_and69_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and69_y0
.names h_u_cla12_and69_y0 h_u_cla12_and70_h_u_cla12_and69_y0
1 1
.names h_u_cla12_and68_y0 h_u_cla12_and70_h_u_cla12_and68_y0
1 1
.subckt and_gate _a=h_u_cla12_and70_h_u_cla12_and69_y0 _b=h_u_cla12_and70_h_u_cla12_and68_y0 _y0=h_u_cla12_and70_y0
.names h_u_cla12_pg_logic4_y0 h_u_cla12_and71_h_u_cla12_pg_logic4_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and71_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and71_h_u_cla12_pg_logic4_y0 _b=h_u_cla12_and71_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and71_y0
.names h_u_cla12_and71_y0 h_u_cla12_and72_h_u_cla12_and71_y0
1 1
.names h_u_cla12_and70_y0 h_u_cla12_and72_h_u_cla12_and70_y0
1 1
.subckt and_gate _a=h_u_cla12_and72_h_u_cla12_and71_y0 _b=h_u_cla12_and72_h_u_cla12_and70_y0 _y0=h_u_cla12_and72_y0
.names h_u_cla12_pg_logic5_y0 h_u_cla12_and73_h_u_cla12_pg_logic5_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and73_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and73_h_u_cla12_pg_logic5_y0 _b=h_u_cla12_and73_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and73_y0
.names h_u_cla12_and73_y0 h_u_cla12_and74_h_u_cla12_and73_y0
1 1
.names h_u_cla12_and72_y0 h_u_cla12_and74_h_u_cla12_and72_y0
1 1
.subckt and_gate _a=h_u_cla12_and74_h_u_cla12_and73_y0 _b=h_u_cla12_and74_h_u_cla12_and72_y0 _y0=h_u_cla12_and74_y0
.names h_u_cla12_pg_logic2_y0 h_u_cla12_and75_h_u_cla12_pg_logic2_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and75_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and75_h_u_cla12_pg_logic2_y0 _b=h_u_cla12_and75_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and75_y0
.names h_u_cla12_pg_logic3_y0 h_u_cla12_and76_h_u_cla12_pg_logic3_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and76_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and76_h_u_cla12_pg_logic3_y0 _b=h_u_cla12_and76_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and76_y0
.names h_u_cla12_and76_y0 h_u_cla12_and77_h_u_cla12_and76_y0
1 1
.names h_u_cla12_and75_y0 h_u_cla12_and77_h_u_cla12_and75_y0
1 1
.subckt and_gate _a=h_u_cla12_and77_h_u_cla12_and76_y0 _b=h_u_cla12_and77_h_u_cla12_and75_y0 _y0=h_u_cla12_and77_y0
.names h_u_cla12_pg_logic4_y0 h_u_cla12_and78_h_u_cla12_pg_logic4_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and78_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and78_h_u_cla12_pg_logic4_y0 _b=h_u_cla12_and78_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and78_y0
.names h_u_cla12_and78_y0 h_u_cla12_and79_h_u_cla12_and78_y0
1 1
.names h_u_cla12_and77_y0 h_u_cla12_and79_h_u_cla12_and77_y0
1 1
.subckt and_gate _a=h_u_cla12_and79_h_u_cla12_and78_y0 _b=h_u_cla12_and79_h_u_cla12_and77_y0 _y0=h_u_cla12_and79_y0
.names h_u_cla12_pg_logic5_y0 h_u_cla12_and80_h_u_cla12_pg_logic5_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and80_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and80_h_u_cla12_pg_logic5_y0 _b=h_u_cla12_and80_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and80_y0
.names h_u_cla12_and80_y0 h_u_cla12_and81_h_u_cla12_and80_y0
1 1
.names h_u_cla12_and79_y0 h_u_cla12_and81_h_u_cla12_and79_y0
1 1
.subckt and_gate _a=h_u_cla12_and81_h_u_cla12_and80_y0 _b=h_u_cla12_and81_h_u_cla12_and79_y0 _y0=h_u_cla12_and81_y0
.names h_u_cla12_pg_logic3_y0 h_u_cla12_and82_h_u_cla12_pg_logic3_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and82_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and82_h_u_cla12_pg_logic3_y0 _b=h_u_cla12_and82_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and82_y0
.names h_u_cla12_pg_logic4_y0 h_u_cla12_and83_h_u_cla12_pg_logic4_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and83_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and83_h_u_cla12_pg_logic4_y0 _b=h_u_cla12_and83_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and83_y0
.names h_u_cla12_and83_y0 h_u_cla12_and84_h_u_cla12_and83_y0
1 1
.names h_u_cla12_and82_y0 h_u_cla12_and84_h_u_cla12_and82_y0
1 1
.subckt and_gate _a=h_u_cla12_and84_h_u_cla12_and83_y0 _b=h_u_cla12_and84_h_u_cla12_and82_y0 _y0=h_u_cla12_and84_y0
.names h_u_cla12_pg_logic5_y0 h_u_cla12_and85_h_u_cla12_pg_logic5_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and85_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and85_h_u_cla12_pg_logic5_y0 _b=h_u_cla12_and85_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and85_y0
.names h_u_cla12_and85_y0 h_u_cla12_and86_h_u_cla12_and85_y0
1 1
.names h_u_cla12_and84_y0 h_u_cla12_and86_h_u_cla12_and84_y0
1 1
.subckt and_gate _a=h_u_cla12_and86_h_u_cla12_and85_y0 _b=h_u_cla12_and86_h_u_cla12_and84_y0 _y0=h_u_cla12_and86_y0
.names h_u_cla12_pg_logic4_y0 h_u_cla12_and87_h_u_cla12_pg_logic4_y0
1 1
.names h_u_cla12_pg_logic3_y1 h_u_cla12_and87_h_u_cla12_pg_logic3_y1
1 1
.subckt and_gate _a=h_u_cla12_and87_h_u_cla12_pg_logic4_y0 _b=h_u_cla12_and87_h_u_cla12_pg_logic3_y1 _y0=h_u_cla12_and87_y0
.names h_u_cla12_pg_logic5_y0 h_u_cla12_and88_h_u_cla12_pg_logic5_y0
1 1
.names h_u_cla12_pg_logic3_y1 h_u_cla12_and88_h_u_cla12_pg_logic3_y1
1 1
.subckt and_gate _a=h_u_cla12_and88_h_u_cla12_pg_logic5_y0 _b=h_u_cla12_and88_h_u_cla12_pg_logic3_y1 _y0=h_u_cla12_and88_y0
.names h_u_cla12_and88_y0 h_u_cla12_and89_h_u_cla12_and88_y0
1 1
.names h_u_cla12_and87_y0 h_u_cla12_and89_h_u_cla12_and87_y0
1 1
.subckt and_gate _a=h_u_cla12_and89_h_u_cla12_and88_y0 _b=h_u_cla12_and89_h_u_cla12_and87_y0 _y0=h_u_cla12_and89_y0
.names h_u_cla12_pg_logic5_y0 h_u_cla12_and90_h_u_cla12_pg_logic5_y0
1 1
.names h_u_cla12_pg_logic4_y1 h_u_cla12_and90_h_u_cla12_pg_logic4_y1
1 1
.subckt and_gate _a=h_u_cla12_and90_h_u_cla12_pg_logic5_y0 _b=h_u_cla12_and90_h_u_cla12_pg_logic4_y1 _y0=h_u_cla12_and90_y0
.names h_u_cla12_and90_y0 h_u_cla12_or15_h_u_cla12_and90_y0
1 1
.names h_u_cla12_and65_y0 h_u_cla12_or15_h_u_cla12_and65_y0
1 1
.subckt or_gate _a=h_u_cla12_or15_h_u_cla12_and90_y0 _b=h_u_cla12_or15_h_u_cla12_and65_y0 _y0=h_u_cla12_or15_y0
.names h_u_cla12_or15_y0 h_u_cla12_or16_h_u_cla12_or15_y0
1 1
.names h_u_cla12_and74_y0 h_u_cla12_or16_h_u_cla12_and74_y0
1 1
.subckt or_gate _a=h_u_cla12_or16_h_u_cla12_or15_y0 _b=h_u_cla12_or16_h_u_cla12_and74_y0 _y0=h_u_cla12_or16_y0
.names h_u_cla12_or16_y0 h_u_cla12_or17_h_u_cla12_or16_y0
1 1
.names h_u_cla12_and81_y0 h_u_cla12_or17_h_u_cla12_and81_y0
1 1
.subckt or_gate _a=h_u_cla12_or17_h_u_cla12_or16_y0 _b=h_u_cla12_or17_h_u_cla12_and81_y0 _y0=h_u_cla12_or17_y0
.names h_u_cla12_or17_y0 h_u_cla12_or18_h_u_cla12_or17_y0
1 1
.names h_u_cla12_and86_y0 h_u_cla12_or18_h_u_cla12_and86_y0
1 1
.subckt or_gate _a=h_u_cla12_or18_h_u_cla12_or17_y0 _b=h_u_cla12_or18_h_u_cla12_and86_y0 _y0=h_u_cla12_or18_y0
.names h_u_cla12_or18_y0 h_u_cla12_or19_h_u_cla12_or18_y0
1 1
.names h_u_cla12_and89_y0 h_u_cla12_or19_h_u_cla12_and89_y0
1 1
.subckt or_gate _a=h_u_cla12_or19_h_u_cla12_or18_y0 _b=h_u_cla12_or19_h_u_cla12_and89_y0 _y0=h_u_cla12_or19_y0
.names h_u_cla12_pg_logic5_y1 h_u_cla12_or20_h_u_cla12_pg_logic5_y1
1 1
.names h_u_cla12_or19_y0 h_u_cla12_or20_h_u_cla12_or19_y0
1 1
.subckt or_gate _a=h_u_cla12_or20_h_u_cla12_pg_logic5_y1 _b=h_u_cla12_or20_h_u_cla12_or19_y0 _y0=h_u_cla12_or20_y0
.names a_6 h_u_cla12_pg_logic6_a_6
1 1
.names b_6 h_u_cla12_pg_logic6_b_6
1 1
.subckt pg_logic a=h_u_cla12_pg_logic6_a_6 b=h_u_cla12_pg_logic6_b_6 pg_logic_y0=h_u_cla12_pg_logic6_y0 pg_logic_y1=h_u_cla12_pg_logic6_y1 pg_logic_y2=h_u_cla12_pg_logic6_y2
.names h_u_cla12_pg_logic6_y2 h_u_cla12_xor6_h_u_cla12_pg_logic6_y2
1 1
.names h_u_cla12_or20_y0 h_u_cla12_xor6_h_u_cla12_or20_y0
1 1
.subckt xor_gate _a=h_u_cla12_xor6_h_u_cla12_pg_logic6_y2 _b=h_u_cla12_xor6_h_u_cla12_or20_y0 _y0=h_u_cla12_xor6_y0
.names h_u_cla12_pg_logic0_y0 h_u_cla12_and91_h_u_cla12_pg_logic0_y0
1 1
.names constant_wire_0 h_u_cla12_and91_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and91_h_u_cla12_pg_logic0_y0 _b=h_u_cla12_and91_constant_wire_0 _y0=h_u_cla12_and91_y0
.names h_u_cla12_pg_logic1_y0 h_u_cla12_and92_h_u_cla12_pg_logic1_y0
1 1
.names constant_wire_0 h_u_cla12_and92_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and92_h_u_cla12_pg_logic1_y0 _b=h_u_cla12_and92_constant_wire_0 _y0=h_u_cla12_and92_y0
.names h_u_cla12_and92_y0 h_u_cla12_and93_h_u_cla12_and92_y0
1 1
.names h_u_cla12_and91_y0 h_u_cla12_and93_h_u_cla12_and91_y0
1 1
.subckt and_gate _a=h_u_cla12_and93_h_u_cla12_and92_y0 _b=h_u_cla12_and93_h_u_cla12_and91_y0 _y0=h_u_cla12_and93_y0
.names h_u_cla12_pg_logic2_y0 h_u_cla12_and94_h_u_cla12_pg_logic2_y0
1 1
.names constant_wire_0 h_u_cla12_and94_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and94_h_u_cla12_pg_logic2_y0 _b=h_u_cla12_and94_constant_wire_0 _y0=h_u_cla12_and94_y0
.names h_u_cla12_and94_y0 h_u_cla12_and95_h_u_cla12_and94_y0
1 1
.names h_u_cla12_and93_y0 h_u_cla12_and95_h_u_cla12_and93_y0
1 1
.subckt and_gate _a=h_u_cla12_and95_h_u_cla12_and94_y0 _b=h_u_cla12_and95_h_u_cla12_and93_y0 _y0=h_u_cla12_and95_y0
.names h_u_cla12_pg_logic3_y0 h_u_cla12_and96_h_u_cla12_pg_logic3_y0
1 1
.names constant_wire_0 h_u_cla12_and96_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and96_h_u_cla12_pg_logic3_y0 _b=h_u_cla12_and96_constant_wire_0 _y0=h_u_cla12_and96_y0
.names h_u_cla12_and96_y0 h_u_cla12_and97_h_u_cla12_and96_y0
1 1
.names h_u_cla12_and95_y0 h_u_cla12_and97_h_u_cla12_and95_y0
1 1
.subckt and_gate _a=h_u_cla12_and97_h_u_cla12_and96_y0 _b=h_u_cla12_and97_h_u_cla12_and95_y0 _y0=h_u_cla12_and97_y0
.names h_u_cla12_pg_logic4_y0 h_u_cla12_and98_h_u_cla12_pg_logic4_y0
1 1
.names constant_wire_0 h_u_cla12_and98_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and98_h_u_cla12_pg_logic4_y0 _b=h_u_cla12_and98_constant_wire_0 _y0=h_u_cla12_and98_y0
.names h_u_cla12_and98_y0 h_u_cla12_and99_h_u_cla12_and98_y0
1 1
.names h_u_cla12_and97_y0 h_u_cla12_and99_h_u_cla12_and97_y0
1 1
.subckt and_gate _a=h_u_cla12_and99_h_u_cla12_and98_y0 _b=h_u_cla12_and99_h_u_cla12_and97_y0 _y0=h_u_cla12_and99_y0
.names h_u_cla12_pg_logic5_y0 h_u_cla12_and100_h_u_cla12_pg_logic5_y0
1 1
.names constant_wire_0 h_u_cla12_and100_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and100_h_u_cla12_pg_logic5_y0 _b=h_u_cla12_and100_constant_wire_0 _y0=h_u_cla12_and100_y0
.names h_u_cla12_and100_y0 h_u_cla12_and101_h_u_cla12_and100_y0
1 1
.names h_u_cla12_and99_y0 h_u_cla12_and101_h_u_cla12_and99_y0
1 1
.subckt and_gate _a=h_u_cla12_and101_h_u_cla12_and100_y0 _b=h_u_cla12_and101_h_u_cla12_and99_y0 _y0=h_u_cla12_and101_y0
.names h_u_cla12_pg_logic6_y0 h_u_cla12_and102_h_u_cla12_pg_logic6_y0
1 1
.names constant_wire_0 h_u_cla12_and102_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and102_h_u_cla12_pg_logic6_y0 _b=h_u_cla12_and102_constant_wire_0 _y0=h_u_cla12_and102_y0
.names h_u_cla12_and102_y0 h_u_cla12_and103_h_u_cla12_and102_y0
1 1
.names h_u_cla12_and101_y0 h_u_cla12_and103_h_u_cla12_and101_y0
1 1
.subckt and_gate _a=h_u_cla12_and103_h_u_cla12_and102_y0 _b=h_u_cla12_and103_h_u_cla12_and101_y0 _y0=h_u_cla12_and103_y0
.names h_u_cla12_pg_logic1_y0 h_u_cla12_and104_h_u_cla12_pg_logic1_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and104_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and104_h_u_cla12_pg_logic1_y0 _b=h_u_cla12_and104_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and104_y0
.names h_u_cla12_pg_logic2_y0 h_u_cla12_and105_h_u_cla12_pg_logic2_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and105_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and105_h_u_cla12_pg_logic2_y0 _b=h_u_cla12_and105_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and105_y0
.names h_u_cla12_and105_y0 h_u_cla12_and106_h_u_cla12_and105_y0
1 1
.names h_u_cla12_and104_y0 h_u_cla12_and106_h_u_cla12_and104_y0
1 1
.subckt and_gate _a=h_u_cla12_and106_h_u_cla12_and105_y0 _b=h_u_cla12_and106_h_u_cla12_and104_y0 _y0=h_u_cla12_and106_y0
.names h_u_cla12_pg_logic3_y0 h_u_cla12_and107_h_u_cla12_pg_logic3_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and107_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and107_h_u_cla12_pg_logic3_y0 _b=h_u_cla12_and107_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and107_y0
.names h_u_cla12_and107_y0 h_u_cla12_and108_h_u_cla12_and107_y0
1 1
.names h_u_cla12_and106_y0 h_u_cla12_and108_h_u_cla12_and106_y0
1 1
.subckt and_gate _a=h_u_cla12_and108_h_u_cla12_and107_y0 _b=h_u_cla12_and108_h_u_cla12_and106_y0 _y0=h_u_cla12_and108_y0
.names h_u_cla12_pg_logic4_y0 h_u_cla12_and109_h_u_cla12_pg_logic4_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and109_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and109_h_u_cla12_pg_logic4_y0 _b=h_u_cla12_and109_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and109_y0
.names h_u_cla12_and109_y0 h_u_cla12_and110_h_u_cla12_and109_y0
1 1
.names h_u_cla12_and108_y0 h_u_cla12_and110_h_u_cla12_and108_y0
1 1
.subckt and_gate _a=h_u_cla12_and110_h_u_cla12_and109_y0 _b=h_u_cla12_and110_h_u_cla12_and108_y0 _y0=h_u_cla12_and110_y0
.names h_u_cla12_pg_logic5_y0 h_u_cla12_and111_h_u_cla12_pg_logic5_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and111_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and111_h_u_cla12_pg_logic5_y0 _b=h_u_cla12_and111_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and111_y0
.names h_u_cla12_and111_y0 h_u_cla12_and112_h_u_cla12_and111_y0
1 1
.names h_u_cla12_and110_y0 h_u_cla12_and112_h_u_cla12_and110_y0
1 1
.subckt and_gate _a=h_u_cla12_and112_h_u_cla12_and111_y0 _b=h_u_cla12_and112_h_u_cla12_and110_y0 _y0=h_u_cla12_and112_y0
.names h_u_cla12_pg_logic6_y0 h_u_cla12_and113_h_u_cla12_pg_logic6_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and113_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and113_h_u_cla12_pg_logic6_y0 _b=h_u_cla12_and113_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and113_y0
.names h_u_cla12_and113_y0 h_u_cla12_and114_h_u_cla12_and113_y0
1 1
.names h_u_cla12_and112_y0 h_u_cla12_and114_h_u_cla12_and112_y0
1 1
.subckt and_gate _a=h_u_cla12_and114_h_u_cla12_and113_y0 _b=h_u_cla12_and114_h_u_cla12_and112_y0 _y0=h_u_cla12_and114_y0
.names h_u_cla12_pg_logic2_y0 h_u_cla12_and115_h_u_cla12_pg_logic2_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and115_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and115_h_u_cla12_pg_logic2_y0 _b=h_u_cla12_and115_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and115_y0
.names h_u_cla12_pg_logic3_y0 h_u_cla12_and116_h_u_cla12_pg_logic3_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and116_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and116_h_u_cla12_pg_logic3_y0 _b=h_u_cla12_and116_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and116_y0
.names h_u_cla12_and116_y0 h_u_cla12_and117_h_u_cla12_and116_y0
1 1
.names h_u_cla12_and115_y0 h_u_cla12_and117_h_u_cla12_and115_y0
1 1
.subckt and_gate _a=h_u_cla12_and117_h_u_cla12_and116_y0 _b=h_u_cla12_and117_h_u_cla12_and115_y0 _y0=h_u_cla12_and117_y0
.names h_u_cla12_pg_logic4_y0 h_u_cla12_and118_h_u_cla12_pg_logic4_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and118_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and118_h_u_cla12_pg_logic4_y0 _b=h_u_cla12_and118_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and118_y0
.names h_u_cla12_and118_y0 h_u_cla12_and119_h_u_cla12_and118_y0
1 1
.names h_u_cla12_and117_y0 h_u_cla12_and119_h_u_cla12_and117_y0
1 1
.subckt and_gate _a=h_u_cla12_and119_h_u_cla12_and118_y0 _b=h_u_cla12_and119_h_u_cla12_and117_y0 _y0=h_u_cla12_and119_y0
.names h_u_cla12_pg_logic5_y0 h_u_cla12_and120_h_u_cla12_pg_logic5_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and120_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and120_h_u_cla12_pg_logic5_y0 _b=h_u_cla12_and120_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and120_y0
.names h_u_cla12_and120_y0 h_u_cla12_and121_h_u_cla12_and120_y0
1 1
.names h_u_cla12_and119_y0 h_u_cla12_and121_h_u_cla12_and119_y0
1 1
.subckt and_gate _a=h_u_cla12_and121_h_u_cla12_and120_y0 _b=h_u_cla12_and121_h_u_cla12_and119_y0 _y0=h_u_cla12_and121_y0
.names h_u_cla12_pg_logic6_y0 h_u_cla12_and122_h_u_cla12_pg_logic6_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and122_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and122_h_u_cla12_pg_logic6_y0 _b=h_u_cla12_and122_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and122_y0
.names h_u_cla12_and122_y0 h_u_cla12_and123_h_u_cla12_and122_y0
1 1
.names h_u_cla12_and121_y0 h_u_cla12_and123_h_u_cla12_and121_y0
1 1
.subckt and_gate _a=h_u_cla12_and123_h_u_cla12_and122_y0 _b=h_u_cla12_and123_h_u_cla12_and121_y0 _y0=h_u_cla12_and123_y0
.names h_u_cla12_pg_logic3_y0 h_u_cla12_and124_h_u_cla12_pg_logic3_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and124_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and124_h_u_cla12_pg_logic3_y0 _b=h_u_cla12_and124_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and124_y0
.names h_u_cla12_pg_logic4_y0 h_u_cla12_and125_h_u_cla12_pg_logic4_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and125_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and125_h_u_cla12_pg_logic4_y0 _b=h_u_cla12_and125_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and125_y0
.names h_u_cla12_and125_y0 h_u_cla12_and126_h_u_cla12_and125_y0
1 1
.names h_u_cla12_and124_y0 h_u_cla12_and126_h_u_cla12_and124_y0
1 1
.subckt and_gate _a=h_u_cla12_and126_h_u_cla12_and125_y0 _b=h_u_cla12_and126_h_u_cla12_and124_y0 _y0=h_u_cla12_and126_y0
.names h_u_cla12_pg_logic5_y0 h_u_cla12_and127_h_u_cla12_pg_logic5_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and127_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and127_h_u_cla12_pg_logic5_y0 _b=h_u_cla12_and127_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and127_y0
.names h_u_cla12_and127_y0 h_u_cla12_and128_h_u_cla12_and127_y0
1 1
.names h_u_cla12_and126_y0 h_u_cla12_and128_h_u_cla12_and126_y0
1 1
.subckt and_gate _a=h_u_cla12_and128_h_u_cla12_and127_y0 _b=h_u_cla12_and128_h_u_cla12_and126_y0 _y0=h_u_cla12_and128_y0
.names h_u_cla12_pg_logic6_y0 h_u_cla12_and129_h_u_cla12_pg_logic6_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and129_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and129_h_u_cla12_pg_logic6_y0 _b=h_u_cla12_and129_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and129_y0
.names h_u_cla12_and129_y0 h_u_cla12_and130_h_u_cla12_and129_y0
1 1
.names h_u_cla12_and128_y0 h_u_cla12_and130_h_u_cla12_and128_y0
1 1
.subckt and_gate _a=h_u_cla12_and130_h_u_cla12_and129_y0 _b=h_u_cla12_and130_h_u_cla12_and128_y0 _y0=h_u_cla12_and130_y0
.names h_u_cla12_pg_logic4_y0 h_u_cla12_and131_h_u_cla12_pg_logic4_y0
1 1
.names h_u_cla12_pg_logic3_y1 h_u_cla12_and131_h_u_cla12_pg_logic3_y1
1 1
.subckt and_gate _a=h_u_cla12_and131_h_u_cla12_pg_logic4_y0 _b=h_u_cla12_and131_h_u_cla12_pg_logic3_y1 _y0=h_u_cla12_and131_y0
.names h_u_cla12_pg_logic5_y0 h_u_cla12_and132_h_u_cla12_pg_logic5_y0
1 1
.names h_u_cla12_pg_logic3_y1 h_u_cla12_and132_h_u_cla12_pg_logic3_y1
1 1
.subckt and_gate _a=h_u_cla12_and132_h_u_cla12_pg_logic5_y0 _b=h_u_cla12_and132_h_u_cla12_pg_logic3_y1 _y0=h_u_cla12_and132_y0
.names h_u_cla12_and132_y0 h_u_cla12_and133_h_u_cla12_and132_y0
1 1
.names h_u_cla12_and131_y0 h_u_cla12_and133_h_u_cla12_and131_y0
1 1
.subckt and_gate _a=h_u_cla12_and133_h_u_cla12_and132_y0 _b=h_u_cla12_and133_h_u_cla12_and131_y0 _y0=h_u_cla12_and133_y0
.names h_u_cla12_pg_logic6_y0 h_u_cla12_and134_h_u_cla12_pg_logic6_y0
1 1
.names h_u_cla12_pg_logic3_y1 h_u_cla12_and134_h_u_cla12_pg_logic3_y1
1 1
.subckt and_gate _a=h_u_cla12_and134_h_u_cla12_pg_logic6_y0 _b=h_u_cla12_and134_h_u_cla12_pg_logic3_y1 _y0=h_u_cla12_and134_y0
.names h_u_cla12_and134_y0 h_u_cla12_and135_h_u_cla12_and134_y0
1 1
.names h_u_cla12_and133_y0 h_u_cla12_and135_h_u_cla12_and133_y0
1 1
.subckt and_gate _a=h_u_cla12_and135_h_u_cla12_and134_y0 _b=h_u_cla12_and135_h_u_cla12_and133_y0 _y0=h_u_cla12_and135_y0
.names h_u_cla12_pg_logic5_y0 h_u_cla12_and136_h_u_cla12_pg_logic5_y0
1 1
.names h_u_cla12_pg_logic4_y1 h_u_cla12_and136_h_u_cla12_pg_logic4_y1
1 1
.subckt and_gate _a=h_u_cla12_and136_h_u_cla12_pg_logic5_y0 _b=h_u_cla12_and136_h_u_cla12_pg_logic4_y1 _y0=h_u_cla12_and136_y0
.names h_u_cla12_pg_logic6_y0 h_u_cla12_and137_h_u_cla12_pg_logic6_y0
1 1
.names h_u_cla12_pg_logic4_y1 h_u_cla12_and137_h_u_cla12_pg_logic4_y1
1 1
.subckt and_gate _a=h_u_cla12_and137_h_u_cla12_pg_logic6_y0 _b=h_u_cla12_and137_h_u_cla12_pg_logic4_y1 _y0=h_u_cla12_and137_y0
.names h_u_cla12_and137_y0 h_u_cla12_and138_h_u_cla12_and137_y0
1 1
.names h_u_cla12_and136_y0 h_u_cla12_and138_h_u_cla12_and136_y0
1 1
.subckt and_gate _a=h_u_cla12_and138_h_u_cla12_and137_y0 _b=h_u_cla12_and138_h_u_cla12_and136_y0 _y0=h_u_cla12_and138_y0
.names h_u_cla12_pg_logic6_y0 h_u_cla12_and139_h_u_cla12_pg_logic6_y0
1 1
.names h_u_cla12_pg_logic5_y1 h_u_cla12_and139_h_u_cla12_pg_logic5_y1
1 1
.subckt and_gate _a=h_u_cla12_and139_h_u_cla12_pg_logic6_y0 _b=h_u_cla12_and139_h_u_cla12_pg_logic5_y1 _y0=h_u_cla12_and139_y0
.names h_u_cla12_and139_y0 h_u_cla12_or21_h_u_cla12_and139_y0
1 1
.names h_u_cla12_and103_y0 h_u_cla12_or21_h_u_cla12_and103_y0
1 1
.subckt or_gate _a=h_u_cla12_or21_h_u_cla12_and139_y0 _b=h_u_cla12_or21_h_u_cla12_and103_y0 _y0=h_u_cla12_or21_y0
.names h_u_cla12_or21_y0 h_u_cla12_or22_h_u_cla12_or21_y0
1 1
.names h_u_cla12_and114_y0 h_u_cla12_or22_h_u_cla12_and114_y0
1 1
.subckt or_gate _a=h_u_cla12_or22_h_u_cla12_or21_y0 _b=h_u_cla12_or22_h_u_cla12_and114_y0 _y0=h_u_cla12_or22_y0
.names h_u_cla12_or22_y0 h_u_cla12_or23_h_u_cla12_or22_y0
1 1
.names h_u_cla12_and123_y0 h_u_cla12_or23_h_u_cla12_and123_y0
1 1
.subckt or_gate _a=h_u_cla12_or23_h_u_cla12_or22_y0 _b=h_u_cla12_or23_h_u_cla12_and123_y0 _y0=h_u_cla12_or23_y0
.names h_u_cla12_or23_y0 h_u_cla12_or24_h_u_cla12_or23_y0
1 1
.names h_u_cla12_and130_y0 h_u_cla12_or24_h_u_cla12_and130_y0
1 1
.subckt or_gate _a=h_u_cla12_or24_h_u_cla12_or23_y0 _b=h_u_cla12_or24_h_u_cla12_and130_y0 _y0=h_u_cla12_or24_y0
.names h_u_cla12_or24_y0 h_u_cla12_or25_h_u_cla12_or24_y0
1 1
.names h_u_cla12_and135_y0 h_u_cla12_or25_h_u_cla12_and135_y0
1 1
.subckt or_gate _a=h_u_cla12_or25_h_u_cla12_or24_y0 _b=h_u_cla12_or25_h_u_cla12_and135_y0 _y0=h_u_cla12_or25_y0
.names h_u_cla12_or25_y0 h_u_cla12_or26_h_u_cla12_or25_y0
1 1
.names h_u_cla12_and138_y0 h_u_cla12_or26_h_u_cla12_and138_y0
1 1
.subckt or_gate _a=h_u_cla12_or26_h_u_cla12_or25_y0 _b=h_u_cla12_or26_h_u_cla12_and138_y0 _y0=h_u_cla12_or26_y0
.names h_u_cla12_pg_logic6_y1 h_u_cla12_or27_h_u_cla12_pg_logic6_y1
1 1
.names h_u_cla12_or26_y0 h_u_cla12_or27_h_u_cla12_or26_y0
1 1
.subckt or_gate _a=h_u_cla12_or27_h_u_cla12_pg_logic6_y1 _b=h_u_cla12_or27_h_u_cla12_or26_y0 _y0=h_u_cla12_or27_y0
.names a_7 h_u_cla12_pg_logic7_a_7
1 1
.names b_7 h_u_cla12_pg_logic7_b_7
1 1
.subckt pg_logic a=h_u_cla12_pg_logic7_a_7 b=h_u_cla12_pg_logic7_b_7 pg_logic_y0=h_u_cla12_pg_logic7_y0 pg_logic_y1=h_u_cla12_pg_logic7_y1 pg_logic_y2=h_u_cla12_pg_logic7_y2
.names h_u_cla12_pg_logic7_y2 h_u_cla12_xor7_h_u_cla12_pg_logic7_y2
1 1
.names h_u_cla12_or27_y0 h_u_cla12_xor7_h_u_cla12_or27_y0
1 1
.subckt xor_gate _a=h_u_cla12_xor7_h_u_cla12_pg_logic7_y2 _b=h_u_cla12_xor7_h_u_cla12_or27_y0 _y0=h_u_cla12_xor7_y0
.names h_u_cla12_pg_logic0_y0 h_u_cla12_and140_h_u_cla12_pg_logic0_y0
1 1
.names constant_wire_0 h_u_cla12_and140_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and140_h_u_cla12_pg_logic0_y0 _b=h_u_cla12_and140_constant_wire_0 _y0=h_u_cla12_and140_y0
.names h_u_cla12_pg_logic1_y0 h_u_cla12_and141_h_u_cla12_pg_logic1_y0
1 1
.names constant_wire_0 h_u_cla12_and141_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and141_h_u_cla12_pg_logic1_y0 _b=h_u_cla12_and141_constant_wire_0 _y0=h_u_cla12_and141_y0
.names h_u_cla12_and141_y0 h_u_cla12_and142_h_u_cla12_and141_y0
1 1
.names h_u_cla12_and140_y0 h_u_cla12_and142_h_u_cla12_and140_y0
1 1
.subckt and_gate _a=h_u_cla12_and142_h_u_cla12_and141_y0 _b=h_u_cla12_and142_h_u_cla12_and140_y0 _y0=h_u_cla12_and142_y0
.names h_u_cla12_pg_logic2_y0 h_u_cla12_and143_h_u_cla12_pg_logic2_y0
1 1
.names constant_wire_0 h_u_cla12_and143_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and143_h_u_cla12_pg_logic2_y0 _b=h_u_cla12_and143_constant_wire_0 _y0=h_u_cla12_and143_y0
.names h_u_cla12_and143_y0 h_u_cla12_and144_h_u_cla12_and143_y0
1 1
.names h_u_cla12_and142_y0 h_u_cla12_and144_h_u_cla12_and142_y0
1 1
.subckt and_gate _a=h_u_cla12_and144_h_u_cla12_and143_y0 _b=h_u_cla12_and144_h_u_cla12_and142_y0 _y0=h_u_cla12_and144_y0
.names h_u_cla12_pg_logic3_y0 h_u_cla12_and145_h_u_cla12_pg_logic3_y0
1 1
.names constant_wire_0 h_u_cla12_and145_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and145_h_u_cla12_pg_logic3_y0 _b=h_u_cla12_and145_constant_wire_0 _y0=h_u_cla12_and145_y0
.names h_u_cla12_and145_y0 h_u_cla12_and146_h_u_cla12_and145_y0
1 1
.names h_u_cla12_and144_y0 h_u_cla12_and146_h_u_cla12_and144_y0
1 1
.subckt and_gate _a=h_u_cla12_and146_h_u_cla12_and145_y0 _b=h_u_cla12_and146_h_u_cla12_and144_y0 _y0=h_u_cla12_and146_y0
.names h_u_cla12_pg_logic4_y0 h_u_cla12_and147_h_u_cla12_pg_logic4_y0
1 1
.names constant_wire_0 h_u_cla12_and147_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and147_h_u_cla12_pg_logic4_y0 _b=h_u_cla12_and147_constant_wire_0 _y0=h_u_cla12_and147_y0
.names h_u_cla12_and147_y0 h_u_cla12_and148_h_u_cla12_and147_y0
1 1
.names h_u_cla12_and146_y0 h_u_cla12_and148_h_u_cla12_and146_y0
1 1
.subckt and_gate _a=h_u_cla12_and148_h_u_cla12_and147_y0 _b=h_u_cla12_and148_h_u_cla12_and146_y0 _y0=h_u_cla12_and148_y0
.names h_u_cla12_pg_logic5_y0 h_u_cla12_and149_h_u_cla12_pg_logic5_y0
1 1
.names constant_wire_0 h_u_cla12_and149_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and149_h_u_cla12_pg_logic5_y0 _b=h_u_cla12_and149_constant_wire_0 _y0=h_u_cla12_and149_y0
.names h_u_cla12_and149_y0 h_u_cla12_and150_h_u_cla12_and149_y0
1 1
.names h_u_cla12_and148_y0 h_u_cla12_and150_h_u_cla12_and148_y0
1 1
.subckt and_gate _a=h_u_cla12_and150_h_u_cla12_and149_y0 _b=h_u_cla12_and150_h_u_cla12_and148_y0 _y0=h_u_cla12_and150_y0
.names h_u_cla12_pg_logic6_y0 h_u_cla12_and151_h_u_cla12_pg_logic6_y0
1 1
.names constant_wire_0 h_u_cla12_and151_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and151_h_u_cla12_pg_logic6_y0 _b=h_u_cla12_and151_constant_wire_0 _y0=h_u_cla12_and151_y0
.names h_u_cla12_and151_y0 h_u_cla12_and152_h_u_cla12_and151_y0
1 1
.names h_u_cla12_and150_y0 h_u_cla12_and152_h_u_cla12_and150_y0
1 1
.subckt and_gate _a=h_u_cla12_and152_h_u_cla12_and151_y0 _b=h_u_cla12_and152_h_u_cla12_and150_y0 _y0=h_u_cla12_and152_y0
.names h_u_cla12_pg_logic7_y0 h_u_cla12_and153_h_u_cla12_pg_logic7_y0
1 1
.names constant_wire_0 h_u_cla12_and153_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and153_h_u_cla12_pg_logic7_y0 _b=h_u_cla12_and153_constant_wire_0 _y0=h_u_cla12_and153_y0
.names h_u_cla12_and153_y0 h_u_cla12_and154_h_u_cla12_and153_y0
1 1
.names h_u_cla12_and152_y0 h_u_cla12_and154_h_u_cla12_and152_y0
1 1
.subckt and_gate _a=h_u_cla12_and154_h_u_cla12_and153_y0 _b=h_u_cla12_and154_h_u_cla12_and152_y0 _y0=h_u_cla12_and154_y0
.names h_u_cla12_pg_logic1_y0 h_u_cla12_and155_h_u_cla12_pg_logic1_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and155_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and155_h_u_cla12_pg_logic1_y0 _b=h_u_cla12_and155_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and155_y0
.names h_u_cla12_pg_logic2_y0 h_u_cla12_and156_h_u_cla12_pg_logic2_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and156_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and156_h_u_cla12_pg_logic2_y0 _b=h_u_cla12_and156_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and156_y0
.names h_u_cla12_and156_y0 h_u_cla12_and157_h_u_cla12_and156_y0
1 1
.names h_u_cla12_and155_y0 h_u_cla12_and157_h_u_cla12_and155_y0
1 1
.subckt and_gate _a=h_u_cla12_and157_h_u_cla12_and156_y0 _b=h_u_cla12_and157_h_u_cla12_and155_y0 _y0=h_u_cla12_and157_y0
.names h_u_cla12_pg_logic3_y0 h_u_cla12_and158_h_u_cla12_pg_logic3_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and158_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and158_h_u_cla12_pg_logic3_y0 _b=h_u_cla12_and158_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and158_y0
.names h_u_cla12_and158_y0 h_u_cla12_and159_h_u_cla12_and158_y0
1 1
.names h_u_cla12_and157_y0 h_u_cla12_and159_h_u_cla12_and157_y0
1 1
.subckt and_gate _a=h_u_cla12_and159_h_u_cla12_and158_y0 _b=h_u_cla12_and159_h_u_cla12_and157_y0 _y0=h_u_cla12_and159_y0
.names h_u_cla12_pg_logic4_y0 h_u_cla12_and160_h_u_cla12_pg_logic4_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and160_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and160_h_u_cla12_pg_logic4_y0 _b=h_u_cla12_and160_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and160_y0
.names h_u_cla12_and160_y0 h_u_cla12_and161_h_u_cla12_and160_y0
1 1
.names h_u_cla12_and159_y0 h_u_cla12_and161_h_u_cla12_and159_y0
1 1
.subckt and_gate _a=h_u_cla12_and161_h_u_cla12_and160_y0 _b=h_u_cla12_and161_h_u_cla12_and159_y0 _y0=h_u_cla12_and161_y0
.names h_u_cla12_pg_logic5_y0 h_u_cla12_and162_h_u_cla12_pg_logic5_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and162_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and162_h_u_cla12_pg_logic5_y0 _b=h_u_cla12_and162_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and162_y0
.names h_u_cla12_and162_y0 h_u_cla12_and163_h_u_cla12_and162_y0
1 1
.names h_u_cla12_and161_y0 h_u_cla12_and163_h_u_cla12_and161_y0
1 1
.subckt and_gate _a=h_u_cla12_and163_h_u_cla12_and162_y0 _b=h_u_cla12_and163_h_u_cla12_and161_y0 _y0=h_u_cla12_and163_y0
.names h_u_cla12_pg_logic6_y0 h_u_cla12_and164_h_u_cla12_pg_logic6_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and164_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and164_h_u_cla12_pg_logic6_y0 _b=h_u_cla12_and164_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and164_y0
.names h_u_cla12_and164_y0 h_u_cla12_and165_h_u_cla12_and164_y0
1 1
.names h_u_cla12_and163_y0 h_u_cla12_and165_h_u_cla12_and163_y0
1 1
.subckt and_gate _a=h_u_cla12_and165_h_u_cla12_and164_y0 _b=h_u_cla12_and165_h_u_cla12_and163_y0 _y0=h_u_cla12_and165_y0
.names h_u_cla12_pg_logic7_y0 h_u_cla12_and166_h_u_cla12_pg_logic7_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and166_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and166_h_u_cla12_pg_logic7_y0 _b=h_u_cla12_and166_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and166_y0
.names h_u_cla12_and166_y0 h_u_cla12_and167_h_u_cla12_and166_y0
1 1
.names h_u_cla12_and165_y0 h_u_cla12_and167_h_u_cla12_and165_y0
1 1
.subckt and_gate _a=h_u_cla12_and167_h_u_cla12_and166_y0 _b=h_u_cla12_and167_h_u_cla12_and165_y0 _y0=h_u_cla12_and167_y0
.names h_u_cla12_pg_logic2_y0 h_u_cla12_and168_h_u_cla12_pg_logic2_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and168_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and168_h_u_cla12_pg_logic2_y0 _b=h_u_cla12_and168_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and168_y0
.names h_u_cla12_pg_logic3_y0 h_u_cla12_and169_h_u_cla12_pg_logic3_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and169_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and169_h_u_cla12_pg_logic3_y0 _b=h_u_cla12_and169_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and169_y0
.names h_u_cla12_and169_y0 h_u_cla12_and170_h_u_cla12_and169_y0
1 1
.names h_u_cla12_and168_y0 h_u_cla12_and170_h_u_cla12_and168_y0
1 1
.subckt and_gate _a=h_u_cla12_and170_h_u_cla12_and169_y0 _b=h_u_cla12_and170_h_u_cla12_and168_y0 _y0=h_u_cla12_and170_y0
.names h_u_cla12_pg_logic4_y0 h_u_cla12_and171_h_u_cla12_pg_logic4_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and171_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and171_h_u_cla12_pg_logic4_y0 _b=h_u_cla12_and171_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and171_y0
.names h_u_cla12_and171_y0 h_u_cla12_and172_h_u_cla12_and171_y0
1 1
.names h_u_cla12_and170_y0 h_u_cla12_and172_h_u_cla12_and170_y0
1 1
.subckt and_gate _a=h_u_cla12_and172_h_u_cla12_and171_y0 _b=h_u_cla12_and172_h_u_cla12_and170_y0 _y0=h_u_cla12_and172_y0
.names h_u_cla12_pg_logic5_y0 h_u_cla12_and173_h_u_cla12_pg_logic5_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and173_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and173_h_u_cla12_pg_logic5_y0 _b=h_u_cla12_and173_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and173_y0
.names h_u_cla12_and173_y0 h_u_cla12_and174_h_u_cla12_and173_y0
1 1
.names h_u_cla12_and172_y0 h_u_cla12_and174_h_u_cla12_and172_y0
1 1
.subckt and_gate _a=h_u_cla12_and174_h_u_cla12_and173_y0 _b=h_u_cla12_and174_h_u_cla12_and172_y0 _y0=h_u_cla12_and174_y0
.names h_u_cla12_pg_logic6_y0 h_u_cla12_and175_h_u_cla12_pg_logic6_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and175_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and175_h_u_cla12_pg_logic6_y0 _b=h_u_cla12_and175_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and175_y0
.names h_u_cla12_and175_y0 h_u_cla12_and176_h_u_cla12_and175_y0
1 1
.names h_u_cla12_and174_y0 h_u_cla12_and176_h_u_cla12_and174_y0
1 1
.subckt and_gate _a=h_u_cla12_and176_h_u_cla12_and175_y0 _b=h_u_cla12_and176_h_u_cla12_and174_y0 _y0=h_u_cla12_and176_y0
.names h_u_cla12_pg_logic7_y0 h_u_cla12_and177_h_u_cla12_pg_logic7_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and177_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and177_h_u_cla12_pg_logic7_y0 _b=h_u_cla12_and177_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and177_y0
.names h_u_cla12_and177_y0 h_u_cla12_and178_h_u_cla12_and177_y0
1 1
.names h_u_cla12_and176_y0 h_u_cla12_and178_h_u_cla12_and176_y0
1 1
.subckt and_gate _a=h_u_cla12_and178_h_u_cla12_and177_y0 _b=h_u_cla12_and178_h_u_cla12_and176_y0 _y0=h_u_cla12_and178_y0
.names h_u_cla12_pg_logic3_y0 h_u_cla12_and179_h_u_cla12_pg_logic3_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and179_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and179_h_u_cla12_pg_logic3_y0 _b=h_u_cla12_and179_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and179_y0
.names h_u_cla12_pg_logic4_y0 h_u_cla12_and180_h_u_cla12_pg_logic4_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and180_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and180_h_u_cla12_pg_logic4_y0 _b=h_u_cla12_and180_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and180_y0
.names h_u_cla12_and180_y0 h_u_cla12_and181_h_u_cla12_and180_y0
1 1
.names h_u_cla12_and179_y0 h_u_cla12_and181_h_u_cla12_and179_y0
1 1
.subckt and_gate _a=h_u_cla12_and181_h_u_cla12_and180_y0 _b=h_u_cla12_and181_h_u_cla12_and179_y0 _y0=h_u_cla12_and181_y0
.names h_u_cla12_pg_logic5_y0 h_u_cla12_and182_h_u_cla12_pg_logic5_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and182_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and182_h_u_cla12_pg_logic5_y0 _b=h_u_cla12_and182_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and182_y0
.names h_u_cla12_and182_y0 h_u_cla12_and183_h_u_cla12_and182_y0
1 1
.names h_u_cla12_and181_y0 h_u_cla12_and183_h_u_cla12_and181_y0
1 1
.subckt and_gate _a=h_u_cla12_and183_h_u_cla12_and182_y0 _b=h_u_cla12_and183_h_u_cla12_and181_y0 _y0=h_u_cla12_and183_y0
.names h_u_cla12_pg_logic6_y0 h_u_cla12_and184_h_u_cla12_pg_logic6_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and184_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and184_h_u_cla12_pg_logic6_y0 _b=h_u_cla12_and184_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and184_y0
.names h_u_cla12_and184_y0 h_u_cla12_and185_h_u_cla12_and184_y0
1 1
.names h_u_cla12_and183_y0 h_u_cla12_and185_h_u_cla12_and183_y0
1 1
.subckt and_gate _a=h_u_cla12_and185_h_u_cla12_and184_y0 _b=h_u_cla12_and185_h_u_cla12_and183_y0 _y0=h_u_cla12_and185_y0
.names h_u_cla12_pg_logic7_y0 h_u_cla12_and186_h_u_cla12_pg_logic7_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and186_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and186_h_u_cla12_pg_logic7_y0 _b=h_u_cla12_and186_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and186_y0
.names h_u_cla12_and186_y0 h_u_cla12_and187_h_u_cla12_and186_y0
1 1
.names h_u_cla12_and185_y0 h_u_cla12_and187_h_u_cla12_and185_y0
1 1
.subckt and_gate _a=h_u_cla12_and187_h_u_cla12_and186_y0 _b=h_u_cla12_and187_h_u_cla12_and185_y0 _y0=h_u_cla12_and187_y0
.names h_u_cla12_pg_logic4_y0 h_u_cla12_and188_h_u_cla12_pg_logic4_y0
1 1
.names h_u_cla12_pg_logic3_y1 h_u_cla12_and188_h_u_cla12_pg_logic3_y1
1 1
.subckt and_gate _a=h_u_cla12_and188_h_u_cla12_pg_logic4_y0 _b=h_u_cla12_and188_h_u_cla12_pg_logic3_y1 _y0=h_u_cla12_and188_y0
.names h_u_cla12_pg_logic5_y0 h_u_cla12_and189_h_u_cla12_pg_logic5_y0
1 1
.names h_u_cla12_pg_logic3_y1 h_u_cla12_and189_h_u_cla12_pg_logic3_y1
1 1
.subckt and_gate _a=h_u_cla12_and189_h_u_cla12_pg_logic5_y0 _b=h_u_cla12_and189_h_u_cla12_pg_logic3_y1 _y0=h_u_cla12_and189_y0
.names h_u_cla12_and189_y0 h_u_cla12_and190_h_u_cla12_and189_y0
1 1
.names h_u_cla12_and188_y0 h_u_cla12_and190_h_u_cla12_and188_y0
1 1
.subckt and_gate _a=h_u_cla12_and190_h_u_cla12_and189_y0 _b=h_u_cla12_and190_h_u_cla12_and188_y0 _y0=h_u_cla12_and190_y0
.names h_u_cla12_pg_logic6_y0 h_u_cla12_and191_h_u_cla12_pg_logic6_y0
1 1
.names h_u_cla12_pg_logic3_y1 h_u_cla12_and191_h_u_cla12_pg_logic3_y1
1 1
.subckt and_gate _a=h_u_cla12_and191_h_u_cla12_pg_logic6_y0 _b=h_u_cla12_and191_h_u_cla12_pg_logic3_y1 _y0=h_u_cla12_and191_y0
.names h_u_cla12_and191_y0 h_u_cla12_and192_h_u_cla12_and191_y0
1 1
.names h_u_cla12_and190_y0 h_u_cla12_and192_h_u_cla12_and190_y0
1 1
.subckt and_gate _a=h_u_cla12_and192_h_u_cla12_and191_y0 _b=h_u_cla12_and192_h_u_cla12_and190_y0 _y0=h_u_cla12_and192_y0
.names h_u_cla12_pg_logic7_y0 h_u_cla12_and193_h_u_cla12_pg_logic7_y0
1 1
.names h_u_cla12_pg_logic3_y1 h_u_cla12_and193_h_u_cla12_pg_logic3_y1
1 1
.subckt and_gate _a=h_u_cla12_and193_h_u_cla12_pg_logic7_y0 _b=h_u_cla12_and193_h_u_cla12_pg_logic3_y1 _y0=h_u_cla12_and193_y0
.names h_u_cla12_and193_y0 h_u_cla12_and194_h_u_cla12_and193_y0
1 1
.names h_u_cla12_and192_y0 h_u_cla12_and194_h_u_cla12_and192_y0
1 1
.subckt and_gate _a=h_u_cla12_and194_h_u_cla12_and193_y0 _b=h_u_cla12_and194_h_u_cla12_and192_y0 _y0=h_u_cla12_and194_y0
.names h_u_cla12_pg_logic5_y0 h_u_cla12_and195_h_u_cla12_pg_logic5_y0
1 1
.names h_u_cla12_pg_logic4_y1 h_u_cla12_and195_h_u_cla12_pg_logic4_y1
1 1
.subckt and_gate _a=h_u_cla12_and195_h_u_cla12_pg_logic5_y0 _b=h_u_cla12_and195_h_u_cla12_pg_logic4_y1 _y0=h_u_cla12_and195_y0
.names h_u_cla12_pg_logic6_y0 h_u_cla12_and196_h_u_cla12_pg_logic6_y0
1 1
.names h_u_cla12_pg_logic4_y1 h_u_cla12_and196_h_u_cla12_pg_logic4_y1
1 1
.subckt and_gate _a=h_u_cla12_and196_h_u_cla12_pg_logic6_y0 _b=h_u_cla12_and196_h_u_cla12_pg_logic4_y1 _y0=h_u_cla12_and196_y0
.names h_u_cla12_and196_y0 h_u_cla12_and197_h_u_cla12_and196_y0
1 1
.names h_u_cla12_and195_y0 h_u_cla12_and197_h_u_cla12_and195_y0
1 1
.subckt and_gate _a=h_u_cla12_and197_h_u_cla12_and196_y0 _b=h_u_cla12_and197_h_u_cla12_and195_y0 _y0=h_u_cla12_and197_y0
.names h_u_cla12_pg_logic7_y0 h_u_cla12_and198_h_u_cla12_pg_logic7_y0
1 1
.names h_u_cla12_pg_logic4_y1 h_u_cla12_and198_h_u_cla12_pg_logic4_y1
1 1
.subckt and_gate _a=h_u_cla12_and198_h_u_cla12_pg_logic7_y0 _b=h_u_cla12_and198_h_u_cla12_pg_logic4_y1 _y0=h_u_cla12_and198_y0
.names h_u_cla12_and198_y0 h_u_cla12_and199_h_u_cla12_and198_y0
1 1
.names h_u_cla12_and197_y0 h_u_cla12_and199_h_u_cla12_and197_y0
1 1
.subckt and_gate _a=h_u_cla12_and199_h_u_cla12_and198_y0 _b=h_u_cla12_and199_h_u_cla12_and197_y0 _y0=h_u_cla12_and199_y0
.names h_u_cla12_pg_logic6_y0 h_u_cla12_and200_h_u_cla12_pg_logic6_y0
1 1
.names h_u_cla12_pg_logic5_y1 h_u_cla12_and200_h_u_cla12_pg_logic5_y1
1 1
.subckt and_gate _a=h_u_cla12_and200_h_u_cla12_pg_logic6_y0 _b=h_u_cla12_and200_h_u_cla12_pg_logic5_y1 _y0=h_u_cla12_and200_y0
.names h_u_cla12_pg_logic7_y0 h_u_cla12_and201_h_u_cla12_pg_logic7_y0
1 1
.names h_u_cla12_pg_logic5_y1 h_u_cla12_and201_h_u_cla12_pg_logic5_y1
1 1
.subckt and_gate _a=h_u_cla12_and201_h_u_cla12_pg_logic7_y0 _b=h_u_cla12_and201_h_u_cla12_pg_logic5_y1 _y0=h_u_cla12_and201_y0
.names h_u_cla12_and201_y0 h_u_cla12_and202_h_u_cla12_and201_y0
1 1
.names h_u_cla12_and200_y0 h_u_cla12_and202_h_u_cla12_and200_y0
1 1
.subckt and_gate _a=h_u_cla12_and202_h_u_cla12_and201_y0 _b=h_u_cla12_and202_h_u_cla12_and200_y0 _y0=h_u_cla12_and202_y0
.names h_u_cla12_pg_logic7_y0 h_u_cla12_and203_h_u_cla12_pg_logic7_y0
1 1
.names h_u_cla12_pg_logic6_y1 h_u_cla12_and203_h_u_cla12_pg_logic6_y1
1 1
.subckt and_gate _a=h_u_cla12_and203_h_u_cla12_pg_logic7_y0 _b=h_u_cla12_and203_h_u_cla12_pg_logic6_y1 _y0=h_u_cla12_and203_y0
.names h_u_cla12_and203_y0 h_u_cla12_or28_h_u_cla12_and203_y0
1 1
.names h_u_cla12_and154_y0 h_u_cla12_or28_h_u_cla12_and154_y0
1 1
.subckt or_gate _a=h_u_cla12_or28_h_u_cla12_and203_y0 _b=h_u_cla12_or28_h_u_cla12_and154_y0 _y0=h_u_cla12_or28_y0
.names h_u_cla12_or28_y0 h_u_cla12_or29_h_u_cla12_or28_y0
1 1
.names h_u_cla12_and167_y0 h_u_cla12_or29_h_u_cla12_and167_y0
1 1
.subckt or_gate _a=h_u_cla12_or29_h_u_cla12_or28_y0 _b=h_u_cla12_or29_h_u_cla12_and167_y0 _y0=h_u_cla12_or29_y0
.names h_u_cla12_or29_y0 h_u_cla12_or30_h_u_cla12_or29_y0
1 1
.names h_u_cla12_and178_y0 h_u_cla12_or30_h_u_cla12_and178_y0
1 1
.subckt or_gate _a=h_u_cla12_or30_h_u_cla12_or29_y0 _b=h_u_cla12_or30_h_u_cla12_and178_y0 _y0=h_u_cla12_or30_y0
.names h_u_cla12_or30_y0 h_u_cla12_or31_h_u_cla12_or30_y0
1 1
.names h_u_cla12_and187_y0 h_u_cla12_or31_h_u_cla12_and187_y0
1 1
.subckt or_gate _a=h_u_cla12_or31_h_u_cla12_or30_y0 _b=h_u_cla12_or31_h_u_cla12_and187_y0 _y0=h_u_cla12_or31_y0
.names h_u_cla12_or31_y0 h_u_cla12_or32_h_u_cla12_or31_y0
1 1
.names h_u_cla12_and194_y0 h_u_cla12_or32_h_u_cla12_and194_y0
1 1
.subckt or_gate _a=h_u_cla12_or32_h_u_cla12_or31_y0 _b=h_u_cla12_or32_h_u_cla12_and194_y0 _y0=h_u_cla12_or32_y0
.names h_u_cla12_or32_y0 h_u_cla12_or33_h_u_cla12_or32_y0
1 1
.names h_u_cla12_and199_y0 h_u_cla12_or33_h_u_cla12_and199_y0
1 1
.subckt or_gate _a=h_u_cla12_or33_h_u_cla12_or32_y0 _b=h_u_cla12_or33_h_u_cla12_and199_y0 _y0=h_u_cla12_or33_y0
.names h_u_cla12_or33_y0 h_u_cla12_or34_h_u_cla12_or33_y0
1 1
.names h_u_cla12_and202_y0 h_u_cla12_or34_h_u_cla12_and202_y0
1 1
.subckt or_gate _a=h_u_cla12_or34_h_u_cla12_or33_y0 _b=h_u_cla12_or34_h_u_cla12_and202_y0 _y0=h_u_cla12_or34_y0
.names h_u_cla12_pg_logic7_y1 h_u_cla12_or35_h_u_cla12_pg_logic7_y1
1 1
.names h_u_cla12_or34_y0 h_u_cla12_or35_h_u_cla12_or34_y0
1 1
.subckt or_gate _a=h_u_cla12_or35_h_u_cla12_pg_logic7_y1 _b=h_u_cla12_or35_h_u_cla12_or34_y0 _y0=h_u_cla12_or35_y0
.names a_8 h_u_cla12_pg_logic8_a_8
1 1
.names b_8 h_u_cla12_pg_logic8_b_8
1 1
.subckt pg_logic a=h_u_cla12_pg_logic8_a_8 b=h_u_cla12_pg_logic8_b_8 pg_logic_y0=h_u_cla12_pg_logic8_y0 pg_logic_y1=h_u_cla12_pg_logic8_y1 pg_logic_y2=h_u_cla12_pg_logic8_y2
.names h_u_cla12_pg_logic8_y2 h_u_cla12_xor8_h_u_cla12_pg_logic8_y2
1 1
.names h_u_cla12_or35_y0 h_u_cla12_xor8_h_u_cla12_or35_y0
1 1
.subckt xor_gate _a=h_u_cla12_xor8_h_u_cla12_pg_logic8_y2 _b=h_u_cla12_xor8_h_u_cla12_or35_y0 _y0=h_u_cla12_xor8_y0
.names h_u_cla12_pg_logic0_y0 h_u_cla12_and204_h_u_cla12_pg_logic0_y0
1 1
.names constant_wire_0 h_u_cla12_and204_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and204_h_u_cla12_pg_logic0_y0 _b=h_u_cla12_and204_constant_wire_0 _y0=h_u_cla12_and204_y0
.names h_u_cla12_pg_logic1_y0 h_u_cla12_and205_h_u_cla12_pg_logic1_y0
1 1
.names constant_wire_0 h_u_cla12_and205_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and205_h_u_cla12_pg_logic1_y0 _b=h_u_cla12_and205_constant_wire_0 _y0=h_u_cla12_and205_y0
.names h_u_cla12_and205_y0 h_u_cla12_and206_h_u_cla12_and205_y0
1 1
.names h_u_cla12_and204_y0 h_u_cla12_and206_h_u_cla12_and204_y0
1 1
.subckt and_gate _a=h_u_cla12_and206_h_u_cla12_and205_y0 _b=h_u_cla12_and206_h_u_cla12_and204_y0 _y0=h_u_cla12_and206_y0
.names h_u_cla12_pg_logic2_y0 h_u_cla12_and207_h_u_cla12_pg_logic2_y0
1 1
.names constant_wire_0 h_u_cla12_and207_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and207_h_u_cla12_pg_logic2_y0 _b=h_u_cla12_and207_constant_wire_0 _y0=h_u_cla12_and207_y0
.names h_u_cla12_and207_y0 h_u_cla12_and208_h_u_cla12_and207_y0
1 1
.names h_u_cla12_and206_y0 h_u_cla12_and208_h_u_cla12_and206_y0
1 1
.subckt and_gate _a=h_u_cla12_and208_h_u_cla12_and207_y0 _b=h_u_cla12_and208_h_u_cla12_and206_y0 _y0=h_u_cla12_and208_y0
.names h_u_cla12_pg_logic3_y0 h_u_cla12_and209_h_u_cla12_pg_logic3_y0
1 1
.names constant_wire_0 h_u_cla12_and209_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and209_h_u_cla12_pg_logic3_y0 _b=h_u_cla12_and209_constant_wire_0 _y0=h_u_cla12_and209_y0
.names h_u_cla12_and209_y0 h_u_cla12_and210_h_u_cla12_and209_y0
1 1
.names h_u_cla12_and208_y0 h_u_cla12_and210_h_u_cla12_and208_y0
1 1
.subckt and_gate _a=h_u_cla12_and210_h_u_cla12_and209_y0 _b=h_u_cla12_and210_h_u_cla12_and208_y0 _y0=h_u_cla12_and210_y0
.names h_u_cla12_pg_logic4_y0 h_u_cla12_and211_h_u_cla12_pg_logic4_y0
1 1
.names constant_wire_0 h_u_cla12_and211_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and211_h_u_cla12_pg_logic4_y0 _b=h_u_cla12_and211_constant_wire_0 _y0=h_u_cla12_and211_y0
.names h_u_cla12_and211_y0 h_u_cla12_and212_h_u_cla12_and211_y0
1 1
.names h_u_cla12_and210_y0 h_u_cla12_and212_h_u_cla12_and210_y0
1 1
.subckt and_gate _a=h_u_cla12_and212_h_u_cla12_and211_y0 _b=h_u_cla12_and212_h_u_cla12_and210_y0 _y0=h_u_cla12_and212_y0
.names h_u_cla12_pg_logic5_y0 h_u_cla12_and213_h_u_cla12_pg_logic5_y0
1 1
.names constant_wire_0 h_u_cla12_and213_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and213_h_u_cla12_pg_logic5_y0 _b=h_u_cla12_and213_constant_wire_0 _y0=h_u_cla12_and213_y0
.names h_u_cla12_and213_y0 h_u_cla12_and214_h_u_cla12_and213_y0
1 1
.names h_u_cla12_and212_y0 h_u_cla12_and214_h_u_cla12_and212_y0
1 1
.subckt and_gate _a=h_u_cla12_and214_h_u_cla12_and213_y0 _b=h_u_cla12_and214_h_u_cla12_and212_y0 _y0=h_u_cla12_and214_y0
.names h_u_cla12_pg_logic6_y0 h_u_cla12_and215_h_u_cla12_pg_logic6_y0
1 1
.names constant_wire_0 h_u_cla12_and215_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and215_h_u_cla12_pg_logic6_y0 _b=h_u_cla12_and215_constant_wire_0 _y0=h_u_cla12_and215_y0
.names h_u_cla12_and215_y0 h_u_cla12_and216_h_u_cla12_and215_y0
1 1
.names h_u_cla12_and214_y0 h_u_cla12_and216_h_u_cla12_and214_y0
1 1
.subckt and_gate _a=h_u_cla12_and216_h_u_cla12_and215_y0 _b=h_u_cla12_and216_h_u_cla12_and214_y0 _y0=h_u_cla12_and216_y0
.names h_u_cla12_pg_logic7_y0 h_u_cla12_and217_h_u_cla12_pg_logic7_y0
1 1
.names constant_wire_0 h_u_cla12_and217_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and217_h_u_cla12_pg_logic7_y0 _b=h_u_cla12_and217_constant_wire_0 _y0=h_u_cla12_and217_y0
.names h_u_cla12_and217_y0 h_u_cla12_and218_h_u_cla12_and217_y0
1 1
.names h_u_cla12_and216_y0 h_u_cla12_and218_h_u_cla12_and216_y0
1 1
.subckt and_gate _a=h_u_cla12_and218_h_u_cla12_and217_y0 _b=h_u_cla12_and218_h_u_cla12_and216_y0 _y0=h_u_cla12_and218_y0
.names h_u_cla12_pg_logic8_y0 h_u_cla12_and219_h_u_cla12_pg_logic8_y0
1 1
.names constant_wire_0 h_u_cla12_and219_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and219_h_u_cla12_pg_logic8_y0 _b=h_u_cla12_and219_constant_wire_0 _y0=h_u_cla12_and219_y0
.names h_u_cla12_and219_y0 h_u_cla12_and220_h_u_cla12_and219_y0
1 1
.names h_u_cla12_and218_y0 h_u_cla12_and220_h_u_cla12_and218_y0
1 1
.subckt and_gate _a=h_u_cla12_and220_h_u_cla12_and219_y0 _b=h_u_cla12_and220_h_u_cla12_and218_y0 _y0=h_u_cla12_and220_y0
.names h_u_cla12_pg_logic1_y0 h_u_cla12_and221_h_u_cla12_pg_logic1_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and221_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and221_h_u_cla12_pg_logic1_y0 _b=h_u_cla12_and221_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and221_y0
.names h_u_cla12_pg_logic2_y0 h_u_cla12_and222_h_u_cla12_pg_logic2_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and222_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and222_h_u_cla12_pg_logic2_y0 _b=h_u_cla12_and222_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and222_y0
.names h_u_cla12_and222_y0 h_u_cla12_and223_h_u_cla12_and222_y0
1 1
.names h_u_cla12_and221_y0 h_u_cla12_and223_h_u_cla12_and221_y0
1 1
.subckt and_gate _a=h_u_cla12_and223_h_u_cla12_and222_y0 _b=h_u_cla12_and223_h_u_cla12_and221_y0 _y0=h_u_cla12_and223_y0
.names h_u_cla12_pg_logic3_y0 h_u_cla12_and224_h_u_cla12_pg_logic3_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and224_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and224_h_u_cla12_pg_logic3_y0 _b=h_u_cla12_and224_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and224_y0
.names h_u_cla12_and224_y0 h_u_cla12_and225_h_u_cla12_and224_y0
1 1
.names h_u_cla12_and223_y0 h_u_cla12_and225_h_u_cla12_and223_y0
1 1
.subckt and_gate _a=h_u_cla12_and225_h_u_cla12_and224_y0 _b=h_u_cla12_and225_h_u_cla12_and223_y0 _y0=h_u_cla12_and225_y0
.names h_u_cla12_pg_logic4_y0 h_u_cla12_and226_h_u_cla12_pg_logic4_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and226_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and226_h_u_cla12_pg_logic4_y0 _b=h_u_cla12_and226_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and226_y0
.names h_u_cla12_and226_y0 h_u_cla12_and227_h_u_cla12_and226_y0
1 1
.names h_u_cla12_and225_y0 h_u_cla12_and227_h_u_cla12_and225_y0
1 1
.subckt and_gate _a=h_u_cla12_and227_h_u_cla12_and226_y0 _b=h_u_cla12_and227_h_u_cla12_and225_y0 _y0=h_u_cla12_and227_y0
.names h_u_cla12_pg_logic5_y0 h_u_cla12_and228_h_u_cla12_pg_logic5_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and228_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and228_h_u_cla12_pg_logic5_y0 _b=h_u_cla12_and228_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and228_y0
.names h_u_cla12_and228_y0 h_u_cla12_and229_h_u_cla12_and228_y0
1 1
.names h_u_cla12_and227_y0 h_u_cla12_and229_h_u_cla12_and227_y0
1 1
.subckt and_gate _a=h_u_cla12_and229_h_u_cla12_and228_y0 _b=h_u_cla12_and229_h_u_cla12_and227_y0 _y0=h_u_cla12_and229_y0
.names h_u_cla12_pg_logic6_y0 h_u_cla12_and230_h_u_cla12_pg_logic6_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and230_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and230_h_u_cla12_pg_logic6_y0 _b=h_u_cla12_and230_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and230_y0
.names h_u_cla12_and230_y0 h_u_cla12_and231_h_u_cla12_and230_y0
1 1
.names h_u_cla12_and229_y0 h_u_cla12_and231_h_u_cla12_and229_y0
1 1
.subckt and_gate _a=h_u_cla12_and231_h_u_cla12_and230_y0 _b=h_u_cla12_and231_h_u_cla12_and229_y0 _y0=h_u_cla12_and231_y0
.names h_u_cla12_pg_logic7_y0 h_u_cla12_and232_h_u_cla12_pg_logic7_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and232_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and232_h_u_cla12_pg_logic7_y0 _b=h_u_cla12_and232_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and232_y0
.names h_u_cla12_and232_y0 h_u_cla12_and233_h_u_cla12_and232_y0
1 1
.names h_u_cla12_and231_y0 h_u_cla12_and233_h_u_cla12_and231_y0
1 1
.subckt and_gate _a=h_u_cla12_and233_h_u_cla12_and232_y0 _b=h_u_cla12_and233_h_u_cla12_and231_y0 _y0=h_u_cla12_and233_y0
.names h_u_cla12_pg_logic8_y0 h_u_cla12_and234_h_u_cla12_pg_logic8_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and234_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and234_h_u_cla12_pg_logic8_y0 _b=h_u_cla12_and234_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and234_y0
.names h_u_cla12_and234_y0 h_u_cla12_and235_h_u_cla12_and234_y0
1 1
.names h_u_cla12_and233_y0 h_u_cla12_and235_h_u_cla12_and233_y0
1 1
.subckt and_gate _a=h_u_cla12_and235_h_u_cla12_and234_y0 _b=h_u_cla12_and235_h_u_cla12_and233_y0 _y0=h_u_cla12_and235_y0
.names h_u_cla12_pg_logic2_y0 h_u_cla12_and236_h_u_cla12_pg_logic2_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and236_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and236_h_u_cla12_pg_logic2_y0 _b=h_u_cla12_and236_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and236_y0
.names h_u_cla12_pg_logic3_y0 h_u_cla12_and237_h_u_cla12_pg_logic3_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and237_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and237_h_u_cla12_pg_logic3_y0 _b=h_u_cla12_and237_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and237_y0
.names h_u_cla12_and237_y0 h_u_cla12_and238_h_u_cla12_and237_y0
1 1
.names h_u_cla12_and236_y0 h_u_cla12_and238_h_u_cla12_and236_y0
1 1
.subckt and_gate _a=h_u_cla12_and238_h_u_cla12_and237_y0 _b=h_u_cla12_and238_h_u_cla12_and236_y0 _y0=h_u_cla12_and238_y0
.names h_u_cla12_pg_logic4_y0 h_u_cla12_and239_h_u_cla12_pg_logic4_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and239_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and239_h_u_cla12_pg_logic4_y0 _b=h_u_cla12_and239_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and239_y0
.names h_u_cla12_and239_y0 h_u_cla12_and240_h_u_cla12_and239_y0
1 1
.names h_u_cla12_and238_y0 h_u_cla12_and240_h_u_cla12_and238_y0
1 1
.subckt and_gate _a=h_u_cla12_and240_h_u_cla12_and239_y0 _b=h_u_cla12_and240_h_u_cla12_and238_y0 _y0=h_u_cla12_and240_y0
.names h_u_cla12_pg_logic5_y0 h_u_cla12_and241_h_u_cla12_pg_logic5_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and241_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and241_h_u_cla12_pg_logic5_y0 _b=h_u_cla12_and241_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and241_y0
.names h_u_cla12_and241_y0 h_u_cla12_and242_h_u_cla12_and241_y0
1 1
.names h_u_cla12_and240_y0 h_u_cla12_and242_h_u_cla12_and240_y0
1 1
.subckt and_gate _a=h_u_cla12_and242_h_u_cla12_and241_y0 _b=h_u_cla12_and242_h_u_cla12_and240_y0 _y0=h_u_cla12_and242_y0
.names h_u_cla12_pg_logic6_y0 h_u_cla12_and243_h_u_cla12_pg_logic6_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and243_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and243_h_u_cla12_pg_logic6_y0 _b=h_u_cla12_and243_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and243_y0
.names h_u_cla12_and243_y0 h_u_cla12_and244_h_u_cla12_and243_y0
1 1
.names h_u_cla12_and242_y0 h_u_cla12_and244_h_u_cla12_and242_y0
1 1
.subckt and_gate _a=h_u_cla12_and244_h_u_cla12_and243_y0 _b=h_u_cla12_and244_h_u_cla12_and242_y0 _y0=h_u_cla12_and244_y0
.names h_u_cla12_pg_logic7_y0 h_u_cla12_and245_h_u_cla12_pg_logic7_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and245_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and245_h_u_cla12_pg_logic7_y0 _b=h_u_cla12_and245_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and245_y0
.names h_u_cla12_and245_y0 h_u_cla12_and246_h_u_cla12_and245_y0
1 1
.names h_u_cla12_and244_y0 h_u_cla12_and246_h_u_cla12_and244_y0
1 1
.subckt and_gate _a=h_u_cla12_and246_h_u_cla12_and245_y0 _b=h_u_cla12_and246_h_u_cla12_and244_y0 _y0=h_u_cla12_and246_y0
.names h_u_cla12_pg_logic8_y0 h_u_cla12_and247_h_u_cla12_pg_logic8_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and247_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and247_h_u_cla12_pg_logic8_y0 _b=h_u_cla12_and247_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and247_y0
.names h_u_cla12_and247_y0 h_u_cla12_and248_h_u_cla12_and247_y0
1 1
.names h_u_cla12_and246_y0 h_u_cla12_and248_h_u_cla12_and246_y0
1 1
.subckt and_gate _a=h_u_cla12_and248_h_u_cla12_and247_y0 _b=h_u_cla12_and248_h_u_cla12_and246_y0 _y0=h_u_cla12_and248_y0
.names h_u_cla12_pg_logic3_y0 h_u_cla12_and249_h_u_cla12_pg_logic3_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and249_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and249_h_u_cla12_pg_logic3_y0 _b=h_u_cla12_and249_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and249_y0
.names h_u_cla12_pg_logic4_y0 h_u_cla12_and250_h_u_cla12_pg_logic4_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and250_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and250_h_u_cla12_pg_logic4_y0 _b=h_u_cla12_and250_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and250_y0
.names h_u_cla12_and250_y0 h_u_cla12_and251_h_u_cla12_and250_y0
1 1
.names h_u_cla12_and249_y0 h_u_cla12_and251_h_u_cla12_and249_y0
1 1
.subckt and_gate _a=h_u_cla12_and251_h_u_cla12_and250_y0 _b=h_u_cla12_and251_h_u_cla12_and249_y0 _y0=h_u_cla12_and251_y0
.names h_u_cla12_pg_logic5_y0 h_u_cla12_and252_h_u_cla12_pg_logic5_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and252_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and252_h_u_cla12_pg_logic5_y0 _b=h_u_cla12_and252_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and252_y0
.names h_u_cla12_and252_y0 h_u_cla12_and253_h_u_cla12_and252_y0
1 1
.names h_u_cla12_and251_y0 h_u_cla12_and253_h_u_cla12_and251_y0
1 1
.subckt and_gate _a=h_u_cla12_and253_h_u_cla12_and252_y0 _b=h_u_cla12_and253_h_u_cla12_and251_y0 _y0=h_u_cla12_and253_y0
.names h_u_cla12_pg_logic6_y0 h_u_cla12_and254_h_u_cla12_pg_logic6_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and254_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and254_h_u_cla12_pg_logic6_y0 _b=h_u_cla12_and254_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and254_y0
.names h_u_cla12_and254_y0 h_u_cla12_and255_h_u_cla12_and254_y0
1 1
.names h_u_cla12_and253_y0 h_u_cla12_and255_h_u_cla12_and253_y0
1 1
.subckt and_gate _a=h_u_cla12_and255_h_u_cla12_and254_y0 _b=h_u_cla12_and255_h_u_cla12_and253_y0 _y0=h_u_cla12_and255_y0
.names h_u_cla12_pg_logic7_y0 h_u_cla12_and256_h_u_cla12_pg_logic7_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and256_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and256_h_u_cla12_pg_logic7_y0 _b=h_u_cla12_and256_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and256_y0
.names h_u_cla12_and256_y0 h_u_cla12_and257_h_u_cla12_and256_y0
1 1
.names h_u_cla12_and255_y0 h_u_cla12_and257_h_u_cla12_and255_y0
1 1
.subckt and_gate _a=h_u_cla12_and257_h_u_cla12_and256_y0 _b=h_u_cla12_and257_h_u_cla12_and255_y0 _y0=h_u_cla12_and257_y0
.names h_u_cla12_pg_logic8_y0 h_u_cla12_and258_h_u_cla12_pg_logic8_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and258_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and258_h_u_cla12_pg_logic8_y0 _b=h_u_cla12_and258_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and258_y0
.names h_u_cla12_and258_y0 h_u_cla12_and259_h_u_cla12_and258_y0
1 1
.names h_u_cla12_and257_y0 h_u_cla12_and259_h_u_cla12_and257_y0
1 1
.subckt and_gate _a=h_u_cla12_and259_h_u_cla12_and258_y0 _b=h_u_cla12_and259_h_u_cla12_and257_y0 _y0=h_u_cla12_and259_y0
.names h_u_cla12_pg_logic4_y0 h_u_cla12_and260_h_u_cla12_pg_logic4_y0
1 1
.names h_u_cla12_pg_logic3_y1 h_u_cla12_and260_h_u_cla12_pg_logic3_y1
1 1
.subckt and_gate _a=h_u_cla12_and260_h_u_cla12_pg_logic4_y0 _b=h_u_cla12_and260_h_u_cla12_pg_logic3_y1 _y0=h_u_cla12_and260_y0
.names h_u_cla12_pg_logic5_y0 h_u_cla12_and261_h_u_cla12_pg_logic5_y0
1 1
.names h_u_cla12_pg_logic3_y1 h_u_cla12_and261_h_u_cla12_pg_logic3_y1
1 1
.subckt and_gate _a=h_u_cla12_and261_h_u_cla12_pg_logic5_y0 _b=h_u_cla12_and261_h_u_cla12_pg_logic3_y1 _y0=h_u_cla12_and261_y0
.names h_u_cla12_and261_y0 h_u_cla12_and262_h_u_cla12_and261_y0
1 1
.names h_u_cla12_and260_y0 h_u_cla12_and262_h_u_cla12_and260_y0
1 1
.subckt and_gate _a=h_u_cla12_and262_h_u_cla12_and261_y0 _b=h_u_cla12_and262_h_u_cla12_and260_y0 _y0=h_u_cla12_and262_y0
.names h_u_cla12_pg_logic6_y0 h_u_cla12_and263_h_u_cla12_pg_logic6_y0
1 1
.names h_u_cla12_pg_logic3_y1 h_u_cla12_and263_h_u_cla12_pg_logic3_y1
1 1
.subckt and_gate _a=h_u_cla12_and263_h_u_cla12_pg_logic6_y0 _b=h_u_cla12_and263_h_u_cla12_pg_logic3_y1 _y0=h_u_cla12_and263_y0
.names h_u_cla12_and263_y0 h_u_cla12_and264_h_u_cla12_and263_y0
1 1
.names h_u_cla12_and262_y0 h_u_cla12_and264_h_u_cla12_and262_y0
1 1
.subckt and_gate _a=h_u_cla12_and264_h_u_cla12_and263_y0 _b=h_u_cla12_and264_h_u_cla12_and262_y0 _y0=h_u_cla12_and264_y0
.names h_u_cla12_pg_logic7_y0 h_u_cla12_and265_h_u_cla12_pg_logic7_y0
1 1
.names h_u_cla12_pg_logic3_y1 h_u_cla12_and265_h_u_cla12_pg_logic3_y1
1 1
.subckt and_gate _a=h_u_cla12_and265_h_u_cla12_pg_logic7_y0 _b=h_u_cla12_and265_h_u_cla12_pg_logic3_y1 _y0=h_u_cla12_and265_y0
.names h_u_cla12_and265_y0 h_u_cla12_and266_h_u_cla12_and265_y0
1 1
.names h_u_cla12_and264_y0 h_u_cla12_and266_h_u_cla12_and264_y0
1 1
.subckt and_gate _a=h_u_cla12_and266_h_u_cla12_and265_y0 _b=h_u_cla12_and266_h_u_cla12_and264_y0 _y0=h_u_cla12_and266_y0
.names h_u_cla12_pg_logic8_y0 h_u_cla12_and267_h_u_cla12_pg_logic8_y0
1 1
.names h_u_cla12_pg_logic3_y1 h_u_cla12_and267_h_u_cla12_pg_logic3_y1
1 1
.subckt and_gate _a=h_u_cla12_and267_h_u_cla12_pg_logic8_y0 _b=h_u_cla12_and267_h_u_cla12_pg_logic3_y1 _y0=h_u_cla12_and267_y0
.names h_u_cla12_and267_y0 h_u_cla12_and268_h_u_cla12_and267_y0
1 1
.names h_u_cla12_and266_y0 h_u_cla12_and268_h_u_cla12_and266_y0
1 1
.subckt and_gate _a=h_u_cla12_and268_h_u_cla12_and267_y0 _b=h_u_cla12_and268_h_u_cla12_and266_y0 _y0=h_u_cla12_and268_y0
.names h_u_cla12_pg_logic5_y0 h_u_cla12_and269_h_u_cla12_pg_logic5_y0
1 1
.names h_u_cla12_pg_logic4_y1 h_u_cla12_and269_h_u_cla12_pg_logic4_y1
1 1
.subckt and_gate _a=h_u_cla12_and269_h_u_cla12_pg_logic5_y0 _b=h_u_cla12_and269_h_u_cla12_pg_logic4_y1 _y0=h_u_cla12_and269_y0
.names h_u_cla12_pg_logic6_y0 h_u_cla12_and270_h_u_cla12_pg_logic6_y0
1 1
.names h_u_cla12_pg_logic4_y1 h_u_cla12_and270_h_u_cla12_pg_logic4_y1
1 1
.subckt and_gate _a=h_u_cla12_and270_h_u_cla12_pg_logic6_y0 _b=h_u_cla12_and270_h_u_cla12_pg_logic4_y1 _y0=h_u_cla12_and270_y0
.names h_u_cla12_and270_y0 h_u_cla12_and271_h_u_cla12_and270_y0
1 1
.names h_u_cla12_and269_y0 h_u_cla12_and271_h_u_cla12_and269_y0
1 1
.subckt and_gate _a=h_u_cla12_and271_h_u_cla12_and270_y0 _b=h_u_cla12_and271_h_u_cla12_and269_y0 _y0=h_u_cla12_and271_y0
.names h_u_cla12_pg_logic7_y0 h_u_cla12_and272_h_u_cla12_pg_logic7_y0
1 1
.names h_u_cla12_pg_logic4_y1 h_u_cla12_and272_h_u_cla12_pg_logic4_y1
1 1
.subckt and_gate _a=h_u_cla12_and272_h_u_cla12_pg_logic7_y0 _b=h_u_cla12_and272_h_u_cla12_pg_logic4_y1 _y0=h_u_cla12_and272_y0
.names h_u_cla12_and272_y0 h_u_cla12_and273_h_u_cla12_and272_y0
1 1
.names h_u_cla12_and271_y0 h_u_cla12_and273_h_u_cla12_and271_y0
1 1
.subckt and_gate _a=h_u_cla12_and273_h_u_cla12_and272_y0 _b=h_u_cla12_and273_h_u_cla12_and271_y0 _y0=h_u_cla12_and273_y0
.names h_u_cla12_pg_logic8_y0 h_u_cla12_and274_h_u_cla12_pg_logic8_y0
1 1
.names h_u_cla12_pg_logic4_y1 h_u_cla12_and274_h_u_cla12_pg_logic4_y1
1 1
.subckt and_gate _a=h_u_cla12_and274_h_u_cla12_pg_logic8_y0 _b=h_u_cla12_and274_h_u_cla12_pg_logic4_y1 _y0=h_u_cla12_and274_y0
.names h_u_cla12_and274_y0 h_u_cla12_and275_h_u_cla12_and274_y0
1 1
.names h_u_cla12_and273_y0 h_u_cla12_and275_h_u_cla12_and273_y0
1 1
.subckt and_gate _a=h_u_cla12_and275_h_u_cla12_and274_y0 _b=h_u_cla12_and275_h_u_cla12_and273_y0 _y0=h_u_cla12_and275_y0
.names h_u_cla12_pg_logic6_y0 h_u_cla12_and276_h_u_cla12_pg_logic6_y0
1 1
.names h_u_cla12_pg_logic5_y1 h_u_cla12_and276_h_u_cla12_pg_logic5_y1
1 1
.subckt and_gate _a=h_u_cla12_and276_h_u_cla12_pg_logic6_y0 _b=h_u_cla12_and276_h_u_cla12_pg_logic5_y1 _y0=h_u_cla12_and276_y0
.names h_u_cla12_pg_logic7_y0 h_u_cla12_and277_h_u_cla12_pg_logic7_y0
1 1
.names h_u_cla12_pg_logic5_y1 h_u_cla12_and277_h_u_cla12_pg_logic5_y1
1 1
.subckt and_gate _a=h_u_cla12_and277_h_u_cla12_pg_logic7_y0 _b=h_u_cla12_and277_h_u_cla12_pg_logic5_y1 _y0=h_u_cla12_and277_y0
.names h_u_cla12_and277_y0 h_u_cla12_and278_h_u_cla12_and277_y0
1 1
.names h_u_cla12_and276_y0 h_u_cla12_and278_h_u_cla12_and276_y0
1 1
.subckt and_gate _a=h_u_cla12_and278_h_u_cla12_and277_y0 _b=h_u_cla12_and278_h_u_cla12_and276_y0 _y0=h_u_cla12_and278_y0
.names h_u_cla12_pg_logic8_y0 h_u_cla12_and279_h_u_cla12_pg_logic8_y0
1 1
.names h_u_cla12_pg_logic5_y1 h_u_cla12_and279_h_u_cla12_pg_logic5_y1
1 1
.subckt and_gate _a=h_u_cla12_and279_h_u_cla12_pg_logic8_y0 _b=h_u_cla12_and279_h_u_cla12_pg_logic5_y1 _y0=h_u_cla12_and279_y0
.names h_u_cla12_and279_y0 h_u_cla12_and280_h_u_cla12_and279_y0
1 1
.names h_u_cla12_and278_y0 h_u_cla12_and280_h_u_cla12_and278_y0
1 1
.subckt and_gate _a=h_u_cla12_and280_h_u_cla12_and279_y0 _b=h_u_cla12_and280_h_u_cla12_and278_y0 _y0=h_u_cla12_and280_y0
.names h_u_cla12_pg_logic7_y0 h_u_cla12_and281_h_u_cla12_pg_logic7_y0
1 1
.names h_u_cla12_pg_logic6_y1 h_u_cla12_and281_h_u_cla12_pg_logic6_y1
1 1
.subckt and_gate _a=h_u_cla12_and281_h_u_cla12_pg_logic7_y0 _b=h_u_cla12_and281_h_u_cla12_pg_logic6_y1 _y0=h_u_cla12_and281_y0
.names h_u_cla12_pg_logic8_y0 h_u_cla12_and282_h_u_cla12_pg_logic8_y0
1 1
.names h_u_cla12_pg_logic6_y1 h_u_cla12_and282_h_u_cla12_pg_logic6_y1
1 1
.subckt and_gate _a=h_u_cla12_and282_h_u_cla12_pg_logic8_y0 _b=h_u_cla12_and282_h_u_cla12_pg_logic6_y1 _y0=h_u_cla12_and282_y0
.names h_u_cla12_and282_y0 h_u_cla12_and283_h_u_cla12_and282_y0
1 1
.names h_u_cla12_and281_y0 h_u_cla12_and283_h_u_cla12_and281_y0
1 1
.subckt and_gate _a=h_u_cla12_and283_h_u_cla12_and282_y0 _b=h_u_cla12_and283_h_u_cla12_and281_y0 _y0=h_u_cla12_and283_y0
.names h_u_cla12_pg_logic8_y0 h_u_cla12_and284_h_u_cla12_pg_logic8_y0
1 1
.names h_u_cla12_pg_logic7_y1 h_u_cla12_and284_h_u_cla12_pg_logic7_y1
1 1
.subckt and_gate _a=h_u_cla12_and284_h_u_cla12_pg_logic8_y0 _b=h_u_cla12_and284_h_u_cla12_pg_logic7_y1 _y0=h_u_cla12_and284_y0
.names h_u_cla12_and284_y0 h_u_cla12_or36_h_u_cla12_and284_y0
1 1
.names h_u_cla12_and220_y0 h_u_cla12_or36_h_u_cla12_and220_y0
1 1
.subckt or_gate _a=h_u_cla12_or36_h_u_cla12_and284_y0 _b=h_u_cla12_or36_h_u_cla12_and220_y0 _y0=h_u_cla12_or36_y0
.names h_u_cla12_or36_y0 h_u_cla12_or37_h_u_cla12_or36_y0
1 1
.names h_u_cla12_and235_y0 h_u_cla12_or37_h_u_cla12_and235_y0
1 1
.subckt or_gate _a=h_u_cla12_or37_h_u_cla12_or36_y0 _b=h_u_cla12_or37_h_u_cla12_and235_y0 _y0=h_u_cla12_or37_y0
.names h_u_cla12_or37_y0 h_u_cla12_or38_h_u_cla12_or37_y0
1 1
.names h_u_cla12_and248_y0 h_u_cla12_or38_h_u_cla12_and248_y0
1 1
.subckt or_gate _a=h_u_cla12_or38_h_u_cla12_or37_y0 _b=h_u_cla12_or38_h_u_cla12_and248_y0 _y0=h_u_cla12_or38_y0
.names h_u_cla12_or38_y0 h_u_cla12_or39_h_u_cla12_or38_y0
1 1
.names h_u_cla12_and259_y0 h_u_cla12_or39_h_u_cla12_and259_y0
1 1
.subckt or_gate _a=h_u_cla12_or39_h_u_cla12_or38_y0 _b=h_u_cla12_or39_h_u_cla12_and259_y0 _y0=h_u_cla12_or39_y0
.names h_u_cla12_or39_y0 h_u_cla12_or40_h_u_cla12_or39_y0
1 1
.names h_u_cla12_and268_y0 h_u_cla12_or40_h_u_cla12_and268_y0
1 1
.subckt or_gate _a=h_u_cla12_or40_h_u_cla12_or39_y0 _b=h_u_cla12_or40_h_u_cla12_and268_y0 _y0=h_u_cla12_or40_y0
.names h_u_cla12_or40_y0 h_u_cla12_or41_h_u_cla12_or40_y0
1 1
.names h_u_cla12_and275_y0 h_u_cla12_or41_h_u_cla12_and275_y0
1 1
.subckt or_gate _a=h_u_cla12_or41_h_u_cla12_or40_y0 _b=h_u_cla12_or41_h_u_cla12_and275_y0 _y0=h_u_cla12_or41_y0
.names h_u_cla12_or41_y0 h_u_cla12_or42_h_u_cla12_or41_y0
1 1
.names h_u_cla12_and280_y0 h_u_cla12_or42_h_u_cla12_and280_y0
1 1
.subckt or_gate _a=h_u_cla12_or42_h_u_cla12_or41_y0 _b=h_u_cla12_or42_h_u_cla12_and280_y0 _y0=h_u_cla12_or42_y0
.names h_u_cla12_or42_y0 h_u_cla12_or43_h_u_cla12_or42_y0
1 1
.names h_u_cla12_and283_y0 h_u_cla12_or43_h_u_cla12_and283_y0
1 1
.subckt or_gate _a=h_u_cla12_or43_h_u_cla12_or42_y0 _b=h_u_cla12_or43_h_u_cla12_and283_y0 _y0=h_u_cla12_or43_y0
.names h_u_cla12_pg_logic8_y1 h_u_cla12_or44_h_u_cla12_pg_logic8_y1
1 1
.names h_u_cla12_or43_y0 h_u_cla12_or44_h_u_cla12_or43_y0
1 1
.subckt or_gate _a=h_u_cla12_or44_h_u_cla12_pg_logic8_y1 _b=h_u_cla12_or44_h_u_cla12_or43_y0 _y0=h_u_cla12_or44_y0
.names a_9 h_u_cla12_pg_logic9_a_9
1 1
.names b_9 h_u_cla12_pg_logic9_b_9
1 1
.subckt pg_logic a=h_u_cla12_pg_logic9_a_9 b=h_u_cla12_pg_logic9_b_9 pg_logic_y0=h_u_cla12_pg_logic9_y0 pg_logic_y1=h_u_cla12_pg_logic9_y1 pg_logic_y2=h_u_cla12_pg_logic9_y2
.names h_u_cla12_pg_logic9_y2 h_u_cla12_xor9_h_u_cla12_pg_logic9_y2
1 1
.names h_u_cla12_or44_y0 h_u_cla12_xor9_h_u_cla12_or44_y0
1 1
.subckt xor_gate _a=h_u_cla12_xor9_h_u_cla12_pg_logic9_y2 _b=h_u_cla12_xor9_h_u_cla12_or44_y0 _y0=h_u_cla12_xor9_y0
.names h_u_cla12_pg_logic0_y0 h_u_cla12_and285_h_u_cla12_pg_logic0_y0
1 1
.names constant_wire_0 h_u_cla12_and285_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and285_h_u_cla12_pg_logic0_y0 _b=h_u_cla12_and285_constant_wire_0 _y0=h_u_cla12_and285_y0
.names h_u_cla12_pg_logic1_y0 h_u_cla12_and286_h_u_cla12_pg_logic1_y0
1 1
.names constant_wire_0 h_u_cla12_and286_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and286_h_u_cla12_pg_logic1_y0 _b=h_u_cla12_and286_constant_wire_0 _y0=h_u_cla12_and286_y0
.names h_u_cla12_and286_y0 h_u_cla12_and287_h_u_cla12_and286_y0
1 1
.names h_u_cla12_and285_y0 h_u_cla12_and287_h_u_cla12_and285_y0
1 1
.subckt and_gate _a=h_u_cla12_and287_h_u_cla12_and286_y0 _b=h_u_cla12_and287_h_u_cla12_and285_y0 _y0=h_u_cla12_and287_y0
.names h_u_cla12_pg_logic2_y0 h_u_cla12_and288_h_u_cla12_pg_logic2_y0
1 1
.names constant_wire_0 h_u_cla12_and288_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and288_h_u_cla12_pg_logic2_y0 _b=h_u_cla12_and288_constant_wire_0 _y0=h_u_cla12_and288_y0
.names h_u_cla12_and288_y0 h_u_cla12_and289_h_u_cla12_and288_y0
1 1
.names h_u_cla12_and287_y0 h_u_cla12_and289_h_u_cla12_and287_y0
1 1
.subckt and_gate _a=h_u_cla12_and289_h_u_cla12_and288_y0 _b=h_u_cla12_and289_h_u_cla12_and287_y0 _y0=h_u_cla12_and289_y0
.names h_u_cla12_pg_logic3_y0 h_u_cla12_and290_h_u_cla12_pg_logic3_y0
1 1
.names constant_wire_0 h_u_cla12_and290_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and290_h_u_cla12_pg_logic3_y0 _b=h_u_cla12_and290_constant_wire_0 _y0=h_u_cla12_and290_y0
.names h_u_cla12_and290_y0 h_u_cla12_and291_h_u_cla12_and290_y0
1 1
.names h_u_cla12_and289_y0 h_u_cla12_and291_h_u_cla12_and289_y0
1 1
.subckt and_gate _a=h_u_cla12_and291_h_u_cla12_and290_y0 _b=h_u_cla12_and291_h_u_cla12_and289_y0 _y0=h_u_cla12_and291_y0
.names h_u_cla12_pg_logic4_y0 h_u_cla12_and292_h_u_cla12_pg_logic4_y0
1 1
.names constant_wire_0 h_u_cla12_and292_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and292_h_u_cla12_pg_logic4_y0 _b=h_u_cla12_and292_constant_wire_0 _y0=h_u_cla12_and292_y0
.names h_u_cla12_and292_y0 h_u_cla12_and293_h_u_cla12_and292_y0
1 1
.names h_u_cla12_and291_y0 h_u_cla12_and293_h_u_cla12_and291_y0
1 1
.subckt and_gate _a=h_u_cla12_and293_h_u_cla12_and292_y0 _b=h_u_cla12_and293_h_u_cla12_and291_y0 _y0=h_u_cla12_and293_y0
.names h_u_cla12_pg_logic5_y0 h_u_cla12_and294_h_u_cla12_pg_logic5_y0
1 1
.names constant_wire_0 h_u_cla12_and294_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and294_h_u_cla12_pg_logic5_y0 _b=h_u_cla12_and294_constant_wire_0 _y0=h_u_cla12_and294_y0
.names h_u_cla12_and294_y0 h_u_cla12_and295_h_u_cla12_and294_y0
1 1
.names h_u_cla12_and293_y0 h_u_cla12_and295_h_u_cla12_and293_y0
1 1
.subckt and_gate _a=h_u_cla12_and295_h_u_cla12_and294_y0 _b=h_u_cla12_and295_h_u_cla12_and293_y0 _y0=h_u_cla12_and295_y0
.names h_u_cla12_pg_logic6_y0 h_u_cla12_and296_h_u_cla12_pg_logic6_y0
1 1
.names constant_wire_0 h_u_cla12_and296_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and296_h_u_cla12_pg_logic6_y0 _b=h_u_cla12_and296_constant_wire_0 _y0=h_u_cla12_and296_y0
.names h_u_cla12_and296_y0 h_u_cla12_and297_h_u_cla12_and296_y0
1 1
.names h_u_cla12_and295_y0 h_u_cla12_and297_h_u_cla12_and295_y0
1 1
.subckt and_gate _a=h_u_cla12_and297_h_u_cla12_and296_y0 _b=h_u_cla12_and297_h_u_cla12_and295_y0 _y0=h_u_cla12_and297_y0
.names h_u_cla12_pg_logic7_y0 h_u_cla12_and298_h_u_cla12_pg_logic7_y0
1 1
.names constant_wire_0 h_u_cla12_and298_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and298_h_u_cla12_pg_logic7_y0 _b=h_u_cla12_and298_constant_wire_0 _y0=h_u_cla12_and298_y0
.names h_u_cla12_and298_y0 h_u_cla12_and299_h_u_cla12_and298_y0
1 1
.names h_u_cla12_and297_y0 h_u_cla12_and299_h_u_cla12_and297_y0
1 1
.subckt and_gate _a=h_u_cla12_and299_h_u_cla12_and298_y0 _b=h_u_cla12_and299_h_u_cla12_and297_y0 _y0=h_u_cla12_and299_y0
.names h_u_cla12_pg_logic8_y0 h_u_cla12_and300_h_u_cla12_pg_logic8_y0
1 1
.names constant_wire_0 h_u_cla12_and300_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and300_h_u_cla12_pg_logic8_y0 _b=h_u_cla12_and300_constant_wire_0 _y0=h_u_cla12_and300_y0
.names h_u_cla12_and300_y0 h_u_cla12_and301_h_u_cla12_and300_y0
1 1
.names h_u_cla12_and299_y0 h_u_cla12_and301_h_u_cla12_and299_y0
1 1
.subckt and_gate _a=h_u_cla12_and301_h_u_cla12_and300_y0 _b=h_u_cla12_and301_h_u_cla12_and299_y0 _y0=h_u_cla12_and301_y0
.names h_u_cla12_pg_logic9_y0 h_u_cla12_and302_h_u_cla12_pg_logic9_y0
1 1
.names constant_wire_0 h_u_cla12_and302_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and302_h_u_cla12_pg_logic9_y0 _b=h_u_cla12_and302_constant_wire_0 _y0=h_u_cla12_and302_y0
.names h_u_cla12_and302_y0 h_u_cla12_and303_h_u_cla12_and302_y0
1 1
.names h_u_cla12_and301_y0 h_u_cla12_and303_h_u_cla12_and301_y0
1 1
.subckt and_gate _a=h_u_cla12_and303_h_u_cla12_and302_y0 _b=h_u_cla12_and303_h_u_cla12_and301_y0 _y0=h_u_cla12_and303_y0
.names h_u_cla12_pg_logic1_y0 h_u_cla12_and304_h_u_cla12_pg_logic1_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and304_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and304_h_u_cla12_pg_logic1_y0 _b=h_u_cla12_and304_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and304_y0
.names h_u_cla12_pg_logic2_y0 h_u_cla12_and305_h_u_cla12_pg_logic2_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and305_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and305_h_u_cla12_pg_logic2_y0 _b=h_u_cla12_and305_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and305_y0
.names h_u_cla12_and305_y0 h_u_cla12_and306_h_u_cla12_and305_y0
1 1
.names h_u_cla12_and304_y0 h_u_cla12_and306_h_u_cla12_and304_y0
1 1
.subckt and_gate _a=h_u_cla12_and306_h_u_cla12_and305_y0 _b=h_u_cla12_and306_h_u_cla12_and304_y0 _y0=h_u_cla12_and306_y0
.names h_u_cla12_pg_logic3_y0 h_u_cla12_and307_h_u_cla12_pg_logic3_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and307_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and307_h_u_cla12_pg_logic3_y0 _b=h_u_cla12_and307_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and307_y0
.names h_u_cla12_and307_y0 h_u_cla12_and308_h_u_cla12_and307_y0
1 1
.names h_u_cla12_and306_y0 h_u_cla12_and308_h_u_cla12_and306_y0
1 1
.subckt and_gate _a=h_u_cla12_and308_h_u_cla12_and307_y0 _b=h_u_cla12_and308_h_u_cla12_and306_y0 _y0=h_u_cla12_and308_y0
.names h_u_cla12_pg_logic4_y0 h_u_cla12_and309_h_u_cla12_pg_logic4_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and309_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and309_h_u_cla12_pg_logic4_y0 _b=h_u_cla12_and309_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and309_y0
.names h_u_cla12_and309_y0 h_u_cla12_and310_h_u_cla12_and309_y0
1 1
.names h_u_cla12_and308_y0 h_u_cla12_and310_h_u_cla12_and308_y0
1 1
.subckt and_gate _a=h_u_cla12_and310_h_u_cla12_and309_y0 _b=h_u_cla12_and310_h_u_cla12_and308_y0 _y0=h_u_cla12_and310_y0
.names h_u_cla12_pg_logic5_y0 h_u_cla12_and311_h_u_cla12_pg_logic5_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and311_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and311_h_u_cla12_pg_logic5_y0 _b=h_u_cla12_and311_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and311_y0
.names h_u_cla12_and311_y0 h_u_cla12_and312_h_u_cla12_and311_y0
1 1
.names h_u_cla12_and310_y0 h_u_cla12_and312_h_u_cla12_and310_y0
1 1
.subckt and_gate _a=h_u_cla12_and312_h_u_cla12_and311_y0 _b=h_u_cla12_and312_h_u_cla12_and310_y0 _y0=h_u_cla12_and312_y0
.names h_u_cla12_pg_logic6_y0 h_u_cla12_and313_h_u_cla12_pg_logic6_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and313_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and313_h_u_cla12_pg_logic6_y0 _b=h_u_cla12_and313_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and313_y0
.names h_u_cla12_and313_y0 h_u_cla12_and314_h_u_cla12_and313_y0
1 1
.names h_u_cla12_and312_y0 h_u_cla12_and314_h_u_cla12_and312_y0
1 1
.subckt and_gate _a=h_u_cla12_and314_h_u_cla12_and313_y0 _b=h_u_cla12_and314_h_u_cla12_and312_y0 _y0=h_u_cla12_and314_y0
.names h_u_cla12_pg_logic7_y0 h_u_cla12_and315_h_u_cla12_pg_logic7_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and315_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and315_h_u_cla12_pg_logic7_y0 _b=h_u_cla12_and315_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and315_y0
.names h_u_cla12_and315_y0 h_u_cla12_and316_h_u_cla12_and315_y0
1 1
.names h_u_cla12_and314_y0 h_u_cla12_and316_h_u_cla12_and314_y0
1 1
.subckt and_gate _a=h_u_cla12_and316_h_u_cla12_and315_y0 _b=h_u_cla12_and316_h_u_cla12_and314_y0 _y0=h_u_cla12_and316_y0
.names h_u_cla12_pg_logic8_y0 h_u_cla12_and317_h_u_cla12_pg_logic8_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and317_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and317_h_u_cla12_pg_logic8_y0 _b=h_u_cla12_and317_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and317_y0
.names h_u_cla12_and317_y0 h_u_cla12_and318_h_u_cla12_and317_y0
1 1
.names h_u_cla12_and316_y0 h_u_cla12_and318_h_u_cla12_and316_y0
1 1
.subckt and_gate _a=h_u_cla12_and318_h_u_cla12_and317_y0 _b=h_u_cla12_and318_h_u_cla12_and316_y0 _y0=h_u_cla12_and318_y0
.names h_u_cla12_pg_logic9_y0 h_u_cla12_and319_h_u_cla12_pg_logic9_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and319_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and319_h_u_cla12_pg_logic9_y0 _b=h_u_cla12_and319_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and319_y0
.names h_u_cla12_and319_y0 h_u_cla12_and320_h_u_cla12_and319_y0
1 1
.names h_u_cla12_and318_y0 h_u_cla12_and320_h_u_cla12_and318_y0
1 1
.subckt and_gate _a=h_u_cla12_and320_h_u_cla12_and319_y0 _b=h_u_cla12_and320_h_u_cla12_and318_y0 _y0=h_u_cla12_and320_y0
.names h_u_cla12_pg_logic2_y0 h_u_cla12_and321_h_u_cla12_pg_logic2_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and321_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and321_h_u_cla12_pg_logic2_y0 _b=h_u_cla12_and321_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and321_y0
.names h_u_cla12_pg_logic3_y0 h_u_cla12_and322_h_u_cla12_pg_logic3_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and322_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and322_h_u_cla12_pg_logic3_y0 _b=h_u_cla12_and322_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and322_y0
.names h_u_cla12_and322_y0 h_u_cla12_and323_h_u_cla12_and322_y0
1 1
.names h_u_cla12_and321_y0 h_u_cla12_and323_h_u_cla12_and321_y0
1 1
.subckt and_gate _a=h_u_cla12_and323_h_u_cla12_and322_y0 _b=h_u_cla12_and323_h_u_cla12_and321_y0 _y0=h_u_cla12_and323_y0
.names h_u_cla12_pg_logic4_y0 h_u_cla12_and324_h_u_cla12_pg_logic4_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and324_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and324_h_u_cla12_pg_logic4_y0 _b=h_u_cla12_and324_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and324_y0
.names h_u_cla12_and324_y0 h_u_cla12_and325_h_u_cla12_and324_y0
1 1
.names h_u_cla12_and323_y0 h_u_cla12_and325_h_u_cla12_and323_y0
1 1
.subckt and_gate _a=h_u_cla12_and325_h_u_cla12_and324_y0 _b=h_u_cla12_and325_h_u_cla12_and323_y0 _y0=h_u_cla12_and325_y0
.names h_u_cla12_pg_logic5_y0 h_u_cla12_and326_h_u_cla12_pg_logic5_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and326_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and326_h_u_cla12_pg_logic5_y0 _b=h_u_cla12_and326_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and326_y0
.names h_u_cla12_and326_y0 h_u_cla12_and327_h_u_cla12_and326_y0
1 1
.names h_u_cla12_and325_y0 h_u_cla12_and327_h_u_cla12_and325_y0
1 1
.subckt and_gate _a=h_u_cla12_and327_h_u_cla12_and326_y0 _b=h_u_cla12_and327_h_u_cla12_and325_y0 _y0=h_u_cla12_and327_y0
.names h_u_cla12_pg_logic6_y0 h_u_cla12_and328_h_u_cla12_pg_logic6_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and328_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and328_h_u_cla12_pg_logic6_y0 _b=h_u_cla12_and328_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and328_y0
.names h_u_cla12_and328_y0 h_u_cla12_and329_h_u_cla12_and328_y0
1 1
.names h_u_cla12_and327_y0 h_u_cla12_and329_h_u_cla12_and327_y0
1 1
.subckt and_gate _a=h_u_cla12_and329_h_u_cla12_and328_y0 _b=h_u_cla12_and329_h_u_cla12_and327_y0 _y0=h_u_cla12_and329_y0
.names h_u_cla12_pg_logic7_y0 h_u_cla12_and330_h_u_cla12_pg_logic7_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and330_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and330_h_u_cla12_pg_logic7_y0 _b=h_u_cla12_and330_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and330_y0
.names h_u_cla12_and330_y0 h_u_cla12_and331_h_u_cla12_and330_y0
1 1
.names h_u_cla12_and329_y0 h_u_cla12_and331_h_u_cla12_and329_y0
1 1
.subckt and_gate _a=h_u_cla12_and331_h_u_cla12_and330_y0 _b=h_u_cla12_and331_h_u_cla12_and329_y0 _y0=h_u_cla12_and331_y0
.names h_u_cla12_pg_logic8_y0 h_u_cla12_and332_h_u_cla12_pg_logic8_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and332_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and332_h_u_cla12_pg_logic8_y0 _b=h_u_cla12_and332_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and332_y0
.names h_u_cla12_and332_y0 h_u_cla12_and333_h_u_cla12_and332_y0
1 1
.names h_u_cla12_and331_y0 h_u_cla12_and333_h_u_cla12_and331_y0
1 1
.subckt and_gate _a=h_u_cla12_and333_h_u_cla12_and332_y0 _b=h_u_cla12_and333_h_u_cla12_and331_y0 _y0=h_u_cla12_and333_y0
.names h_u_cla12_pg_logic9_y0 h_u_cla12_and334_h_u_cla12_pg_logic9_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and334_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and334_h_u_cla12_pg_logic9_y0 _b=h_u_cla12_and334_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and334_y0
.names h_u_cla12_and334_y0 h_u_cla12_and335_h_u_cla12_and334_y0
1 1
.names h_u_cla12_and333_y0 h_u_cla12_and335_h_u_cla12_and333_y0
1 1
.subckt and_gate _a=h_u_cla12_and335_h_u_cla12_and334_y0 _b=h_u_cla12_and335_h_u_cla12_and333_y0 _y0=h_u_cla12_and335_y0
.names h_u_cla12_pg_logic3_y0 h_u_cla12_and336_h_u_cla12_pg_logic3_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and336_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and336_h_u_cla12_pg_logic3_y0 _b=h_u_cla12_and336_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and336_y0
.names h_u_cla12_pg_logic4_y0 h_u_cla12_and337_h_u_cla12_pg_logic4_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and337_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and337_h_u_cla12_pg_logic4_y0 _b=h_u_cla12_and337_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and337_y0
.names h_u_cla12_and337_y0 h_u_cla12_and338_h_u_cla12_and337_y0
1 1
.names h_u_cla12_and336_y0 h_u_cla12_and338_h_u_cla12_and336_y0
1 1
.subckt and_gate _a=h_u_cla12_and338_h_u_cla12_and337_y0 _b=h_u_cla12_and338_h_u_cla12_and336_y0 _y0=h_u_cla12_and338_y0
.names h_u_cla12_pg_logic5_y0 h_u_cla12_and339_h_u_cla12_pg_logic5_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and339_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and339_h_u_cla12_pg_logic5_y0 _b=h_u_cla12_and339_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and339_y0
.names h_u_cla12_and339_y0 h_u_cla12_and340_h_u_cla12_and339_y0
1 1
.names h_u_cla12_and338_y0 h_u_cla12_and340_h_u_cla12_and338_y0
1 1
.subckt and_gate _a=h_u_cla12_and340_h_u_cla12_and339_y0 _b=h_u_cla12_and340_h_u_cla12_and338_y0 _y0=h_u_cla12_and340_y0
.names h_u_cla12_pg_logic6_y0 h_u_cla12_and341_h_u_cla12_pg_logic6_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and341_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and341_h_u_cla12_pg_logic6_y0 _b=h_u_cla12_and341_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and341_y0
.names h_u_cla12_and341_y0 h_u_cla12_and342_h_u_cla12_and341_y0
1 1
.names h_u_cla12_and340_y0 h_u_cla12_and342_h_u_cla12_and340_y0
1 1
.subckt and_gate _a=h_u_cla12_and342_h_u_cla12_and341_y0 _b=h_u_cla12_and342_h_u_cla12_and340_y0 _y0=h_u_cla12_and342_y0
.names h_u_cla12_pg_logic7_y0 h_u_cla12_and343_h_u_cla12_pg_logic7_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and343_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and343_h_u_cla12_pg_logic7_y0 _b=h_u_cla12_and343_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and343_y0
.names h_u_cla12_and343_y0 h_u_cla12_and344_h_u_cla12_and343_y0
1 1
.names h_u_cla12_and342_y0 h_u_cla12_and344_h_u_cla12_and342_y0
1 1
.subckt and_gate _a=h_u_cla12_and344_h_u_cla12_and343_y0 _b=h_u_cla12_and344_h_u_cla12_and342_y0 _y0=h_u_cla12_and344_y0
.names h_u_cla12_pg_logic8_y0 h_u_cla12_and345_h_u_cla12_pg_logic8_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and345_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and345_h_u_cla12_pg_logic8_y0 _b=h_u_cla12_and345_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and345_y0
.names h_u_cla12_and345_y0 h_u_cla12_and346_h_u_cla12_and345_y0
1 1
.names h_u_cla12_and344_y0 h_u_cla12_and346_h_u_cla12_and344_y0
1 1
.subckt and_gate _a=h_u_cla12_and346_h_u_cla12_and345_y0 _b=h_u_cla12_and346_h_u_cla12_and344_y0 _y0=h_u_cla12_and346_y0
.names h_u_cla12_pg_logic9_y0 h_u_cla12_and347_h_u_cla12_pg_logic9_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and347_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and347_h_u_cla12_pg_logic9_y0 _b=h_u_cla12_and347_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and347_y0
.names h_u_cla12_and347_y0 h_u_cla12_and348_h_u_cla12_and347_y0
1 1
.names h_u_cla12_and346_y0 h_u_cla12_and348_h_u_cla12_and346_y0
1 1
.subckt and_gate _a=h_u_cla12_and348_h_u_cla12_and347_y0 _b=h_u_cla12_and348_h_u_cla12_and346_y0 _y0=h_u_cla12_and348_y0
.names h_u_cla12_pg_logic4_y0 h_u_cla12_and349_h_u_cla12_pg_logic4_y0
1 1
.names h_u_cla12_pg_logic3_y1 h_u_cla12_and349_h_u_cla12_pg_logic3_y1
1 1
.subckt and_gate _a=h_u_cla12_and349_h_u_cla12_pg_logic4_y0 _b=h_u_cla12_and349_h_u_cla12_pg_logic3_y1 _y0=h_u_cla12_and349_y0
.names h_u_cla12_pg_logic5_y0 h_u_cla12_and350_h_u_cla12_pg_logic5_y0
1 1
.names h_u_cla12_pg_logic3_y1 h_u_cla12_and350_h_u_cla12_pg_logic3_y1
1 1
.subckt and_gate _a=h_u_cla12_and350_h_u_cla12_pg_logic5_y0 _b=h_u_cla12_and350_h_u_cla12_pg_logic3_y1 _y0=h_u_cla12_and350_y0
.names h_u_cla12_and350_y0 h_u_cla12_and351_h_u_cla12_and350_y0
1 1
.names h_u_cla12_and349_y0 h_u_cla12_and351_h_u_cla12_and349_y0
1 1
.subckt and_gate _a=h_u_cla12_and351_h_u_cla12_and350_y0 _b=h_u_cla12_and351_h_u_cla12_and349_y0 _y0=h_u_cla12_and351_y0
.names h_u_cla12_pg_logic6_y0 h_u_cla12_and352_h_u_cla12_pg_logic6_y0
1 1
.names h_u_cla12_pg_logic3_y1 h_u_cla12_and352_h_u_cla12_pg_logic3_y1
1 1
.subckt and_gate _a=h_u_cla12_and352_h_u_cla12_pg_logic6_y0 _b=h_u_cla12_and352_h_u_cla12_pg_logic3_y1 _y0=h_u_cla12_and352_y0
.names h_u_cla12_and352_y0 h_u_cla12_and353_h_u_cla12_and352_y0
1 1
.names h_u_cla12_and351_y0 h_u_cla12_and353_h_u_cla12_and351_y0
1 1
.subckt and_gate _a=h_u_cla12_and353_h_u_cla12_and352_y0 _b=h_u_cla12_and353_h_u_cla12_and351_y0 _y0=h_u_cla12_and353_y0
.names h_u_cla12_pg_logic7_y0 h_u_cla12_and354_h_u_cla12_pg_logic7_y0
1 1
.names h_u_cla12_pg_logic3_y1 h_u_cla12_and354_h_u_cla12_pg_logic3_y1
1 1
.subckt and_gate _a=h_u_cla12_and354_h_u_cla12_pg_logic7_y0 _b=h_u_cla12_and354_h_u_cla12_pg_logic3_y1 _y0=h_u_cla12_and354_y0
.names h_u_cla12_and354_y0 h_u_cla12_and355_h_u_cla12_and354_y0
1 1
.names h_u_cla12_and353_y0 h_u_cla12_and355_h_u_cla12_and353_y0
1 1
.subckt and_gate _a=h_u_cla12_and355_h_u_cla12_and354_y0 _b=h_u_cla12_and355_h_u_cla12_and353_y0 _y0=h_u_cla12_and355_y0
.names h_u_cla12_pg_logic8_y0 h_u_cla12_and356_h_u_cla12_pg_logic8_y0
1 1
.names h_u_cla12_pg_logic3_y1 h_u_cla12_and356_h_u_cla12_pg_logic3_y1
1 1
.subckt and_gate _a=h_u_cla12_and356_h_u_cla12_pg_logic8_y0 _b=h_u_cla12_and356_h_u_cla12_pg_logic3_y1 _y0=h_u_cla12_and356_y0
.names h_u_cla12_and356_y0 h_u_cla12_and357_h_u_cla12_and356_y0
1 1
.names h_u_cla12_and355_y0 h_u_cla12_and357_h_u_cla12_and355_y0
1 1
.subckt and_gate _a=h_u_cla12_and357_h_u_cla12_and356_y0 _b=h_u_cla12_and357_h_u_cla12_and355_y0 _y0=h_u_cla12_and357_y0
.names h_u_cla12_pg_logic9_y0 h_u_cla12_and358_h_u_cla12_pg_logic9_y0
1 1
.names h_u_cla12_pg_logic3_y1 h_u_cla12_and358_h_u_cla12_pg_logic3_y1
1 1
.subckt and_gate _a=h_u_cla12_and358_h_u_cla12_pg_logic9_y0 _b=h_u_cla12_and358_h_u_cla12_pg_logic3_y1 _y0=h_u_cla12_and358_y0
.names h_u_cla12_and358_y0 h_u_cla12_and359_h_u_cla12_and358_y0
1 1
.names h_u_cla12_and357_y0 h_u_cla12_and359_h_u_cla12_and357_y0
1 1
.subckt and_gate _a=h_u_cla12_and359_h_u_cla12_and358_y0 _b=h_u_cla12_and359_h_u_cla12_and357_y0 _y0=h_u_cla12_and359_y0
.names h_u_cla12_pg_logic5_y0 h_u_cla12_and360_h_u_cla12_pg_logic5_y0
1 1
.names h_u_cla12_pg_logic4_y1 h_u_cla12_and360_h_u_cla12_pg_logic4_y1
1 1
.subckt and_gate _a=h_u_cla12_and360_h_u_cla12_pg_logic5_y0 _b=h_u_cla12_and360_h_u_cla12_pg_logic4_y1 _y0=h_u_cla12_and360_y0
.names h_u_cla12_pg_logic6_y0 h_u_cla12_and361_h_u_cla12_pg_logic6_y0
1 1
.names h_u_cla12_pg_logic4_y1 h_u_cla12_and361_h_u_cla12_pg_logic4_y1
1 1
.subckt and_gate _a=h_u_cla12_and361_h_u_cla12_pg_logic6_y0 _b=h_u_cla12_and361_h_u_cla12_pg_logic4_y1 _y0=h_u_cla12_and361_y0
.names h_u_cla12_and361_y0 h_u_cla12_and362_h_u_cla12_and361_y0
1 1
.names h_u_cla12_and360_y0 h_u_cla12_and362_h_u_cla12_and360_y0
1 1
.subckt and_gate _a=h_u_cla12_and362_h_u_cla12_and361_y0 _b=h_u_cla12_and362_h_u_cla12_and360_y0 _y0=h_u_cla12_and362_y0
.names h_u_cla12_pg_logic7_y0 h_u_cla12_and363_h_u_cla12_pg_logic7_y0
1 1
.names h_u_cla12_pg_logic4_y1 h_u_cla12_and363_h_u_cla12_pg_logic4_y1
1 1
.subckt and_gate _a=h_u_cla12_and363_h_u_cla12_pg_logic7_y0 _b=h_u_cla12_and363_h_u_cla12_pg_logic4_y1 _y0=h_u_cla12_and363_y0
.names h_u_cla12_and363_y0 h_u_cla12_and364_h_u_cla12_and363_y0
1 1
.names h_u_cla12_and362_y0 h_u_cla12_and364_h_u_cla12_and362_y0
1 1
.subckt and_gate _a=h_u_cla12_and364_h_u_cla12_and363_y0 _b=h_u_cla12_and364_h_u_cla12_and362_y0 _y0=h_u_cla12_and364_y0
.names h_u_cla12_pg_logic8_y0 h_u_cla12_and365_h_u_cla12_pg_logic8_y0
1 1
.names h_u_cla12_pg_logic4_y1 h_u_cla12_and365_h_u_cla12_pg_logic4_y1
1 1
.subckt and_gate _a=h_u_cla12_and365_h_u_cla12_pg_logic8_y0 _b=h_u_cla12_and365_h_u_cla12_pg_logic4_y1 _y0=h_u_cla12_and365_y0
.names h_u_cla12_and365_y0 h_u_cla12_and366_h_u_cla12_and365_y0
1 1
.names h_u_cla12_and364_y0 h_u_cla12_and366_h_u_cla12_and364_y0
1 1
.subckt and_gate _a=h_u_cla12_and366_h_u_cla12_and365_y0 _b=h_u_cla12_and366_h_u_cla12_and364_y0 _y0=h_u_cla12_and366_y0
.names h_u_cla12_pg_logic9_y0 h_u_cla12_and367_h_u_cla12_pg_logic9_y0
1 1
.names h_u_cla12_pg_logic4_y1 h_u_cla12_and367_h_u_cla12_pg_logic4_y1
1 1
.subckt and_gate _a=h_u_cla12_and367_h_u_cla12_pg_logic9_y0 _b=h_u_cla12_and367_h_u_cla12_pg_logic4_y1 _y0=h_u_cla12_and367_y0
.names h_u_cla12_and367_y0 h_u_cla12_and368_h_u_cla12_and367_y0
1 1
.names h_u_cla12_and366_y0 h_u_cla12_and368_h_u_cla12_and366_y0
1 1
.subckt and_gate _a=h_u_cla12_and368_h_u_cla12_and367_y0 _b=h_u_cla12_and368_h_u_cla12_and366_y0 _y0=h_u_cla12_and368_y0
.names h_u_cla12_pg_logic6_y0 h_u_cla12_and369_h_u_cla12_pg_logic6_y0
1 1
.names h_u_cla12_pg_logic5_y1 h_u_cla12_and369_h_u_cla12_pg_logic5_y1
1 1
.subckt and_gate _a=h_u_cla12_and369_h_u_cla12_pg_logic6_y0 _b=h_u_cla12_and369_h_u_cla12_pg_logic5_y1 _y0=h_u_cla12_and369_y0
.names h_u_cla12_pg_logic7_y0 h_u_cla12_and370_h_u_cla12_pg_logic7_y0
1 1
.names h_u_cla12_pg_logic5_y1 h_u_cla12_and370_h_u_cla12_pg_logic5_y1
1 1
.subckt and_gate _a=h_u_cla12_and370_h_u_cla12_pg_logic7_y0 _b=h_u_cla12_and370_h_u_cla12_pg_logic5_y1 _y0=h_u_cla12_and370_y0
.names h_u_cla12_and370_y0 h_u_cla12_and371_h_u_cla12_and370_y0
1 1
.names h_u_cla12_and369_y0 h_u_cla12_and371_h_u_cla12_and369_y0
1 1
.subckt and_gate _a=h_u_cla12_and371_h_u_cla12_and370_y0 _b=h_u_cla12_and371_h_u_cla12_and369_y0 _y0=h_u_cla12_and371_y0
.names h_u_cla12_pg_logic8_y0 h_u_cla12_and372_h_u_cla12_pg_logic8_y0
1 1
.names h_u_cla12_pg_logic5_y1 h_u_cla12_and372_h_u_cla12_pg_logic5_y1
1 1
.subckt and_gate _a=h_u_cla12_and372_h_u_cla12_pg_logic8_y0 _b=h_u_cla12_and372_h_u_cla12_pg_logic5_y1 _y0=h_u_cla12_and372_y0
.names h_u_cla12_and372_y0 h_u_cla12_and373_h_u_cla12_and372_y0
1 1
.names h_u_cla12_and371_y0 h_u_cla12_and373_h_u_cla12_and371_y0
1 1
.subckt and_gate _a=h_u_cla12_and373_h_u_cla12_and372_y0 _b=h_u_cla12_and373_h_u_cla12_and371_y0 _y0=h_u_cla12_and373_y0
.names h_u_cla12_pg_logic9_y0 h_u_cla12_and374_h_u_cla12_pg_logic9_y0
1 1
.names h_u_cla12_pg_logic5_y1 h_u_cla12_and374_h_u_cla12_pg_logic5_y1
1 1
.subckt and_gate _a=h_u_cla12_and374_h_u_cla12_pg_logic9_y0 _b=h_u_cla12_and374_h_u_cla12_pg_logic5_y1 _y0=h_u_cla12_and374_y0
.names h_u_cla12_and374_y0 h_u_cla12_and375_h_u_cla12_and374_y0
1 1
.names h_u_cla12_and373_y0 h_u_cla12_and375_h_u_cla12_and373_y0
1 1
.subckt and_gate _a=h_u_cla12_and375_h_u_cla12_and374_y0 _b=h_u_cla12_and375_h_u_cla12_and373_y0 _y0=h_u_cla12_and375_y0
.names h_u_cla12_pg_logic7_y0 h_u_cla12_and376_h_u_cla12_pg_logic7_y0
1 1
.names h_u_cla12_pg_logic6_y1 h_u_cla12_and376_h_u_cla12_pg_logic6_y1
1 1
.subckt and_gate _a=h_u_cla12_and376_h_u_cla12_pg_logic7_y0 _b=h_u_cla12_and376_h_u_cla12_pg_logic6_y1 _y0=h_u_cla12_and376_y0
.names h_u_cla12_pg_logic8_y0 h_u_cla12_and377_h_u_cla12_pg_logic8_y0
1 1
.names h_u_cla12_pg_logic6_y1 h_u_cla12_and377_h_u_cla12_pg_logic6_y1
1 1
.subckt and_gate _a=h_u_cla12_and377_h_u_cla12_pg_logic8_y0 _b=h_u_cla12_and377_h_u_cla12_pg_logic6_y1 _y0=h_u_cla12_and377_y0
.names h_u_cla12_and377_y0 h_u_cla12_and378_h_u_cla12_and377_y0
1 1
.names h_u_cla12_and376_y0 h_u_cla12_and378_h_u_cla12_and376_y0
1 1
.subckt and_gate _a=h_u_cla12_and378_h_u_cla12_and377_y0 _b=h_u_cla12_and378_h_u_cla12_and376_y0 _y0=h_u_cla12_and378_y0
.names h_u_cla12_pg_logic9_y0 h_u_cla12_and379_h_u_cla12_pg_logic9_y0
1 1
.names h_u_cla12_pg_logic6_y1 h_u_cla12_and379_h_u_cla12_pg_logic6_y1
1 1
.subckt and_gate _a=h_u_cla12_and379_h_u_cla12_pg_logic9_y0 _b=h_u_cla12_and379_h_u_cla12_pg_logic6_y1 _y0=h_u_cla12_and379_y0
.names h_u_cla12_and379_y0 h_u_cla12_and380_h_u_cla12_and379_y0
1 1
.names h_u_cla12_and378_y0 h_u_cla12_and380_h_u_cla12_and378_y0
1 1
.subckt and_gate _a=h_u_cla12_and380_h_u_cla12_and379_y0 _b=h_u_cla12_and380_h_u_cla12_and378_y0 _y0=h_u_cla12_and380_y0
.names h_u_cla12_pg_logic8_y0 h_u_cla12_and381_h_u_cla12_pg_logic8_y0
1 1
.names h_u_cla12_pg_logic7_y1 h_u_cla12_and381_h_u_cla12_pg_logic7_y1
1 1
.subckt and_gate _a=h_u_cla12_and381_h_u_cla12_pg_logic8_y0 _b=h_u_cla12_and381_h_u_cla12_pg_logic7_y1 _y0=h_u_cla12_and381_y0
.names h_u_cla12_pg_logic9_y0 h_u_cla12_and382_h_u_cla12_pg_logic9_y0
1 1
.names h_u_cla12_pg_logic7_y1 h_u_cla12_and382_h_u_cla12_pg_logic7_y1
1 1
.subckt and_gate _a=h_u_cla12_and382_h_u_cla12_pg_logic9_y0 _b=h_u_cla12_and382_h_u_cla12_pg_logic7_y1 _y0=h_u_cla12_and382_y0
.names h_u_cla12_and382_y0 h_u_cla12_and383_h_u_cla12_and382_y0
1 1
.names h_u_cla12_and381_y0 h_u_cla12_and383_h_u_cla12_and381_y0
1 1
.subckt and_gate _a=h_u_cla12_and383_h_u_cla12_and382_y0 _b=h_u_cla12_and383_h_u_cla12_and381_y0 _y0=h_u_cla12_and383_y0
.names h_u_cla12_pg_logic9_y0 h_u_cla12_and384_h_u_cla12_pg_logic9_y0
1 1
.names h_u_cla12_pg_logic8_y1 h_u_cla12_and384_h_u_cla12_pg_logic8_y1
1 1
.subckt and_gate _a=h_u_cla12_and384_h_u_cla12_pg_logic9_y0 _b=h_u_cla12_and384_h_u_cla12_pg_logic8_y1 _y0=h_u_cla12_and384_y0
.names h_u_cla12_and384_y0 h_u_cla12_or45_h_u_cla12_and384_y0
1 1
.names h_u_cla12_and303_y0 h_u_cla12_or45_h_u_cla12_and303_y0
1 1
.subckt or_gate _a=h_u_cla12_or45_h_u_cla12_and384_y0 _b=h_u_cla12_or45_h_u_cla12_and303_y0 _y0=h_u_cla12_or45_y0
.names h_u_cla12_or45_y0 h_u_cla12_or46_h_u_cla12_or45_y0
1 1
.names h_u_cla12_and320_y0 h_u_cla12_or46_h_u_cla12_and320_y0
1 1
.subckt or_gate _a=h_u_cla12_or46_h_u_cla12_or45_y0 _b=h_u_cla12_or46_h_u_cla12_and320_y0 _y0=h_u_cla12_or46_y0
.names h_u_cla12_or46_y0 h_u_cla12_or47_h_u_cla12_or46_y0
1 1
.names h_u_cla12_and335_y0 h_u_cla12_or47_h_u_cla12_and335_y0
1 1
.subckt or_gate _a=h_u_cla12_or47_h_u_cla12_or46_y0 _b=h_u_cla12_or47_h_u_cla12_and335_y0 _y0=h_u_cla12_or47_y0
.names h_u_cla12_or47_y0 h_u_cla12_or48_h_u_cla12_or47_y0
1 1
.names h_u_cla12_and348_y0 h_u_cla12_or48_h_u_cla12_and348_y0
1 1
.subckt or_gate _a=h_u_cla12_or48_h_u_cla12_or47_y0 _b=h_u_cla12_or48_h_u_cla12_and348_y0 _y0=h_u_cla12_or48_y0
.names h_u_cla12_or48_y0 h_u_cla12_or49_h_u_cla12_or48_y0
1 1
.names h_u_cla12_and359_y0 h_u_cla12_or49_h_u_cla12_and359_y0
1 1
.subckt or_gate _a=h_u_cla12_or49_h_u_cla12_or48_y0 _b=h_u_cla12_or49_h_u_cla12_and359_y0 _y0=h_u_cla12_or49_y0
.names h_u_cla12_or49_y0 h_u_cla12_or50_h_u_cla12_or49_y0
1 1
.names h_u_cla12_and368_y0 h_u_cla12_or50_h_u_cla12_and368_y0
1 1
.subckt or_gate _a=h_u_cla12_or50_h_u_cla12_or49_y0 _b=h_u_cla12_or50_h_u_cla12_and368_y0 _y0=h_u_cla12_or50_y0
.names h_u_cla12_or50_y0 h_u_cla12_or51_h_u_cla12_or50_y0
1 1
.names h_u_cla12_and375_y0 h_u_cla12_or51_h_u_cla12_and375_y0
1 1
.subckt or_gate _a=h_u_cla12_or51_h_u_cla12_or50_y0 _b=h_u_cla12_or51_h_u_cla12_and375_y0 _y0=h_u_cla12_or51_y0
.names h_u_cla12_or51_y0 h_u_cla12_or52_h_u_cla12_or51_y0
1 1
.names h_u_cla12_and380_y0 h_u_cla12_or52_h_u_cla12_and380_y0
1 1
.subckt or_gate _a=h_u_cla12_or52_h_u_cla12_or51_y0 _b=h_u_cla12_or52_h_u_cla12_and380_y0 _y0=h_u_cla12_or52_y0
.names h_u_cla12_or52_y0 h_u_cla12_or53_h_u_cla12_or52_y0
1 1
.names h_u_cla12_and383_y0 h_u_cla12_or53_h_u_cla12_and383_y0
1 1
.subckt or_gate _a=h_u_cla12_or53_h_u_cla12_or52_y0 _b=h_u_cla12_or53_h_u_cla12_and383_y0 _y0=h_u_cla12_or53_y0
.names h_u_cla12_pg_logic9_y1 h_u_cla12_or54_h_u_cla12_pg_logic9_y1
1 1
.names h_u_cla12_or53_y0 h_u_cla12_or54_h_u_cla12_or53_y0
1 1
.subckt or_gate _a=h_u_cla12_or54_h_u_cla12_pg_logic9_y1 _b=h_u_cla12_or54_h_u_cla12_or53_y0 _y0=h_u_cla12_or54_y0
.names a_10 h_u_cla12_pg_logic10_a_10
1 1
.names b_10 h_u_cla12_pg_logic10_b_10
1 1
.subckt pg_logic a=h_u_cla12_pg_logic10_a_10 b=h_u_cla12_pg_logic10_b_10 pg_logic_y0=h_u_cla12_pg_logic10_y0 pg_logic_y1=h_u_cla12_pg_logic10_y1 pg_logic_y2=h_u_cla12_pg_logic10_y2
.names h_u_cla12_pg_logic10_y2 h_u_cla12_xor10_h_u_cla12_pg_logic10_y2
1 1
.names h_u_cla12_or54_y0 h_u_cla12_xor10_h_u_cla12_or54_y0
1 1
.subckt xor_gate _a=h_u_cla12_xor10_h_u_cla12_pg_logic10_y2 _b=h_u_cla12_xor10_h_u_cla12_or54_y0 _y0=h_u_cla12_xor10_y0
.names h_u_cla12_pg_logic0_y0 h_u_cla12_and385_h_u_cla12_pg_logic0_y0
1 1
.names constant_wire_0 h_u_cla12_and385_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and385_h_u_cla12_pg_logic0_y0 _b=h_u_cla12_and385_constant_wire_0 _y0=h_u_cla12_and385_y0
.names h_u_cla12_pg_logic1_y0 h_u_cla12_and386_h_u_cla12_pg_logic1_y0
1 1
.names constant_wire_0 h_u_cla12_and386_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and386_h_u_cla12_pg_logic1_y0 _b=h_u_cla12_and386_constant_wire_0 _y0=h_u_cla12_and386_y0
.names h_u_cla12_and386_y0 h_u_cla12_and387_h_u_cla12_and386_y0
1 1
.names h_u_cla12_and385_y0 h_u_cla12_and387_h_u_cla12_and385_y0
1 1
.subckt and_gate _a=h_u_cla12_and387_h_u_cla12_and386_y0 _b=h_u_cla12_and387_h_u_cla12_and385_y0 _y0=h_u_cla12_and387_y0
.names h_u_cla12_pg_logic2_y0 h_u_cla12_and388_h_u_cla12_pg_logic2_y0
1 1
.names constant_wire_0 h_u_cla12_and388_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and388_h_u_cla12_pg_logic2_y0 _b=h_u_cla12_and388_constant_wire_0 _y0=h_u_cla12_and388_y0
.names h_u_cla12_and388_y0 h_u_cla12_and389_h_u_cla12_and388_y0
1 1
.names h_u_cla12_and387_y0 h_u_cla12_and389_h_u_cla12_and387_y0
1 1
.subckt and_gate _a=h_u_cla12_and389_h_u_cla12_and388_y0 _b=h_u_cla12_and389_h_u_cla12_and387_y0 _y0=h_u_cla12_and389_y0
.names h_u_cla12_pg_logic3_y0 h_u_cla12_and390_h_u_cla12_pg_logic3_y0
1 1
.names constant_wire_0 h_u_cla12_and390_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and390_h_u_cla12_pg_logic3_y0 _b=h_u_cla12_and390_constant_wire_0 _y0=h_u_cla12_and390_y0
.names h_u_cla12_and390_y0 h_u_cla12_and391_h_u_cla12_and390_y0
1 1
.names h_u_cla12_and389_y0 h_u_cla12_and391_h_u_cla12_and389_y0
1 1
.subckt and_gate _a=h_u_cla12_and391_h_u_cla12_and390_y0 _b=h_u_cla12_and391_h_u_cla12_and389_y0 _y0=h_u_cla12_and391_y0
.names h_u_cla12_pg_logic4_y0 h_u_cla12_and392_h_u_cla12_pg_logic4_y0
1 1
.names constant_wire_0 h_u_cla12_and392_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and392_h_u_cla12_pg_logic4_y0 _b=h_u_cla12_and392_constant_wire_0 _y0=h_u_cla12_and392_y0
.names h_u_cla12_and392_y0 h_u_cla12_and393_h_u_cla12_and392_y0
1 1
.names h_u_cla12_and391_y0 h_u_cla12_and393_h_u_cla12_and391_y0
1 1
.subckt and_gate _a=h_u_cla12_and393_h_u_cla12_and392_y0 _b=h_u_cla12_and393_h_u_cla12_and391_y0 _y0=h_u_cla12_and393_y0
.names h_u_cla12_pg_logic5_y0 h_u_cla12_and394_h_u_cla12_pg_logic5_y0
1 1
.names constant_wire_0 h_u_cla12_and394_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and394_h_u_cla12_pg_logic5_y0 _b=h_u_cla12_and394_constant_wire_0 _y0=h_u_cla12_and394_y0
.names h_u_cla12_and394_y0 h_u_cla12_and395_h_u_cla12_and394_y0
1 1
.names h_u_cla12_and393_y0 h_u_cla12_and395_h_u_cla12_and393_y0
1 1
.subckt and_gate _a=h_u_cla12_and395_h_u_cla12_and394_y0 _b=h_u_cla12_and395_h_u_cla12_and393_y0 _y0=h_u_cla12_and395_y0
.names h_u_cla12_pg_logic6_y0 h_u_cla12_and396_h_u_cla12_pg_logic6_y0
1 1
.names constant_wire_0 h_u_cla12_and396_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and396_h_u_cla12_pg_logic6_y0 _b=h_u_cla12_and396_constant_wire_0 _y0=h_u_cla12_and396_y0
.names h_u_cla12_and396_y0 h_u_cla12_and397_h_u_cla12_and396_y0
1 1
.names h_u_cla12_and395_y0 h_u_cla12_and397_h_u_cla12_and395_y0
1 1
.subckt and_gate _a=h_u_cla12_and397_h_u_cla12_and396_y0 _b=h_u_cla12_and397_h_u_cla12_and395_y0 _y0=h_u_cla12_and397_y0
.names h_u_cla12_pg_logic7_y0 h_u_cla12_and398_h_u_cla12_pg_logic7_y0
1 1
.names constant_wire_0 h_u_cla12_and398_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and398_h_u_cla12_pg_logic7_y0 _b=h_u_cla12_and398_constant_wire_0 _y0=h_u_cla12_and398_y0
.names h_u_cla12_and398_y0 h_u_cla12_and399_h_u_cla12_and398_y0
1 1
.names h_u_cla12_and397_y0 h_u_cla12_and399_h_u_cla12_and397_y0
1 1
.subckt and_gate _a=h_u_cla12_and399_h_u_cla12_and398_y0 _b=h_u_cla12_and399_h_u_cla12_and397_y0 _y0=h_u_cla12_and399_y0
.names h_u_cla12_pg_logic8_y0 h_u_cla12_and400_h_u_cla12_pg_logic8_y0
1 1
.names constant_wire_0 h_u_cla12_and400_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and400_h_u_cla12_pg_logic8_y0 _b=h_u_cla12_and400_constant_wire_0 _y0=h_u_cla12_and400_y0
.names h_u_cla12_and400_y0 h_u_cla12_and401_h_u_cla12_and400_y0
1 1
.names h_u_cla12_and399_y0 h_u_cla12_and401_h_u_cla12_and399_y0
1 1
.subckt and_gate _a=h_u_cla12_and401_h_u_cla12_and400_y0 _b=h_u_cla12_and401_h_u_cla12_and399_y0 _y0=h_u_cla12_and401_y0
.names h_u_cla12_pg_logic9_y0 h_u_cla12_and402_h_u_cla12_pg_logic9_y0
1 1
.names constant_wire_0 h_u_cla12_and402_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and402_h_u_cla12_pg_logic9_y0 _b=h_u_cla12_and402_constant_wire_0 _y0=h_u_cla12_and402_y0
.names h_u_cla12_and402_y0 h_u_cla12_and403_h_u_cla12_and402_y0
1 1
.names h_u_cla12_and401_y0 h_u_cla12_and403_h_u_cla12_and401_y0
1 1
.subckt and_gate _a=h_u_cla12_and403_h_u_cla12_and402_y0 _b=h_u_cla12_and403_h_u_cla12_and401_y0 _y0=h_u_cla12_and403_y0
.names h_u_cla12_pg_logic10_y0 h_u_cla12_and404_h_u_cla12_pg_logic10_y0
1 1
.names constant_wire_0 h_u_cla12_and404_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and404_h_u_cla12_pg_logic10_y0 _b=h_u_cla12_and404_constant_wire_0 _y0=h_u_cla12_and404_y0
.names h_u_cla12_and404_y0 h_u_cla12_and405_h_u_cla12_and404_y0
1 1
.names h_u_cla12_and403_y0 h_u_cla12_and405_h_u_cla12_and403_y0
1 1
.subckt and_gate _a=h_u_cla12_and405_h_u_cla12_and404_y0 _b=h_u_cla12_and405_h_u_cla12_and403_y0 _y0=h_u_cla12_and405_y0
.names h_u_cla12_pg_logic1_y0 h_u_cla12_and406_h_u_cla12_pg_logic1_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and406_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and406_h_u_cla12_pg_logic1_y0 _b=h_u_cla12_and406_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and406_y0
.names h_u_cla12_pg_logic2_y0 h_u_cla12_and407_h_u_cla12_pg_logic2_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and407_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and407_h_u_cla12_pg_logic2_y0 _b=h_u_cla12_and407_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and407_y0
.names h_u_cla12_and407_y0 h_u_cla12_and408_h_u_cla12_and407_y0
1 1
.names h_u_cla12_and406_y0 h_u_cla12_and408_h_u_cla12_and406_y0
1 1
.subckt and_gate _a=h_u_cla12_and408_h_u_cla12_and407_y0 _b=h_u_cla12_and408_h_u_cla12_and406_y0 _y0=h_u_cla12_and408_y0
.names h_u_cla12_pg_logic3_y0 h_u_cla12_and409_h_u_cla12_pg_logic3_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and409_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and409_h_u_cla12_pg_logic3_y0 _b=h_u_cla12_and409_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and409_y0
.names h_u_cla12_and409_y0 h_u_cla12_and410_h_u_cla12_and409_y0
1 1
.names h_u_cla12_and408_y0 h_u_cla12_and410_h_u_cla12_and408_y0
1 1
.subckt and_gate _a=h_u_cla12_and410_h_u_cla12_and409_y0 _b=h_u_cla12_and410_h_u_cla12_and408_y0 _y0=h_u_cla12_and410_y0
.names h_u_cla12_pg_logic4_y0 h_u_cla12_and411_h_u_cla12_pg_logic4_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and411_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and411_h_u_cla12_pg_logic4_y0 _b=h_u_cla12_and411_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and411_y0
.names h_u_cla12_and411_y0 h_u_cla12_and412_h_u_cla12_and411_y0
1 1
.names h_u_cla12_and410_y0 h_u_cla12_and412_h_u_cla12_and410_y0
1 1
.subckt and_gate _a=h_u_cla12_and412_h_u_cla12_and411_y0 _b=h_u_cla12_and412_h_u_cla12_and410_y0 _y0=h_u_cla12_and412_y0
.names h_u_cla12_pg_logic5_y0 h_u_cla12_and413_h_u_cla12_pg_logic5_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and413_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and413_h_u_cla12_pg_logic5_y0 _b=h_u_cla12_and413_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and413_y0
.names h_u_cla12_and413_y0 h_u_cla12_and414_h_u_cla12_and413_y0
1 1
.names h_u_cla12_and412_y0 h_u_cla12_and414_h_u_cla12_and412_y0
1 1
.subckt and_gate _a=h_u_cla12_and414_h_u_cla12_and413_y0 _b=h_u_cla12_and414_h_u_cla12_and412_y0 _y0=h_u_cla12_and414_y0
.names h_u_cla12_pg_logic6_y0 h_u_cla12_and415_h_u_cla12_pg_logic6_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and415_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and415_h_u_cla12_pg_logic6_y0 _b=h_u_cla12_and415_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and415_y0
.names h_u_cla12_and415_y0 h_u_cla12_and416_h_u_cla12_and415_y0
1 1
.names h_u_cla12_and414_y0 h_u_cla12_and416_h_u_cla12_and414_y0
1 1
.subckt and_gate _a=h_u_cla12_and416_h_u_cla12_and415_y0 _b=h_u_cla12_and416_h_u_cla12_and414_y0 _y0=h_u_cla12_and416_y0
.names h_u_cla12_pg_logic7_y0 h_u_cla12_and417_h_u_cla12_pg_logic7_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and417_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and417_h_u_cla12_pg_logic7_y0 _b=h_u_cla12_and417_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and417_y0
.names h_u_cla12_and417_y0 h_u_cla12_and418_h_u_cla12_and417_y0
1 1
.names h_u_cla12_and416_y0 h_u_cla12_and418_h_u_cla12_and416_y0
1 1
.subckt and_gate _a=h_u_cla12_and418_h_u_cla12_and417_y0 _b=h_u_cla12_and418_h_u_cla12_and416_y0 _y0=h_u_cla12_and418_y0
.names h_u_cla12_pg_logic8_y0 h_u_cla12_and419_h_u_cla12_pg_logic8_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and419_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and419_h_u_cla12_pg_logic8_y0 _b=h_u_cla12_and419_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and419_y0
.names h_u_cla12_and419_y0 h_u_cla12_and420_h_u_cla12_and419_y0
1 1
.names h_u_cla12_and418_y0 h_u_cla12_and420_h_u_cla12_and418_y0
1 1
.subckt and_gate _a=h_u_cla12_and420_h_u_cla12_and419_y0 _b=h_u_cla12_and420_h_u_cla12_and418_y0 _y0=h_u_cla12_and420_y0
.names h_u_cla12_pg_logic9_y0 h_u_cla12_and421_h_u_cla12_pg_logic9_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and421_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and421_h_u_cla12_pg_logic9_y0 _b=h_u_cla12_and421_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and421_y0
.names h_u_cla12_and421_y0 h_u_cla12_and422_h_u_cla12_and421_y0
1 1
.names h_u_cla12_and420_y0 h_u_cla12_and422_h_u_cla12_and420_y0
1 1
.subckt and_gate _a=h_u_cla12_and422_h_u_cla12_and421_y0 _b=h_u_cla12_and422_h_u_cla12_and420_y0 _y0=h_u_cla12_and422_y0
.names h_u_cla12_pg_logic10_y0 h_u_cla12_and423_h_u_cla12_pg_logic10_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and423_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and423_h_u_cla12_pg_logic10_y0 _b=h_u_cla12_and423_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and423_y0
.names h_u_cla12_and423_y0 h_u_cla12_and424_h_u_cla12_and423_y0
1 1
.names h_u_cla12_and422_y0 h_u_cla12_and424_h_u_cla12_and422_y0
1 1
.subckt and_gate _a=h_u_cla12_and424_h_u_cla12_and423_y0 _b=h_u_cla12_and424_h_u_cla12_and422_y0 _y0=h_u_cla12_and424_y0
.names h_u_cla12_pg_logic2_y0 h_u_cla12_and425_h_u_cla12_pg_logic2_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and425_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and425_h_u_cla12_pg_logic2_y0 _b=h_u_cla12_and425_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and425_y0
.names h_u_cla12_pg_logic3_y0 h_u_cla12_and426_h_u_cla12_pg_logic3_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and426_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and426_h_u_cla12_pg_logic3_y0 _b=h_u_cla12_and426_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and426_y0
.names h_u_cla12_and426_y0 h_u_cla12_and427_h_u_cla12_and426_y0
1 1
.names h_u_cla12_and425_y0 h_u_cla12_and427_h_u_cla12_and425_y0
1 1
.subckt and_gate _a=h_u_cla12_and427_h_u_cla12_and426_y0 _b=h_u_cla12_and427_h_u_cla12_and425_y0 _y0=h_u_cla12_and427_y0
.names h_u_cla12_pg_logic4_y0 h_u_cla12_and428_h_u_cla12_pg_logic4_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and428_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and428_h_u_cla12_pg_logic4_y0 _b=h_u_cla12_and428_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and428_y0
.names h_u_cla12_and428_y0 h_u_cla12_and429_h_u_cla12_and428_y0
1 1
.names h_u_cla12_and427_y0 h_u_cla12_and429_h_u_cla12_and427_y0
1 1
.subckt and_gate _a=h_u_cla12_and429_h_u_cla12_and428_y0 _b=h_u_cla12_and429_h_u_cla12_and427_y0 _y0=h_u_cla12_and429_y0
.names h_u_cla12_pg_logic5_y0 h_u_cla12_and430_h_u_cla12_pg_logic5_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and430_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and430_h_u_cla12_pg_logic5_y0 _b=h_u_cla12_and430_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and430_y0
.names h_u_cla12_and430_y0 h_u_cla12_and431_h_u_cla12_and430_y0
1 1
.names h_u_cla12_and429_y0 h_u_cla12_and431_h_u_cla12_and429_y0
1 1
.subckt and_gate _a=h_u_cla12_and431_h_u_cla12_and430_y0 _b=h_u_cla12_and431_h_u_cla12_and429_y0 _y0=h_u_cla12_and431_y0
.names h_u_cla12_pg_logic6_y0 h_u_cla12_and432_h_u_cla12_pg_logic6_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and432_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and432_h_u_cla12_pg_logic6_y0 _b=h_u_cla12_and432_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and432_y0
.names h_u_cla12_and432_y0 h_u_cla12_and433_h_u_cla12_and432_y0
1 1
.names h_u_cla12_and431_y0 h_u_cla12_and433_h_u_cla12_and431_y0
1 1
.subckt and_gate _a=h_u_cla12_and433_h_u_cla12_and432_y0 _b=h_u_cla12_and433_h_u_cla12_and431_y0 _y0=h_u_cla12_and433_y0
.names h_u_cla12_pg_logic7_y0 h_u_cla12_and434_h_u_cla12_pg_logic7_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and434_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and434_h_u_cla12_pg_logic7_y0 _b=h_u_cla12_and434_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and434_y0
.names h_u_cla12_and434_y0 h_u_cla12_and435_h_u_cla12_and434_y0
1 1
.names h_u_cla12_and433_y0 h_u_cla12_and435_h_u_cla12_and433_y0
1 1
.subckt and_gate _a=h_u_cla12_and435_h_u_cla12_and434_y0 _b=h_u_cla12_and435_h_u_cla12_and433_y0 _y0=h_u_cla12_and435_y0
.names h_u_cla12_pg_logic8_y0 h_u_cla12_and436_h_u_cla12_pg_logic8_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and436_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and436_h_u_cla12_pg_logic8_y0 _b=h_u_cla12_and436_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and436_y0
.names h_u_cla12_and436_y0 h_u_cla12_and437_h_u_cla12_and436_y0
1 1
.names h_u_cla12_and435_y0 h_u_cla12_and437_h_u_cla12_and435_y0
1 1
.subckt and_gate _a=h_u_cla12_and437_h_u_cla12_and436_y0 _b=h_u_cla12_and437_h_u_cla12_and435_y0 _y0=h_u_cla12_and437_y0
.names h_u_cla12_pg_logic9_y0 h_u_cla12_and438_h_u_cla12_pg_logic9_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and438_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and438_h_u_cla12_pg_logic9_y0 _b=h_u_cla12_and438_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and438_y0
.names h_u_cla12_and438_y0 h_u_cla12_and439_h_u_cla12_and438_y0
1 1
.names h_u_cla12_and437_y0 h_u_cla12_and439_h_u_cla12_and437_y0
1 1
.subckt and_gate _a=h_u_cla12_and439_h_u_cla12_and438_y0 _b=h_u_cla12_and439_h_u_cla12_and437_y0 _y0=h_u_cla12_and439_y0
.names h_u_cla12_pg_logic10_y0 h_u_cla12_and440_h_u_cla12_pg_logic10_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and440_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and440_h_u_cla12_pg_logic10_y0 _b=h_u_cla12_and440_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and440_y0
.names h_u_cla12_and440_y0 h_u_cla12_and441_h_u_cla12_and440_y0
1 1
.names h_u_cla12_and439_y0 h_u_cla12_and441_h_u_cla12_and439_y0
1 1
.subckt and_gate _a=h_u_cla12_and441_h_u_cla12_and440_y0 _b=h_u_cla12_and441_h_u_cla12_and439_y0 _y0=h_u_cla12_and441_y0
.names h_u_cla12_pg_logic3_y0 h_u_cla12_and442_h_u_cla12_pg_logic3_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and442_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and442_h_u_cla12_pg_logic3_y0 _b=h_u_cla12_and442_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and442_y0
.names h_u_cla12_pg_logic4_y0 h_u_cla12_and443_h_u_cla12_pg_logic4_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and443_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and443_h_u_cla12_pg_logic4_y0 _b=h_u_cla12_and443_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and443_y0
.names h_u_cla12_and443_y0 h_u_cla12_and444_h_u_cla12_and443_y0
1 1
.names h_u_cla12_and442_y0 h_u_cla12_and444_h_u_cla12_and442_y0
1 1
.subckt and_gate _a=h_u_cla12_and444_h_u_cla12_and443_y0 _b=h_u_cla12_and444_h_u_cla12_and442_y0 _y0=h_u_cla12_and444_y0
.names h_u_cla12_pg_logic5_y0 h_u_cla12_and445_h_u_cla12_pg_logic5_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and445_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and445_h_u_cla12_pg_logic5_y0 _b=h_u_cla12_and445_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and445_y0
.names h_u_cla12_and445_y0 h_u_cla12_and446_h_u_cla12_and445_y0
1 1
.names h_u_cla12_and444_y0 h_u_cla12_and446_h_u_cla12_and444_y0
1 1
.subckt and_gate _a=h_u_cla12_and446_h_u_cla12_and445_y0 _b=h_u_cla12_and446_h_u_cla12_and444_y0 _y0=h_u_cla12_and446_y0
.names h_u_cla12_pg_logic6_y0 h_u_cla12_and447_h_u_cla12_pg_logic6_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and447_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and447_h_u_cla12_pg_logic6_y0 _b=h_u_cla12_and447_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and447_y0
.names h_u_cla12_and447_y0 h_u_cla12_and448_h_u_cla12_and447_y0
1 1
.names h_u_cla12_and446_y0 h_u_cla12_and448_h_u_cla12_and446_y0
1 1
.subckt and_gate _a=h_u_cla12_and448_h_u_cla12_and447_y0 _b=h_u_cla12_and448_h_u_cla12_and446_y0 _y0=h_u_cla12_and448_y0
.names h_u_cla12_pg_logic7_y0 h_u_cla12_and449_h_u_cla12_pg_logic7_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and449_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and449_h_u_cla12_pg_logic7_y0 _b=h_u_cla12_and449_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and449_y0
.names h_u_cla12_and449_y0 h_u_cla12_and450_h_u_cla12_and449_y0
1 1
.names h_u_cla12_and448_y0 h_u_cla12_and450_h_u_cla12_and448_y0
1 1
.subckt and_gate _a=h_u_cla12_and450_h_u_cla12_and449_y0 _b=h_u_cla12_and450_h_u_cla12_and448_y0 _y0=h_u_cla12_and450_y0
.names h_u_cla12_pg_logic8_y0 h_u_cla12_and451_h_u_cla12_pg_logic8_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and451_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and451_h_u_cla12_pg_logic8_y0 _b=h_u_cla12_and451_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and451_y0
.names h_u_cla12_and451_y0 h_u_cla12_and452_h_u_cla12_and451_y0
1 1
.names h_u_cla12_and450_y0 h_u_cla12_and452_h_u_cla12_and450_y0
1 1
.subckt and_gate _a=h_u_cla12_and452_h_u_cla12_and451_y0 _b=h_u_cla12_and452_h_u_cla12_and450_y0 _y0=h_u_cla12_and452_y0
.names h_u_cla12_pg_logic9_y0 h_u_cla12_and453_h_u_cla12_pg_logic9_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and453_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and453_h_u_cla12_pg_logic9_y0 _b=h_u_cla12_and453_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and453_y0
.names h_u_cla12_and453_y0 h_u_cla12_and454_h_u_cla12_and453_y0
1 1
.names h_u_cla12_and452_y0 h_u_cla12_and454_h_u_cla12_and452_y0
1 1
.subckt and_gate _a=h_u_cla12_and454_h_u_cla12_and453_y0 _b=h_u_cla12_and454_h_u_cla12_and452_y0 _y0=h_u_cla12_and454_y0
.names h_u_cla12_pg_logic10_y0 h_u_cla12_and455_h_u_cla12_pg_logic10_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and455_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and455_h_u_cla12_pg_logic10_y0 _b=h_u_cla12_and455_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and455_y0
.names h_u_cla12_and455_y0 h_u_cla12_and456_h_u_cla12_and455_y0
1 1
.names h_u_cla12_and454_y0 h_u_cla12_and456_h_u_cla12_and454_y0
1 1
.subckt and_gate _a=h_u_cla12_and456_h_u_cla12_and455_y0 _b=h_u_cla12_and456_h_u_cla12_and454_y0 _y0=h_u_cla12_and456_y0
.names h_u_cla12_pg_logic4_y0 h_u_cla12_and457_h_u_cla12_pg_logic4_y0
1 1
.names h_u_cla12_pg_logic3_y1 h_u_cla12_and457_h_u_cla12_pg_logic3_y1
1 1
.subckt and_gate _a=h_u_cla12_and457_h_u_cla12_pg_logic4_y0 _b=h_u_cla12_and457_h_u_cla12_pg_logic3_y1 _y0=h_u_cla12_and457_y0
.names h_u_cla12_pg_logic5_y0 h_u_cla12_and458_h_u_cla12_pg_logic5_y0
1 1
.names h_u_cla12_pg_logic3_y1 h_u_cla12_and458_h_u_cla12_pg_logic3_y1
1 1
.subckt and_gate _a=h_u_cla12_and458_h_u_cla12_pg_logic5_y0 _b=h_u_cla12_and458_h_u_cla12_pg_logic3_y1 _y0=h_u_cla12_and458_y0
.names h_u_cla12_and458_y0 h_u_cla12_and459_h_u_cla12_and458_y0
1 1
.names h_u_cla12_and457_y0 h_u_cla12_and459_h_u_cla12_and457_y0
1 1
.subckt and_gate _a=h_u_cla12_and459_h_u_cla12_and458_y0 _b=h_u_cla12_and459_h_u_cla12_and457_y0 _y0=h_u_cla12_and459_y0
.names h_u_cla12_pg_logic6_y0 h_u_cla12_and460_h_u_cla12_pg_logic6_y0
1 1
.names h_u_cla12_pg_logic3_y1 h_u_cla12_and460_h_u_cla12_pg_logic3_y1
1 1
.subckt and_gate _a=h_u_cla12_and460_h_u_cla12_pg_logic6_y0 _b=h_u_cla12_and460_h_u_cla12_pg_logic3_y1 _y0=h_u_cla12_and460_y0
.names h_u_cla12_and460_y0 h_u_cla12_and461_h_u_cla12_and460_y0
1 1
.names h_u_cla12_and459_y0 h_u_cla12_and461_h_u_cla12_and459_y0
1 1
.subckt and_gate _a=h_u_cla12_and461_h_u_cla12_and460_y0 _b=h_u_cla12_and461_h_u_cla12_and459_y0 _y0=h_u_cla12_and461_y0
.names h_u_cla12_pg_logic7_y0 h_u_cla12_and462_h_u_cla12_pg_logic7_y0
1 1
.names h_u_cla12_pg_logic3_y1 h_u_cla12_and462_h_u_cla12_pg_logic3_y1
1 1
.subckt and_gate _a=h_u_cla12_and462_h_u_cla12_pg_logic7_y0 _b=h_u_cla12_and462_h_u_cla12_pg_logic3_y1 _y0=h_u_cla12_and462_y0
.names h_u_cla12_and462_y0 h_u_cla12_and463_h_u_cla12_and462_y0
1 1
.names h_u_cla12_and461_y0 h_u_cla12_and463_h_u_cla12_and461_y0
1 1
.subckt and_gate _a=h_u_cla12_and463_h_u_cla12_and462_y0 _b=h_u_cla12_and463_h_u_cla12_and461_y0 _y0=h_u_cla12_and463_y0
.names h_u_cla12_pg_logic8_y0 h_u_cla12_and464_h_u_cla12_pg_logic8_y0
1 1
.names h_u_cla12_pg_logic3_y1 h_u_cla12_and464_h_u_cla12_pg_logic3_y1
1 1
.subckt and_gate _a=h_u_cla12_and464_h_u_cla12_pg_logic8_y0 _b=h_u_cla12_and464_h_u_cla12_pg_logic3_y1 _y0=h_u_cla12_and464_y0
.names h_u_cla12_and464_y0 h_u_cla12_and465_h_u_cla12_and464_y0
1 1
.names h_u_cla12_and463_y0 h_u_cla12_and465_h_u_cla12_and463_y0
1 1
.subckt and_gate _a=h_u_cla12_and465_h_u_cla12_and464_y0 _b=h_u_cla12_and465_h_u_cla12_and463_y0 _y0=h_u_cla12_and465_y0
.names h_u_cla12_pg_logic9_y0 h_u_cla12_and466_h_u_cla12_pg_logic9_y0
1 1
.names h_u_cla12_pg_logic3_y1 h_u_cla12_and466_h_u_cla12_pg_logic3_y1
1 1
.subckt and_gate _a=h_u_cla12_and466_h_u_cla12_pg_logic9_y0 _b=h_u_cla12_and466_h_u_cla12_pg_logic3_y1 _y0=h_u_cla12_and466_y0
.names h_u_cla12_and466_y0 h_u_cla12_and467_h_u_cla12_and466_y0
1 1
.names h_u_cla12_and465_y0 h_u_cla12_and467_h_u_cla12_and465_y0
1 1
.subckt and_gate _a=h_u_cla12_and467_h_u_cla12_and466_y0 _b=h_u_cla12_and467_h_u_cla12_and465_y0 _y0=h_u_cla12_and467_y0
.names h_u_cla12_pg_logic10_y0 h_u_cla12_and468_h_u_cla12_pg_logic10_y0
1 1
.names h_u_cla12_pg_logic3_y1 h_u_cla12_and468_h_u_cla12_pg_logic3_y1
1 1
.subckt and_gate _a=h_u_cla12_and468_h_u_cla12_pg_logic10_y0 _b=h_u_cla12_and468_h_u_cla12_pg_logic3_y1 _y0=h_u_cla12_and468_y0
.names h_u_cla12_and468_y0 h_u_cla12_and469_h_u_cla12_and468_y0
1 1
.names h_u_cla12_and467_y0 h_u_cla12_and469_h_u_cla12_and467_y0
1 1
.subckt and_gate _a=h_u_cla12_and469_h_u_cla12_and468_y0 _b=h_u_cla12_and469_h_u_cla12_and467_y0 _y0=h_u_cla12_and469_y0
.names h_u_cla12_pg_logic5_y0 h_u_cla12_and470_h_u_cla12_pg_logic5_y0
1 1
.names h_u_cla12_pg_logic4_y1 h_u_cla12_and470_h_u_cla12_pg_logic4_y1
1 1
.subckt and_gate _a=h_u_cla12_and470_h_u_cla12_pg_logic5_y0 _b=h_u_cla12_and470_h_u_cla12_pg_logic4_y1 _y0=h_u_cla12_and470_y0
.names h_u_cla12_pg_logic6_y0 h_u_cla12_and471_h_u_cla12_pg_logic6_y0
1 1
.names h_u_cla12_pg_logic4_y1 h_u_cla12_and471_h_u_cla12_pg_logic4_y1
1 1
.subckt and_gate _a=h_u_cla12_and471_h_u_cla12_pg_logic6_y0 _b=h_u_cla12_and471_h_u_cla12_pg_logic4_y1 _y0=h_u_cla12_and471_y0
.names h_u_cla12_and471_y0 h_u_cla12_and472_h_u_cla12_and471_y0
1 1
.names h_u_cla12_and470_y0 h_u_cla12_and472_h_u_cla12_and470_y0
1 1
.subckt and_gate _a=h_u_cla12_and472_h_u_cla12_and471_y0 _b=h_u_cla12_and472_h_u_cla12_and470_y0 _y0=h_u_cla12_and472_y0
.names h_u_cla12_pg_logic7_y0 h_u_cla12_and473_h_u_cla12_pg_logic7_y0
1 1
.names h_u_cla12_pg_logic4_y1 h_u_cla12_and473_h_u_cla12_pg_logic4_y1
1 1
.subckt and_gate _a=h_u_cla12_and473_h_u_cla12_pg_logic7_y0 _b=h_u_cla12_and473_h_u_cla12_pg_logic4_y1 _y0=h_u_cla12_and473_y0
.names h_u_cla12_and473_y0 h_u_cla12_and474_h_u_cla12_and473_y0
1 1
.names h_u_cla12_and472_y0 h_u_cla12_and474_h_u_cla12_and472_y0
1 1
.subckt and_gate _a=h_u_cla12_and474_h_u_cla12_and473_y0 _b=h_u_cla12_and474_h_u_cla12_and472_y0 _y0=h_u_cla12_and474_y0
.names h_u_cla12_pg_logic8_y0 h_u_cla12_and475_h_u_cla12_pg_logic8_y0
1 1
.names h_u_cla12_pg_logic4_y1 h_u_cla12_and475_h_u_cla12_pg_logic4_y1
1 1
.subckt and_gate _a=h_u_cla12_and475_h_u_cla12_pg_logic8_y0 _b=h_u_cla12_and475_h_u_cla12_pg_logic4_y1 _y0=h_u_cla12_and475_y0
.names h_u_cla12_and475_y0 h_u_cla12_and476_h_u_cla12_and475_y0
1 1
.names h_u_cla12_and474_y0 h_u_cla12_and476_h_u_cla12_and474_y0
1 1
.subckt and_gate _a=h_u_cla12_and476_h_u_cla12_and475_y0 _b=h_u_cla12_and476_h_u_cla12_and474_y0 _y0=h_u_cla12_and476_y0
.names h_u_cla12_pg_logic9_y0 h_u_cla12_and477_h_u_cla12_pg_logic9_y0
1 1
.names h_u_cla12_pg_logic4_y1 h_u_cla12_and477_h_u_cla12_pg_logic4_y1
1 1
.subckt and_gate _a=h_u_cla12_and477_h_u_cla12_pg_logic9_y0 _b=h_u_cla12_and477_h_u_cla12_pg_logic4_y1 _y0=h_u_cla12_and477_y0
.names h_u_cla12_and477_y0 h_u_cla12_and478_h_u_cla12_and477_y0
1 1
.names h_u_cla12_and476_y0 h_u_cla12_and478_h_u_cla12_and476_y0
1 1
.subckt and_gate _a=h_u_cla12_and478_h_u_cla12_and477_y0 _b=h_u_cla12_and478_h_u_cla12_and476_y0 _y0=h_u_cla12_and478_y0
.names h_u_cla12_pg_logic10_y0 h_u_cla12_and479_h_u_cla12_pg_logic10_y0
1 1
.names h_u_cla12_pg_logic4_y1 h_u_cla12_and479_h_u_cla12_pg_logic4_y1
1 1
.subckt and_gate _a=h_u_cla12_and479_h_u_cla12_pg_logic10_y0 _b=h_u_cla12_and479_h_u_cla12_pg_logic4_y1 _y0=h_u_cla12_and479_y0
.names h_u_cla12_and479_y0 h_u_cla12_and480_h_u_cla12_and479_y0
1 1
.names h_u_cla12_and478_y0 h_u_cla12_and480_h_u_cla12_and478_y0
1 1
.subckt and_gate _a=h_u_cla12_and480_h_u_cla12_and479_y0 _b=h_u_cla12_and480_h_u_cla12_and478_y0 _y0=h_u_cla12_and480_y0
.names h_u_cla12_pg_logic6_y0 h_u_cla12_and481_h_u_cla12_pg_logic6_y0
1 1
.names h_u_cla12_pg_logic5_y1 h_u_cla12_and481_h_u_cla12_pg_logic5_y1
1 1
.subckt and_gate _a=h_u_cla12_and481_h_u_cla12_pg_logic6_y0 _b=h_u_cla12_and481_h_u_cla12_pg_logic5_y1 _y0=h_u_cla12_and481_y0
.names h_u_cla12_pg_logic7_y0 h_u_cla12_and482_h_u_cla12_pg_logic7_y0
1 1
.names h_u_cla12_pg_logic5_y1 h_u_cla12_and482_h_u_cla12_pg_logic5_y1
1 1
.subckt and_gate _a=h_u_cla12_and482_h_u_cla12_pg_logic7_y0 _b=h_u_cla12_and482_h_u_cla12_pg_logic5_y1 _y0=h_u_cla12_and482_y0
.names h_u_cla12_and482_y0 h_u_cla12_and483_h_u_cla12_and482_y0
1 1
.names h_u_cla12_and481_y0 h_u_cla12_and483_h_u_cla12_and481_y0
1 1
.subckt and_gate _a=h_u_cla12_and483_h_u_cla12_and482_y0 _b=h_u_cla12_and483_h_u_cla12_and481_y0 _y0=h_u_cla12_and483_y0
.names h_u_cla12_pg_logic8_y0 h_u_cla12_and484_h_u_cla12_pg_logic8_y0
1 1
.names h_u_cla12_pg_logic5_y1 h_u_cla12_and484_h_u_cla12_pg_logic5_y1
1 1
.subckt and_gate _a=h_u_cla12_and484_h_u_cla12_pg_logic8_y0 _b=h_u_cla12_and484_h_u_cla12_pg_logic5_y1 _y0=h_u_cla12_and484_y0
.names h_u_cla12_and484_y0 h_u_cla12_and485_h_u_cla12_and484_y0
1 1
.names h_u_cla12_and483_y0 h_u_cla12_and485_h_u_cla12_and483_y0
1 1
.subckt and_gate _a=h_u_cla12_and485_h_u_cla12_and484_y0 _b=h_u_cla12_and485_h_u_cla12_and483_y0 _y0=h_u_cla12_and485_y0
.names h_u_cla12_pg_logic9_y0 h_u_cla12_and486_h_u_cla12_pg_logic9_y0
1 1
.names h_u_cla12_pg_logic5_y1 h_u_cla12_and486_h_u_cla12_pg_logic5_y1
1 1
.subckt and_gate _a=h_u_cla12_and486_h_u_cla12_pg_logic9_y0 _b=h_u_cla12_and486_h_u_cla12_pg_logic5_y1 _y0=h_u_cla12_and486_y0
.names h_u_cla12_and486_y0 h_u_cla12_and487_h_u_cla12_and486_y0
1 1
.names h_u_cla12_and485_y0 h_u_cla12_and487_h_u_cla12_and485_y0
1 1
.subckt and_gate _a=h_u_cla12_and487_h_u_cla12_and486_y0 _b=h_u_cla12_and487_h_u_cla12_and485_y0 _y0=h_u_cla12_and487_y0
.names h_u_cla12_pg_logic10_y0 h_u_cla12_and488_h_u_cla12_pg_logic10_y0
1 1
.names h_u_cla12_pg_logic5_y1 h_u_cla12_and488_h_u_cla12_pg_logic5_y1
1 1
.subckt and_gate _a=h_u_cla12_and488_h_u_cla12_pg_logic10_y0 _b=h_u_cla12_and488_h_u_cla12_pg_logic5_y1 _y0=h_u_cla12_and488_y0
.names h_u_cla12_and488_y0 h_u_cla12_and489_h_u_cla12_and488_y0
1 1
.names h_u_cla12_and487_y0 h_u_cla12_and489_h_u_cla12_and487_y0
1 1
.subckt and_gate _a=h_u_cla12_and489_h_u_cla12_and488_y0 _b=h_u_cla12_and489_h_u_cla12_and487_y0 _y0=h_u_cla12_and489_y0
.names h_u_cla12_pg_logic7_y0 h_u_cla12_and490_h_u_cla12_pg_logic7_y0
1 1
.names h_u_cla12_pg_logic6_y1 h_u_cla12_and490_h_u_cla12_pg_logic6_y1
1 1
.subckt and_gate _a=h_u_cla12_and490_h_u_cla12_pg_logic7_y0 _b=h_u_cla12_and490_h_u_cla12_pg_logic6_y1 _y0=h_u_cla12_and490_y0
.names h_u_cla12_pg_logic8_y0 h_u_cla12_and491_h_u_cla12_pg_logic8_y0
1 1
.names h_u_cla12_pg_logic6_y1 h_u_cla12_and491_h_u_cla12_pg_logic6_y1
1 1
.subckt and_gate _a=h_u_cla12_and491_h_u_cla12_pg_logic8_y0 _b=h_u_cla12_and491_h_u_cla12_pg_logic6_y1 _y0=h_u_cla12_and491_y0
.names h_u_cla12_and491_y0 h_u_cla12_and492_h_u_cla12_and491_y0
1 1
.names h_u_cla12_and490_y0 h_u_cla12_and492_h_u_cla12_and490_y0
1 1
.subckt and_gate _a=h_u_cla12_and492_h_u_cla12_and491_y0 _b=h_u_cla12_and492_h_u_cla12_and490_y0 _y0=h_u_cla12_and492_y0
.names h_u_cla12_pg_logic9_y0 h_u_cla12_and493_h_u_cla12_pg_logic9_y0
1 1
.names h_u_cla12_pg_logic6_y1 h_u_cla12_and493_h_u_cla12_pg_logic6_y1
1 1
.subckt and_gate _a=h_u_cla12_and493_h_u_cla12_pg_logic9_y0 _b=h_u_cla12_and493_h_u_cla12_pg_logic6_y1 _y0=h_u_cla12_and493_y0
.names h_u_cla12_and493_y0 h_u_cla12_and494_h_u_cla12_and493_y0
1 1
.names h_u_cla12_and492_y0 h_u_cla12_and494_h_u_cla12_and492_y0
1 1
.subckt and_gate _a=h_u_cla12_and494_h_u_cla12_and493_y0 _b=h_u_cla12_and494_h_u_cla12_and492_y0 _y0=h_u_cla12_and494_y0
.names h_u_cla12_pg_logic10_y0 h_u_cla12_and495_h_u_cla12_pg_logic10_y0
1 1
.names h_u_cla12_pg_logic6_y1 h_u_cla12_and495_h_u_cla12_pg_logic6_y1
1 1
.subckt and_gate _a=h_u_cla12_and495_h_u_cla12_pg_logic10_y0 _b=h_u_cla12_and495_h_u_cla12_pg_logic6_y1 _y0=h_u_cla12_and495_y0
.names h_u_cla12_and495_y0 h_u_cla12_and496_h_u_cla12_and495_y0
1 1
.names h_u_cla12_and494_y0 h_u_cla12_and496_h_u_cla12_and494_y0
1 1
.subckt and_gate _a=h_u_cla12_and496_h_u_cla12_and495_y0 _b=h_u_cla12_and496_h_u_cla12_and494_y0 _y0=h_u_cla12_and496_y0
.names h_u_cla12_pg_logic8_y0 h_u_cla12_and497_h_u_cla12_pg_logic8_y0
1 1
.names h_u_cla12_pg_logic7_y1 h_u_cla12_and497_h_u_cla12_pg_logic7_y1
1 1
.subckt and_gate _a=h_u_cla12_and497_h_u_cla12_pg_logic8_y0 _b=h_u_cla12_and497_h_u_cla12_pg_logic7_y1 _y0=h_u_cla12_and497_y0
.names h_u_cla12_pg_logic9_y0 h_u_cla12_and498_h_u_cla12_pg_logic9_y0
1 1
.names h_u_cla12_pg_logic7_y1 h_u_cla12_and498_h_u_cla12_pg_logic7_y1
1 1
.subckt and_gate _a=h_u_cla12_and498_h_u_cla12_pg_logic9_y0 _b=h_u_cla12_and498_h_u_cla12_pg_logic7_y1 _y0=h_u_cla12_and498_y0
.names h_u_cla12_and498_y0 h_u_cla12_and499_h_u_cla12_and498_y0
1 1
.names h_u_cla12_and497_y0 h_u_cla12_and499_h_u_cla12_and497_y0
1 1
.subckt and_gate _a=h_u_cla12_and499_h_u_cla12_and498_y0 _b=h_u_cla12_and499_h_u_cla12_and497_y0 _y0=h_u_cla12_and499_y0
.names h_u_cla12_pg_logic10_y0 h_u_cla12_and500_h_u_cla12_pg_logic10_y0
1 1
.names h_u_cla12_pg_logic7_y1 h_u_cla12_and500_h_u_cla12_pg_logic7_y1
1 1
.subckt and_gate _a=h_u_cla12_and500_h_u_cla12_pg_logic10_y0 _b=h_u_cla12_and500_h_u_cla12_pg_logic7_y1 _y0=h_u_cla12_and500_y0
.names h_u_cla12_and500_y0 h_u_cla12_and501_h_u_cla12_and500_y0
1 1
.names h_u_cla12_and499_y0 h_u_cla12_and501_h_u_cla12_and499_y0
1 1
.subckt and_gate _a=h_u_cla12_and501_h_u_cla12_and500_y0 _b=h_u_cla12_and501_h_u_cla12_and499_y0 _y0=h_u_cla12_and501_y0
.names h_u_cla12_pg_logic9_y0 h_u_cla12_and502_h_u_cla12_pg_logic9_y0
1 1
.names h_u_cla12_pg_logic8_y1 h_u_cla12_and502_h_u_cla12_pg_logic8_y1
1 1
.subckt and_gate _a=h_u_cla12_and502_h_u_cla12_pg_logic9_y0 _b=h_u_cla12_and502_h_u_cla12_pg_logic8_y1 _y0=h_u_cla12_and502_y0
.names h_u_cla12_pg_logic10_y0 h_u_cla12_and503_h_u_cla12_pg_logic10_y0
1 1
.names h_u_cla12_pg_logic8_y1 h_u_cla12_and503_h_u_cla12_pg_logic8_y1
1 1
.subckt and_gate _a=h_u_cla12_and503_h_u_cla12_pg_logic10_y0 _b=h_u_cla12_and503_h_u_cla12_pg_logic8_y1 _y0=h_u_cla12_and503_y0
.names h_u_cla12_and503_y0 h_u_cla12_and504_h_u_cla12_and503_y0
1 1
.names h_u_cla12_and502_y0 h_u_cla12_and504_h_u_cla12_and502_y0
1 1
.subckt and_gate _a=h_u_cla12_and504_h_u_cla12_and503_y0 _b=h_u_cla12_and504_h_u_cla12_and502_y0 _y0=h_u_cla12_and504_y0
.names h_u_cla12_pg_logic10_y0 h_u_cla12_and505_h_u_cla12_pg_logic10_y0
1 1
.names h_u_cla12_pg_logic9_y1 h_u_cla12_and505_h_u_cla12_pg_logic9_y1
1 1
.subckt and_gate _a=h_u_cla12_and505_h_u_cla12_pg_logic10_y0 _b=h_u_cla12_and505_h_u_cla12_pg_logic9_y1 _y0=h_u_cla12_and505_y0
.names h_u_cla12_and505_y0 h_u_cla12_or55_h_u_cla12_and505_y0
1 1
.names h_u_cla12_and405_y0 h_u_cla12_or55_h_u_cla12_and405_y0
1 1
.subckt or_gate _a=h_u_cla12_or55_h_u_cla12_and505_y0 _b=h_u_cla12_or55_h_u_cla12_and405_y0 _y0=h_u_cla12_or55_y0
.names h_u_cla12_or55_y0 h_u_cla12_or56_h_u_cla12_or55_y0
1 1
.names h_u_cla12_and424_y0 h_u_cla12_or56_h_u_cla12_and424_y0
1 1
.subckt or_gate _a=h_u_cla12_or56_h_u_cla12_or55_y0 _b=h_u_cla12_or56_h_u_cla12_and424_y0 _y0=h_u_cla12_or56_y0
.names h_u_cla12_or56_y0 h_u_cla12_or57_h_u_cla12_or56_y0
1 1
.names h_u_cla12_and441_y0 h_u_cla12_or57_h_u_cla12_and441_y0
1 1
.subckt or_gate _a=h_u_cla12_or57_h_u_cla12_or56_y0 _b=h_u_cla12_or57_h_u_cla12_and441_y0 _y0=h_u_cla12_or57_y0
.names h_u_cla12_or57_y0 h_u_cla12_or58_h_u_cla12_or57_y0
1 1
.names h_u_cla12_and456_y0 h_u_cla12_or58_h_u_cla12_and456_y0
1 1
.subckt or_gate _a=h_u_cla12_or58_h_u_cla12_or57_y0 _b=h_u_cla12_or58_h_u_cla12_and456_y0 _y0=h_u_cla12_or58_y0
.names h_u_cla12_or58_y0 h_u_cla12_or59_h_u_cla12_or58_y0
1 1
.names h_u_cla12_and469_y0 h_u_cla12_or59_h_u_cla12_and469_y0
1 1
.subckt or_gate _a=h_u_cla12_or59_h_u_cla12_or58_y0 _b=h_u_cla12_or59_h_u_cla12_and469_y0 _y0=h_u_cla12_or59_y0
.names h_u_cla12_or59_y0 h_u_cla12_or60_h_u_cla12_or59_y0
1 1
.names h_u_cla12_and480_y0 h_u_cla12_or60_h_u_cla12_and480_y0
1 1
.subckt or_gate _a=h_u_cla12_or60_h_u_cla12_or59_y0 _b=h_u_cla12_or60_h_u_cla12_and480_y0 _y0=h_u_cla12_or60_y0
.names h_u_cla12_or60_y0 h_u_cla12_or61_h_u_cla12_or60_y0
1 1
.names h_u_cla12_and489_y0 h_u_cla12_or61_h_u_cla12_and489_y0
1 1
.subckt or_gate _a=h_u_cla12_or61_h_u_cla12_or60_y0 _b=h_u_cla12_or61_h_u_cla12_and489_y0 _y0=h_u_cla12_or61_y0
.names h_u_cla12_or61_y0 h_u_cla12_or62_h_u_cla12_or61_y0
1 1
.names h_u_cla12_and496_y0 h_u_cla12_or62_h_u_cla12_and496_y0
1 1
.subckt or_gate _a=h_u_cla12_or62_h_u_cla12_or61_y0 _b=h_u_cla12_or62_h_u_cla12_and496_y0 _y0=h_u_cla12_or62_y0
.names h_u_cla12_or62_y0 h_u_cla12_or63_h_u_cla12_or62_y0
1 1
.names h_u_cla12_and501_y0 h_u_cla12_or63_h_u_cla12_and501_y0
1 1
.subckt or_gate _a=h_u_cla12_or63_h_u_cla12_or62_y0 _b=h_u_cla12_or63_h_u_cla12_and501_y0 _y0=h_u_cla12_or63_y0
.names h_u_cla12_or63_y0 h_u_cla12_or64_h_u_cla12_or63_y0
1 1
.names h_u_cla12_and504_y0 h_u_cla12_or64_h_u_cla12_and504_y0
1 1
.subckt or_gate _a=h_u_cla12_or64_h_u_cla12_or63_y0 _b=h_u_cla12_or64_h_u_cla12_and504_y0 _y0=h_u_cla12_or64_y0
.names h_u_cla12_pg_logic10_y1 h_u_cla12_or65_h_u_cla12_pg_logic10_y1
1 1
.names h_u_cla12_or64_y0 h_u_cla12_or65_h_u_cla12_or64_y0
1 1
.subckt or_gate _a=h_u_cla12_or65_h_u_cla12_pg_logic10_y1 _b=h_u_cla12_or65_h_u_cla12_or64_y0 _y0=h_u_cla12_or65_y0
.names a_11 h_u_cla12_pg_logic11_a_11
1 1
.names b_11 h_u_cla12_pg_logic11_b_11
1 1
.subckt pg_logic a=h_u_cla12_pg_logic11_a_11 b=h_u_cla12_pg_logic11_b_11 pg_logic_y0=h_u_cla12_pg_logic11_y0 pg_logic_y1=h_u_cla12_pg_logic11_y1 pg_logic_y2=h_u_cla12_pg_logic11_y2
.names h_u_cla12_pg_logic11_y2 h_u_cla12_xor11_h_u_cla12_pg_logic11_y2
1 1
.names h_u_cla12_or65_y0 h_u_cla12_xor11_h_u_cla12_or65_y0
1 1
.subckt xor_gate _a=h_u_cla12_xor11_h_u_cla12_pg_logic11_y2 _b=h_u_cla12_xor11_h_u_cla12_or65_y0 _y0=h_u_cla12_xor11_y0
.names h_u_cla12_pg_logic0_y0 h_u_cla12_and506_h_u_cla12_pg_logic0_y0
1 1
.names constant_wire_0 h_u_cla12_and506_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and506_h_u_cla12_pg_logic0_y0 _b=h_u_cla12_and506_constant_wire_0 _y0=h_u_cla12_and506_y0
.names h_u_cla12_pg_logic1_y0 h_u_cla12_and507_h_u_cla12_pg_logic1_y0
1 1
.names constant_wire_0 h_u_cla12_and507_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and507_h_u_cla12_pg_logic1_y0 _b=h_u_cla12_and507_constant_wire_0 _y0=h_u_cla12_and507_y0
.names h_u_cla12_and507_y0 h_u_cla12_and508_h_u_cla12_and507_y0
1 1
.names h_u_cla12_and506_y0 h_u_cla12_and508_h_u_cla12_and506_y0
1 1
.subckt and_gate _a=h_u_cla12_and508_h_u_cla12_and507_y0 _b=h_u_cla12_and508_h_u_cla12_and506_y0 _y0=h_u_cla12_and508_y0
.names h_u_cla12_pg_logic2_y0 h_u_cla12_and509_h_u_cla12_pg_logic2_y0
1 1
.names constant_wire_0 h_u_cla12_and509_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and509_h_u_cla12_pg_logic2_y0 _b=h_u_cla12_and509_constant_wire_0 _y0=h_u_cla12_and509_y0
.names h_u_cla12_and509_y0 h_u_cla12_and510_h_u_cla12_and509_y0
1 1
.names h_u_cla12_and508_y0 h_u_cla12_and510_h_u_cla12_and508_y0
1 1
.subckt and_gate _a=h_u_cla12_and510_h_u_cla12_and509_y0 _b=h_u_cla12_and510_h_u_cla12_and508_y0 _y0=h_u_cla12_and510_y0
.names h_u_cla12_pg_logic3_y0 h_u_cla12_and511_h_u_cla12_pg_logic3_y0
1 1
.names constant_wire_0 h_u_cla12_and511_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and511_h_u_cla12_pg_logic3_y0 _b=h_u_cla12_and511_constant_wire_0 _y0=h_u_cla12_and511_y0
.names h_u_cla12_and511_y0 h_u_cla12_and512_h_u_cla12_and511_y0
1 1
.names h_u_cla12_and510_y0 h_u_cla12_and512_h_u_cla12_and510_y0
1 1
.subckt and_gate _a=h_u_cla12_and512_h_u_cla12_and511_y0 _b=h_u_cla12_and512_h_u_cla12_and510_y0 _y0=h_u_cla12_and512_y0
.names h_u_cla12_pg_logic4_y0 h_u_cla12_and513_h_u_cla12_pg_logic4_y0
1 1
.names constant_wire_0 h_u_cla12_and513_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and513_h_u_cla12_pg_logic4_y0 _b=h_u_cla12_and513_constant_wire_0 _y0=h_u_cla12_and513_y0
.names h_u_cla12_and513_y0 h_u_cla12_and514_h_u_cla12_and513_y0
1 1
.names h_u_cla12_and512_y0 h_u_cla12_and514_h_u_cla12_and512_y0
1 1
.subckt and_gate _a=h_u_cla12_and514_h_u_cla12_and513_y0 _b=h_u_cla12_and514_h_u_cla12_and512_y0 _y0=h_u_cla12_and514_y0
.names h_u_cla12_pg_logic5_y0 h_u_cla12_and515_h_u_cla12_pg_logic5_y0
1 1
.names constant_wire_0 h_u_cla12_and515_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and515_h_u_cla12_pg_logic5_y0 _b=h_u_cla12_and515_constant_wire_0 _y0=h_u_cla12_and515_y0
.names h_u_cla12_and515_y0 h_u_cla12_and516_h_u_cla12_and515_y0
1 1
.names h_u_cla12_and514_y0 h_u_cla12_and516_h_u_cla12_and514_y0
1 1
.subckt and_gate _a=h_u_cla12_and516_h_u_cla12_and515_y0 _b=h_u_cla12_and516_h_u_cla12_and514_y0 _y0=h_u_cla12_and516_y0
.names h_u_cla12_pg_logic6_y0 h_u_cla12_and517_h_u_cla12_pg_logic6_y0
1 1
.names constant_wire_0 h_u_cla12_and517_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and517_h_u_cla12_pg_logic6_y0 _b=h_u_cla12_and517_constant_wire_0 _y0=h_u_cla12_and517_y0
.names h_u_cla12_and517_y0 h_u_cla12_and518_h_u_cla12_and517_y0
1 1
.names h_u_cla12_and516_y0 h_u_cla12_and518_h_u_cla12_and516_y0
1 1
.subckt and_gate _a=h_u_cla12_and518_h_u_cla12_and517_y0 _b=h_u_cla12_and518_h_u_cla12_and516_y0 _y0=h_u_cla12_and518_y0
.names h_u_cla12_pg_logic7_y0 h_u_cla12_and519_h_u_cla12_pg_logic7_y0
1 1
.names constant_wire_0 h_u_cla12_and519_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and519_h_u_cla12_pg_logic7_y0 _b=h_u_cla12_and519_constant_wire_0 _y0=h_u_cla12_and519_y0
.names h_u_cla12_and519_y0 h_u_cla12_and520_h_u_cla12_and519_y0
1 1
.names h_u_cla12_and518_y0 h_u_cla12_and520_h_u_cla12_and518_y0
1 1
.subckt and_gate _a=h_u_cla12_and520_h_u_cla12_and519_y0 _b=h_u_cla12_and520_h_u_cla12_and518_y0 _y0=h_u_cla12_and520_y0
.names h_u_cla12_pg_logic8_y0 h_u_cla12_and521_h_u_cla12_pg_logic8_y0
1 1
.names constant_wire_0 h_u_cla12_and521_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and521_h_u_cla12_pg_logic8_y0 _b=h_u_cla12_and521_constant_wire_0 _y0=h_u_cla12_and521_y0
.names h_u_cla12_and521_y0 h_u_cla12_and522_h_u_cla12_and521_y0
1 1
.names h_u_cla12_and520_y0 h_u_cla12_and522_h_u_cla12_and520_y0
1 1
.subckt and_gate _a=h_u_cla12_and522_h_u_cla12_and521_y0 _b=h_u_cla12_and522_h_u_cla12_and520_y0 _y0=h_u_cla12_and522_y0
.names h_u_cla12_pg_logic9_y0 h_u_cla12_and523_h_u_cla12_pg_logic9_y0
1 1
.names constant_wire_0 h_u_cla12_and523_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and523_h_u_cla12_pg_logic9_y0 _b=h_u_cla12_and523_constant_wire_0 _y0=h_u_cla12_and523_y0
.names h_u_cla12_and523_y0 h_u_cla12_and524_h_u_cla12_and523_y0
1 1
.names h_u_cla12_and522_y0 h_u_cla12_and524_h_u_cla12_and522_y0
1 1
.subckt and_gate _a=h_u_cla12_and524_h_u_cla12_and523_y0 _b=h_u_cla12_and524_h_u_cla12_and522_y0 _y0=h_u_cla12_and524_y0
.names h_u_cla12_pg_logic10_y0 h_u_cla12_and525_h_u_cla12_pg_logic10_y0
1 1
.names constant_wire_0 h_u_cla12_and525_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and525_h_u_cla12_pg_logic10_y0 _b=h_u_cla12_and525_constant_wire_0 _y0=h_u_cla12_and525_y0
.names h_u_cla12_and525_y0 h_u_cla12_and526_h_u_cla12_and525_y0
1 1
.names h_u_cla12_and524_y0 h_u_cla12_and526_h_u_cla12_and524_y0
1 1
.subckt and_gate _a=h_u_cla12_and526_h_u_cla12_and525_y0 _b=h_u_cla12_and526_h_u_cla12_and524_y0 _y0=h_u_cla12_and526_y0
.names h_u_cla12_pg_logic11_y0 h_u_cla12_and527_h_u_cla12_pg_logic11_y0
1 1
.names constant_wire_0 h_u_cla12_and527_constant_wire_0
1 1
.subckt and_gate _a=h_u_cla12_and527_h_u_cla12_pg_logic11_y0 _b=h_u_cla12_and527_constant_wire_0 _y0=h_u_cla12_and527_y0
.names h_u_cla12_and527_y0 h_u_cla12_and528_h_u_cla12_and527_y0
1 1
.names h_u_cla12_and526_y0 h_u_cla12_and528_h_u_cla12_and526_y0
1 1
.subckt and_gate _a=h_u_cla12_and528_h_u_cla12_and527_y0 _b=h_u_cla12_and528_h_u_cla12_and526_y0 _y0=h_u_cla12_and528_y0
.names h_u_cla12_pg_logic1_y0 h_u_cla12_and529_h_u_cla12_pg_logic1_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and529_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and529_h_u_cla12_pg_logic1_y0 _b=h_u_cla12_and529_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and529_y0
.names h_u_cla12_pg_logic2_y0 h_u_cla12_and530_h_u_cla12_pg_logic2_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and530_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and530_h_u_cla12_pg_logic2_y0 _b=h_u_cla12_and530_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and530_y0
.names h_u_cla12_and530_y0 h_u_cla12_and531_h_u_cla12_and530_y0
1 1
.names h_u_cla12_and529_y0 h_u_cla12_and531_h_u_cla12_and529_y0
1 1
.subckt and_gate _a=h_u_cla12_and531_h_u_cla12_and530_y0 _b=h_u_cla12_and531_h_u_cla12_and529_y0 _y0=h_u_cla12_and531_y0
.names h_u_cla12_pg_logic3_y0 h_u_cla12_and532_h_u_cla12_pg_logic3_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and532_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and532_h_u_cla12_pg_logic3_y0 _b=h_u_cla12_and532_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and532_y0
.names h_u_cla12_and532_y0 h_u_cla12_and533_h_u_cla12_and532_y0
1 1
.names h_u_cla12_and531_y0 h_u_cla12_and533_h_u_cla12_and531_y0
1 1
.subckt and_gate _a=h_u_cla12_and533_h_u_cla12_and532_y0 _b=h_u_cla12_and533_h_u_cla12_and531_y0 _y0=h_u_cla12_and533_y0
.names h_u_cla12_pg_logic4_y0 h_u_cla12_and534_h_u_cla12_pg_logic4_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and534_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and534_h_u_cla12_pg_logic4_y0 _b=h_u_cla12_and534_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and534_y0
.names h_u_cla12_and534_y0 h_u_cla12_and535_h_u_cla12_and534_y0
1 1
.names h_u_cla12_and533_y0 h_u_cla12_and535_h_u_cla12_and533_y0
1 1
.subckt and_gate _a=h_u_cla12_and535_h_u_cla12_and534_y0 _b=h_u_cla12_and535_h_u_cla12_and533_y0 _y0=h_u_cla12_and535_y0
.names h_u_cla12_pg_logic5_y0 h_u_cla12_and536_h_u_cla12_pg_logic5_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and536_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and536_h_u_cla12_pg_logic5_y0 _b=h_u_cla12_and536_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and536_y0
.names h_u_cla12_and536_y0 h_u_cla12_and537_h_u_cla12_and536_y0
1 1
.names h_u_cla12_and535_y0 h_u_cla12_and537_h_u_cla12_and535_y0
1 1
.subckt and_gate _a=h_u_cla12_and537_h_u_cla12_and536_y0 _b=h_u_cla12_and537_h_u_cla12_and535_y0 _y0=h_u_cla12_and537_y0
.names h_u_cla12_pg_logic6_y0 h_u_cla12_and538_h_u_cla12_pg_logic6_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and538_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and538_h_u_cla12_pg_logic6_y0 _b=h_u_cla12_and538_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and538_y0
.names h_u_cla12_and538_y0 h_u_cla12_and539_h_u_cla12_and538_y0
1 1
.names h_u_cla12_and537_y0 h_u_cla12_and539_h_u_cla12_and537_y0
1 1
.subckt and_gate _a=h_u_cla12_and539_h_u_cla12_and538_y0 _b=h_u_cla12_and539_h_u_cla12_and537_y0 _y0=h_u_cla12_and539_y0
.names h_u_cla12_pg_logic7_y0 h_u_cla12_and540_h_u_cla12_pg_logic7_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and540_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and540_h_u_cla12_pg_logic7_y0 _b=h_u_cla12_and540_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and540_y0
.names h_u_cla12_and540_y0 h_u_cla12_and541_h_u_cla12_and540_y0
1 1
.names h_u_cla12_and539_y0 h_u_cla12_and541_h_u_cla12_and539_y0
1 1
.subckt and_gate _a=h_u_cla12_and541_h_u_cla12_and540_y0 _b=h_u_cla12_and541_h_u_cla12_and539_y0 _y0=h_u_cla12_and541_y0
.names h_u_cla12_pg_logic8_y0 h_u_cla12_and542_h_u_cla12_pg_logic8_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and542_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and542_h_u_cla12_pg_logic8_y0 _b=h_u_cla12_and542_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and542_y0
.names h_u_cla12_and542_y0 h_u_cla12_and543_h_u_cla12_and542_y0
1 1
.names h_u_cla12_and541_y0 h_u_cla12_and543_h_u_cla12_and541_y0
1 1
.subckt and_gate _a=h_u_cla12_and543_h_u_cla12_and542_y0 _b=h_u_cla12_and543_h_u_cla12_and541_y0 _y0=h_u_cla12_and543_y0
.names h_u_cla12_pg_logic9_y0 h_u_cla12_and544_h_u_cla12_pg_logic9_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and544_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and544_h_u_cla12_pg_logic9_y0 _b=h_u_cla12_and544_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and544_y0
.names h_u_cla12_and544_y0 h_u_cla12_and545_h_u_cla12_and544_y0
1 1
.names h_u_cla12_and543_y0 h_u_cla12_and545_h_u_cla12_and543_y0
1 1
.subckt and_gate _a=h_u_cla12_and545_h_u_cla12_and544_y0 _b=h_u_cla12_and545_h_u_cla12_and543_y0 _y0=h_u_cla12_and545_y0
.names h_u_cla12_pg_logic10_y0 h_u_cla12_and546_h_u_cla12_pg_logic10_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and546_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and546_h_u_cla12_pg_logic10_y0 _b=h_u_cla12_and546_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and546_y0
.names h_u_cla12_and546_y0 h_u_cla12_and547_h_u_cla12_and546_y0
1 1
.names h_u_cla12_and545_y0 h_u_cla12_and547_h_u_cla12_and545_y0
1 1
.subckt and_gate _a=h_u_cla12_and547_h_u_cla12_and546_y0 _b=h_u_cla12_and547_h_u_cla12_and545_y0 _y0=h_u_cla12_and547_y0
.names h_u_cla12_pg_logic11_y0 h_u_cla12_and548_h_u_cla12_pg_logic11_y0
1 1
.names h_u_cla12_pg_logic0_y1 h_u_cla12_and548_h_u_cla12_pg_logic0_y1
1 1
.subckt and_gate _a=h_u_cla12_and548_h_u_cla12_pg_logic11_y0 _b=h_u_cla12_and548_h_u_cla12_pg_logic0_y1 _y0=h_u_cla12_and548_y0
.names h_u_cla12_and548_y0 h_u_cla12_and549_h_u_cla12_and548_y0
1 1
.names h_u_cla12_and547_y0 h_u_cla12_and549_h_u_cla12_and547_y0
1 1
.subckt and_gate _a=h_u_cla12_and549_h_u_cla12_and548_y0 _b=h_u_cla12_and549_h_u_cla12_and547_y0 _y0=h_u_cla12_and549_y0
.names h_u_cla12_pg_logic2_y0 h_u_cla12_and550_h_u_cla12_pg_logic2_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and550_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and550_h_u_cla12_pg_logic2_y0 _b=h_u_cla12_and550_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and550_y0
.names h_u_cla12_pg_logic3_y0 h_u_cla12_and551_h_u_cla12_pg_logic3_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and551_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and551_h_u_cla12_pg_logic3_y0 _b=h_u_cla12_and551_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and551_y0
.names h_u_cla12_and551_y0 h_u_cla12_and552_h_u_cla12_and551_y0
1 1
.names h_u_cla12_and550_y0 h_u_cla12_and552_h_u_cla12_and550_y0
1 1
.subckt and_gate _a=h_u_cla12_and552_h_u_cla12_and551_y0 _b=h_u_cla12_and552_h_u_cla12_and550_y0 _y0=h_u_cla12_and552_y0
.names h_u_cla12_pg_logic4_y0 h_u_cla12_and553_h_u_cla12_pg_logic4_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and553_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and553_h_u_cla12_pg_logic4_y0 _b=h_u_cla12_and553_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and553_y0
.names h_u_cla12_and553_y0 h_u_cla12_and554_h_u_cla12_and553_y0
1 1
.names h_u_cla12_and552_y0 h_u_cla12_and554_h_u_cla12_and552_y0
1 1
.subckt and_gate _a=h_u_cla12_and554_h_u_cla12_and553_y0 _b=h_u_cla12_and554_h_u_cla12_and552_y0 _y0=h_u_cla12_and554_y0
.names h_u_cla12_pg_logic5_y0 h_u_cla12_and555_h_u_cla12_pg_logic5_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and555_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and555_h_u_cla12_pg_logic5_y0 _b=h_u_cla12_and555_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and555_y0
.names h_u_cla12_and555_y0 h_u_cla12_and556_h_u_cla12_and555_y0
1 1
.names h_u_cla12_and554_y0 h_u_cla12_and556_h_u_cla12_and554_y0
1 1
.subckt and_gate _a=h_u_cla12_and556_h_u_cla12_and555_y0 _b=h_u_cla12_and556_h_u_cla12_and554_y0 _y0=h_u_cla12_and556_y0
.names h_u_cla12_pg_logic6_y0 h_u_cla12_and557_h_u_cla12_pg_logic6_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and557_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and557_h_u_cla12_pg_logic6_y0 _b=h_u_cla12_and557_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and557_y0
.names h_u_cla12_and557_y0 h_u_cla12_and558_h_u_cla12_and557_y0
1 1
.names h_u_cla12_and556_y0 h_u_cla12_and558_h_u_cla12_and556_y0
1 1
.subckt and_gate _a=h_u_cla12_and558_h_u_cla12_and557_y0 _b=h_u_cla12_and558_h_u_cla12_and556_y0 _y0=h_u_cla12_and558_y0
.names h_u_cla12_pg_logic7_y0 h_u_cla12_and559_h_u_cla12_pg_logic7_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and559_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and559_h_u_cla12_pg_logic7_y0 _b=h_u_cla12_and559_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and559_y0
.names h_u_cla12_and559_y0 h_u_cla12_and560_h_u_cla12_and559_y0
1 1
.names h_u_cla12_and558_y0 h_u_cla12_and560_h_u_cla12_and558_y0
1 1
.subckt and_gate _a=h_u_cla12_and560_h_u_cla12_and559_y0 _b=h_u_cla12_and560_h_u_cla12_and558_y0 _y0=h_u_cla12_and560_y0
.names h_u_cla12_pg_logic8_y0 h_u_cla12_and561_h_u_cla12_pg_logic8_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and561_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and561_h_u_cla12_pg_logic8_y0 _b=h_u_cla12_and561_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and561_y0
.names h_u_cla12_and561_y0 h_u_cla12_and562_h_u_cla12_and561_y0
1 1
.names h_u_cla12_and560_y0 h_u_cla12_and562_h_u_cla12_and560_y0
1 1
.subckt and_gate _a=h_u_cla12_and562_h_u_cla12_and561_y0 _b=h_u_cla12_and562_h_u_cla12_and560_y0 _y0=h_u_cla12_and562_y0
.names h_u_cla12_pg_logic9_y0 h_u_cla12_and563_h_u_cla12_pg_logic9_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and563_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and563_h_u_cla12_pg_logic9_y0 _b=h_u_cla12_and563_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and563_y0
.names h_u_cla12_and563_y0 h_u_cla12_and564_h_u_cla12_and563_y0
1 1
.names h_u_cla12_and562_y0 h_u_cla12_and564_h_u_cla12_and562_y0
1 1
.subckt and_gate _a=h_u_cla12_and564_h_u_cla12_and563_y0 _b=h_u_cla12_and564_h_u_cla12_and562_y0 _y0=h_u_cla12_and564_y0
.names h_u_cla12_pg_logic10_y0 h_u_cla12_and565_h_u_cla12_pg_logic10_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and565_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and565_h_u_cla12_pg_logic10_y0 _b=h_u_cla12_and565_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and565_y0
.names h_u_cla12_and565_y0 h_u_cla12_and566_h_u_cla12_and565_y0
1 1
.names h_u_cla12_and564_y0 h_u_cla12_and566_h_u_cla12_and564_y0
1 1
.subckt and_gate _a=h_u_cla12_and566_h_u_cla12_and565_y0 _b=h_u_cla12_and566_h_u_cla12_and564_y0 _y0=h_u_cla12_and566_y0
.names h_u_cla12_pg_logic11_y0 h_u_cla12_and567_h_u_cla12_pg_logic11_y0
1 1
.names h_u_cla12_pg_logic1_y1 h_u_cla12_and567_h_u_cla12_pg_logic1_y1
1 1
.subckt and_gate _a=h_u_cla12_and567_h_u_cla12_pg_logic11_y0 _b=h_u_cla12_and567_h_u_cla12_pg_logic1_y1 _y0=h_u_cla12_and567_y0
.names h_u_cla12_and567_y0 h_u_cla12_and568_h_u_cla12_and567_y0
1 1
.names h_u_cla12_and566_y0 h_u_cla12_and568_h_u_cla12_and566_y0
1 1
.subckt and_gate _a=h_u_cla12_and568_h_u_cla12_and567_y0 _b=h_u_cla12_and568_h_u_cla12_and566_y0 _y0=h_u_cla12_and568_y0
.names h_u_cla12_pg_logic3_y0 h_u_cla12_and569_h_u_cla12_pg_logic3_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and569_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and569_h_u_cla12_pg_logic3_y0 _b=h_u_cla12_and569_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and569_y0
.names h_u_cla12_pg_logic4_y0 h_u_cla12_and570_h_u_cla12_pg_logic4_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and570_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and570_h_u_cla12_pg_logic4_y0 _b=h_u_cla12_and570_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and570_y0
.names h_u_cla12_and570_y0 h_u_cla12_and571_h_u_cla12_and570_y0
1 1
.names h_u_cla12_and569_y0 h_u_cla12_and571_h_u_cla12_and569_y0
1 1
.subckt and_gate _a=h_u_cla12_and571_h_u_cla12_and570_y0 _b=h_u_cla12_and571_h_u_cla12_and569_y0 _y0=h_u_cla12_and571_y0
.names h_u_cla12_pg_logic5_y0 h_u_cla12_and572_h_u_cla12_pg_logic5_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and572_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and572_h_u_cla12_pg_logic5_y0 _b=h_u_cla12_and572_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and572_y0
.names h_u_cla12_and572_y0 h_u_cla12_and573_h_u_cla12_and572_y0
1 1
.names h_u_cla12_and571_y0 h_u_cla12_and573_h_u_cla12_and571_y0
1 1
.subckt and_gate _a=h_u_cla12_and573_h_u_cla12_and572_y0 _b=h_u_cla12_and573_h_u_cla12_and571_y0 _y0=h_u_cla12_and573_y0
.names h_u_cla12_pg_logic6_y0 h_u_cla12_and574_h_u_cla12_pg_logic6_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and574_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and574_h_u_cla12_pg_logic6_y0 _b=h_u_cla12_and574_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and574_y0
.names h_u_cla12_and574_y0 h_u_cla12_and575_h_u_cla12_and574_y0
1 1
.names h_u_cla12_and573_y0 h_u_cla12_and575_h_u_cla12_and573_y0
1 1
.subckt and_gate _a=h_u_cla12_and575_h_u_cla12_and574_y0 _b=h_u_cla12_and575_h_u_cla12_and573_y0 _y0=h_u_cla12_and575_y0
.names h_u_cla12_pg_logic7_y0 h_u_cla12_and576_h_u_cla12_pg_logic7_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and576_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and576_h_u_cla12_pg_logic7_y0 _b=h_u_cla12_and576_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and576_y0
.names h_u_cla12_and576_y0 h_u_cla12_and577_h_u_cla12_and576_y0
1 1
.names h_u_cla12_and575_y0 h_u_cla12_and577_h_u_cla12_and575_y0
1 1
.subckt and_gate _a=h_u_cla12_and577_h_u_cla12_and576_y0 _b=h_u_cla12_and577_h_u_cla12_and575_y0 _y0=h_u_cla12_and577_y0
.names h_u_cla12_pg_logic8_y0 h_u_cla12_and578_h_u_cla12_pg_logic8_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and578_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and578_h_u_cla12_pg_logic8_y0 _b=h_u_cla12_and578_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and578_y0
.names h_u_cla12_and578_y0 h_u_cla12_and579_h_u_cla12_and578_y0
1 1
.names h_u_cla12_and577_y0 h_u_cla12_and579_h_u_cla12_and577_y0
1 1
.subckt and_gate _a=h_u_cla12_and579_h_u_cla12_and578_y0 _b=h_u_cla12_and579_h_u_cla12_and577_y0 _y0=h_u_cla12_and579_y0
.names h_u_cla12_pg_logic9_y0 h_u_cla12_and580_h_u_cla12_pg_logic9_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and580_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and580_h_u_cla12_pg_logic9_y0 _b=h_u_cla12_and580_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and580_y0
.names h_u_cla12_and580_y0 h_u_cla12_and581_h_u_cla12_and580_y0
1 1
.names h_u_cla12_and579_y0 h_u_cla12_and581_h_u_cla12_and579_y0
1 1
.subckt and_gate _a=h_u_cla12_and581_h_u_cla12_and580_y0 _b=h_u_cla12_and581_h_u_cla12_and579_y0 _y0=h_u_cla12_and581_y0
.names h_u_cla12_pg_logic10_y0 h_u_cla12_and582_h_u_cla12_pg_logic10_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and582_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and582_h_u_cla12_pg_logic10_y0 _b=h_u_cla12_and582_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and582_y0
.names h_u_cla12_and582_y0 h_u_cla12_and583_h_u_cla12_and582_y0
1 1
.names h_u_cla12_and581_y0 h_u_cla12_and583_h_u_cla12_and581_y0
1 1
.subckt and_gate _a=h_u_cla12_and583_h_u_cla12_and582_y0 _b=h_u_cla12_and583_h_u_cla12_and581_y0 _y0=h_u_cla12_and583_y0
.names h_u_cla12_pg_logic11_y0 h_u_cla12_and584_h_u_cla12_pg_logic11_y0
1 1
.names h_u_cla12_pg_logic2_y1 h_u_cla12_and584_h_u_cla12_pg_logic2_y1
1 1
.subckt and_gate _a=h_u_cla12_and584_h_u_cla12_pg_logic11_y0 _b=h_u_cla12_and584_h_u_cla12_pg_logic2_y1 _y0=h_u_cla12_and584_y0
.names h_u_cla12_and584_y0 h_u_cla12_and585_h_u_cla12_and584_y0
1 1
.names h_u_cla12_and583_y0 h_u_cla12_and585_h_u_cla12_and583_y0
1 1
.subckt and_gate _a=h_u_cla12_and585_h_u_cla12_and584_y0 _b=h_u_cla12_and585_h_u_cla12_and583_y0 _y0=h_u_cla12_and585_y0
.names h_u_cla12_pg_logic4_y0 h_u_cla12_and586_h_u_cla12_pg_logic4_y0
1 1
.names h_u_cla12_pg_logic3_y1 h_u_cla12_and586_h_u_cla12_pg_logic3_y1
1 1
.subckt and_gate _a=h_u_cla12_and586_h_u_cla12_pg_logic4_y0 _b=h_u_cla12_and586_h_u_cla12_pg_logic3_y1 _y0=h_u_cla12_and586_y0
.names h_u_cla12_pg_logic5_y0 h_u_cla12_and587_h_u_cla12_pg_logic5_y0
1 1
.names h_u_cla12_pg_logic3_y1 h_u_cla12_and587_h_u_cla12_pg_logic3_y1
1 1
.subckt and_gate _a=h_u_cla12_and587_h_u_cla12_pg_logic5_y0 _b=h_u_cla12_and587_h_u_cla12_pg_logic3_y1 _y0=h_u_cla12_and587_y0
.names h_u_cla12_and587_y0 h_u_cla12_and588_h_u_cla12_and587_y0
1 1
.names h_u_cla12_and586_y0 h_u_cla12_and588_h_u_cla12_and586_y0
1 1
.subckt and_gate _a=h_u_cla12_and588_h_u_cla12_and587_y0 _b=h_u_cla12_and588_h_u_cla12_and586_y0 _y0=h_u_cla12_and588_y0
.names h_u_cla12_pg_logic6_y0 h_u_cla12_and589_h_u_cla12_pg_logic6_y0
1 1
.names h_u_cla12_pg_logic3_y1 h_u_cla12_and589_h_u_cla12_pg_logic3_y1
1 1
.subckt and_gate _a=h_u_cla12_and589_h_u_cla12_pg_logic6_y0 _b=h_u_cla12_and589_h_u_cla12_pg_logic3_y1 _y0=h_u_cla12_and589_y0
.names h_u_cla12_and589_y0 h_u_cla12_and590_h_u_cla12_and589_y0
1 1
.names h_u_cla12_and588_y0 h_u_cla12_and590_h_u_cla12_and588_y0
1 1
.subckt and_gate _a=h_u_cla12_and590_h_u_cla12_and589_y0 _b=h_u_cla12_and590_h_u_cla12_and588_y0 _y0=h_u_cla12_and590_y0
.names h_u_cla12_pg_logic7_y0 h_u_cla12_and591_h_u_cla12_pg_logic7_y0
1 1
.names h_u_cla12_pg_logic3_y1 h_u_cla12_and591_h_u_cla12_pg_logic3_y1
1 1
.subckt and_gate _a=h_u_cla12_and591_h_u_cla12_pg_logic7_y0 _b=h_u_cla12_and591_h_u_cla12_pg_logic3_y1 _y0=h_u_cla12_and591_y0
.names h_u_cla12_and591_y0 h_u_cla12_and592_h_u_cla12_and591_y0
1 1
.names h_u_cla12_and590_y0 h_u_cla12_and592_h_u_cla12_and590_y0
1 1
.subckt and_gate _a=h_u_cla12_and592_h_u_cla12_and591_y0 _b=h_u_cla12_and592_h_u_cla12_and590_y0 _y0=h_u_cla12_and592_y0
.names h_u_cla12_pg_logic8_y0 h_u_cla12_and593_h_u_cla12_pg_logic8_y0
1 1
.names h_u_cla12_pg_logic3_y1 h_u_cla12_and593_h_u_cla12_pg_logic3_y1
1 1
.subckt and_gate _a=h_u_cla12_and593_h_u_cla12_pg_logic8_y0 _b=h_u_cla12_and593_h_u_cla12_pg_logic3_y1 _y0=h_u_cla12_and593_y0
.names h_u_cla12_and593_y0 h_u_cla12_and594_h_u_cla12_and593_y0
1 1
.names h_u_cla12_and592_y0 h_u_cla12_and594_h_u_cla12_and592_y0
1 1
.subckt and_gate _a=h_u_cla12_and594_h_u_cla12_and593_y0 _b=h_u_cla12_and594_h_u_cla12_and592_y0 _y0=h_u_cla12_and594_y0
.names h_u_cla12_pg_logic9_y0 h_u_cla12_and595_h_u_cla12_pg_logic9_y0
1 1
.names h_u_cla12_pg_logic3_y1 h_u_cla12_and595_h_u_cla12_pg_logic3_y1
1 1
.subckt and_gate _a=h_u_cla12_and595_h_u_cla12_pg_logic9_y0 _b=h_u_cla12_and595_h_u_cla12_pg_logic3_y1 _y0=h_u_cla12_and595_y0
.names h_u_cla12_and595_y0 h_u_cla12_and596_h_u_cla12_and595_y0
1 1
.names h_u_cla12_and594_y0 h_u_cla12_and596_h_u_cla12_and594_y0
1 1
.subckt and_gate _a=h_u_cla12_and596_h_u_cla12_and595_y0 _b=h_u_cla12_and596_h_u_cla12_and594_y0 _y0=h_u_cla12_and596_y0
.names h_u_cla12_pg_logic10_y0 h_u_cla12_and597_h_u_cla12_pg_logic10_y0
1 1
.names h_u_cla12_pg_logic3_y1 h_u_cla12_and597_h_u_cla12_pg_logic3_y1
1 1
.subckt and_gate _a=h_u_cla12_and597_h_u_cla12_pg_logic10_y0 _b=h_u_cla12_and597_h_u_cla12_pg_logic3_y1 _y0=h_u_cla12_and597_y0
.names h_u_cla12_and597_y0 h_u_cla12_and598_h_u_cla12_and597_y0
1 1
.names h_u_cla12_and596_y0 h_u_cla12_and598_h_u_cla12_and596_y0
1 1
.subckt and_gate _a=h_u_cla12_and598_h_u_cla12_and597_y0 _b=h_u_cla12_and598_h_u_cla12_and596_y0 _y0=h_u_cla12_and598_y0
.names h_u_cla12_pg_logic11_y0 h_u_cla12_and599_h_u_cla12_pg_logic11_y0
1 1
.names h_u_cla12_pg_logic3_y1 h_u_cla12_and599_h_u_cla12_pg_logic3_y1
1 1
.subckt and_gate _a=h_u_cla12_and599_h_u_cla12_pg_logic11_y0 _b=h_u_cla12_and599_h_u_cla12_pg_logic3_y1 _y0=h_u_cla12_and599_y0
.names h_u_cla12_and599_y0 h_u_cla12_and600_h_u_cla12_and599_y0
1 1
.names h_u_cla12_and598_y0 h_u_cla12_and600_h_u_cla12_and598_y0
1 1
.subckt and_gate _a=h_u_cla12_and600_h_u_cla12_and599_y0 _b=h_u_cla12_and600_h_u_cla12_and598_y0 _y0=h_u_cla12_and600_y0
.names h_u_cla12_pg_logic5_y0 h_u_cla12_and601_h_u_cla12_pg_logic5_y0
1 1
.names h_u_cla12_pg_logic4_y1 h_u_cla12_and601_h_u_cla12_pg_logic4_y1
1 1
.subckt and_gate _a=h_u_cla12_and601_h_u_cla12_pg_logic5_y0 _b=h_u_cla12_and601_h_u_cla12_pg_logic4_y1 _y0=h_u_cla12_and601_y0
.names h_u_cla12_pg_logic6_y0 h_u_cla12_and602_h_u_cla12_pg_logic6_y0
1 1
.names h_u_cla12_pg_logic4_y1 h_u_cla12_and602_h_u_cla12_pg_logic4_y1
1 1
.subckt and_gate _a=h_u_cla12_and602_h_u_cla12_pg_logic6_y0 _b=h_u_cla12_and602_h_u_cla12_pg_logic4_y1 _y0=h_u_cla12_and602_y0
.names h_u_cla12_and602_y0 h_u_cla12_and603_h_u_cla12_and602_y0
1 1
.names h_u_cla12_and601_y0 h_u_cla12_and603_h_u_cla12_and601_y0
1 1
.subckt and_gate _a=h_u_cla12_and603_h_u_cla12_and602_y0 _b=h_u_cla12_and603_h_u_cla12_and601_y0 _y0=h_u_cla12_and603_y0
.names h_u_cla12_pg_logic7_y0 h_u_cla12_and604_h_u_cla12_pg_logic7_y0
1 1
.names h_u_cla12_pg_logic4_y1 h_u_cla12_and604_h_u_cla12_pg_logic4_y1
1 1
.subckt and_gate _a=h_u_cla12_and604_h_u_cla12_pg_logic7_y0 _b=h_u_cla12_and604_h_u_cla12_pg_logic4_y1 _y0=h_u_cla12_and604_y0
.names h_u_cla12_and604_y0 h_u_cla12_and605_h_u_cla12_and604_y0
1 1
.names h_u_cla12_and603_y0 h_u_cla12_and605_h_u_cla12_and603_y0
1 1
.subckt and_gate _a=h_u_cla12_and605_h_u_cla12_and604_y0 _b=h_u_cla12_and605_h_u_cla12_and603_y0 _y0=h_u_cla12_and605_y0
.names h_u_cla12_pg_logic8_y0 h_u_cla12_and606_h_u_cla12_pg_logic8_y0
1 1
.names h_u_cla12_pg_logic4_y1 h_u_cla12_and606_h_u_cla12_pg_logic4_y1
1 1
.subckt and_gate _a=h_u_cla12_and606_h_u_cla12_pg_logic8_y0 _b=h_u_cla12_and606_h_u_cla12_pg_logic4_y1 _y0=h_u_cla12_and606_y0
.names h_u_cla12_and606_y0 h_u_cla12_and607_h_u_cla12_and606_y0
1 1
.names h_u_cla12_and605_y0 h_u_cla12_and607_h_u_cla12_and605_y0
1 1
.subckt and_gate _a=h_u_cla12_and607_h_u_cla12_and606_y0 _b=h_u_cla12_and607_h_u_cla12_and605_y0 _y0=h_u_cla12_and607_y0
.names h_u_cla12_pg_logic9_y0 h_u_cla12_and608_h_u_cla12_pg_logic9_y0
1 1
.names h_u_cla12_pg_logic4_y1 h_u_cla12_and608_h_u_cla12_pg_logic4_y1
1 1
.subckt and_gate _a=h_u_cla12_and608_h_u_cla12_pg_logic9_y0 _b=h_u_cla12_and608_h_u_cla12_pg_logic4_y1 _y0=h_u_cla12_and608_y0
.names h_u_cla12_and608_y0 h_u_cla12_and609_h_u_cla12_and608_y0
1 1
.names h_u_cla12_and607_y0 h_u_cla12_and609_h_u_cla12_and607_y0
1 1
.subckt and_gate _a=h_u_cla12_and609_h_u_cla12_and608_y0 _b=h_u_cla12_and609_h_u_cla12_and607_y0 _y0=h_u_cla12_and609_y0
.names h_u_cla12_pg_logic10_y0 h_u_cla12_and610_h_u_cla12_pg_logic10_y0
1 1
.names h_u_cla12_pg_logic4_y1 h_u_cla12_and610_h_u_cla12_pg_logic4_y1
1 1
.subckt and_gate _a=h_u_cla12_and610_h_u_cla12_pg_logic10_y0 _b=h_u_cla12_and610_h_u_cla12_pg_logic4_y1 _y0=h_u_cla12_and610_y0
.names h_u_cla12_and610_y0 h_u_cla12_and611_h_u_cla12_and610_y0
1 1
.names h_u_cla12_and609_y0 h_u_cla12_and611_h_u_cla12_and609_y0
1 1
.subckt and_gate _a=h_u_cla12_and611_h_u_cla12_and610_y0 _b=h_u_cla12_and611_h_u_cla12_and609_y0 _y0=h_u_cla12_and611_y0
.names h_u_cla12_pg_logic11_y0 h_u_cla12_and612_h_u_cla12_pg_logic11_y0
1 1
.names h_u_cla12_pg_logic4_y1 h_u_cla12_and612_h_u_cla12_pg_logic4_y1
1 1
.subckt and_gate _a=h_u_cla12_and612_h_u_cla12_pg_logic11_y0 _b=h_u_cla12_and612_h_u_cla12_pg_logic4_y1 _y0=h_u_cla12_and612_y0
.names h_u_cla12_and612_y0 h_u_cla12_and613_h_u_cla12_and612_y0
1 1
.names h_u_cla12_and611_y0 h_u_cla12_and613_h_u_cla12_and611_y0
1 1
.subckt and_gate _a=h_u_cla12_and613_h_u_cla12_and612_y0 _b=h_u_cla12_and613_h_u_cla12_and611_y0 _y0=h_u_cla12_and613_y0
.names h_u_cla12_pg_logic6_y0 h_u_cla12_and614_h_u_cla12_pg_logic6_y0
1 1
.names h_u_cla12_pg_logic5_y1 h_u_cla12_and614_h_u_cla12_pg_logic5_y1
1 1
.subckt and_gate _a=h_u_cla12_and614_h_u_cla12_pg_logic6_y0 _b=h_u_cla12_and614_h_u_cla12_pg_logic5_y1 _y0=h_u_cla12_and614_y0
.names h_u_cla12_pg_logic7_y0 h_u_cla12_and615_h_u_cla12_pg_logic7_y0
1 1
.names h_u_cla12_pg_logic5_y1 h_u_cla12_and615_h_u_cla12_pg_logic5_y1
1 1
.subckt and_gate _a=h_u_cla12_and615_h_u_cla12_pg_logic7_y0 _b=h_u_cla12_and615_h_u_cla12_pg_logic5_y1 _y0=h_u_cla12_and615_y0
.names h_u_cla12_and615_y0 h_u_cla12_and616_h_u_cla12_and615_y0
1 1
.names h_u_cla12_and614_y0 h_u_cla12_and616_h_u_cla12_and614_y0
1 1
.subckt and_gate _a=h_u_cla12_and616_h_u_cla12_and615_y0 _b=h_u_cla12_and616_h_u_cla12_and614_y0 _y0=h_u_cla12_and616_y0
.names h_u_cla12_pg_logic8_y0 h_u_cla12_and617_h_u_cla12_pg_logic8_y0
1 1
.names h_u_cla12_pg_logic5_y1 h_u_cla12_and617_h_u_cla12_pg_logic5_y1
1 1
.subckt and_gate _a=h_u_cla12_and617_h_u_cla12_pg_logic8_y0 _b=h_u_cla12_and617_h_u_cla12_pg_logic5_y1 _y0=h_u_cla12_and617_y0
.names h_u_cla12_and617_y0 h_u_cla12_and618_h_u_cla12_and617_y0
1 1
.names h_u_cla12_and616_y0 h_u_cla12_and618_h_u_cla12_and616_y0
1 1
.subckt and_gate _a=h_u_cla12_and618_h_u_cla12_and617_y0 _b=h_u_cla12_and618_h_u_cla12_and616_y0 _y0=h_u_cla12_and618_y0
.names h_u_cla12_pg_logic9_y0 h_u_cla12_and619_h_u_cla12_pg_logic9_y0
1 1
.names h_u_cla12_pg_logic5_y1 h_u_cla12_and619_h_u_cla12_pg_logic5_y1
1 1
.subckt and_gate _a=h_u_cla12_and619_h_u_cla12_pg_logic9_y0 _b=h_u_cla12_and619_h_u_cla12_pg_logic5_y1 _y0=h_u_cla12_and619_y0
.names h_u_cla12_and619_y0 h_u_cla12_and620_h_u_cla12_and619_y0
1 1
.names h_u_cla12_and618_y0 h_u_cla12_and620_h_u_cla12_and618_y0
1 1
.subckt and_gate _a=h_u_cla12_and620_h_u_cla12_and619_y0 _b=h_u_cla12_and620_h_u_cla12_and618_y0 _y0=h_u_cla12_and620_y0
.names h_u_cla12_pg_logic10_y0 h_u_cla12_and621_h_u_cla12_pg_logic10_y0
1 1
.names h_u_cla12_pg_logic5_y1 h_u_cla12_and621_h_u_cla12_pg_logic5_y1
1 1
.subckt and_gate _a=h_u_cla12_and621_h_u_cla12_pg_logic10_y0 _b=h_u_cla12_and621_h_u_cla12_pg_logic5_y1 _y0=h_u_cla12_and621_y0
.names h_u_cla12_and621_y0 h_u_cla12_and622_h_u_cla12_and621_y0
1 1
.names h_u_cla12_and620_y0 h_u_cla12_and622_h_u_cla12_and620_y0
1 1
.subckt and_gate _a=h_u_cla12_and622_h_u_cla12_and621_y0 _b=h_u_cla12_and622_h_u_cla12_and620_y0 _y0=h_u_cla12_and622_y0
.names h_u_cla12_pg_logic11_y0 h_u_cla12_and623_h_u_cla12_pg_logic11_y0
1 1
.names h_u_cla12_pg_logic5_y1 h_u_cla12_and623_h_u_cla12_pg_logic5_y1
1 1
.subckt and_gate _a=h_u_cla12_and623_h_u_cla12_pg_logic11_y0 _b=h_u_cla12_and623_h_u_cla12_pg_logic5_y1 _y0=h_u_cla12_and623_y0
.names h_u_cla12_and623_y0 h_u_cla12_and624_h_u_cla12_and623_y0
1 1
.names h_u_cla12_and622_y0 h_u_cla12_and624_h_u_cla12_and622_y0
1 1
.subckt and_gate _a=h_u_cla12_and624_h_u_cla12_and623_y0 _b=h_u_cla12_and624_h_u_cla12_and622_y0 _y0=h_u_cla12_and624_y0
.names h_u_cla12_pg_logic7_y0 h_u_cla12_and625_h_u_cla12_pg_logic7_y0
1 1
.names h_u_cla12_pg_logic6_y1 h_u_cla12_and625_h_u_cla12_pg_logic6_y1
1 1
.subckt and_gate _a=h_u_cla12_and625_h_u_cla12_pg_logic7_y0 _b=h_u_cla12_and625_h_u_cla12_pg_logic6_y1 _y0=h_u_cla12_and625_y0
.names h_u_cla12_pg_logic8_y0 h_u_cla12_and626_h_u_cla12_pg_logic8_y0
1 1
.names h_u_cla12_pg_logic6_y1 h_u_cla12_and626_h_u_cla12_pg_logic6_y1
1 1
.subckt and_gate _a=h_u_cla12_and626_h_u_cla12_pg_logic8_y0 _b=h_u_cla12_and626_h_u_cla12_pg_logic6_y1 _y0=h_u_cla12_and626_y0
.names h_u_cla12_and626_y0 h_u_cla12_and627_h_u_cla12_and626_y0
1 1
.names h_u_cla12_and625_y0 h_u_cla12_and627_h_u_cla12_and625_y0
1 1
.subckt and_gate _a=h_u_cla12_and627_h_u_cla12_and626_y0 _b=h_u_cla12_and627_h_u_cla12_and625_y0 _y0=h_u_cla12_and627_y0
.names h_u_cla12_pg_logic9_y0 h_u_cla12_and628_h_u_cla12_pg_logic9_y0
1 1
.names h_u_cla12_pg_logic6_y1 h_u_cla12_and628_h_u_cla12_pg_logic6_y1
1 1
.subckt and_gate _a=h_u_cla12_and628_h_u_cla12_pg_logic9_y0 _b=h_u_cla12_and628_h_u_cla12_pg_logic6_y1 _y0=h_u_cla12_and628_y0
.names h_u_cla12_and628_y0 h_u_cla12_and629_h_u_cla12_and628_y0
1 1
.names h_u_cla12_and627_y0 h_u_cla12_and629_h_u_cla12_and627_y0
1 1
.subckt and_gate _a=h_u_cla12_and629_h_u_cla12_and628_y0 _b=h_u_cla12_and629_h_u_cla12_and627_y0 _y0=h_u_cla12_and629_y0
.names h_u_cla12_pg_logic10_y0 h_u_cla12_and630_h_u_cla12_pg_logic10_y0
1 1
.names h_u_cla12_pg_logic6_y1 h_u_cla12_and630_h_u_cla12_pg_logic6_y1
1 1
.subckt and_gate _a=h_u_cla12_and630_h_u_cla12_pg_logic10_y0 _b=h_u_cla12_and630_h_u_cla12_pg_logic6_y1 _y0=h_u_cla12_and630_y0
.names h_u_cla12_and630_y0 h_u_cla12_and631_h_u_cla12_and630_y0
1 1
.names h_u_cla12_and629_y0 h_u_cla12_and631_h_u_cla12_and629_y0
1 1
.subckt and_gate _a=h_u_cla12_and631_h_u_cla12_and630_y0 _b=h_u_cla12_and631_h_u_cla12_and629_y0 _y0=h_u_cla12_and631_y0
.names h_u_cla12_pg_logic11_y0 h_u_cla12_and632_h_u_cla12_pg_logic11_y0
1 1
.names h_u_cla12_pg_logic6_y1 h_u_cla12_and632_h_u_cla12_pg_logic6_y1
1 1
.subckt and_gate _a=h_u_cla12_and632_h_u_cla12_pg_logic11_y0 _b=h_u_cla12_and632_h_u_cla12_pg_logic6_y1 _y0=h_u_cla12_and632_y0
.names h_u_cla12_and632_y0 h_u_cla12_and633_h_u_cla12_and632_y0
1 1
.names h_u_cla12_and631_y0 h_u_cla12_and633_h_u_cla12_and631_y0
1 1
.subckt and_gate _a=h_u_cla12_and633_h_u_cla12_and632_y0 _b=h_u_cla12_and633_h_u_cla12_and631_y0 _y0=h_u_cla12_and633_y0
.names h_u_cla12_pg_logic8_y0 h_u_cla12_and634_h_u_cla12_pg_logic8_y0
1 1
.names h_u_cla12_pg_logic7_y1 h_u_cla12_and634_h_u_cla12_pg_logic7_y1
1 1
.subckt and_gate _a=h_u_cla12_and634_h_u_cla12_pg_logic8_y0 _b=h_u_cla12_and634_h_u_cla12_pg_logic7_y1 _y0=h_u_cla12_and634_y0
.names h_u_cla12_pg_logic9_y0 h_u_cla12_and635_h_u_cla12_pg_logic9_y0
1 1
.names h_u_cla12_pg_logic7_y1 h_u_cla12_and635_h_u_cla12_pg_logic7_y1
1 1
.subckt and_gate _a=h_u_cla12_and635_h_u_cla12_pg_logic9_y0 _b=h_u_cla12_and635_h_u_cla12_pg_logic7_y1 _y0=h_u_cla12_and635_y0
.names h_u_cla12_and635_y0 h_u_cla12_and636_h_u_cla12_and635_y0
1 1
.names h_u_cla12_and634_y0 h_u_cla12_and636_h_u_cla12_and634_y0
1 1
.subckt and_gate _a=h_u_cla12_and636_h_u_cla12_and635_y0 _b=h_u_cla12_and636_h_u_cla12_and634_y0 _y0=h_u_cla12_and636_y0
.names h_u_cla12_pg_logic10_y0 h_u_cla12_and637_h_u_cla12_pg_logic10_y0
1 1
.names h_u_cla12_pg_logic7_y1 h_u_cla12_and637_h_u_cla12_pg_logic7_y1
1 1
.subckt and_gate _a=h_u_cla12_and637_h_u_cla12_pg_logic10_y0 _b=h_u_cla12_and637_h_u_cla12_pg_logic7_y1 _y0=h_u_cla12_and637_y0
.names h_u_cla12_and637_y0 h_u_cla12_and638_h_u_cla12_and637_y0
1 1
.names h_u_cla12_and636_y0 h_u_cla12_and638_h_u_cla12_and636_y0
1 1
.subckt and_gate _a=h_u_cla12_and638_h_u_cla12_and637_y0 _b=h_u_cla12_and638_h_u_cla12_and636_y0 _y0=h_u_cla12_and638_y0
.names h_u_cla12_pg_logic11_y0 h_u_cla12_and639_h_u_cla12_pg_logic11_y0
1 1
.names h_u_cla12_pg_logic7_y1 h_u_cla12_and639_h_u_cla12_pg_logic7_y1
1 1
.subckt and_gate _a=h_u_cla12_and639_h_u_cla12_pg_logic11_y0 _b=h_u_cla12_and639_h_u_cla12_pg_logic7_y1 _y0=h_u_cla12_and639_y0
.names h_u_cla12_and639_y0 h_u_cla12_and640_h_u_cla12_and639_y0
1 1
.names h_u_cla12_and638_y0 h_u_cla12_and640_h_u_cla12_and638_y0
1 1
.subckt and_gate _a=h_u_cla12_and640_h_u_cla12_and639_y0 _b=h_u_cla12_and640_h_u_cla12_and638_y0 _y0=h_u_cla12_and640_y0
.names h_u_cla12_pg_logic9_y0 h_u_cla12_and641_h_u_cla12_pg_logic9_y0
1 1
.names h_u_cla12_pg_logic8_y1 h_u_cla12_and641_h_u_cla12_pg_logic8_y1
1 1
.subckt and_gate _a=h_u_cla12_and641_h_u_cla12_pg_logic9_y0 _b=h_u_cla12_and641_h_u_cla12_pg_logic8_y1 _y0=h_u_cla12_and641_y0
.names h_u_cla12_pg_logic10_y0 h_u_cla12_and642_h_u_cla12_pg_logic10_y0
1 1
.names h_u_cla12_pg_logic8_y1 h_u_cla12_and642_h_u_cla12_pg_logic8_y1
1 1
.subckt and_gate _a=h_u_cla12_and642_h_u_cla12_pg_logic10_y0 _b=h_u_cla12_and642_h_u_cla12_pg_logic8_y1 _y0=h_u_cla12_and642_y0
.names h_u_cla12_and642_y0 h_u_cla12_and643_h_u_cla12_and642_y0
1 1
.names h_u_cla12_and641_y0 h_u_cla12_and643_h_u_cla12_and641_y0
1 1
.subckt and_gate _a=h_u_cla12_and643_h_u_cla12_and642_y0 _b=h_u_cla12_and643_h_u_cla12_and641_y0 _y0=h_u_cla12_and643_y0
.names h_u_cla12_pg_logic11_y0 h_u_cla12_and644_h_u_cla12_pg_logic11_y0
1 1
.names h_u_cla12_pg_logic8_y1 h_u_cla12_and644_h_u_cla12_pg_logic8_y1
1 1
.subckt and_gate _a=h_u_cla12_and644_h_u_cla12_pg_logic11_y0 _b=h_u_cla12_and644_h_u_cla12_pg_logic8_y1 _y0=h_u_cla12_and644_y0
.names h_u_cla12_and644_y0 h_u_cla12_and645_h_u_cla12_and644_y0
1 1
.names h_u_cla12_and643_y0 h_u_cla12_and645_h_u_cla12_and643_y0
1 1
.subckt and_gate _a=h_u_cla12_and645_h_u_cla12_and644_y0 _b=h_u_cla12_and645_h_u_cla12_and643_y0 _y0=h_u_cla12_and645_y0
.names h_u_cla12_pg_logic10_y0 h_u_cla12_and646_h_u_cla12_pg_logic10_y0
1 1
.names h_u_cla12_pg_logic9_y1 h_u_cla12_and646_h_u_cla12_pg_logic9_y1
1 1
.subckt and_gate _a=h_u_cla12_and646_h_u_cla12_pg_logic10_y0 _b=h_u_cla12_and646_h_u_cla12_pg_logic9_y1 _y0=h_u_cla12_and646_y0
.names h_u_cla12_pg_logic11_y0 h_u_cla12_and647_h_u_cla12_pg_logic11_y0
1 1
.names h_u_cla12_pg_logic9_y1 h_u_cla12_and647_h_u_cla12_pg_logic9_y1
1 1
.subckt and_gate _a=h_u_cla12_and647_h_u_cla12_pg_logic11_y0 _b=h_u_cla12_and647_h_u_cla12_pg_logic9_y1 _y0=h_u_cla12_and647_y0
.names h_u_cla12_and647_y0 h_u_cla12_and648_h_u_cla12_and647_y0
1 1
.names h_u_cla12_and646_y0 h_u_cla12_and648_h_u_cla12_and646_y0
1 1
.subckt and_gate _a=h_u_cla12_and648_h_u_cla12_and647_y0 _b=h_u_cla12_and648_h_u_cla12_and646_y0 _y0=h_u_cla12_and648_y0
.names h_u_cla12_pg_logic11_y0 h_u_cla12_and649_h_u_cla12_pg_logic11_y0
1 1
.names h_u_cla12_pg_logic10_y1 h_u_cla12_and649_h_u_cla12_pg_logic10_y1
1 1
.subckt and_gate _a=h_u_cla12_and649_h_u_cla12_pg_logic11_y0 _b=h_u_cla12_and649_h_u_cla12_pg_logic10_y1 _y0=h_u_cla12_and649_y0
.names h_u_cla12_and649_y0 h_u_cla12_or66_h_u_cla12_and649_y0
1 1
.names h_u_cla12_and528_y0 h_u_cla12_or66_h_u_cla12_and528_y0
1 1
.subckt or_gate _a=h_u_cla12_or66_h_u_cla12_and649_y0 _b=h_u_cla12_or66_h_u_cla12_and528_y0 _y0=h_u_cla12_or66_y0
.names h_u_cla12_or66_y0 h_u_cla12_or67_h_u_cla12_or66_y0
1 1
.names h_u_cla12_and549_y0 h_u_cla12_or67_h_u_cla12_and549_y0
1 1
.subckt or_gate _a=h_u_cla12_or67_h_u_cla12_or66_y0 _b=h_u_cla12_or67_h_u_cla12_and549_y0 _y0=h_u_cla12_or67_y0
.names h_u_cla12_or67_y0 h_u_cla12_or68_h_u_cla12_or67_y0
1 1
.names h_u_cla12_and568_y0 h_u_cla12_or68_h_u_cla12_and568_y0
1 1
.subckt or_gate _a=h_u_cla12_or68_h_u_cla12_or67_y0 _b=h_u_cla12_or68_h_u_cla12_and568_y0 _y0=h_u_cla12_or68_y0
.names h_u_cla12_or68_y0 h_u_cla12_or69_h_u_cla12_or68_y0
1 1
.names h_u_cla12_and585_y0 h_u_cla12_or69_h_u_cla12_and585_y0
1 1
.subckt or_gate _a=h_u_cla12_or69_h_u_cla12_or68_y0 _b=h_u_cla12_or69_h_u_cla12_and585_y0 _y0=h_u_cla12_or69_y0
.names h_u_cla12_or69_y0 h_u_cla12_or70_h_u_cla12_or69_y0
1 1
.names h_u_cla12_and600_y0 h_u_cla12_or70_h_u_cla12_and600_y0
1 1
.subckt or_gate _a=h_u_cla12_or70_h_u_cla12_or69_y0 _b=h_u_cla12_or70_h_u_cla12_and600_y0 _y0=h_u_cla12_or70_y0
.names h_u_cla12_or70_y0 h_u_cla12_or71_h_u_cla12_or70_y0
1 1
.names h_u_cla12_and613_y0 h_u_cla12_or71_h_u_cla12_and613_y0
1 1
.subckt or_gate _a=h_u_cla12_or71_h_u_cla12_or70_y0 _b=h_u_cla12_or71_h_u_cla12_and613_y0 _y0=h_u_cla12_or71_y0
.names h_u_cla12_or71_y0 h_u_cla12_or72_h_u_cla12_or71_y0
1 1
.names h_u_cla12_and624_y0 h_u_cla12_or72_h_u_cla12_and624_y0
1 1
.subckt or_gate _a=h_u_cla12_or72_h_u_cla12_or71_y0 _b=h_u_cla12_or72_h_u_cla12_and624_y0 _y0=h_u_cla12_or72_y0
.names h_u_cla12_or72_y0 h_u_cla12_or73_h_u_cla12_or72_y0
1 1
.names h_u_cla12_and633_y0 h_u_cla12_or73_h_u_cla12_and633_y0
1 1
.subckt or_gate _a=h_u_cla12_or73_h_u_cla12_or72_y0 _b=h_u_cla12_or73_h_u_cla12_and633_y0 _y0=h_u_cla12_or73_y0
.names h_u_cla12_or73_y0 h_u_cla12_or74_h_u_cla12_or73_y0
1 1
.names h_u_cla12_and640_y0 h_u_cla12_or74_h_u_cla12_and640_y0
1 1
.subckt or_gate _a=h_u_cla12_or74_h_u_cla12_or73_y0 _b=h_u_cla12_or74_h_u_cla12_and640_y0 _y0=h_u_cla12_or74_y0
.names h_u_cla12_or74_y0 h_u_cla12_or75_h_u_cla12_or74_y0
1 1
.names h_u_cla12_and645_y0 h_u_cla12_or75_h_u_cla12_and645_y0
1 1
.subckt or_gate _a=h_u_cla12_or75_h_u_cla12_or74_y0 _b=h_u_cla12_or75_h_u_cla12_and645_y0 _y0=h_u_cla12_or75_y0
.names h_u_cla12_or75_y0 h_u_cla12_or76_h_u_cla12_or75_y0
1 1
.names h_u_cla12_and648_y0 h_u_cla12_or76_h_u_cla12_and648_y0
1 1
.subckt or_gate _a=h_u_cla12_or76_h_u_cla12_or75_y0 _b=h_u_cla12_or76_h_u_cla12_and648_y0 _y0=h_u_cla12_or76_y0
.names h_u_cla12_pg_logic11_y1 h_u_cla12_or77_h_u_cla12_pg_logic11_y1
1 1
.names h_u_cla12_or76_y0 h_u_cla12_or77_h_u_cla12_or76_y0
1 1
.subckt or_gate _a=h_u_cla12_or77_h_u_cla12_pg_logic11_y1 _b=h_u_cla12_or77_h_u_cla12_or76_y0 _y0=h_u_cla12_or77_y0
.names h_u_cla12_xor0_y0 out[0]
1 1
.names h_u_cla12_xor1_y0 out[1]
1 1
.names h_u_cla12_xor2_y0 out[2]
1 1
.names h_u_cla12_xor3_y0 out[3]
1 1
.names h_u_cla12_xor4_y0 out[4]
1 1
.names h_u_cla12_xor5_y0 out[5]
1 1
.names h_u_cla12_xor6_y0 out[6]
1 1
.names h_u_cla12_xor7_y0 out[7]
1 1
.names h_u_cla12_xor8_y0 out[8]
1 1
.names h_u_cla12_xor9_y0 out[9]
1 1
.names h_u_cla12_xor10_y0 out[10]
1 1
.names h_u_cla12_xor11_y0 out[11]
1 1
.names h_u_cla12_or77_y0 out[12]
1 1
.end

.model pg_logic
.inputs a b
.outputs pg_logic_y0 pg_logic_y1 pg_logic_y2
.names a pg_logic_a
1 1
.names b pg_logic_b
1 1
.subckt or_gate _a=pg_logic_a _b=pg_logic_b _y0=pg_logic_y0
.subckt and_gate _a=pg_logic_a _b=pg_logic_b _y0=pg_logic_y1
.subckt xor_gate _a=pg_logic_a _b=pg_logic_b _y0=pg_logic_y2
.end

.model constant_wire_value_0
.inputs a b
.outputs constant_wire_0
.names a constant_wire_value_0_a
1 1
.names b constant_wire_value_0_b
1 1
.subckt xor_gate _a=constant_wire_value_0_a _b=constant_wire_value_0_b _y0=constant_wire_value_0_y0
.subckt xnor_gate _a=constant_wire_value_0_a _b=constant_wire_value_0_b _y0=constant_wire_value_0_y1
.subckt nor_gate _a=constant_wire_value_0_y0 _b=constant_wire_value_0_y1 _y0=constant_wire_0
.end

.model and_gate
.inputs _a _b
.outputs _y0
.names _a _b _y0
11 1
.end

.model or_gate
.inputs _a _b
.outputs _y0
.names _a _b _y0
1- 1
-1 1
.end

.model nor_gate
.inputs _a _b
.outputs _y0
.names _a _b _y0
00 1
.end

.model xnor_gate
.inputs _a _b
.outputs _y0
.names _a _b _y0
00 1
11 1
.end

.model xor_gate
.inputs _a _b
.outputs _y0
.names _a _b _y0
01 1
10 1
.end