.model f_u_cla32
.inputs a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] a[8] a[9] a[10] a[11] a[12] a[13] a[14] a[15] a[16] a[17] a[18] a[19] a[20] a[21] a[22] a[23] a[24] a[25] a[26] a[27] a[28] a[29] a[30] a[31] b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9] b[10] b[11] b[12] b[13] b[14] b[15] b[16] b[17] b[18] b[19] b[20] b[21] b[22] b[23] b[24] b[25] b[26] b[27] b[28] b[29] b[30] b[31]
.outputs f_u_cla32_out[0] f_u_cla32_out[1] f_u_cla32_out[2] f_u_cla32_out[3] f_u_cla32_out[4] f_u_cla32_out[5] f_u_cla32_out[6] f_u_cla32_out[7] f_u_cla32_out[8] f_u_cla32_out[9] f_u_cla32_out[10] f_u_cla32_out[11] f_u_cla32_out[12] f_u_cla32_out[13] f_u_cla32_out[14] f_u_cla32_out[15] f_u_cla32_out[16] f_u_cla32_out[17] f_u_cla32_out[18] f_u_cla32_out[19] f_u_cla32_out[20] f_u_cla32_out[21] f_u_cla32_out[22] f_u_cla32_out[23] f_u_cla32_out[24] f_u_cla32_out[25] f_u_cla32_out[26] f_u_cla32_out[27] f_u_cla32_out[28] f_u_cla32_out[29] f_u_cla32_out[30] f_u_cla32_out[31] f_u_cla32_out[32]
.names vdd
1
.names gnd
0
.names a[0] b[0] f_u_cla32_pg_logic0_or0
1- 1
-1 1
.names a[0] b[0] f_u_cla32_pg_logic0_and0
11 1
.names a[0] b[0] f_u_cla32_pg_logic0_xor0
01 1
10 1
.names a[1] b[1] f_u_cla32_pg_logic1_or0
1- 1
-1 1
.names a[1] b[1] f_u_cla32_pg_logic1_and0
11 1
.names a[1] b[1] f_u_cla32_pg_logic1_xor0
01 1
10 1
.names f_u_cla32_pg_logic1_xor0 f_u_cla32_pg_logic0_and0 f_u_cla32_xor1
01 1
10 1
.names f_u_cla32_pg_logic0_and0 f_u_cla32_pg_logic1_or0 f_u_cla32_and0
11 1
.names f_u_cla32_pg_logic1_and0 f_u_cla32_and0 f_u_cla32_or0
1- 1
-1 1
.names a[2] b[2] f_u_cla32_pg_logic2_or0
1- 1
-1 1
.names a[2] b[2] f_u_cla32_pg_logic2_and0
11 1
.names a[2] b[2] f_u_cla32_pg_logic2_xor0
01 1
10 1
.names f_u_cla32_pg_logic2_xor0 f_u_cla32_or0 f_u_cla32_xor2
01 1
10 1
.names f_u_cla32_pg_logic2_or0 f_u_cla32_pg_logic0_or0 f_u_cla32_and1
11 1
.names f_u_cla32_pg_logic0_and0 f_u_cla32_pg_logic2_or0 f_u_cla32_and2
11 1
.names f_u_cla32_and2 f_u_cla32_pg_logic1_or0 f_u_cla32_and3
11 1
.names f_u_cla32_pg_logic1_and0 f_u_cla32_pg_logic2_or0 f_u_cla32_and4
11 1
.names f_u_cla32_and3 f_u_cla32_and4 f_u_cla32_or1
1- 1
-1 1
.names f_u_cla32_pg_logic2_and0 f_u_cla32_or1 f_u_cla32_or2
1- 1
-1 1
.names a[3] b[3] f_u_cla32_pg_logic3_or0
1- 1
-1 1
.names a[3] b[3] f_u_cla32_pg_logic3_and0
11 1
.names a[3] b[3] f_u_cla32_pg_logic3_xor0
01 1
10 1
.names f_u_cla32_pg_logic3_xor0 f_u_cla32_or2 f_u_cla32_xor3
01 1
10 1
.names f_u_cla32_pg_logic3_or0 f_u_cla32_pg_logic1_or0 f_u_cla32_and5
11 1
.names f_u_cla32_pg_logic0_and0 f_u_cla32_pg_logic2_or0 f_u_cla32_and6
11 1
.names f_u_cla32_pg_logic3_or0 f_u_cla32_pg_logic1_or0 f_u_cla32_and7
11 1
.names f_u_cla32_and6 f_u_cla32_and7 f_u_cla32_and8
11 1
.names f_u_cla32_pg_logic1_and0 f_u_cla32_pg_logic3_or0 f_u_cla32_and9
11 1
.names f_u_cla32_and9 f_u_cla32_pg_logic2_or0 f_u_cla32_and10
11 1
.names f_u_cla32_pg_logic2_and0 f_u_cla32_pg_logic3_or0 f_u_cla32_and11
11 1
.names f_u_cla32_and8 f_u_cla32_and11 f_u_cla32_or3
1- 1
-1 1
.names f_u_cla32_and10 f_u_cla32_or3 f_u_cla32_or4
1- 1
-1 1
.names f_u_cla32_pg_logic3_and0 f_u_cla32_or4 f_u_cla32_or5
1- 1
-1 1
.names a[4] b[4] f_u_cla32_pg_logic4_or0
1- 1
-1 1
.names a[4] b[4] f_u_cla32_pg_logic4_and0
11 1
.names a[4] b[4] f_u_cla32_pg_logic4_xor0
01 1
10 1
.names f_u_cla32_pg_logic4_xor0 f_u_cla32_or5 f_u_cla32_xor4
01 1
10 1
.names f_u_cla32_or5 f_u_cla32_pg_logic4_or0 f_u_cla32_and12
11 1
.names f_u_cla32_pg_logic4_and0 f_u_cla32_and12 f_u_cla32_or6
1- 1
-1 1
.names a[5] b[5] f_u_cla32_pg_logic5_or0
1- 1
-1 1
.names a[5] b[5] f_u_cla32_pg_logic5_and0
11 1
.names a[5] b[5] f_u_cla32_pg_logic5_xor0
01 1
10 1
.names f_u_cla32_pg_logic5_xor0 f_u_cla32_or6 f_u_cla32_xor5
01 1
10 1
.names f_u_cla32_or5 f_u_cla32_pg_logic5_or0 f_u_cla32_and13
11 1
.names f_u_cla32_and13 f_u_cla32_pg_logic4_or0 f_u_cla32_and14
11 1
.names f_u_cla32_pg_logic4_and0 f_u_cla32_pg_logic5_or0 f_u_cla32_and15
11 1
.names f_u_cla32_and14 f_u_cla32_and15 f_u_cla32_or7
1- 1
-1 1
.names f_u_cla32_pg_logic5_and0 f_u_cla32_or7 f_u_cla32_or8
1- 1
-1 1
.names a[6] b[6] f_u_cla32_pg_logic6_or0
1- 1
-1 1
.names a[6] b[6] f_u_cla32_pg_logic6_and0
11 1
.names a[6] b[6] f_u_cla32_pg_logic6_xor0
01 1
10 1
.names f_u_cla32_pg_logic6_xor0 f_u_cla32_or8 f_u_cla32_xor6
01 1
10 1
.names f_u_cla32_or5 f_u_cla32_pg_logic5_or0 f_u_cla32_and16
11 1
.names f_u_cla32_pg_logic6_or0 f_u_cla32_pg_logic4_or0 f_u_cla32_and17
11 1
.names f_u_cla32_and16 f_u_cla32_and17 f_u_cla32_and18
11 1
.names f_u_cla32_pg_logic4_and0 f_u_cla32_pg_logic6_or0 f_u_cla32_and19
11 1
.names f_u_cla32_and19 f_u_cla32_pg_logic5_or0 f_u_cla32_and20
11 1
.names f_u_cla32_pg_logic5_and0 f_u_cla32_pg_logic6_or0 f_u_cla32_and21
11 1
.names f_u_cla32_and18 f_u_cla32_and20 f_u_cla32_or9
1- 1
-1 1
.names f_u_cla32_or9 f_u_cla32_and21 f_u_cla32_or10
1- 1
-1 1
.names f_u_cla32_pg_logic6_and0 f_u_cla32_or10 f_u_cla32_or11
1- 1
-1 1
.names a[7] b[7] f_u_cla32_pg_logic7_or0
1- 1
-1 1
.names a[7] b[7] f_u_cla32_pg_logic7_and0
11 1
.names a[7] b[7] f_u_cla32_pg_logic7_xor0
01 1
10 1
.names f_u_cla32_pg_logic7_xor0 f_u_cla32_or11 f_u_cla32_xor7
01 1
10 1
.names f_u_cla32_or5 f_u_cla32_pg_logic6_or0 f_u_cla32_and22
11 1
.names f_u_cla32_pg_logic7_or0 f_u_cla32_pg_logic5_or0 f_u_cla32_and23
11 1
.names f_u_cla32_and22 f_u_cla32_and23 f_u_cla32_and24
11 1
.names f_u_cla32_and24 f_u_cla32_pg_logic4_or0 f_u_cla32_and25
11 1
.names f_u_cla32_pg_logic4_and0 f_u_cla32_pg_logic6_or0 f_u_cla32_and26
11 1
.names f_u_cla32_pg_logic7_or0 f_u_cla32_pg_logic5_or0 f_u_cla32_and27
11 1
.names f_u_cla32_and26 f_u_cla32_and27 f_u_cla32_and28
11 1
.names f_u_cla32_pg_logic5_and0 f_u_cla32_pg_logic7_or0 f_u_cla32_and29
11 1
.names f_u_cla32_and29 f_u_cla32_pg_logic6_or0 f_u_cla32_and30
11 1
.names f_u_cla32_pg_logic6_and0 f_u_cla32_pg_logic7_or0 f_u_cla32_and31
11 1
.names f_u_cla32_and25 f_u_cla32_and30 f_u_cla32_or12
1- 1
-1 1
.names f_u_cla32_and28 f_u_cla32_and31 f_u_cla32_or13
1- 1
-1 1
.names f_u_cla32_or12 f_u_cla32_or13 f_u_cla32_or14
1- 1
-1 1
.names f_u_cla32_pg_logic7_and0 f_u_cla32_or14 f_u_cla32_or15
1- 1
-1 1
.names a[8] b[8] f_u_cla32_pg_logic8_or0
1- 1
-1 1
.names a[8] b[8] f_u_cla32_pg_logic8_and0
11 1
.names a[8] b[8] f_u_cla32_pg_logic8_xor0
01 1
10 1
.names f_u_cla32_pg_logic8_xor0 f_u_cla32_or15 f_u_cla32_xor8
01 1
10 1
.names f_u_cla32_or15 f_u_cla32_pg_logic8_or0 f_u_cla32_and32
11 1
.names f_u_cla32_pg_logic8_and0 f_u_cla32_and32 f_u_cla32_or16
1- 1
-1 1
.names a[9] b[9] f_u_cla32_pg_logic9_or0
1- 1
-1 1
.names a[9] b[9] f_u_cla32_pg_logic9_and0
11 1
.names a[9] b[9] f_u_cla32_pg_logic9_xor0
01 1
10 1
.names f_u_cla32_pg_logic9_xor0 f_u_cla32_or16 f_u_cla32_xor9
01 1
10 1
.names f_u_cla32_or15 f_u_cla32_pg_logic9_or0 f_u_cla32_and33
11 1
.names f_u_cla32_and33 f_u_cla32_pg_logic8_or0 f_u_cla32_and34
11 1
.names f_u_cla32_pg_logic8_and0 f_u_cla32_pg_logic9_or0 f_u_cla32_and35
11 1
.names f_u_cla32_and34 f_u_cla32_and35 f_u_cla32_or17
1- 1
-1 1
.names f_u_cla32_pg_logic9_and0 f_u_cla32_or17 f_u_cla32_or18
1- 1
-1 1
.names a[10] b[10] f_u_cla32_pg_logic10_or0
1- 1
-1 1
.names a[10] b[10] f_u_cla32_pg_logic10_and0
11 1
.names a[10] b[10] f_u_cla32_pg_logic10_xor0
01 1
10 1
.names f_u_cla32_pg_logic10_xor0 f_u_cla32_or18 f_u_cla32_xor10
01 1
10 1
.names f_u_cla32_or15 f_u_cla32_pg_logic9_or0 f_u_cla32_and36
11 1
.names f_u_cla32_pg_logic10_or0 f_u_cla32_pg_logic8_or0 f_u_cla32_and37
11 1
.names f_u_cla32_and36 f_u_cla32_and37 f_u_cla32_and38
11 1
.names f_u_cla32_pg_logic8_and0 f_u_cla32_pg_logic10_or0 f_u_cla32_and39
11 1
.names f_u_cla32_and39 f_u_cla32_pg_logic9_or0 f_u_cla32_and40
11 1
.names f_u_cla32_pg_logic9_and0 f_u_cla32_pg_logic10_or0 f_u_cla32_and41
11 1
.names f_u_cla32_and38 f_u_cla32_and40 f_u_cla32_or19
1- 1
-1 1
.names f_u_cla32_or19 f_u_cla32_and41 f_u_cla32_or20
1- 1
-1 1
.names f_u_cla32_pg_logic10_and0 f_u_cla32_or20 f_u_cla32_or21
1- 1
-1 1
.names a[11] b[11] f_u_cla32_pg_logic11_or0
1- 1
-1 1
.names a[11] b[11] f_u_cla32_pg_logic11_and0
11 1
.names a[11] b[11] f_u_cla32_pg_logic11_xor0
01 1
10 1
.names f_u_cla32_pg_logic11_xor0 f_u_cla32_or21 f_u_cla32_xor11
01 1
10 1
.names f_u_cla32_or15 f_u_cla32_pg_logic10_or0 f_u_cla32_and42
11 1
.names f_u_cla32_pg_logic11_or0 f_u_cla32_pg_logic9_or0 f_u_cla32_and43
11 1
.names f_u_cla32_and42 f_u_cla32_and43 f_u_cla32_and44
11 1
.names f_u_cla32_and44 f_u_cla32_pg_logic8_or0 f_u_cla32_and45
11 1
.names f_u_cla32_pg_logic8_and0 f_u_cla32_pg_logic10_or0 f_u_cla32_and46
11 1
.names f_u_cla32_pg_logic11_or0 f_u_cla32_pg_logic9_or0 f_u_cla32_and47
11 1
.names f_u_cla32_and46 f_u_cla32_and47 f_u_cla32_and48
11 1
.names f_u_cla32_pg_logic9_and0 f_u_cla32_pg_logic11_or0 f_u_cla32_and49
11 1
.names f_u_cla32_and49 f_u_cla32_pg_logic10_or0 f_u_cla32_and50
11 1
.names f_u_cla32_pg_logic10_and0 f_u_cla32_pg_logic11_or0 f_u_cla32_and51
11 1
.names f_u_cla32_and45 f_u_cla32_and50 f_u_cla32_or22
1- 1
-1 1
.names f_u_cla32_and48 f_u_cla32_and51 f_u_cla32_or23
1- 1
-1 1
.names f_u_cla32_or22 f_u_cla32_or23 f_u_cla32_or24
1- 1
-1 1
.names f_u_cla32_pg_logic11_and0 f_u_cla32_or24 f_u_cla32_or25
1- 1
-1 1
.names a[12] b[12] f_u_cla32_pg_logic12_or0
1- 1
-1 1
.names a[12] b[12] f_u_cla32_pg_logic12_and0
11 1
.names a[12] b[12] f_u_cla32_pg_logic12_xor0
01 1
10 1
.names f_u_cla32_pg_logic12_xor0 f_u_cla32_or25 f_u_cla32_xor12
01 1
10 1
.names f_u_cla32_or25 f_u_cla32_pg_logic12_or0 f_u_cla32_and52
11 1
.names f_u_cla32_pg_logic12_and0 f_u_cla32_and52 f_u_cla32_or26
1- 1
-1 1
.names a[13] b[13] f_u_cla32_pg_logic13_or0
1- 1
-1 1
.names a[13] b[13] f_u_cla32_pg_logic13_and0
11 1
.names a[13] b[13] f_u_cla32_pg_logic13_xor0
01 1
10 1
.names f_u_cla32_pg_logic13_xor0 f_u_cla32_or26 f_u_cla32_xor13
01 1
10 1
.names f_u_cla32_or25 f_u_cla32_pg_logic13_or0 f_u_cla32_and53
11 1
.names f_u_cla32_and53 f_u_cla32_pg_logic12_or0 f_u_cla32_and54
11 1
.names f_u_cla32_pg_logic12_and0 f_u_cla32_pg_logic13_or0 f_u_cla32_and55
11 1
.names f_u_cla32_and54 f_u_cla32_and55 f_u_cla32_or27
1- 1
-1 1
.names f_u_cla32_pg_logic13_and0 f_u_cla32_or27 f_u_cla32_or28
1- 1
-1 1
.names a[14] b[14] f_u_cla32_pg_logic14_or0
1- 1
-1 1
.names a[14] b[14] f_u_cla32_pg_logic14_and0
11 1
.names a[14] b[14] f_u_cla32_pg_logic14_xor0
01 1
10 1
.names f_u_cla32_pg_logic14_xor0 f_u_cla32_or28 f_u_cla32_xor14
01 1
10 1
.names f_u_cla32_or25 f_u_cla32_pg_logic13_or0 f_u_cla32_and56
11 1
.names f_u_cla32_pg_logic14_or0 f_u_cla32_pg_logic12_or0 f_u_cla32_and57
11 1
.names f_u_cla32_and56 f_u_cla32_and57 f_u_cla32_and58
11 1
.names f_u_cla32_pg_logic12_and0 f_u_cla32_pg_logic14_or0 f_u_cla32_and59
11 1
.names f_u_cla32_and59 f_u_cla32_pg_logic13_or0 f_u_cla32_and60
11 1
.names f_u_cla32_pg_logic13_and0 f_u_cla32_pg_logic14_or0 f_u_cla32_and61
11 1
.names f_u_cla32_and58 f_u_cla32_and60 f_u_cla32_or29
1- 1
-1 1
.names f_u_cla32_or29 f_u_cla32_and61 f_u_cla32_or30
1- 1
-1 1
.names f_u_cla32_pg_logic14_and0 f_u_cla32_or30 f_u_cla32_or31
1- 1
-1 1
.names a[15] b[15] f_u_cla32_pg_logic15_or0
1- 1
-1 1
.names a[15] b[15] f_u_cla32_pg_logic15_and0
11 1
.names a[15] b[15] f_u_cla32_pg_logic15_xor0
01 1
10 1
.names f_u_cla32_pg_logic15_xor0 f_u_cla32_or31 f_u_cla32_xor15
01 1
10 1
.names f_u_cla32_or25 f_u_cla32_pg_logic14_or0 f_u_cla32_and62
11 1
.names f_u_cla32_pg_logic15_or0 f_u_cla32_pg_logic13_or0 f_u_cla32_and63
11 1
.names f_u_cla32_and62 f_u_cla32_and63 f_u_cla32_and64
11 1
.names f_u_cla32_and64 f_u_cla32_pg_logic12_or0 f_u_cla32_and65
11 1
.names f_u_cla32_pg_logic12_and0 f_u_cla32_pg_logic14_or0 f_u_cla32_and66
11 1
.names f_u_cla32_pg_logic15_or0 f_u_cla32_pg_logic13_or0 f_u_cla32_and67
11 1
.names f_u_cla32_and66 f_u_cla32_and67 f_u_cla32_and68
11 1
.names f_u_cla32_pg_logic13_and0 f_u_cla32_pg_logic15_or0 f_u_cla32_and69
11 1
.names f_u_cla32_and69 f_u_cla32_pg_logic14_or0 f_u_cla32_and70
11 1
.names f_u_cla32_pg_logic14_and0 f_u_cla32_pg_logic15_or0 f_u_cla32_and71
11 1
.names f_u_cla32_and65 f_u_cla32_and70 f_u_cla32_or32
1- 1
-1 1
.names f_u_cla32_and68 f_u_cla32_and71 f_u_cla32_or33
1- 1
-1 1
.names f_u_cla32_or32 f_u_cla32_or33 f_u_cla32_or34
1- 1
-1 1
.names f_u_cla32_pg_logic15_and0 f_u_cla32_or34 f_u_cla32_or35
1- 1
-1 1
.names a[16] b[16] f_u_cla32_pg_logic16_or0
1- 1
-1 1
.names a[16] b[16] f_u_cla32_pg_logic16_and0
11 1
.names a[16] b[16] f_u_cla32_pg_logic16_xor0
01 1
10 1
.names f_u_cla32_pg_logic16_xor0 f_u_cla32_or35 f_u_cla32_xor16
01 1
10 1
.names f_u_cla32_or35 f_u_cla32_pg_logic16_or0 f_u_cla32_and72
11 1
.names f_u_cla32_pg_logic16_and0 f_u_cla32_and72 f_u_cla32_or36
1- 1
-1 1
.names a[17] b[17] f_u_cla32_pg_logic17_or0
1- 1
-1 1
.names a[17] b[17] f_u_cla32_pg_logic17_and0
11 1
.names a[17] b[17] f_u_cla32_pg_logic17_xor0
01 1
10 1
.names f_u_cla32_pg_logic17_xor0 f_u_cla32_or36 f_u_cla32_xor17
01 1
10 1
.names f_u_cla32_or35 f_u_cla32_pg_logic17_or0 f_u_cla32_and73
11 1
.names f_u_cla32_and73 f_u_cla32_pg_logic16_or0 f_u_cla32_and74
11 1
.names f_u_cla32_pg_logic16_and0 f_u_cla32_pg_logic17_or0 f_u_cla32_and75
11 1
.names f_u_cla32_and74 f_u_cla32_and75 f_u_cla32_or37
1- 1
-1 1
.names f_u_cla32_pg_logic17_and0 f_u_cla32_or37 f_u_cla32_or38
1- 1
-1 1
.names a[18] b[18] f_u_cla32_pg_logic18_or0
1- 1
-1 1
.names a[18] b[18] f_u_cla32_pg_logic18_and0
11 1
.names a[18] b[18] f_u_cla32_pg_logic18_xor0
01 1
10 1
.names f_u_cla32_pg_logic18_xor0 f_u_cla32_or38 f_u_cla32_xor18
01 1
10 1
.names f_u_cla32_or35 f_u_cla32_pg_logic17_or0 f_u_cla32_and76
11 1
.names f_u_cla32_pg_logic18_or0 f_u_cla32_pg_logic16_or0 f_u_cla32_and77
11 1
.names f_u_cla32_and76 f_u_cla32_and77 f_u_cla32_and78
11 1
.names f_u_cla32_pg_logic16_and0 f_u_cla32_pg_logic18_or0 f_u_cla32_and79
11 1
.names f_u_cla32_and79 f_u_cla32_pg_logic17_or0 f_u_cla32_and80
11 1
.names f_u_cla32_pg_logic17_and0 f_u_cla32_pg_logic18_or0 f_u_cla32_and81
11 1
.names f_u_cla32_and78 f_u_cla32_and80 f_u_cla32_or39
1- 1
-1 1
.names f_u_cla32_or39 f_u_cla32_and81 f_u_cla32_or40
1- 1
-1 1
.names f_u_cla32_pg_logic18_and0 f_u_cla32_or40 f_u_cla32_or41
1- 1
-1 1
.names a[19] b[19] f_u_cla32_pg_logic19_or0
1- 1
-1 1
.names a[19] b[19] f_u_cla32_pg_logic19_and0
11 1
.names a[19] b[19] f_u_cla32_pg_logic19_xor0
01 1
10 1
.names f_u_cla32_pg_logic19_xor0 f_u_cla32_or41 f_u_cla32_xor19
01 1
10 1
.names f_u_cla32_or35 f_u_cla32_pg_logic18_or0 f_u_cla32_and82
11 1
.names f_u_cla32_pg_logic19_or0 f_u_cla32_pg_logic17_or0 f_u_cla32_and83
11 1
.names f_u_cla32_and82 f_u_cla32_and83 f_u_cla32_and84
11 1
.names f_u_cla32_and84 f_u_cla32_pg_logic16_or0 f_u_cla32_and85
11 1
.names f_u_cla32_pg_logic16_and0 f_u_cla32_pg_logic18_or0 f_u_cla32_and86
11 1
.names f_u_cla32_pg_logic19_or0 f_u_cla32_pg_logic17_or0 f_u_cla32_and87
11 1
.names f_u_cla32_and86 f_u_cla32_and87 f_u_cla32_and88
11 1
.names f_u_cla32_pg_logic17_and0 f_u_cla32_pg_logic19_or0 f_u_cla32_and89
11 1
.names f_u_cla32_and89 f_u_cla32_pg_logic18_or0 f_u_cla32_and90
11 1
.names f_u_cla32_pg_logic18_and0 f_u_cla32_pg_logic19_or0 f_u_cla32_and91
11 1
.names f_u_cla32_and85 f_u_cla32_and90 f_u_cla32_or42
1- 1
-1 1
.names f_u_cla32_and88 f_u_cla32_and91 f_u_cla32_or43
1- 1
-1 1
.names f_u_cla32_or42 f_u_cla32_or43 f_u_cla32_or44
1- 1
-1 1
.names f_u_cla32_pg_logic19_and0 f_u_cla32_or44 f_u_cla32_or45
1- 1
-1 1
.names a[20] b[20] f_u_cla32_pg_logic20_or0
1- 1
-1 1
.names a[20] b[20] f_u_cla32_pg_logic20_and0
11 1
.names a[20] b[20] f_u_cla32_pg_logic20_xor0
01 1
10 1
.names f_u_cla32_pg_logic20_xor0 f_u_cla32_or45 f_u_cla32_xor20
01 1
10 1
.names f_u_cla32_or45 f_u_cla32_pg_logic20_or0 f_u_cla32_and92
11 1
.names f_u_cla32_pg_logic20_and0 f_u_cla32_and92 f_u_cla32_or46
1- 1
-1 1
.names a[21] b[21] f_u_cla32_pg_logic21_or0
1- 1
-1 1
.names a[21] b[21] f_u_cla32_pg_logic21_and0
11 1
.names a[21] b[21] f_u_cla32_pg_logic21_xor0
01 1
10 1
.names f_u_cla32_pg_logic21_xor0 f_u_cla32_or46 f_u_cla32_xor21
01 1
10 1
.names f_u_cla32_or45 f_u_cla32_pg_logic21_or0 f_u_cla32_and93
11 1
.names f_u_cla32_and93 f_u_cla32_pg_logic20_or0 f_u_cla32_and94
11 1
.names f_u_cla32_pg_logic20_and0 f_u_cla32_pg_logic21_or0 f_u_cla32_and95
11 1
.names f_u_cla32_and94 f_u_cla32_and95 f_u_cla32_or47
1- 1
-1 1
.names f_u_cla32_pg_logic21_and0 f_u_cla32_or47 f_u_cla32_or48
1- 1
-1 1
.names a[22] b[22] f_u_cla32_pg_logic22_or0
1- 1
-1 1
.names a[22] b[22] f_u_cla32_pg_logic22_and0
11 1
.names a[22] b[22] f_u_cla32_pg_logic22_xor0
01 1
10 1
.names f_u_cla32_pg_logic22_xor0 f_u_cla32_or48 f_u_cla32_xor22
01 1
10 1
.names f_u_cla32_or45 f_u_cla32_pg_logic21_or0 f_u_cla32_and96
11 1
.names f_u_cla32_pg_logic22_or0 f_u_cla32_pg_logic20_or0 f_u_cla32_and97
11 1
.names f_u_cla32_and96 f_u_cla32_and97 f_u_cla32_and98
11 1
.names f_u_cla32_pg_logic20_and0 f_u_cla32_pg_logic22_or0 f_u_cla32_and99
11 1
.names f_u_cla32_and99 f_u_cla32_pg_logic21_or0 f_u_cla32_and100
11 1
.names f_u_cla32_pg_logic21_and0 f_u_cla32_pg_logic22_or0 f_u_cla32_and101
11 1
.names f_u_cla32_and98 f_u_cla32_and100 f_u_cla32_or49
1- 1
-1 1
.names f_u_cla32_or49 f_u_cla32_and101 f_u_cla32_or50
1- 1
-1 1
.names f_u_cla32_pg_logic22_and0 f_u_cla32_or50 f_u_cla32_or51
1- 1
-1 1
.names a[23] b[23] f_u_cla32_pg_logic23_or0
1- 1
-1 1
.names a[23] b[23] f_u_cla32_pg_logic23_and0
11 1
.names a[23] b[23] f_u_cla32_pg_logic23_xor0
01 1
10 1
.names f_u_cla32_pg_logic23_xor0 f_u_cla32_or51 f_u_cla32_xor23
01 1
10 1
.names f_u_cla32_or45 f_u_cla32_pg_logic22_or0 f_u_cla32_and102
11 1
.names f_u_cla32_pg_logic23_or0 f_u_cla32_pg_logic21_or0 f_u_cla32_and103
11 1
.names f_u_cla32_and102 f_u_cla32_and103 f_u_cla32_and104
11 1
.names f_u_cla32_and104 f_u_cla32_pg_logic20_or0 f_u_cla32_and105
11 1
.names f_u_cla32_pg_logic20_and0 f_u_cla32_pg_logic22_or0 f_u_cla32_and106
11 1
.names f_u_cla32_pg_logic23_or0 f_u_cla32_pg_logic21_or0 f_u_cla32_and107
11 1
.names f_u_cla32_and106 f_u_cla32_and107 f_u_cla32_and108
11 1
.names f_u_cla32_pg_logic21_and0 f_u_cla32_pg_logic23_or0 f_u_cla32_and109
11 1
.names f_u_cla32_and109 f_u_cla32_pg_logic22_or0 f_u_cla32_and110
11 1
.names f_u_cla32_pg_logic22_and0 f_u_cla32_pg_logic23_or0 f_u_cla32_and111
11 1
.names f_u_cla32_and105 f_u_cla32_and110 f_u_cla32_or52
1- 1
-1 1
.names f_u_cla32_and108 f_u_cla32_and111 f_u_cla32_or53
1- 1
-1 1
.names f_u_cla32_or52 f_u_cla32_or53 f_u_cla32_or54
1- 1
-1 1
.names f_u_cla32_pg_logic23_and0 f_u_cla32_or54 f_u_cla32_or55
1- 1
-1 1
.names a[24] b[24] f_u_cla32_pg_logic24_or0
1- 1
-1 1
.names a[24] b[24] f_u_cla32_pg_logic24_and0
11 1
.names a[24] b[24] f_u_cla32_pg_logic24_xor0
01 1
10 1
.names f_u_cla32_pg_logic24_xor0 f_u_cla32_or55 f_u_cla32_xor24
01 1
10 1
.names f_u_cla32_or55 f_u_cla32_pg_logic24_or0 f_u_cla32_and112
11 1
.names f_u_cla32_pg_logic24_and0 f_u_cla32_and112 f_u_cla32_or56
1- 1
-1 1
.names a[25] b[25] f_u_cla32_pg_logic25_or0
1- 1
-1 1
.names a[25] b[25] f_u_cla32_pg_logic25_and0
11 1
.names a[25] b[25] f_u_cla32_pg_logic25_xor0
01 1
10 1
.names f_u_cla32_pg_logic25_xor0 f_u_cla32_or56 f_u_cla32_xor25
01 1
10 1
.names f_u_cla32_or55 f_u_cla32_pg_logic25_or0 f_u_cla32_and113
11 1
.names f_u_cla32_and113 f_u_cla32_pg_logic24_or0 f_u_cla32_and114
11 1
.names f_u_cla32_pg_logic24_and0 f_u_cla32_pg_logic25_or0 f_u_cla32_and115
11 1
.names f_u_cla32_and114 f_u_cla32_and115 f_u_cla32_or57
1- 1
-1 1
.names f_u_cla32_pg_logic25_and0 f_u_cla32_or57 f_u_cla32_or58
1- 1
-1 1
.names a[26] b[26] f_u_cla32_pg_logic26_or0
1- 1
-1 1
.names a[26] b[26] f_u_cla32_pg_logic26_and0
11 1
.names a[26] b[26] f_u_cla32_pg_logic26_xor0
01 1
10 1
.names f_u_cla32_pg_logic26_xor0 f_u_cla32_or58 f_u_cla32_xor26
01 1
10 1
.names f_u_cla32_or55 f_u_cla32_pg_logic25_or0 f_u_cla32_and116
11 1
.names f_u_cla32_pg_logic26_or0 f_u_cla32_pg_logic24_or0 f_u_cla32_and117
11 1
.names f_u_cla32_and116 f_u_cla32_and117 f_u_cla32_and118
11 1
.names f_u_cla32_pg_logic24_and0 f_u_cla32_pg_logic26_or0 f_u_cla32_and119
11 1
.names f_u_cla32_and119 f_u_cla32_pg_logic25_or0 f_u_cla32_and120
11 1
.names f_u_cla32_pg_logic25_and0 f_u_cla32_pg_logic26_or0 f_u_cla32_and121
11 1
.names f_u_cla32_and118 f_u_cla32_and120 f_u_cla32_or59
1- 1
-1 1
.names f_u_cla32_or59 f_u_cla32_and121 f_u_cla32_or60
1- 1
-1 1
.names f_u_cla32_pg_logic26_and0 f_u_cla32_or60 f_u_cla32_or61
1- 1
-1 1
.names a[27] b[27] f_u_cla32_pg_logic27_or0
1- 1
-1 1
.names a[27] b[27] f_u_cla32_pg_logic27_and0
11 1
.names a[27] b[27] f_u_cla32_pg_logic27_xor0
01 1
10 1
.names f_u_cla32_pg_logic27_xor0 f_u_cla32_or61 f_u_cla32_xor27
01 1
10 1
.names f_u_cla32_or55 f_u_cla32_pg_logic26_or0 f_u_cla32_and122
11 1
.names f_u_cla32_pg_logic27_or0 f_u_cla32_pg_logic25_or0 f_u_cla32_and123
11 1
.names f_u_cla32_and122 f_u_cla32_and123 f_u_cla32_and124
11 1
.names f_u_cla32_and124 f_u_cla32_pg_logic24_or0 f_u_cla32_and125
11 1
.names f_u_cla32_pg_logic24_and0 f_u_cla32_pg_logic26_or0 f_u_cla32_and126
11 1
.names f_u_cla32_pg_logic27_or0 f_u_cla32_pg_logic25_or0 f_u_cla32_and127
11 1
.names f_u_cla32_and126 f_u_cla32_and127 f_u_cla32_and128
11 1
.names f_u_cla32_pg_logic25_and0 f_u_cla32_pg_logic27_or0 f_u_cla32_and129
11 1
.names f_u_cla32_and129 f_u_cla32_pg_logic26_or0 f_u_cla32_and130
11 1
.names f_u_cla32_pg_logic26_and0 f_u_cla32_pg_logic27_or0 f_u_cla32_and131
11 1
.names f_u_cla32_and125 f_u_cla32_and130 f_u_cla32_or62
1- 1
-1 1
.names f_u_cla32_and128 f_u_cla32_and131 f_u_cla32_or63
1- 1
-1 1
.names f_u_cla32_or62 f_u_cla32_or63 f_u_cla32_or64
1- 1
-1 1
.names f_u_cla32_pg_logic27_and0 f_u_cla32_or64 f_u_cla32_or65
1- 1
-1 1
.names a[28] b[28] f_u_cla32_pg_logic28_or0
1- 1
-1 1
.names a[28] b[28] f_u_cla32_pg_logic28_and0
11 1
.names a[28] b[28] f_u_cla32_pg_logic28_xor0
01 1
10 1
.names f_u_cla32_pg_logic28_xor0 f_u_cla32_or65 f_u_cla32_xor28
01 1
10 1
.names f_u_cla32_or65 f_u_cla32_pg_logic28_or0 f_u_cla32_and132
11 1
.names f_u_cla32_pg_logic28_and0 f_u_cla32_and132 f_u_cla32_or66
1- 1
-1 1
.names a[29] b[29] f_u_cla32_pg_logic29_or0
1- 1
-1 1
.names a[29] b[29] f_u_cla32_pg_logic29_and0
11 1
.names a[29] b[29] f_u_cla32_pg_logic29_xor0
01 1
10 1
.names f_u_cla32_pg_logic29_xor0 f_u_cla32_or66 f_u_cla32_xor29
01 1
10 1
.names f_u_cla32_or65 f_u_cla32_pg_logic29_or0 f_u_cla32_and133
11 1
.names f_u_cla32_and133 f_u_cla32_pg_logic28_or0 f_u_cla32_and134
11 1
.names f_u_cla32_pg_logic28_and0 f_u_cla32_pg_logic29_or0 f_u_cla32_and135
11 1
.names f_u_cla32_and134 f_u_cla32_and135 f_u_cla32_or67
1- 1
-1 1
.names f_u_cla32_pg_logic29_and0 f_u_cla32_or67 f_u_cla32_or68
1- 1
-1 1
.names a[30] b[30] f_u_cla32_pg_logic30_or0
1- 1
-1 1
.names a[30] b[30] f_u_cla32_pg_logic30_and0
11 1
.names a[30] b[30] f_u_cla32_pg_logic30_xor0
01 1
10 1
.names f_u_cla32_pg_logic30_xor0 f_u_cla32_or68 f_u_cla32_xor30
01 1
10 1
.names f_u_cla32_or65 f_u_cla32_pg_logic29_or0 f_u_cla32_and136
11 1
.names f_u_cla32_pg_logic30_or0 f_u_cla32_pg_logic28_or0 f_u_cla32_and137
11 1
.names f_u_cla32_and136 f_u_cla32_and137 f_u_cla32_and138
11 1
.names f_u_cla32_pg_logic28_and0 f_u_cla32_pg_logic30_or0 f_u_cla32_and139
11 1
.names f_u_cla32_and139 f_u_cla32_pg_logic29_or0 f_u_cla32_and140
11 1
.names f_u_cla32_pg_logic29_and0 f_u_cla32_pg_logic30_or0 f_u_cla32_and141
11 1
.names f_u_cla32_and138 f_u_cla32_and140 f_u_cla32_or69
1- 1
-1 1
.names f_u_cla32_or69 f_u_cla32_and141 f_u_cla32_or70
1- 1
-1 1
.names f_u_cla32_pg_logic30_and0 f_u_cla32_or70 f_u_cla32_or71
1- 1
-1 1
.names a[31] b[31] f_u_cla32_pg_logic31_or0
1- 1
-1 1
.names a[31] b[31] f_u_cla32_pg_logic31_and0
11 1
.names a[31] b[31] f_u_cla32_pg_logic31_xor0
01 1
10 1
.names f_u_cla32_pg_logic31_xor0 f_u_cla32_or71 f_u_cla32_xor31
01 1
10 1
.names f_u_cla32_or65 f_u_cla32_pg_logic30_or0 f_u_cla32_and142
11 1
.names f_u_cla32_pg_logic31_or0 f_u_cla32_pg_logic29_or0 f_u_cla32_and143
11 1
.names f_u_cla32_and142 f_u_cla32_and143 f_u_cla32_and144
11 1
.names f_u_cla32_and144 f_u_cla32_pg_logic28_or0 f_u_cla32_and145
11 1
.names f_u_cla32_pg_logic28_and0 f_u_cla32_pg_logic30_or0 f_u_cla32_and146
11 1
.names f_u_cla32_pg_logic31_or0 f_u_cla32_pg_logic29_or0 f_u_cla32_and147
11 1
.names f_u_cla32_and146 f_u_cla32_and147 f_u_cla32_and148
11 1
.names f_u_cla32_pg_logic29_and0 f_u_cla32_pg_logic31_or0 f_u_cla32_and149
11 1
.names f_u_cla32_and149 f_u_cla32_pg_logic30_or0 f_u_cla32_and150
11 1
.names f_u_cla32_pg_logic30_and0 f_u_cla32_pg_logic31_or0 f_u_cla32_and151
11 1
.names f_u_cla32_and145 f_u_cla32_and150 f_u_cla32_or72
1- 1
-1 1
.names f_u_cla32_and148 f_u_cla32_and151 f_u_cla32_or73
1- 1
-1 1
.names f_u_cla32_or72 f_u_cla32_or73 f_u_cla32_or74
1- 1
-1 1
.names f_u_cla32_pg_logic31_and0 f_u_cla32_or74 f_u_cla32_or75
1- 1
-1 1
.names f_u_cla32_pg_logic0_xor0 f_u_cla32_out[0]
1 1
.names f_u_cla32_xor1 f_u_cla32_out[1]
1 1
.names f_u_cla32_xor2 f_u_cla32_out[2]
1 1
.names f_u_cla32_xor3 f_u_cla32_out[3]
1 1
.names f_u_cla32_xor4 f_u_cla32_out[4]
1 1
.names f_u_cla32_xor5 f_u_cla32_out[5]
1 1
.names f_u_cla32_xor6 f_u_cla32_out[6]
1 1
.names f_u_cla32_xor7 f_u_cla32_out[7]
1 1
.names f_u_cla32_xor8 f_u_cla32_out[8]
1 1
.names f_u_cla32_xor9 f_u_cla32_out[9]
1 1
.names f_u_cla32_xor10 f_u_cla32_out[10]
1 1
.names f_u_cla32_xor11 f_u_cla32_out[11]
1 1
.names f_u_cla32_xor12 f_u_cla32_out[12]
1 1
.names f_u_cla32_xor13 f_u_cla32_out[13]
1 1
.names f_u_cla32_xor14 f_u_cla32_out[14]
1 1
.names f_u_cla32_xor15 f_u_cla32_out[15]
1 1
.names f_u_cla32_xor16 f_u_cla32_out[16]
1 1
.names f_u_cla32_xor17 f_u_cla32_out[17]
1 1
.names f_u_cla32_xor18 f_u_cla32_out[18]
1 1
.names f_u_cla32_xor19 f_u_cla32_out[19]
1 1
.names f_u_cla32_xor20 f_u_cla32_out[20]
1 1
.names f_u_cla32_xor21 f_u_cla32_out[21]
1 1
.names f_u_cla32_xor22 f_u_cla32_out[22]
1 1
.names f_u_cla32_xor23 f_u_cla32_out[23]
1 1
.names f_u_cla32_xor24 f_u_cla32_out[24]
1 1
.names f_u_cla32_xor25 f_u_cla32_out[25]
1 1
.names f_u_cla32_xor26 f_u_cla32_out[26]
1 1
.names f_u_cla32_xor27 f_u_cla32_out[27]
1 1
.names f_u_cla32_xor28 f_u_cla32_out[28]
1 1
.names f_u_cla32_xor29 f_u_cla32_out[29]
1 1
.names f_u_cla32_xor30 f_u_cla32_out[30]
1 1
.names f_u_cla32_xor31 f_u_cla32_out[31]
1 1
.names f_u_cla32_or75 f_u_cla32_out[32]
1 1
.end