Module ariths_gen.core.arithmetic_circuits.arithmetic_circuit

Classes

class ArithmeticCircuit (a, b, prefix: str, name: str, out_N: int, inner_component: bool = False, one_bit_circuit: bool = False, signed: bool = False)

Class represents a general arithmetic circuit and ensures its generation to various representations.

The init method fills some mandatory attributes concerning arithmetic circuit that are later used for generation into various representations.

Expand source code

class ArithmeticCircuit(GeneralCircuit):
    """Class represents a general arithmetic circuit and ensures its generation to various representations.

    The __init__ method fills some mandatory attributes concerning arithmetic circuit
    that are later used for generation into various representations.
    """

    def __init__(self, a, b, prefix: str, name: str, out_N: int, inner_component: bool = False, one_bit_circuit: bool = False, signed: bool = False):
        super().__init__(prefix, name, out_N, inner_component, inputs=[a, b], signed=signed)
        if one_bit_circuit is False:
            if prefix == "":
                self.prefix = name
            else:
                self.prefix = prefix + "_" + name

            self.inner_component = inner_component
            if self.inner_component is True:
                self.a = Bus(prefix=f"{self.prefix}_{a.prefix}", wires_list=a.bus)
                self.b = Bus(prefix=f"{self.prefix}_{b.prefix}", wires_list=b.bus)

                if a.is_output_bus():
                    self.a.connect_bus(connecting_bus=a)
                if b.is_output_bus():
                    self.b.connect_bus(connecting_bus=b)
            else:
                self.a = Bus(prefix=f"{a.prefix}", wires_list=a.bus)
                self.b = Bus(prefix=f"{b.prefix}", wires_list=b.bus)

            # N output wires for given circuit
            self.out = Bus(self.prefix+"_out", out_N, out_bus=True, signed=self.signed)

    """ C CODE GENERATION """
    def get_prototype_c(self):
        """Generates C code function header to describe corresponding arithmetic circuit's interface in C code.

        Returns:
            str: Function's name and parameters in C code.
        """
        return f"{self.c_data_type} {self.prefix}({self.c_data_type} {self.a.prefix}, {self.c_data_type} {self.b.prefix})" + "{" + "\n"

    """ VERILOG CODE GENERATION """
    def get_prototype_v(self):
        """Generates Verilog code module header to describe corresponding arithmetic circuit's interface in Verilog code.

        Returns:
            str: Module's name and parameters in Verilog code.
        """
        return f"module {self.prefix}(input [{self.N-1}:0] {self.a.prefix}, input [{self.N-1}:0] {self.b.prefix}, output [{self.out.N-1}:0] {self.out.prefix});\n"

    """ BLIF CODE GENERATION """
    def get_declaration_blif(self):
        """Generates flat Blif code declaration of input/output circuit wires.

        Returns:
            str: Flat Blif code containing declaration of circuit's wires.
        """
        if self.N == 1:
            return f".inputs {self.a.prefix} {self.b.prefix}\n" + \
                   f".outputs{self.out.get_wire_declaration_blif()}\n" + \
                   f".names vdd\n1\n" + \
                   f".names gnd\n0\n"
        else:
            return f".inputs{self.a.get_wire_declaration_blif()}{self.b.get_wire_declaration_blif()}\n" + \
                   f".outputs{self.out.get_wire_declaration_blif()}\n" + \
                   f".names vdd\n1\n" + \
                   f".names gnd\n0\n"

Ancestors

• GeneralCircuit

Subclasses

• MultiplierCircuit
• TwoInputOneBitCircuit
• SignedCarryLookaheadAdder
• UnsignedCarryLookaheadAdder
• SignedCarrySkipAdder
• UnsignedCarrySkipAdder
• SignedPGRippleCarryAdder
• UnsignedPGRippleCarryAdder
• SignedRippleCarryAdder
• UnsignedRippleCarryAdder
• ArrayDivider

Inherited members

• GeneralCircuit:
  • add_component
  • get_blif_code_flat
  • get_blif_code_hier
  • get_c_code_flat
  • get_c_code_hier
  • get_carry_wire
  • get_cgp_code_flat
  • get_cgp_wires
  • get_circuit_blif
  • get_circuit_c
  • get_circuit_gates
  • get_circuit_v
  • get_circuit_wire_index
  • get_component_types
  • get_declaration_blif
  • get_declaration_c_flat
  • get_declaration_c_hier
  • get_declaration_v_flat
  • get_declaration_v_hier
  • get_declarations_c_hier
  • get_declarations_v_hier
  • get_function_blif_flat
  • get_function_block_blif
  • get_function_block_c
  • get_function_block_v
  • get_function_blocks_blif
  • get_function_blocks_c
  • get_function_blocks_v
  • get_function_out_blif
  • get_function_out_c_flat
  • get_function_out_c_hier
  • get_function_out_python_flat
  • get_function_out_v_flat
  • get_function_out_v_hier
  • get_includes_c
  • get_init_c_flat
  • get_init_c_hier
  • get_init_python_flat
  • get_init_v_flat
  • get_init_v_hier
  • get_instance_num
  • get_invocation_blif_hier
  • get_invocations_blif_hier
  • get_multi_bit_components
  • get_one_bit_components
  • get_out_invocation_c
  • get_out_invocation_v
  • get_outputs_cgp
  • get_parameters_cgp
  • get_previous_component
  • get_prototype_blif
  • get_prototype_c
  • get_prototype_python
  • get_prototype_v
  • get_python_code_flat
  • get_sum_wire
  • get_triplets_cgp
  • get_unique_types
  • get_v_code_flat
  • get_v_code_hier
  • save_wire_id