.model s_pg_rca12 .inputs a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] a[8] a[9] a[10] a[11] b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9] b[10] b[11] .outputs s_pg_rca12_out[0] s_pg_rca12_out[1] s_pg_rca12_out[2] s_pg_rca12_out[3] s_pg_rca12_out[4] s_pg_rca12_out[5] s_pg_rca12_out[6] s_pg_rca12_out[7] s_pg_rca12_out[8] s_pg_rca12_out[9] s_pg_rca12_out[10] s_pg_rca12_out[11] s_pg_rca12_out[12] .names vdd 1 .names gnd 0 .subckt pg_fa a=a[0] b=b[0] cin=gnd pg_fa_xor0=s_pg_rca12_pg_fa0_xor0 pg_fa_and0=s_pg_rca12_pg_fa0_and0 .subckt pg_fa a=a[1] b=b[1] cin=s_pg_rca12_pg_fa0_and0 pg_fa_xor0=s_pg_rca12_pg_fa1_xor0 pg_fa_and0=s_pg_rca12_pg_fa1_and0 pg_fa_xor1=s_pg_rca12_pg_fa1_xor1 .subckt and_gate a=s_pg_rca12_pg_fa0_and0 b=s_pg_rca12_pg_fa1_xor0 out=s_pg_rca12_and1 .subckt or_gate a=s_pg_rca12_and1 b=s_pg_rca12_pg_fa1_and0 out=s_pg_rca12_or1 .subckt pg_fa a=a[2] b=b[2] cin=s_pg_rca12_or1 pg_fa_xor0=s_pg_rca12_pg_fa2_xor0 pg_fa_and0=s_pg_rca12_pg_fa2_and0 pg_fa_xor1=s_pg_rca12_pg_fa2_xor1 .subckt and_gate a=s_pg_rca12_or1 b=s_pg_rca12_pg_fa2_xor0 out=s_pg_rca12_and2 .subckt or_gate a=s_pg_rca12_and2 b=s_pg_rca12_pg_fa2_and0 out=s_pg_rca12_or2 .subckt pg_fa a=a[3] b=b[3] cin=s_pg_rca12_or2 pg_fa_xor0=s_pg_rca12_pg_fa3_xor0 pg_fa_and0=s_pg_rca12_pg_fa3_and0 pg_fa_xor1=s_pg_rca12_pg_fa3_xor1 .subckt and_gate a=s_pg_rca12_or2 b=s_pg_rca12_pg_fa3_xor0 out=s_pg_rca12_and3 .subckt or_gate a=s_pg_rca12_and3 b=s_pg_rca12_pg_fa3_and0 out=s_pg_rca12_or3 .subckt pg_fa a=a[4] b=b[4] cin=s_pg_rca12_or3 pg_fa_xor0=s_pg_rca12_pg_fa4_xor0 pg_fa_and0=s_pg_rca12_pg_fa4_and0 pg_fa_xor1=s_pg_rca12_pg_fa4_xor1 .subckt and_gate a=s_pg_rca12_or3 b=s_pg_rca12_pg_fa4_xor0 out=s_pg_rca12_and4 .subckt or_gate a=s_pg_rca12_and4 b=s_pg_rca12_pg_fa4_and0 out=s_pg_rca12_or4 .subckt pg_fa a=a[5] b=b[5] cin=s_pg_rca12_or4 pg_fa_xor0=s_pg_rca12_pg_fa5_xor0 pg_fa_and0=s_pg_rca12_pg_fa5_and0 pg_fa_xor1=s_pg_rca12_pg_fa5_xor1 .subckt and_gate a=s_pg_rca12_or4 b=s_pg_rca12_pg_fa5_xor0 out=s_pg_rca12_and5 .subckt or_gate a=s_pg_rca12_and5 b=s_pg_rca12_pg_fa5_and0 out=s_pg_rca12_or5 .subckt pg_fa a=a[6] b=b[6] cin=s_pg_rca12_or5 pg_fa_xor0=s_pg_rca12_pg_fa6_xor0 pg_fa_and0=s_pg_rca12_pg_fa6_and0 pg_fa_xor1=s_pg_rca12_pg_fa6_xor1 .subckt and_gate a=s_pg_rca12_or5 b=s_pg_rca12_pg_fa6_xor0 out=s_pg_rca12_and6 .subckt or_gate a=s_pg_rca12_and6 b=s_pg_rca12_pg_fa6_and0 out=s_pg_rca12_or6 .subckt pg_fa a=a[7] b=b[7] cin=s_pg_rca12_or6 pg_fa_xor0=s_pg_rca12_pg_fa7_xor0 pg_fa_and0=s_pg_rca12_pg_fa7_and0 pg_fa_xor1=s_pg_rca12_pg_fa7_xor1 .subckt and_gate a=s_pg_rca12_or6 b=s_pg_rca12_pg_fa7_xor0 out=s_pg_rca12_and7 .subckt or_gate a=s_pg_rca12_and7 b=s_pg_rca12_pg_fa7_and0 out=s_pg_rca12_or7 .subckt pg_fa a=a[8] b=b[8] cin=s_pg_rca12_or7 pg_fa_xor0=s_pg_rca12_pg_fa8_xor0 pg_fa_and0=s_pg_rca12_pg_fa8_and0 pg_fa_xor1=s_pg_rca12_pg_fa8_xor1 .subckt and_gate a=s_pg_rca12_or7 b=s_pg_rca12_pg_fa8_xor0 out=s_pg_rca12_and8 .subckt or_gate a=s_pg_rca12_and8 b=s_pg_rca12_pg_fa8_and0 out=s_pg_rca12_or8 .subckt pg_fa a=a[9] b=b[9] cin=s_pg_rca12_or8 pg_fa_xor0=s_pg_rca12_pg_fa9_xor0 pg_fa_and0=s_pg_rca12_pg_fa9_and0 pg_fa_xor1=s_pg_rca12_pg_fa9_xor1 .subckt and_gate a=s_pg_rca12_or8 b=s_pg_rca12_pg_fa9_xor0 out=s_pg_rca12_and9 .subckt or_gate a=s_pg_rca12_and9 b=s_pg_rca12_pg_fa9_and0 out=s_pg_rca12_or9 .subckt pg_fa a=a[10] b=b[10] cin=s_pg_rca12_or9 pg_fa_xor0=s_pg_rca12_pg_fa10_xor0 pg_fa_and0=s_pg_rca12_pg_fa10_and0 pg_fa_xor1=s_pg_rca12_pg_fa10_xor1 .subckt and_gate a=s_pg_rca12_or9 b=s_pg_rca12_pg_fa10_xor0 out=s_pg_rca12_and10 .subckt or_gate a=s_pg_rca12_and10 b=s_pg_rca12_pg_fa10_and0 out=s_pg_rca12_or10 .subckt pg_fa a=a[11] b=b[11] cin=s_pg_rca12_or10 pg_fa_xor0=s_pg_rca12_pg_fa11_xor0 pg_fa_and0=s_pg_rca12_pg_fa11_and0 pg_fa_xor1=s_pg_rca12_pg_fa11_xor1 .subckt and_gate a=s_pg_rca12_or10 b=s_pg_rca12_pg_fa11_xor0 out=s_pg_rca12_and11 .subckt or_gate a=s_pg_rca12_and11 b=s_pg_rca12_pg_fa11_and0 out=s_pg_rca12_or11 .subckt xor_gate a=a[11] b=b[11] out=s_pg_rca12_xor0 .subckt xor_gate a=s_pg_rca12_xor0 b=s_pg_rca12_or11 out=s_pg_rca12_xor1 .names s_pg_rca12_pg_fa0_xor0 s_pg_rca12_out[0] 1 1 .names s_pg_rca12_pg_fa1_xor1 s_pg_rca12_out[1] 1 1 .names s_pg_rca12_pg_fa2_xor1 s_pg_rca12_out[2] 1 1 .names s_pg_rca12_pg_fa3_xor1 s_pg_rca12_out[3] 1 1 .names s_pg_rca12_pg_fa4_xor1 s_pg_rca12_out[4] 1 1 .names s_pg_rca12_pg_fa5_xor1 s_pg_rca12_out[5] 1 1 .names s_pg_rca12_pg_fa6_xor1 s_pg_rca12_out[6] 1 1 .names s_pg_rca12_pg_fa7_xor1 s_pg_rca12_out[7] 1 1 .names s_pg_rca12_pg_fa8_xor1 s_pg_rca12_out[8] 1 1 .names s_pg_rca12_pg_fa9_xor1 s_pg_rca12_out[9] 1 1 .names s_pg_rca12_pg_fa10_xor1 s_pg_rca12_out[10] 1 1 .names s_pg_rca12_pg_fa11_xor1 s_pg_rca12_out[11] 1 1 .names s_pg_rca12_xor1 s_pg_rca12_out[12] 1 1 .end .model pg_fa .inputs a b cin .outputs pg_fa_xor0 pg_fa_and0 pg_fa_xor1 .names vdd 1 .names gnd 0 .subckt xor_gate a=a b=b out=pg_fa_xor0 .subckt and_gate a=a b=b out=pg_fa_and0 .subckt xor_gate a=pg_fa_xor0 b=cin out=pg_fa_xor1 .end .model or_gate .inputs a b .outputs out .names vdd 1 .names gnd 0 .names a b out 1- 1 -1 1 .end .model and_gate .inputs a b .outputs out .names vdd 1 .names gnd 0 .names a b out 11 1 .end .model xor_gate .inputs a b .outputs out .names vdd 1 .names gnd 0 .names a b out 01 1 10 1 .end