.model s_CSAwallace_cla4 .inputs a[0] a[1] a[2] a[3] b[0] b[1] b[2] b[3] .outputs s_CSAwallace_cla4_out[0] s_CSAwallace_cla4_out[1] s_CSAwallace_cla4_out[2] s_CSAwallace_cla4_out[3] s_CSAwallace_cla4_out[4] s_CSAwallace_cla4_out[5] s_CSAwallace_cla4_out[6] s_CSAwallace_cla4_out[7] .names vdd 1 .names gnd 0 .subckt and_gate a=a[0] b=b[0] out=s_CSAwallace_cla4_and_0_0 .subckt and_gate a=a[1] b=b[0] out=s_CSAwallace_cla4_and_1_0 .subckt and_gate a=a[2] b=b[0] out=s_CSAwallace_cla4_and_2_0 .subckt nand_gate a=a[3] b=b[0] out=s_CSAwallace_cla4_nand_3_0 .subckt and_gate a=a[0] b=b[1] out=s_CSAwallace_cla4_and_0_1 .subckt and_gate a=a[1] b=b[1] out=s_CSAwallace_cla4_and_1_1 .subckt and_gate a=a[2] b=b[1] out=s_CSAwallace_cla4_and_2_1 .subckt nand_gate a=a[3] b=b[1] out=s_CSAwallace_cla4_nand_3_1 .subckt and_gate a=a[0] b=b[2] out=s_CSAwallace_cla4_and_0_2 .subckt and_gate a=a[1] b=b[2] out=s_CSAwallace_cla4_and_1_2 .subckt and_gate a=a[2] b=b[2] out=s_CSAwallace_cla4_and_2_2 .subckt nand_gate a=a[3] b=b[2] out=s_CSAwallace_cla4_nand_3_2 .subckt nand_gate a=a[0] b=b[3] out=s_CSAwallace_cla4_nand_0_3 .subckt nand_gate a=a[1] b=b[3] out=s_CSAwallace_cla4_nand_1_3 .subckt nand_gate a=a[2] b=b[3] out=s_CSAwallace_cla4_nand_2_3 .subckt and_gate a=a[3] b=b[3] out=s_CSAwallace_cla4_and_3_3 .names s_CSAwallace_cla4_and_0_0 s_CSAwallace_cla4_csa0_csa_component_pp_row0[0] 1 1 .names s_CSAwallace_cla4_and_1_0 s_CSAwallace_cla4_csa0_csa_component_pp_row0[1] 1 1 .names s_CSAwallace_cla4_and_2_0 s_CSAwallace_cla4_csa0_csa_component_pp_row0[2] 1 1 .names s_CSAwallace_cla4_nand_3_0 s_CSAwallace_cla4_csa0_csa_component_pp_row0[3] 1 1 .names vdd s_CSAwallace_cla4_csa0_csa_component_pp_row0[4] 1 1 .names vdd s_CSAwallace_cla4_csa0_csa_component_pp_row0[5] 1 1 .names gnd s_CSAwallace_cla4_csa0_csa_component_pp_row1[0] 1 1 .names s_CSAwallace_cla4_and_0_1 s_CSAwallace_cla4_csa0_csa_component_pp_row1[1] 1 1 .names s_CSAwallace_cla4_and_1_1 s_CSAwallace_cla4_csa0_csa_component_pp_row1[2] 1 1 .names s_CSAwallace_cla4_and_2_1 s_CSAwallace_cla4_csa0_csa_component_pp_row1[3] 1 1 .names s_CSAwallace_cla4_nand_3_1 s_CSAwallace_cla4_csa0_csa_component_pp_row1[4] 1 1 .names vdd s_CSAwallace_cla4_csa0_csa_component_pp_row1[5] 1 1 .names gnd s_CSAwallace_cla4_csa0_csa_component_pp_row2[0] 1 1 .names gnd s_CSAwallace_cla4_csa0_csa_component_pp_row2[1] 1 1 .names s_CSAwallace_cla4_and_0_2 s_CSAwallace_cla4_csa0_csa_component_pp_row2[2] 1 1 .names s_CSAwallace_cla4_and_1_2 s_CSAwallace_cla4_csa0_csa_component_pp_row2[3] 1 1 .names s_CSAwallace_cla4_and_2_2 s_CSAwallace_cla4_csa0_csa_component_pp_row2[4] 1 1 .names s_CSAwallace_cla4_nand_3_2 s_CSAwallace_cla4_csa0_csa_component_pp_row2[5] 1 1 .subckt csa_component6 a[0]=s_CSAwallace_cla4_csa0_csa_component_pp_row0[0] a[1]=s_CSAwallace_cla4_csa0_csa_component_pp_row0[1] a[2]=s_CSAwallace_cla4_csa0_csa_component_pp_row0[2] a[3]=s_CSAwallace_cla4_csa0_csa_component_pp_row0[3] a[4]=s_CSAwallace_cla4_csa0_csa_component_pp_row0[4] a[4]=s_CSAwallace_cla4_csa0_csa_component_pp_row0[4] b[0]=s_CSAwallace_cla4_csa0_csa_component_pp_row1[0] b[1]=s_CSAwallace_cla4_csa0_csa_component_pp_row1[1] b[2]=s_CSAwallace_cla4_csa0_csa_component_pp_row1[2] b[3]=s_CSAwallace_cla4_csa0_csa_component_pp_row1[3] b[4]=s_CSAwallace_cla4_csa0_csa_component_pp_row1[4] b[5]=s_CSAwallace_cla4_csa0_csa_component_pp_row1[5] c[0]=s_CSAwallace_cla4_csa0_csa_component_pp_row2[0] c[1]=s_CSAwallace_cla4_csa0_csa_component_pp_row2[1] c[2]=s_CSAwallace_cla4_csa0_csa_component_pp_row2[2] c[3]=s_CSAwallace_cla4_csa0_csa_component_pp_row2[3] c[4]=s_CSAwallace_cla4_csa0_csa_component_pp_row2[4] c[5]=s_CSAwallace_cla4_csa0_csa_component_pp_row2[5] csa_component6_out[0]=s_CSAwallace_cla4_and_0_0 csa_component6_out[1]=s_CSAwallace_cla4_csa0_csa_component_fa1_xor0 csa_component6_out[2]=s_CSAwallace_cla4_csa0_csa_component_fa2_xor1 csa_component6_out[3]=s_CSAwallace_cla4_csa0_csa_component_fa3_xor1 csa_component6_out[4]=s_CSAwallace_cla4_csa0_csa_component_fa4_xor1 csa_component6_out[5]=s_CSAwallace_cla4_nand_3_2 csa_component6_out[6]=constant_value_1 csa_component6_out[7]=constant_value_0 csa_component6_out[8]=constant_value_0 csa_component6_out[9]=s_CSAwallace_cla4_csa0_csa_component_fa1_and0 csa_component6_out[10]=s_CSAwallace_cla4_csa0_csa_component_fa2_or0 csa_component6_out[11]=s_CSAwallace_cla4_csa0_csa_component_fa3_or0 csa_component6_out[12]=s_CSAwallace_cla4_csa0_csa_component_fa4_or0 csa_component6_out[13]=constant_value_1 .names s_CSAwallace_cla4_and_0_0 s_CSAwallace_cla4_csa1_csa_component_s_CSAwallace_cla4_csa_s1[0] 1 1 .names s_CSAwallace_cla4_csa0_csa_component_fa1_xor0 s_CSAwallace_cla4_csa1_csa_component_s_CSAwallace_cla4_csa_s1[1] 1 1 .names s_CSAwallace_cla4_csa0_csa_component_fa2_xor1 s_CSAwallace_cla4_csa1_csa_component_s_CSAwallace_cla4_csa_s1[2] 1 1 .names s_CSAwallace_cla4_csa0_csa_component_fa3_xor1 s_CSAwallace_cla4_csa1_csa_component_s_CSAwallace_cla4_csa_s1[3] 1 1 .names s_CSAwallace_cla4_csa0_csa_component_fa4_xor1 s_CSAwallace_cla4_csa1_csa_component_s_CSAwallace_cla4_csa_s1[4] 1 1 .names s_CSAwallace_cla4_nand_3_2 s_CSAwallace_cla4_csa1_csa_component_s_CSAwallace_cla4_csa_s1[5] 1 1 .names vdd s_CSAwallace_cla4_csa1_csa_component_s_CSAwallace_cla4_csa_s1[6] 1 1 .names gnd s_CSAwallace_cla4_csa1_csa_component_s_CSAwallace_cla4_csa_c1[0] 1 1 .names gnd s_CSAwallace_cla4_csa1_csa_component_s_CSAwallace_cla4_csa_c1[1] 1 1 .names s_CSAwallace_cla4_csa0_csa_component_fa1_and0 s_CSAwallace_cla4_csa1_csa_component_s_CSAwallace_cla4_csa_c1[2] 1 1 .names s_CSAwallace_cla4_csa0_csa_component_fa2_or0 s_CSAwallace_cla4_csa1_csa_component_s_CSAwallace_cla4_csa_c1[3] 1 1 .names s_CSAwallace_cla4_csa0_csa_component_fa3_or0 s_CSAwallace_cla4_csa1_csa_component_s_CSAwallace_cla4_csa_c1[4] 1 1 .names s_CSAwallace_cla4_csa0_csa_component_fa4_or0 s_CSAwallace_cla4_csa1_csa_component_s_CSAwallace_cla4_csa_c1[5] 1 1 .names vdd s_CSAwallace_cla4_csa1_csa_component_s_CSAwallace_cla4_csa_c1[6] 1 1 .names gnd s_CSAwallace_cla4_csa1_csa_component_pp_row3[0] 1 1 .names gnd s_CSAwallace_cla4_csa1_csa_component_pp_row3[1] 1 1 .names gnd s_CSAwallace_cla4_csa1_csa_component_pp_row3[2] 1 1 .names s_CSAwallace_cla4_nand_0_3 s_CSAwallace_cla4_csa1_csa_component_pp_row3[3] 1 1 .names s_CSAwallace_cla4_nand_1_3 s_CSAwallace_cla4_csa1_csa_component_pp_row3[4] 1 1 .names s_CSAwallace_cla4_nand_2_3 s_CSAwallace_cla4_csa1_csa_component_pp_row3[5] 1 1 .names s_CSAwallace_cla4_and_3_3 s_CSAwallace_cla4_csa1_csa_component_pp_row3[6] 1 1 .subckt csa_component7 a[0]=s_CSAwallace_cla4_csa1_csa_component_s_CSAwallace_cla4_csa_s1[0] a[1]=s_CSAwallace_cla4_csa1_csa_component_s_CSAwallace_cla4_csa_s1[1] a[2]=s_CSAwallace_cla4_csa1_csa_component_s_CSAwallace_cla4_csa_s1[2] a[3]=s_CSAwallace_cla4_csa1_csa_component_s_CSAwallace_cla4_csa_s1[3] a[4]=s_CSAwallace_cla4_csa1_csa_component_s_CSAwallace_cla4_csa_s1[4] a[5]=s_CSAwallace_cla4_csa1_csa_component_s_CSAwallace_cla4_csa_s1[5] a[6]=s_CSAwallace_cla4_csa1_csa_component_s_CSAwallace_cla4_csa_s1[6] b[0]=s_CSAwallace_cla4_csa1_csa_component_s_CSAwallace_cla4_csa_c1[0] b[1]=s_CSAwallace_cla4_csa1_csa_component_s_CSAwallace_cla4_csa_c1[1] b[2]=s_CSAwallace_cla4_csa1_csa_component_s_CSAwallace_cla4_csa_c1[2] b[3]=s_CSAwallace_cla4_csa1_csa_component_s_CSAwallace_cla4_csa_c1[3] b[4]=s_CSAwallace_cla4_csa1_csa_component_s_CSAwallace_cla4_csa_c1[4] b[5]=s_CSAwallace_cla4_csa1_csa_component_s_CSAwallace_cla4_csa_c1[5] b[6]=s_CSAwallace_cla4_csa1_csa_component_s_CSAwallace_cla4_csa_c1[6] c[0]=s_CSAwallace_cla4_csa1_csa_component_pp_row3[0] c[1]=s_CSAwallace_cla4_csa1_csa_component_pp_row3[1] c[2]=s_CSAwallace_cla4_csa1_csa_component_pp_row3[2] c[3]=s_CSAwallace_cla4_csa1_csa_component_pp_row3[3] c[4]=s_CSAwallace_cla4_csa1_csa_component_pp_row3[4] c[5]=s_CSAwallace_cla4_csa1_csa_component_pp_row3[5] c[6]=s_CSAwallace_cla4_csa1_csa_component_pp_row3[6] csa_component7_out[0]=s_CSAwallace_cla4_and_0_0 csa_component7_out[1]=s_CSAwallace_cla4_csa0_csa_component_fa1_xor0 csa_component7_out[2]=s_CSAwallace_cla4_csa1_csa_component_fa2_xor0 csa_component7_out[3]=s_CSAwallace_cla4_csa1_csa_component_fa3_xor1 csa_component7_out[4]=s_CSAwallace_cla4_csa1_csa_component_fa4_xor1 csa_component7_out[5]=s_CSAwallace_cla4_csa1_csa_component_fa5_xor1 csa_component7_out[6]=s_CSAwallace_cla4_and_3_3 csa_component7_out[7]=constant_value_1 csa_component7_out[8]=constant_value_0 csa_component7_out[9]=constant_value_0 csa_component7_out[10]=constant_value_0 csa_component7_out[11]=s_CSAwallace_cla4_csa1_csa_component_fa2_and0 csa_component7_out[12]=s_CSAwallace_cla4_csa1_csa_component_fa3_or0 csa_component7_out[13]=s_CSAwallace_cla4_csa1_csa_component_fa4_or0 csa_component7_out[14]=s_CSAwallace_cla4_csa1_csa_component_fa5_or0 csa_component7_out[15]=constant_value_1 .names s_CSAwallace_cla4_and_0_0 s_CSAwallace_cla4_u_cla8_a[0] 1 1 .names s_CSAwallace_cla4_csa0_csa_component_fa1_xor0 s_CSAwallace_cla4_u_cla8_a[1] 1 1 .names s_CSAwallace_cla4_csa1_csa_component_fa2_xor0 s_CSAwallace_cla4_u_cla8_a[2] 1 1 .names s_CSAwallace_cla4_csa1_csa_component_fa3_xor1 s_CSAwallace_cla4_u_cla8_a[3] 1 1 .names s_CSAwallace_cla4_csa1_csa_component_fa4_xor1 s_CSAwallace_cla4_u_cla8_a[4] 1 1 .names s_CSAwallace_cla4_csa1_csa_component_fa5_xor1 s_CSAwallace_cla4_u_cla8_a[5] 1 1 .names s_CSAwallace_cla4_and_3_3 s_CSAwallace_cla4_u_cla8_a[6] 1 1 .names vdd s_CSAwallace_cla4_u_cla8_a[7] 1 1 .names gnd s_CSAwallace_cla4_u_cla8_b[0] 1 1 .names gnd s_CSAwallace_cla4_u_cla8_b[1] 1 1 .names gnd s_CSAwallace_cla4_u_cla8_b[2] 1 1 .names s_CSAwallace_cla4_csa1_csa_component_fa2_and0 s_CSAwallace_cla4_u_cla8_b[3] 1 1 .names s_CSAwallace_cla4_csa1_csa_component_fa3_or0 s_CSAwallace_cla4_u_cla8_b[4] 1 1 .names s_CSAwallace_cla4_csa1_csa_component_fa4_or0 s_CSAwallace_cla4_u_cla8_b[5] 1 1 .names s_CSAwallace_cla4_csa1_csa_component_fa5_or0 s_CSAwallace_cla4_u_cla8_b[6] 1 1 .names vdd s_CSAwallace_cla4_u_cla8_b[7] 1 1 .subckt u_cla8 a[0]=s_CSAwallace_cla4_u_cla8_a[0] a[1]=s_CSAwallace_cla4_u_cla8_a[1] a[2]=s_CSAwallace_cla4_u_cla8_a[2] a[3]=s_CSAwallace_cla4_u_cla8_a[3] a[4]=s_CSAwallace_cla4_u_cla8_a[4] a[5]=s_CSAwallace_cla4_u_cla8_a[5] a[6]=s_CSAwallace_cla4_u_cla8_a[6] a[7]=s_CSAwallace_cla4_u_cla8_a[7] b[0]=s_CSAwallace_cla4_u_cla8_b[0] b[1]=s_CSAwallace_cla4_u_cla8_b[1] b[2]=s_CSAwallace_cla4_u_cla8_b[2] b[3]=s_CSAwallace_cla4_u_cla8_b[3] b[4]=s_CSAwallace_cla4_u_cla8_b[4] b[5]=s_CSAwallace_cla4_u_cla8_b[5] b[6]=s_CSAwallace_cla4_u_cla8_b[6] b[7]=s_CSAwallace_cla4_u_cla8_b[7] u_cla8_out[0]=s_CSAwallace_cla4_and_0_0 u_cla8_out[1]=s_CSAwallace_cla4_csa0_csa_component_fa1_xor0 u_cla8_out[2]=s_CSAwallace_cla4_csa1_csa_component_fa2_xor0 u_cla8_out[3]=s_CSAwallace_cla4_u_cla8_pg_logic3_xor0 u_cla8_out[4]=s_CSAwallace_cla4_u_cla8_xor4 u_cla8_out[5]=s_CSAwallace_cla4_u_cla8_xor5 u_cla8_out[6]=s_CSAwallace_cla4_u_cla8_xor6 u_cla8_out[7]=s_CSAwallace_cla4_u_cla8_or5 u_cla8_out[8]=constant_value_1 .subckt not_gate a=s_CSAwallace_cla4_u_cla8_or5 out=s_CSAwallace_cla4_xor0 .names s_CSAwallace_cla4_and_0_0 s_CSAwallace_cla4_out[0] 1 1 .names s_CSAwallace_cla4_csa0_csa_component_fa1_xor0 s_CSAwallace_cla4_out[1] 1 1 .names s_CSAwallace_cla4_csa1_csa_component_fa2_xor0 s_CSAwallace_cla4_out[2] 1 1 .names s_CSAwallace_cla4_u_cla8_pg_logic3_xor0 s_CSAwallace_cla4_out[3] 1 1 .names s_CSAwallace_cla4_u_cla8_xor4 s_CSAwallace_cla4_out[4] 1 1 .names s_CSAwallace_cla4_u_cla8_xor5 s_CSAwallace_cla4_out[5] 1 1 .names s_CSAwallace_cla4_u_cla8_xor6 s_CSAwallace_cla4_out[6] 1 1 .names s_CSAwallace_cla4_xor0 s_CSAwallace_cla4_out[7] 1 1 .end .model u_cla8 .inputs a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] .outputs u_cla8_out[0] u_cla8_out[1] u_cla8_out[2] u_cla8_out[3] u_cla8_out[4] u_cla8_out[5] u_cla8_out[6] u_cla8_out[7] u_cla8_out[8] .names vdd 1 .names gnd 0 .subckt pg_logic a=a[0] b=b[0] pg_logic_or0=u_cla8_pg_logic0_or0 pg_logic_and0=u_cla8_pg_logic0_and0 pg_logic_xor0=u_cla8_pg_logic0_xor0 .subckt pg_logic a=a[1] b=b[1] pg_logic_or0=u_cla8_pg_logic1_or0 pg_logic_and0=u_cla8_pg_logic1_and0 pg_logic_xor0=u_cla8_pg_logic1_xor0 .subckt xor_gate a=u_cla8_pg_logic1_xor0 b=u_cla8_pg_logic0_and0 out=u_cla8_xor1 .subckt and_gate a=u_cla8_pg_logic0_and0 b=u_cla8_pg_logic1_or0 out=u_cla8_and0 .subckt or_gate a=u_cla8_pg_logic1_and0 b=u_cla8_and0 out=u_cla8_or0 .subckt pg_logic a=a[2] b=b[2] pg_logic_or0=u_cla8_pg_logic2_or0 pg_logic_and0=u_cla8_pg_logic2_and0 pg_logic_xor0=u_cla8_pg_logic2_xor0 .subckt xor_gate a=u_cla8_pg_logic2_xor0 b=u_cla8_or0 out=u_cla8_xor2 .subckt and_gate a=u_cla8_pg_logic2_or0 b=u_cla8_pg_logic0_or0 out=u_cla8_and1 .subckt and_gate a=u_cla8_pg_logic0_and0 b=u_cla8_pg_logic2_or0 out=u_cla8_and2 .subckt and_gate a=u_cla8_and2 b=u_cla8_pg_logic1_or0 out=u_cla8_and3 .subckt and_gate a=u_cla8_pg_logic1_and0 b=u_cla8_pg_logic2_or0 out=u_cla8_and4 .subckt or_gate a=u_cla8_and3 b=u_cla8_and4 out=u_cla8_or1 .subckt or_gate a=u_cla8_pg_logic2_and0 b=u_cla8_or1 out=u_cla8_or2 .subckt pg_logic a=a[3] b=b[3] pg_logic_or0=u_cla8_pg_logic3_or0 pg_logic_and0=u_cla8_pg_logic3_and0 pg_logic_xor0=u_cla8_pg_logic3_xor0 .subckt xor_gate a=u_cla8_pg_logic3_xor0 b=u_cla8_or2 out=u_cla8_xor3 .subckt and_gate a=u_cla8_pg_logic3_or0 b=u_cla8_pg_logic1_or0 out=u_cla8_and5 .subckt and_gate a=u_cla8_pg_logic0_and0 b=u_cla8_pg_logic2_or0 out=u_cla8_and6 .subckt and_gate a=u_cla8_pg_logic3_or0 b=u_cla8_pg_logic1_or0 out=u_cla8_and7 .subckt and_gate a=u_cla8_and6 b=u_cla8_and7 out=u_cla8_and8 .subckt and_gate a=u_cla8_pg_logic1_and0 b=u_cla8_pg_logic3_or0 out=u_cla8_and9 .subckt and_gate a=u_cla8_and9 b=u_cla8_pg_logic2_or0 out=u_cla8_and10 .subckt and_gate a=u_cla8_pg_logic2_and0 b=u_cla8_pg_logic3_or0 out=u_cla8_and11 .subckt or_gate a=u_cla8_and8 b=u_cla8_and11 out=u_cla8_or3 .subckt or_gate a=u_cla8_and10 b=u_cla8_or3 out=u_cla8_or4 .subckt or_gate a=u_cla8_pg_logic3_and0 b=u_cla8_or4 out=u_cla8_or5 .subckt pg_logic a=a[4] b=b[4] pg_logic_or0=u_cla8_pg_logic4_or0 pg_logic_and0=u_cla8_pg_logic4_and0 pg_logic_xor0=u_cla8_pg_logic4_xor0 .subckt xor_gate a=u_cla8_pg_logic4_xor0 b=u_cla8_or5 out=u_cla8_xor4 .subckt and_gate a=u_cla8_or5 b=u_cla8_pg_logic4_or0 out=u_cla8_and12 .subckt or_gate a=u_cla8_pg_logic4_and0 b=u_cla8_and12 out=u_cla8_or6 .subckt pg_logic a=a[5] b=b[5] pg_logic_or0=u_cla8_pg_logic5_or0 pg_logic_and0=u_cla8_pg_logic5_and0 pg_logic_xor0=u_cla8_pg_logic5_xor0 .subckt xor_gate a=u_cla8_pg_logic5_xor0 b=u_cla8_or6 out=u_cla8_xor5 .subckt and_gate a=u_cla8_or5 b=u_cla8_pg_logic5_or0 out=u_cla8_and13 .subckt and_gate a=u_cla8_and13 b=u_cla8_pg_logic4_or0 out=u_cla8_and14 .subckt and_gate a=u_cla8_pg_logic4_and0 b=u_cla8_pg_logic5_or0 out=u_cla8_and15 .subckt or_gate a=u_cla8_and14 b=u_cla8_and15 out=u_cla8_or7 .subckt or_gate a=u_cla8_pg_logic5_and0 b=u_cla8_or7 out=u_cla8_or8 .subckt pg_logic a=a[6] b=b[6] pg_logic_or0=u_cla8_pg_logic6_or0 pg_logic_and0=u_cla8_pg_logic6_and0 pg_logic_xor0=u_cla8_pg_logic6_xor0 .subckt xor_gate a=u_cla8_pg_logic6_xor0 b=u_cla8_or8 out=u_cla8_xor6 .subckt and_gate a=u_cla8_or5 b=u_cla8_pg_logic5_or0 out=u_cla8_and16 .subckt and_gate a=u_cla8_pg_logic6_or0 b=u_cla8_pg_logic4_or0 out=u_cla8_and17 .subckt and_gate a=u_cla8_and16 b=u_cla8_and17 out=u_cla8_and18 .subckt and_gate a=u_cla8_pg_logic4_and0 b=u_cla8_pg_logic6_or0 out=u_cla8_and19 .subckt and_gate a=u_cla8_and19 b=u_cla8_pg_logic5_or0 out=u_cla8_and20 .subckt and_gate a=u_cla8_pg_logic5_and0 b=u_cla8_pg_logic6_or0 out=u_cla8_and21 .subckt or_gate a=u_cla8_and18 b=u_cla8_and20 out=u_cla8_or9 .subckt or_gate a=u_cla8_or9 b=u_cla8_and21 out=u_cla8_or10 .subckt or_gate a=u_cla8_pg_logic6_and0 b=u_cla8_or10 out=u_cla8_or11 .subckt pg_logic a=a[7] b=b[7] pg_logic_or0=u_cla8_pg_logic7_or0 pg_logic_and0=u_cla8_pg_logic7_and0 pg_logic_xor0=u_cla8_pg_logic7_xor0 .subckt xor_gate a=u_cla8_pg_logic7_xor0 b=u_cla8_or11 out=u_cla8_xor7 .subckt and_gate a=u_cla8_or5 b=u_cla8_pg_logic6_or0 out=u_cla8_and22 .subckt and_gate a=u_cla8_pg_logic7_or0 b=u_cla8_pg_logic5_or0 out=u_cla8_and23 .subckt and_gate a=u_cla8_and22 b=u_cla8_and23 out=u_cla8_and24 .subckt and_gate a=u_cla8_and24 b=u_cla8_pg_logic4_or0 out=u_cla8_and25 .subckt and_gate a=u_cla8_pg_logic4_and0 b=u_cla8_pg_logic6_or0 out=u_cla8_and26 .subckt and_gate a=u_cla8_pg_logic7_or0 b=u_cla8_pg_logic5_or0 out=u_cla8_and27 .subckt and_gate a=u_cla8_and26 b=u_cla8_and27 out=u_cla8_and28 .subckt and_gate a=u_cla8_pg_logic5_and0 b=u_cla8_pg_logic7_or0 out=u_cla8_and29 .subckt and_gate a=u_cla8_and29 b=u_cla8_pg_logic6_or0 out=u_cla8_and30 .subckt and_gate a=u_cla8_pg_logic6_and0 b=u_cla8_pg_logic7_or0 out=u_cla8_and31 .subckt or_gate a=u_cla8_and25 b=u_cla8_and30 out=u_cla8_or12 .subckt or_gate a=u_cla8_and28 b=u_cla8_and31 out=u_cla8_or13 .subckt or_gate a=u_cla8_or12 b=u_cla8_or13 out=u_cla8_or14 .subckt or_gate a=u_cla8_pg_logic7_and0 b=u_cla8_or14 out=u_cla8_or15 .names u_cla8_pg_logic0_xor0 u_cla8_out[0] 1 1 .names u_cla8_xor1 u_cla8_out[1] 1 1 .names u_cla8_xor2 u_cla8_out[2] 1 1 .names u_cla8_xor3 u_cla8_out[3] 1 1 .names u_cla8_xor4 u_cla8_out[4] 1 1 .names u_cla8_xor5 u_cla8_out[5] 1 1 .names u_cla8_xor6 u_cla8_out[6] 1 1 .names u_cla8_xor7 u_cla8_out[7] 1 1 .names u_cla8_or15 u_cla8_out[8] 1 1 .end .model csa_component7 .inputs a[0] a[1] a[2] a[3] a[4] a[5] a[6] b[0] b[1] b[2] b[3] b[4] b[5] b[6] c[0] c[1] c[2] c[3] c[4] c[5] c[6] .outputs csa_component7_out[0] csa_component7_out[1] csa_component7_out[2] csa_component7_out[3] csa_component7_out[4] csa_component7_out[5] csa_component7_out[6] csa_component7_out[7] csa_component7_out[8] csa_component7_out[9] csa_component7_out[10] csa_component7_out[11] csa_component7_out[12] csa_component7_out[13] csa_component7_out[14] csa_component7_out[15] .names vdd 1 .names gnd 0 .subckt fa a=a[0] b=b[0] cin=c[0] fa_xor1=csa_component7_fa0_xor1 fa_or0=csa_component7_fa0_or0 .subckt fa a=a[1] b=b[1] cin=c[1] fa_xor1=csa_component7_fa1_xor1 fa_or0=csa_component7_fa1_or0 .subckt fa a=a[2] b=b[2] cin=c[2] fa_xor1=csa_component7_fa2_xor1 fa_or0=csa_component7_fa2_or0 .subckt fa a=a[3] b=b[3] cin=c[3] fa_xor1=csa_component7_fa3_xor1 fa_or0=csa_component7_fa3_or0 .subckt fa a=a[4] b=b[4] cin=c[4] fa_xor1=csa_component7_fa4_xor1 fa_or0=csa_component7_fa4_or0 .subckt fa a=a[5] b=b[5] cin=c[5] fa_xor1=csa_component7_fa5_xor1 fa_or0=csa_component7_fa5_or0 .subckt fa a=a[6] b=b[6] cin=c[6] fa_xor1=csa_component7_fa6_xor1 fa_or0=csa_component7_fa6_or0 .names csa_component7_fa0_xor1 csa_component7_out[0] 1 1 .names csa_component7_fa1_xor1 csa_component7_out[1] 1 1 .names csa_component7_fa2_xor1 csa_component7_out[2] 1 1 .names csa_component7_fa3_xor1 csa_component7_out[3] 1 1 .names csa_component7_fa4_xor1 csa_component7_out[4] 1 1 .names csa_component7_fa5_xor1 csa_component7_out[5] 1 1 .names csa_component7_fa6_xor1 csa_component7_out[6] 1 1 .names gnd csa_component7_out[7] 1 1 .names gnd csa_component7_out[8] 1 1 .names csa_component7_fa0_or0 csa_component7_out[9] 1 1 .names csa_component7_fa1_or0 csa_component7_out[10] 1 1 .names csa_component7_fa2_or0 csa_component7_out[11] 1 1 .names csa_component7_fa3_or0 csa_component7_out[12] 1 1 .names csa_component7_fa4_or0 csa_component7_out[13] 1 1 .names csa_component7_fa5_or0 csa_component7_out[14] 1 1 .names csa_component7_fa6_or0 csa_component7_out[15] 1 1 .end .model csa_component6 .inputs a[0] a[1] a[2] a[3] a[4] a[5] b[0] b[1] b[2] b[3] b[4] b[5] c[0] c[1] c[2] c[3] c[4] c[5] .outputs csa_component6_out[0] csa_component6_out[1] csa_component6_out[2] csa_component6_out[3] csa_component6_out[4] csa_component6_out[5] csa_component6_out[6] csa_component6_out[7] csa_component6_out[8] csa_component6_out[9] csa_component6_out[10] csa_component6_out[11] csa_component6_out[12] csa_component6_out[13] .names vdd 1 .names gnd 0 .subckt fa a=a[0] b=b[0] cin=c[0] fa_xor1=csa_component6_fa0_xor1 fa_or0=csa_component6_fa0_or0 .subckt fa a=a[1] b=b[1] cin=c[1] fa_xor1=csa_component6_fa1_xor1 fa_or0=csa_component6_fa1_or0 .subckt fa a=a[2] b=b[2] cin=c[2] fa_xor1=csa_component6_fa2_xor1 fa_or0=csa_component6_fa2_or0 .subckt fa a=a[3] b=b[3] cin=c[3] fa_xor1=csa_component6_fa3_xor1 fa_or0=csa_component6_fa3_or0 .subckt fa a=a[4] b=b[4] cin=c[4] fa_xor1=csa_component6_fa4_xor1 fa_or0=csa_component6_fa4_or0 .subckt fa a=a[5] b=b[5] cin=c[5] fa_xor1=csa_component6_fa5_xor1 fa_or0=csa_component6_fa5_or0 .names csa_component6_fa0_xor1 csa_component6_out[0] 1 1 .names csa_component6_fa1_xor1 csa_component6_out[1] 1 1 .names csa_component6_fa2_xor1 csa_component6_out[2] 1 1 .names csa_component6_fa3_xor1 csa_component6_out[3] 1 1 .names csa_component6_fa4_xor1 csa_component6_out[4] 1 1 .names csa_component6_fa5_xor1 csa_component6_out[5] 1 1 .names gnd csa_component6_out[6] 1 1 .names gnd csa_component6_out[7] 1 1 .names csa_component6_fa0_or0 csa_component6_out[8] 1 1 .names csa_component6_fa1_or0 csa_component6_out[9] 1 1 .names csa_component6_fa2_or0 csa_component6_out[10] 1 1 .names csa_component6_fa3_or0 csa_component6_out[11] 1 1 .names csa_component6_fa4_or0 csa_component6_out[12] 1 1 .names csa_component6_fa5_or0 csa_component6_out[13] 1 1 .end .model pg_logic .inputs a b .outputs pg_logic_or0 pg_logic_and0 pg_logic_xor0 .names vdd 1 .names gnd 0 .subckt or_gate a=a b=b out=pg_logic_or0 .subckt and_gate a=a b=b out=pg_logic_and0 .subckt xor_gate a=a b=b out=pg_logic_xor0 .end .model fa .inputs a b cin .outputs fa_xor1 fa_or0 .names vdd 1 .names gnd 0 .subckt xor_gate a=a b=b out=fa_xor0 .subckt and_gate a=a b=b out=fa_and0 .subckt xor_gate a=fa_xor0 b=cin out=fa_xor1 .subckt and_gate a=fa_xor0 b=cin out=fa_and1 .subckt or_gate a=fa_and0 b=fa_and1 out=fa_or0 .end .model not_gate .inputs a .outputs out .names vdd 1 .names gnd 0 .names a out 0 1 .end .model or_gate .inputs a b .outputs out .names vdd 1 .names gnd 0 .names a b out 1- 1 -1 1 .end .model xor_gate .inputs a b .outputs out .names vdd 1 .names gnd 0 .names a b out 01 1 10 1 .end .model nand_gate .inputs a b .outputs out .names vdd 1 .names gnd 0 .names a b out 0- 1 -0 1 .end .model and_gate .inputs a b .outputs out .names vdd 1 .names gnd 0 .names a b out 11 1 .end