.model u_wallace_cla12
.inputs a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] a[8] a[9] a[10] a[11] b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9] b[10] b[11]
.outputs u_wallace_cla12_out[0] u_wallace_cla12_out[1] u_wallace_cla12_out[2] u_wallace_cla12_out[3] u_wallace_cla12_out[4] u_wallace_cla12_out[5] u_wallace_cla12_out[6] u_wallace_cla12_out[7] u_wallace_cla12_out[8] u_wallace_cla12_out[9] u_wallace_cla12_out[10] u_wallace_cla12_out[11] u_wallace_cla12_out[12] u_wallace_cla12_out[13] u_wallace_cla12_out[14] u_wallace_cla12_out[15] u_wallace_cla12_out[16] u_wallace_cla12_out[17] u_wallace_cla12_out[18] u_wallace_cla12_out[19] u_wallace_cla12_out[20] u_wallace_cla12_out[21] u_wallace_cla12_out[22] u_wallace_cla12_out[23]
.names vdd
1
.names gnd
0
.subckt and_gate a=a[2] b=b[0] out=u_wallace_cla12_and_2_0
.subckt and_gate a=a[1] b=b[1] out=u_wallace_cla12_and_1_1
.subckt ha a=u_wallace_cla12_and_2_0 b=u_wallace_cla12_and_1_1 ha_xor0=u_wallace_cla12_ha0_xor0 ha_and0=u_wallace_cla12_ha0_and0
.subckt and_gate a=a[3] b=b[0] out=u_wallace_cla12_and_3_0
.subckt and_gate a=a[2] b=b[1] out=u_wallace_cla12_and_2_1
.subckt fa a=u_wallace_cla12_ha0_and0 b=u_wallace_cla12_and_3_0 cin=u_wallace_cla12_and_2_1 fa_xor1=u_wallace_cla12_fa0_xor1 fa_or0=u_wallace_cla12_fa0_or0
.subckt and_gate a=a[4] b=b[0] out=u_wallace_cla12_and_4_0
.subckt and_gate a=a[3] b=b[1] out=u_wallace_cla12_and_3_1
.subckt fa a=u_wallace_cla12_fa0_or0 b=u_wallace_cla12_and_4_0 cin=u_wallace_cla12_and_3_1 fa_xor1=u_wallace_cla12_fa1_xor1 fa_or0=u_wallace_cla12_fa1_or0
.subckt and_gate a=a[5] b=b[0] out=u_wallace_cla12_and_5_0
.subckt and_gate a=a[4] b=b[1] out=u_wallace_cla12_and_4_1
.subckt fa a=u_wallace_cla12_fa1_or0 b=u_wallace_cla12_and_5_0 cin=u_wallace_cla12_and_4_1 fa_xor1=u_wallace_cla12_fa2_xor1 fa_or0=u_wallace_cla12_fa2_or0
.subckt and_gate a=a[6] b=b[0] out=u_wallace_cla12_and_6_0
.subckt and_gate a=a[5] b=b[1] out=u_wallace_cla12_and_5_1
.subckt fa a=u_wallace_cla12_fa2_or0 b=u_wallace_cla12_and_6_0 cin=u_wallace_cla12_and_5_1 fa_xor1=u_wallace_cla12_fa3_xor1 fa_or0=u_wallace_cla12_fa3_or0
.subckt and_gate a=a[7] b=b[0] out=u_wallace_cla12_and_7_0
.subckt and_gate a=a[6] b=b[1] out=u_wallace_cla12_and_6_1
.subckt fa a=u_wallace_cla12_fa3_or0 b=u_wallace_cla12_and_7_0 cin=u_wallace_cla12_and_6_1 fa_xor1=u_wallace_cla12_fa4_xor1 fa_or0=u_wallace_cla12_fa4_or0
.subckt and_gate a=a[8] b=b[0] out=u_wallace_cla12_and_8_0
.subckt and_gate a=a[7] b=b[1] out=u_wallace_cla12_and_7_1
.subckt fa a=u_wallace_cla12_fa4_or0 b=u_wallace_cla12_and_8_0 cin=u_wallace_cla12_and_7_1 fa_xor1=u_wallace_cla12_fa5_xor1 fa_or0=u_wallace_cla12_fa5_or0
.subckt and_gate a=a[9] b=b[0] out=u_wallace_cla12_and_9_0
.subckt and_gate a=a[8] b=b[1] out=u_wallace_cla12_and_8_1
.subckt fa a=u_wallace_cla12_fa5_or0 b=u_wallace_cla12_and_9_0 cin=u_wallace_cla12_and_8_1 fa_xor1=u_wallace_cla12_fa6_xor1 fa_or0=u_wallace_cla12_fa6_or0
.subckt and_gate a=a[10] b=b[0] out=u_wallace_cla12_and_10_0
.subckt and_gate a=a[9] b=b[1] out=u_wallace_cla12_and_9_1
.subckt fa a=u_wallace_cla12_fa6_or0 b=u_wallace_cla12_and_10_0 cin=u_wallace_cla12_and_9_1 fa_xor1=u_wallace_cla12_fa7_xor1 fa_or0=u_wallace_cla12_fa7_or0
.subckt and_gate a=a[11] b=b[0] out=u_wallace_cla12_and_11_0
.subckt and_gate a=a[10] b=b[1] out=u_wallace_cla12_and_10_1
.subckt fa a=u_wallace_cla12_fa7_or0 b=u_wallace_cla12_and_11_0 cin=u_wallace_cla12_and_10_1 fa_xor1=u_wallace_cla12_fa8_xor1 fa_or0=u_wallace_cla12_fa8_or0
.subckt and_gate a=a[11] b=b[1] out=u_wallace_cla12_and_11_1
.subckt and_gate a=a[10] b=b[2] out=u_wallace_cla12_and_10_2
.subckt fa a=u_wallace_cla12_fa8_or0 b=u_wallace_cla12_and_11_1 cin=u_wallace_cla12_and_10_2 fa_xor1=u_wallace_cla12_fa9_xor1 fa_or0=u_wallace_cla12_fa9_or0
.subckt and_gate a=a[11] b=b[2] out=u_wallace_cla12_and_11_2
.subckt and_gate a=a[10] b=b[3] out=u_wallace_cla12_and_10_3
.subckt fa a=u_wallace_cla12_fa9_or0 b=u_wallace_cla12_and_11_2 cin=u_wallace_cla12_and_10_3 fa_xor1=u_wallace_cla12_fa10_xor1 fa_or0=u_wallace_cla12_fa10_or0
.subckt and_gate a=a[11] b=b[3] out=u_wallace_cla12_and_11_3
.subckt and_gate a=a[10] b=b[4] out=u_wallace_cla12_and_10_4
.subckt fa a=u_wallace_cla12_fa10_or0 b=u_wallace_cla12_and_11_3 cin=u_wallace_cla12_and_10_4 fa_xor1=u_wallace_cla12_fa11_xor1 fa_or0=u_wallace_cla12_fa11_or0
.subckt and_gate a=a[11] b=b[4] out=u_wallace_cla12_and_11_4
.subckt and_gate a=a[10] b=b[5] out=u_wallace_cla12_and_10_5
.subckt fa a=u_wallace_cla12_fa11_or0 b=u_wallace_cla12_and_11_4 cin=u_wallace_cla12_and_10_5 fa_xor1=u_wallace_cla12_fa12_xor1 fa_or0=u_wallace_cla12_fa12_or0
.subckt and_gate a=a[11] b=b[5] out=u_wallace_cla12_and_11_5
.subckt and_gate a=a[10] b=b[6] out=u_wallace_cla12_and_10_6
.subckt fa a=u_wallace_cla12_fa12_or0 b=u_wallace_cla12_and_11_5 cin=u_wallace_cla12_and_10_6 fa_xor1=u_wallace_cla12_fa13_xor1 fa_or0=u_wallace_cla12_fa13_or0
.subckt and_gate a=a[11] b=b[6] out=u_wallace_cla12_and_11_6
.subckt and_gate a=a[10] b=b[7] out=u_wallace_cla12_and_10_7
.subckt fa a=u_wallace_cla12_fa13_or0 b=u_wallace_cla12_and_11_6 cin=u_wallace_cla12_and_10_7 fa_xor1=u_wallace_cla12_fa14_xor1 fa_or0=u_wallace_cla12_fa14_or0
.subckt and_gate a=a[11] b=b[7] out=u_wallace_cla12_and_11_7
.subckt and_gate a=a[10] b=b[8] out=u_wallace_cla12_and_10_8
.subckt fa a=u_wallace_cla12_fa14_or0 b=u_wallace_cla12_and_11_7 cin=u_wallace_cla12_and_10_8 fa_xor1=u_wallace_cla12_fa15_xor1 fa_or0=u_wallace_cla12_fa15_or0
.subckt and_gate a=a[11] b=b[8] out=u_wallace_cla12_and_11_8
.subckt and_gate a=a[10] b=b[9] out=u_wallace_cla12_and_10_9
.subckt fa a=u_wallace_cla12_fa15_or0 b=u_wallace_cla12_and_11_8 cin=u_wallace_cla12_and_10_9 fa_xor1=u_wallace_cla12_fa16_xor1 fa_or0=u_wallace_cla12_fa16_or0
.subckt and_gate a=a[11] b=b[9] out=u_wallace_cla12_and_11_9
.subckt and_gate a=a[10] b=b[10] out=u_wallace_cla12_and_10_10
.subckt fa a=u_wallace_cla12_fa16_or0 b=u_wallace_cla12_and_11_9 cin=u_wallace_cla12_and_10_10 fa_xor1=u_wallace_cla12_fa17_xor1 fa_or0=u_wallace_cla12_fa17_or0
.subckt and_gate a=a[1] b=b[2] out=u_wallace_cla12_and_1_2
.subckt and_gate a=a[0] b=b[3] out=u_wallace_cla12_and_0_3
.subckt ha a=u_wallace_cla12_and_1_2 b=u_wallace_cla12_and_0_3 ha_xor0=u_wallace_cla12_ha1_xor0 ha_and0=u_wallace_cla12_ha1_and0
.subckt and_gate a=a[2] b=b[2] out=u_wallace_cla12_and_2_2
.subckt and_gate a=a[1] b=b[3] out=u_wallace_cla12_and_1_3
.subckt fa a=u_wallace_cla12_ha1_and0 b=u_wallace_cla12_and_2_2 cin=u_wallace_cla12_and_1_3 fa_xor1=u_wallace_cla12_fa18_xor1 fa_or0=u_wallace_cla12_fa18_or0
.subckt and_gate a=a[3] b=b[2] out=u_wallace_cla12_and_3_2
.subckt and_gate a=a[2] b=b[3] out=u_wallace_cla12_and_2_3
.subckt fa a=u_wallace_cla12_fa18_or0 b=u_wallace_cla12_and_3_2 cin=u_wallace_cla12_and_2_3 fa_xor1=u_wallace_cla12_fa19_xor1 fa_or0=u_wallace_cla12_fa19_or0
.subckt and_gate a=a[4] b=b[2] out=u_wallace_cla12_and_4_2
.subckt and_gate a=a[3] b=b[3] out=u_wallace_cla12_and_3_3
.subckt fa a=u_wallace_cla12_fa19_or0 b=u_wallace_cla12_and_4_2 cin=u_wallace_cla12_and_3_3 fa_xor1=u_wallace_cla12_fa20_xor1 fa_or0=u_wallace_cla12_fa20_or0
.subckt and_gate a=a[5] b=b[2] out=u_wallace_cla12_and_5_2
.subckt and_gate a=a[4] b=b[3] out=u_wallace_cla12_and_4_3
.subckt fa a=u_wallace_cla12_fa20_or0 b=u_wallace_cla12_and_5_2 cin=u_wallace_cla12_and_4_3 fa_xor1=u_wallace_cla12_fa21_xor1 fa_or0=u_wallace_cla12_fa21_or0
.subckt and_gate a=a[6] b=b[2] out=u_wallace_cla12_and_6_2
.subckt and_gate a=a[5] b=b[3] out=u_wallace_cla12_and_5_3
.subckt fa a=u_wallace_cla12_fa21_or0 b=u_wallace_cla12_and_6_2 cin=u_wallace_cla12_and_5_3 fa_xor1=u_wallace_cla12_fa22_xor1 fa_or0=u_wallace_cla12_fa22_or0
.subckt and_gate a=a[7] b=b[2] out=u_wallace_cla12_and_7_2
.subckt and_gate a=a[6] b=b[3] out=u_wallace_cla12_and_6_3
.subckt fa a=u_wallace_cla12_fa22_or0 b=u_wallace_cla12_and_7_2 cin=u_wallace_cla12_and_6_3 fa_xor1=u_wallace_cla12_fa23_xor1 fa_or0=u_wallace_cla12_fa23_or0
.subckt and_gate a=a[8] b=b[2] out=u_wallace_cla12_and_8_2
.subckt and_gate a=a[7] b=b[3] out=u_wallace_cla12_and_7_3
.subckt fa a=u_wallace_cla12_fa23_or0 b=u_wallace_cla12_and_8_2 cin=u_wallace_cla12_and_7_3 fa_xor1=u_wallace_cla12_fa24_xor1 fa_or0=u_wallace_cla12_fa24_or0
.subckt and_gate a=a[9] b=b[2] out=u_wallace_cla12_and_9_2
.subckt and_gate a=a[8] b=b[3] out=u_wallace_cla12_and_8_3
.subckt fa a=u_wallace_cla12_fa24_or0 b=u_wallace_cla12_and_9_2 cin=u_wallace_cla12_and_8_3 fa_xor1=u_wallace_cla12_fa25_xor1 fa_or0=u_wallace_cla12_fa25_or0
.subckt and_gate a=a[9] b=b[3] out=u_wallace_cla12_and_9_3
.subckt and_gate a=a[8] b=b[4] out=u_wallace_cla12_and_8_4
.subckt fa a=u_wallace_cla12_fa25_or0 b=u_wallace_cla12_and_9_3 cin=u_wallace_cla12_and_8_4 fa_xor1=u_wallace_cla12_fa26_xor1 fa_or0=u_wallace_cla12_fa26_or0
.subckt and_gate a=a[9] b=b[4] out=u_wallace_cla12_and_9_4
.subckt and_gate a=a[8] b=b[5] out=u_wallace_cla12_and_8_5
.subckt fa a=u_wallace_cla12_fa26_or0 b=u_wallace_cla12_and_9_4 cin=u_wallace_cla12_and_8_5 fa_xor1=u_wallace_cla12_fa27_xor1 fa_or0=u_wallace_cla12_fa27_or0
.subckt and_gate a=a[9] b=b[5] out=u_wallace_cla12_and_9_5
.subckt and_gate a=a[8] b=b[6] out=u_wallace_cla12_and_8_6
.subckt fa a=u_wallace_cla12_fa27_or0 b=u_wallace_cla12_and_9_5 cin=u_wallace_cla12_and_8_6 fa_xor1=u_wallace_cla12_fa28_xor1 fa_or0=u_wallace_cla12_fa28_or0
.subckt and_gate a=a[9] b=b[6] out=u_wallace_cla12_and_9_6
.subckt and_gate a=a[8] b=b[7] out=u_wallace_cla12_and_8_7
.subckt fa a=u_wallace_cla12_fa28_or0 b=u_wallace_cla12_and_9_6 cin=u_wallace_cla12_and_8_7 fa_xor1=u_wallace_cla12_fa29_xor1 fa_or0=u_wallace_cla12_fa29_or0
.subckt and_gate a=a[9] b=b[7] out=u_wallace_cla12_and_9_7
.subckt and_gate a=a[8] b=b[8] out=u_wallace_cla12_and_8_8
.subckt fa a=u_wallace_cla12_fa29_or0 b=u_wallace_cla12_and_9_7 cin=u_wallace_cla12_and_8_8 fa_xor1=u_wallace_cla12_fa30_xor1 fa_or0=u_wallace_cla12_fa30_or0
.subckt and_gate a=a[9] b=b[8] out=u_wallace_cla12_and_9_8
.subckt and_gate a=a[8] b=b[9] out=u_wallace_cla12_and_8_9
.subckt fa a=u_wallace_cla12_fa30_or0 b=u_wallace_cla12_and_9_8 cin=u_wallace_cla12_and_8_9 fa_xor1=u_wallace_cla12_fa31_xor1 fa_or0=u_wallace_cla12_fa31_or0
.subckt and_gate a=a[9] b=b[9] out=u_wallace_cla12_and_9_9
.subckt and_gate a=a[8] b=b[10] out=u_wallace_cla12_and_8_10
.subckt fa a=u_wallace_cla12_fa31_or0 b=u_wallace_cla12_and_9_9 cin=u_wallace_cla12_and_8_10 fa_xor1=u_wallace_cla12_fa32_xor1 fa_or0=u_wallace_cla12_fa32_or0
.subckt and_gate a=a[9] b=b[10] out=u_wallace_cla12_and_9_10
.subckt and_gate a=a[8] b=b[11] out=u_wallace_cla12_and_8_11
.subckt fa a=u_wallace_cla12_fa32_or0 b=u_wallace_cla12_and_9_10 cin=u_wallace_cla12_and_8_11 fa_xor1=u_wallace_cla12_fa33_xor1 fa_or0=u_wallace_cla12_fa33_or0
.subckt and_gate a=a[0] b=b[4] out=u_wallace_cla12_and_0_4
.subckt ha a=u_wallace_cla12_and_0_4 b=u_wallace_cla12_fa1_xor1 ha_xor0=u_wallace_cla12_ha2_xor0 ha_and0=u_wallace_cla12_ha2_and0
.subckt and_gate a=a[1] b=b[4] out=u_wallace_cla12_and_1_4
.subckt and_gate a=a[0] b=b[5] out=u_wallace_cla12_and_0_5
.subckt fa a=u_wallace_cla12_ha2_and0 b=u_wallace_cla12_and_1_4 cin=u_wallace_cla12_and_0_5 fa_xor1=u_wallace_cla12_fa34_xor1 fa_or0=u_wallace_cla12_fa34_or0
.subckt and_gate a=a[2] b=b[4] out=u_wallace_cla12_and_2_4
.subckt and_gate a=a[1] b=b[5] out=u_wallace_cla12_and_1_5
.subckt fa a=u_wallace_cla12_fa34_or0 b=u_wallace_cla12_and_2_4 cin=u_wallace_cla12_and_1_5 fa_xor1=u_wallace_cla12_fa35_xor1 fa_or0=u_wallace_cla12_fa35_or0
.subckt and_gate a=a[3] b=b[4] out=u_wallace_cla12_and_3_4
.subckt and_gate a=a[2] b=b[5] out=u_wallace_cla12_and_2_5
.subckt fa a=u_wallace_cla12_fa35_or0 b=u_wallace_cla12_and_3_4 cin=u_wallace_cla12_and_2_5 fa_xor1=u_wallace_cla12_fa36_xor1 fa_or0=u_wallace_cla12_fa36_or0
.subckt and_gate a=a[4] b=b[4] out=u_wallace_cla12_and_4_4
.subckt and_gate a=a[3] b=b[5] out=u_wallace_cla12_and_3_5
.subckt fa a=u_wallace_cla12_fa36_or0 b=u_wallace_cla12_and_4_4 cin=u_wallace_cla12_and_3_5 fa_xor1=u_wallace_cla12_fa37_xor1 fa_or0=u_wallace_cla12_fa37_or0
.subckt and_gate a=a[5] b=b[4] out=u_wallace_cla12_and_5_4
.subckt and_gate a=a[4] b=b[5] out=u_wallace_cla12_and_4_5
.subckt fa a=u_wallace_cla12_fa37_or0 b=u_wallace_cla12_and_5_4 cin=u_wallace_cla12_and_4_5 fa_xor1=u_wallace_cla12_fa38_xor1 fa_or0=u_wallace_cla12_fa38_or0
.subckt and_gate a=a[6] b=b[4] out=u_wallace_cla12_and_6_4
.subckt and_gate a=a[5] b=b[5] out=u_wallace_cla12_and_5_5
.subckt fa a=u_wallace_cla12_fa38_or0 b=u_wallace_cla12_and_6_4 cin=u_wallace_cla12_and_5_5 fa_xor1=u_wallace_cla12_fa39_xor1 fa_or0=u_wallace_cla12_fa39_or0
.subckt and_gate a=a[7] b=b[4] out=u_wallace_cla12_and_7_4
.subckt and_gate a=a[6] b=b[5] out=u_wallace_cla12_and_6_5
.subckt fa a=u_wallace_cla12_fa39_or0 b=u_wallace_cla12_and_7_4 cin=u_wallace_cla12_and_6_5 fa_xor1=u_wallace_cla12_fa40_xor1 fa_or0=u_wallace_cla12_fa40_or0
.subckt and_gate a=a[7] b=b[5] out=u_wallace_cla12_and_7_5
.subckt and_gate a=a[6] b=b[6] out=u_wallace_cla12_and_6_6
.subckt fa a=u_wallace_cla12_fa40_or0 b=u_wallace_cla12_and_7_5 cin=u_wallace_cla12_and_6_6 fa_xor1=u_wallace_cla12_fa41_xor1 fa_or0=u_wallace_cla12_fa41_or0
.subckt and_gate a=a[7] b=b[6] out=u_wallace_cla12_and_7_6
.subckt and_gate a=a[6] b=b[7] out=u_wallace_cla12_and_6_7
.subckt fa a=u_wallace_cla12_fa41_or0 b=u_wallace_cla12_and_7_6 cin=u_wallace_cla12_and_6_7 fa_xor1=u_wallace_cla12_fa42_xor1 fa_or0=u_wallace_cla12_fa42_or0
.subckt and_gate a=a[7] b=b[7] out=u_wallace_cla12_and_7_7
.subckt and_gate a=a[6] b=b[8] out=u_wallace_cla12_and_6_8
.subckt fa a=u_wallace_cla12_fa42_or0 b=u_wallace_cla12_and_7_7 cin=u_wallace_cla12_and_6_8 fa_xor1=u_wallace_cla12_fa43_xor1 fa_or0=u_wallace_cla12_fa43_or0
.subckt and_gate a=a[7] b=b[8] out=u_wallace_cla12_and_7_8
.subckt and_gate a=a[6] b=b[9] out=u_wallace_cla12_and_6_9
.subckt fa a=u_wallace_cla12_fa43_or0 b=u_wallace_cla12_and_7_8 cin=u_wallace_cla12_and_6_9 fa_xor1=u_wallace_cla12_fa44_xor1 fa_or0=u_wallace_cla12_fa44_or0
.subckt and_gate a=a[7] b=b[9] out=u_wallace_cla12_and_7_9
.subckt and_gate a=a[6] b=b[10] out=u_wallace_cla12_and_6_10
.subckt fa a=u_wallace_cla12_fa44_or0 b=u_wallace_cla12_and_7_9 cin=u_wallace_cla12_and_6_10 fa_xor1=u_wallace_cla12_fa45_xor1 fa_or0=u_wallace_cla12_fa45_or0
.subckt and_gate a=a[7] b=b[10] out=u_wallace_cla12_and_7_10
.subckt and_gate a=a[6] b=b[11] out=u_wallace_cla12_and_6_11
.subckt fa a=u_wallace_cla12_fa45_or0 b=u_wallace_cla12_and_7_10 cin=u_wallace_cla12_and_6_11 fa_xor1=u_wallace_cla12_fa46_xor1 fa_or0=u_wallace_cla12_fa46_or0
.subckt and_gate a=a[7] b=b[11] out=u_wallace_cla12_and_7_11
.subckt fa a=u_wallace_cla12_fa46_or0 b=u_wallace_cla12_and_7_11 cin=u_wallace_cla12_fa15_xor1 fa_xor1=u_wallace_cla12_fa47_xor1 fa_or0=u_wallace_cla12_fa47_or0
.subckt ha a=u_wallace_cla12_fa2_xor1 b=u_wallace_cla12_fa19_xor1 ha_xor0=u_wallace_cla12_ha3_xor0 ha_and0=u_wallace_cla12_ha3_and0
.subckt and_gate a=a[0] b=b[6] out=u_wallace_cla12_and_0_6
.subckt fa a=u_wallace_cla12_ha3_and0 b=u_wallace_cla12_and_0_6 cin=u_wallace_cla12_fa3_xor1 fa_xor1=u_wallace_cla12_fa48_xor1 fa_or0=u_wallace_cla12_fa48_or0
.subckt and_gate a=a[1] b=b[6] out=u_wallace_cla12_and_1_6
.subckt and_gate a=a[0] b=b[7] out=u_wallace_cla12_and_0_7
.subckt fa a=u_wallace_cla12_fa48_or0 b=u_wallace_cla12_and_1_6 cin=u_wallace_cla12_and_0_7 fa_xor1=u_wallace_cla12_fa49_xor1 fa_or0=u_wallace_cla12_fa49_or0
.subckt and_gate a=a[2] b=b[6] out=u_wallace_cla12_and_2_6
.subckt and_gate a=a[1] b=b[7] out=u_wallace_cla12_and_1_7
.subckt fa a=u_wallace_cla12_fa49_or0 b=u_wallace_cla12_and_2_6 cin=u_wallace_cla12_and_1_7 fa_xor1=u_wallace_cla12_fa50_xor1 fa_or0=u_wallace_cla12_fa50_or0
.subckt and_gate a=a[3] b=b[6] out=u_wallace_cla12_and_3_6
.subckt and_gate a=a[2] b=b[7] out=u_wallace_cla12_and_2_7
.subckt fa a=u_wallace_cla12_fa50_or0 b=u_wallace_cla12_and_3_6 cin=u_wallace_cla12_and_2_7 fa_xor1=u_wallace_cla12_fa51_xor1 fa_or0=u_wallace_cla12_fa51_or0
.subckt and_gate a=a[4] b=b[6] out=u_wallace_cla12_and_4_6
.subckt and_gate a=a[3] b=b[7] out=u_wallace_cla12_and_3_7
.subckt fa a=u_wallace_cla12_fa51_or0 b=u_wallace_cla12_and_4_6 cin=u_wallace_cla12_and_3_7 fa_xor1=u_wallace_cla12_fa52_xor1 fa_or0=u_wallace_cla12_fa52_or0
.subckt and_gate a=a[5] b=b[6] out=u_wallace_cla12_and_5_6
.subckt and_gate a=a[4] b=b[7] out=u_wallace_cla12_and_4_7
.subckt fa a=u_wallace_cla12_fa52_or0 b=u_wallace_cla12_and_5_6 cin=u_wallace_cla12_and_4_7 fa_xor1=u_wallace_cla12_fa53_xor1 fa_or0=u_wallace_cla12_fa53_or0
.subckt and_gate a=a[5] b=b[7] out=u_wallace_cla12_and_5_7
.subckt and_gate a=a[4] b=b[8] out=u_wallace_cla12_and_4_8
.subckt fa a=u_wallace_cla12_fa53_or0 b=u_wallace_cla12_and_5_7 cin=u_wallace_cla12_and_4_8 fa_xor1=u_wallace_cla12_fa54_xor1 fa_or0=u_wallace_cla12_fa54_or0
.subckt and_gate a=a[5] b=b[8] out=u_wallace_cla12_and_5_8
.subckt and_gate a=a[4] b=b[9] out=u_wallace_cla12_and_4_9
.subckt fa a=u_wallace_cla12_fa54_or0 b=u_wallace_cla12_and_5_8 cin=u_wallace_cla12_and_4_9 fa_xor1=u_wallace_cla12_fa55_xor1 fa_or0=u_wallace_cla12_fa55_or0
.subckt and_gate a=a[5] b=b[9] out=u_wallace_cla12_and_5_9
.subckt and_gate a=a[4] b=b[10] out=u_wallace_cla12_and_4_10
.subckt fa a=u_wallace_cla12_fa55_or0 b=u_wallace_cla12_and_5_9 cin=u_wallace_cla12_and_4_10 fa_xor1=u_wallace_cla12_fa56_xor1 fa_or0=u_wallace_cla12_fa56_or0
.subckt and_gate a=a[5] b=b[10] out=u_wallace_cla12_and_5_10
.subckt and_gate a=a[4] b=b[11] out=u_wallace_cla12_and_4_11
.subckt fa a=u_wallace_cla12_fa56_or0 b=u_wallace_cla12_and_5_10 cin=u_wallace_cla12_and_4_11 fa_xor1=u_wallace_cla12_fa57_xor1 fa_or0=u_wallace_cla12_fa57_or0
.subckt and_gate a=a[5] b=b[11] out=u_wallace_cla12_and_5_11
.subckt fa a=u_wallace_cla12_fa57_or0 b=u_wallace_cla12_and_5_11 cin=u_wallace_cla12_fa13_xor1 fa_xor1=u_wallace_cla12_fa58_xor1 fa_or0=u_wallace_cla12_fa58_or0
.subckt fa a=u_wallace_cla12_fa58_or0 b=u_wallace_cla12_fa14_xor1 cin=u_wallace_cla12_fa31_xor1 fa_xor1=u_wallace_cla12_fa59_xor1 fa_or0=u_wallace_cla12_fa59_or0
.subckt ha a=u_wallace_cla12_fa20_xor1 b=u_wallace_cla12_fa35_xor1 ha_xor0=u_wallace_cla12_ha4_xor0 ha_and0=u_wallace_cla12_ha4_and0
.subckt fa a=u_wallace_cla12_ha4_and0 b=u_wallace_cla12_fa4_xor1 cin=u_wallace_cla12_fa21_xor1 fa_xor1=u_wallace_cla12_fa60_xor1 fa_or0=u_wallace_cla12_fa60_or0
.subckt and_gate a=a[0] b=b[8] out=u_wallace_cla12_and_0_8
.subckt fa a=u_wallace_cla12_fa60_or0 b=u_wallace_cla12_and_0_8 cin=u_wallace_cla12_fa5_xor1 fa_xor1=u_wallace_cla12_fa61_xor1 fa_or0=u_wallace_cla12_fa61_or0
.subckt and_gate a=a[1] b=b[8] out=u_wallace_cla12_and_1_8
.subckt and_gate a=a[0] b=b[9] out=u_wallace_cla12_and_0_9
.subckt fa a=u_wallace_cla12_fa61_or0 b=u_wallace_cla12_and_1_8 cin=u_wallace_cla12_and_0_9 fa_xor1=u_wallace_cla12_fa62_xor1 fa_or0=u_wallace_cla12_fa62_or0
.subckt and_gate a=a[2] b=b[8] out=u_wallace_cla12_and_2_8
.subckt and_gate a=a[1] b=b[9] out=u_wallace_cla12_and_1_9
.subckt fa a=u_wallace_cla12_fa62_or0 b=u_wallace_cla12_and_2_8 cin=u_wallace_cla12_and_1_9 fa_xor1=u_wallace_cla12_fa63_xor1 fa_or0=u_wallace_cla12_fa63_or0
.subckt and_gate a=a[3] b=b[8] out=u_wallace_cla12_and_3_8
.subckt and_gate a=a[2] b=b[9] out=u_wallace_cla12_and_2_9
.subckt fa a=u_wallace_cla12_fa63_or0 b=u_wallace_cla12_and_3_8 cin=u_wallace_cla12_and_2_9 fa_xor1=u_wallace_cla12_fa64_xor1 fa_or0=u_wallace_cla12_fa64_or0
.subckt and_gate a=a[3] b=b[9] out=u_wallace_cla12_and_3_9
.subckt and_gate a=a[2] b=b[10] out=u_wallace_cla12_and_2_10
.subckt fa a=u_wallace_cla12_fa64_or0 b=u_wallace_cla12_and_3_9 cin=u_wallace_cla12_and_2_10 fa_xor1=u_wallace_cla12_fa65_xor1 fa_or0=u_wallace_cla12_fa65_or0
.subckt and_gate a=a[3] b=b[10] out=u_wallace_cla12_and_3_10
.subckt and_gate a=a[2] b=b[11] out=u_wallace_cla12_and_2_11
.subckt fa a=u_wallace_cla12_fa65_or0 b=u_wallace_cla12_and_3_10 cin=u_wallace_cla12_and_2_11 fa_xor1=u_wallace_cla12_fa66_xor1 fa_or0=u_wallace_cla12_fa66_or0
.subckt and_gate a=a[3] b=b[11] out=u_wallace_cla12_and_3_11
.subckt fa a=u_wallace_cla12_fa66_or0 b=u_wallace_cla12_and_3_11 cin=u_wallace_cla12_fa11_xor1 fa_xor1=u_wallace_cla12_fa67_xor1 fa_or0=u_wallace_cla12_fa67_or0
.subckt fa a=u_wallace_cla12_fa67_or0 b=u_wallace_cla12_fa12_xor1 cin=u_wallace_cla12_fa29_xor1 fa_xor1=u_wallace_cla12_fa68_xor1 fa_or0=u_wallace_cla12_fa68_or0
.subckt fa a=u_wallace_cla12_fa68_or0 b=u_wallace_cla12_fa30_xor1 cin=u_wallace_cla12_fa45_xor1 fa_xor1=u_wallace_cla12_fa69_xor1 fa_or0=u_wallace_cla12_fa69_or0
.subckt ha a=u_wallace_cla12_fa36_xor1 b=u_wallace_cla12_fa49_xor1 ha_xor0=u_wallace_cla12_ha5_xor0 ha_and0=u_wallace_cla12_ha5_and0
.subckt fa a=u_wallace_cla12_ha5_and0 b=u_wallace_cla12_fa22_xor1 cin=u_wallace_cla12_fa37_xor1 fa_xor1=u_wallace_cla12_fa70_xor1 fa_or0=u_wallace_cla12_fa70_or0
.subckt fa a=u_wallace_cla12_fa70_or0 b=u_wallace_cla12_fa6_xor1 cin=u_wallace_cla12_fa23_xor1 fa_xor1=u_wallace_cla12_fa71_xor1 fa_or0=u_wallace_cla12_fa71_or0
.subckt and_gate a=a[0] b=b[10] out=u_wallace_cla12_and_0_10
.subckt fa a=u_wallace_cla12_fa71_or0 b=u_wallace_cla12_and_0_10 cin=u_wallace_cla12_fa7_xor1 fa_xor1=u_wallace_cla12_fa72_xor1 fa_or0=u_wallace_cla12_fa72_or0
.subckt and_gate a=a[1] b=b[10] out=u_wallace_cla12_and_1_10
.subckt and_gate a=a[0] b=b[11] out=u_wallace_cla12_and_0_11
.subckt fa a=u_wallace_cla12_fa72_or0 b=u_wallace_cla12_and_1_10 cin=u_wallace_cla12_and_0_11 fa_xor1=u_wallace_cla12_fa73_xor1 fa_or0=u_wallace_cla12_fa73_or0
.subckt and_gate a=a[1] b=b[11] out=u_wallace_cla12_and_1_11
.subckt fa a=u_wallace_cla12_fa73_or0 b=u_wallace_cla12_and_1_11 cin=u_wallace_cla12_fa9_xor1 fa_xor1=u_wallace_cla12_fa74_xor1 fa_or0=u_wallace_cla12_fa74_or0
.subckt fa a=u_wallace_cla12_fa74_or0 b=u_wallace_cla12_fa10_xor1 cin=u_wallace_cla12_fa27_xor1 fa_xor1=u_wallace_cla12_fa75_xor1 fa_or0=u_wallace_cla12_fa75_or0
.subckt fa a=u_wallace_cla12_fa75_or0 b=u_wallace_cla12_fa28_xor1 cin=u_wallace_cla12_fa43_xor1 fa_xor1=u_wallace_cla12_fa76_xor1 fa_or0=u_wallace_cla12_fa76_or0
.subckt fa a=u_wallace_cla12_fa76_or0 b=u_wallace_cla12_fa44_xor1 cin=u_wallace_cla12_fa57_xor1 fa_xor1=u_wallace_cla12_fa77_xor1 fa_or0=u_wallace_cla12_fa77_or0
.subckt ha a=u_wallace_cla12_fa50_xor1 b=u_wallace_cla12_fa61_xor1 ha_xor0=u_wallace_cla12_ha6_xor0 ha_and0=u_wallace_cla12_ha6_and0
.subckt fa a=u_wallace_cla12_ha6_and0 b=u_wallace_cla12_fa38_xor1 cin=u_wallace_cla12_fa51_xor1 fa_xor1=u_wallace_cla12_fa78_xor1 fa_or0=u_wallace_cla12_fa78_or0
.subckt fa a=u_wallace_cla12_fa78_or0 b=u_wallace_cla12_fa24_xor1 cin=u_wallace_cla12_fa39_xor1 fa_xor1=u_wallace_cla12_fa79_xor1 fa_or0=u_wallace_cla12_fa79_or0
.subckt fa a=u_wallace_cla12_fa79_or0 b=u_wallace_cla12_fa8_xor1 cin=u_wallace_cla12_fa25_xor1 fa_xor1=u_wallace_cla12_fa80_xor1 fa_or0=u_wallace_cla12_fa80_or0
.subckt fa a=u_wallace_cla12_fa80_or0 b=u_wallace_cla12_fa26_xor1 cin=u_wallace_cla12_fa41_xor1 fa_xor1=u_wallace_cla12_fa81_xor1 fa_or0=u_wallace_cla12_fa81_or0
.subckt fa a=u_wallace_cla12_fa81_or0 b=u_wallace_cla12_fa42_xor1 cin=u_wallace_cla12_fa55_xor1 fa_xor1=u_wallace_cla12_fa82_xor1 fa_or0=u_wallace_cla12_fa82_or0
.subckt fa a=u_wallace_cla12_fa82_or0 b=u_wallace_cla12_fa56_xor1 cin=u_wallace_cla12_fa67_xor1 fa_xor1=u_wallace_cla12_fa83_xor1 fa_or0=u_wallace_cla12_fa83_or0
.subckt ha a=u_wallace_cla12_fa62_xor1 b=u_wallace_cla12_fa71_xor1 ha_xor0=u_wallace_cla12_ha7_xor0 ha_and0=u_wallace_cla12_ha7_and0
.subckt fa a=u_wallace_cla12_ha7_and0 b=u_wallace_cla12_fa52_xor1 cin=u_wallace_cla12_fa63_xor1 fa_xor1=u_wallace_cla12_fa84_xor1 fa_or0=u_wallace_cla12_fa84_or0
.subckt fa a=u_wallace_cla12_fa84_or0 b=u_wallace_cla12_fa40_xor1 cin=u_wallace_cla12_fa53_xor1 fa_xor1=u_wallace_cla12_fa85_xor1 fa_or0=u_wallace_cla12_fa85_or0
.subckt fa a=u_wallace_cla12_fa85_or0 b=u_wallace_cla12_fa54_xor1 cin=u_wallace_cla12_fa65_xor1 fa_xor1=u_wallace_cla12_fa86_xor1 fa_or0=u_wallace_cla12_fa86_or0
.subckt fa a=u_wallace_cla12_fa86_or0 b=u_wallace_cla12_fa66_xor1 cin=u_wallace_cla12_fa75_xor1 fa_xor1=u_wallace_cla12_fa87_xor1 fa_or0=u_wallace_cla12_fa87_or0
.subckt ha a=u_wallace_cla12_fa72_xor1 b=u_wallace_cla12_fa79_xor1 ha_xor0=u_wallace_cla12_ha8_xor0 ha_and0=u_wallace_cla12_ha8_and0
.subckt fa a=u_wallace_cla12_ha8_and0 b=u_wallace_cla12_fa64_xor1 cin=u_wallace_cla12_fa73_xor1 fa_xor1=u_wallace_cla12_fa88_xor1 fa_or0=u_wallace_cla12_fa88_or0
.subckt fa a=u_wallace_cla12_fa88_or0 b=u_wallace_cla12_fa74_xor1 cin=u_wallace_cla12_fa81_xor1 fa_xor1=u_wallace_cla12_fa89_xor1 fa_or0=u_wallace_cla12_fa89_or0
.subckt ha a=u_wallace_cla12_fa80_xor1 b=u_wallace_cla12_fa85_xor1 ha_xor0=u_wallace_cla12_ha9_xor0 ha_and0=u_wallace_cla12_ha9_and0
.subckt ha a=u_wallace_cla12_ha9_and0 b=u_wallace_cla12_fa86_xor1 ha_xor0=u_wallace_cla12_ha10_xor0 ha_and0=u_wallace_cla12_ha10_and0
.subckt fa a=u_wallace_cla12_ha10_and0 b=u_wallace_cla12_fa89_or0 cin=u_wallace_cla12_fa82_xor1 fa_xor1=u_wallace_cla12_fa90_xor1 fa_or0=u_wallace_cla12_fa90_or0
.subckt fa a=u_wallace_cla12_fa90_or0 b=u_wallace_cla12_fa87_or0 cin=u_wallace_cla12_fa76_xor1 fa_xor1=u_wallace_cla12_fa91_xor1 fa_or0=u_wallace_cla12_fa91_or0
.subckt fa a=u_wallace_cla12_fa91_or0 b=u_wallace_cla12_fa83_or0 cin=u_wallace_cla12_fa68_xor1 fa_xor1=u_wallace_cla12_fa92_xor1 fa_or0=u_wallace_cla12_fa92_or0
.subckt fa a=u_wallace_cla12_fa92_or0 b=u_wallace_cla12_fa77_or0 cin=u_wallace_cla12_fa58_xor1 fa_xor1=u_wallace_cla12_fa93_xor1 fa_or0=u_wallace_cla12_fa93_or0
.subckt fa a=u_wallace_cla12_fa93_or0 b=u_wallace_cla12_fa69_or0 cin=u_wallace_cla12_fa46_xor1 fa_xor1=u_wallace_cla12_fa94_xor1 fa_or0=u_wallace_cla12_fa94_or0
.subckt fa a=u_wallace_cla12_fa94_or0 b=u_wallace_cla12_fa59_or0 cin=u_wallace_cla12_fa32_xor1 fa_xor1=u_wallace_cla12_fa95_xor1 fa_or0=u_wallace_cla12_fa95_or0
.subckt fa a=u_wallace_cla12_fa95_or0 b=u_wallace_cla12_fa47_or0 cin=u_wallace_cla12_fa16_xor1 fa_xor1=u_wallace_cla12_fa96_xor1 fa_or0=u_wallace_cla12_fa96_or0
.subckt and_gate a=a[9] b=b[11] out=u_wallace_cla12_and_9_11
.subckt fa a=u_wallace_cla12_fa96_or0 b=u_wallace_cla12_fa33_or0 cin=u_wallace_cla12_and_9_11 fa_xor1=u_wallace_cla12_fa97_xor1 fa_or0=u_wallace_cla12_fa97_or0
.subckt and_gate a=a[11] b=b[10] out=u_wallace_cla12_and_11_10
.subckt fa a=u_wallace_cla12_fa97_or0 b=u_wallace_cla12_fa17_or0 cin=u_wallace_cla12_and_11_10 fa_xor1=u_wallace_cla12_fa98_xor1 fa_or0=u_wallace_cla12_fa98_or0
.subckt and_gate a=a[0] b=b[0] out=u_wallace_cla12_and_0_0
.subckt and_gate a=a[1] b=b[0] out=u_wallace_cla12_and_1_0
.subckt and_gate a=a[0] b=b[2] out=u_wallace_cla12_and_0_2
.subckt and_gate a=a[10] b=b[11] out=u_wallace_cla12_and_10_11
.subckt and_gate a=a[0] b=b[1] out=u_wallace_cla12_and_0_1
.subckt and_gate a=a[11] b=b[11] out=u_wallace_cla12_and_11_11
.names u_wallace_cla12_and_1_0 u_wallace_cla12_u_cla22_a[0]
1 1
.names u_wallace_cla12_and_0_2 u_wallace_cla12_u_cla22_a[1]
1 1
.names u_wallace_cla12_fa0_xor1 u_wallace_cla12_u_cla22_a[2]
1 1
.names u_wallace_cla12_fa18_xor1 u_wallace_cla12_u_cla22_a[3]
1 1
.names u_wallace_cla12_fa34_xor1 u_wallace_cla12_u_cla22_a[4]
1 1
.names u_wallace_cla12_fa48_xor1 u_wallace_cla12_u_cla22_a[5]
1 1
.names u_wallace_cla12_fa60_xor1 u_wallace_cla12_u_cla22_a[6]
1 1
.names u_wallace_cla12_fa70_xor1 u_wallace_cla12_u_cla22_a[7]
1 1
.names u_wallace_cla12_fa78_xor1 u_wallace_cla12_u_cla22_a[8]
1 1
.names u_wallace_cla12_fa84_xor1 u_wallace_cla12_u_cla22_a[9]
1 1
.names u_wallace_cla12_fa88_xor1 u_wallace_cla12_u_cla22_a[10]
1 1
.names u_wallace_cla12_fa89_xor1 u_wallace_cla12_u_cla22_a[11]
1 1
.names u_wallace_cla12_fa87_xor1 u_wallace_cla12_u_cla22_a[12]
1 1
.names u_wallace_cla12_fa83_xor1 u_wallace_cla12_u_cla22_a[13]
1 1
.names u_wallace_cla12_fa77_xor1 u_wallace_cla12_u_cla22_a[14]
1 1
.names u_wallace_cla12_fa69_xor1 u_wallace_cla12_u_cla22_a[15]
1 1
.names u_wallace_cla12_fa59_xor1 u_wallace_cla12_u_cla22_a[16]
1 1
.names u_wallace_cla12_fa47_xor1 u_wallace_cla12_u_cla22_a[17]
1 1
.names u_wallace_cla12_fa33_xor1 u_wallace_cla12_u_cla22_a[18]
1 1
.names u_wallace_cla12_fa17_xor1 u_wallace_cla12_u_cla22_a[19]
1 1
.names u_wallace_cla12_and_10_11 u_wallace_cla12_u_cla22_a[20]
1 1
.names u_wallace_cla12_fa98_or0 u_wallace_cla12_u_cla22_a[21]
1 1
.names u_wallace_cla12_and_0_1 u_wallace_cla12_u_cla22_b[0]
1 1
.names u_wallace_cla12_ha0_xor0 u_wallace_cla12_u_cla22_b[1]
1 1
.names u_wallace_cla12_ha1_xor0 u_wallace_cla12_u_cla22_b[2]
1 1
.names u_wallace_cla12_ha2_xor0 u_wallace_cla12_u_cla22_b[3]
1 1
.names u_wallace_cla12_ha3_xor0 u_wallace_cla12_u_cla22_b[4]
1 1
.names u_wallace_cla12_ha4_xor0 u_wallace_cla12_u_cla22_b[5]
1 1
.names u_wallace_cla12_ha5_xor0 u_wallace_cla12_u_cla22_b[6]
1 1
.names u_wallace_cla12_ha6_xor0 u_wallace_cla12_u_cla22_b[7]
1 1
.names u_wallace_cla12_ha7_xor0 u_wallace_cla12_u_cla22_b[8]
1 1
.names u_wallace_cla12_ha8_xor0 u_wallace_cla12_u_cla22_b[9]
1 1
.names u_wallace_cla12_ha9_xor0 u_wallace_cla12_u_cla22_b[10]
1 1
.names u_wallace_cla12_ha10_xor0 u_wallace_cla12_u_cla22_b[11]
1 1
.names u_wallace_cla12_fa90_xor1 u_wallace_cla12_u_cla22_b[12]
1 1
.names u_wallace_cla12_fa91_xor1 u_wallace_cla12_u_cla22_b[13]
1 1
.names u_wallace_cla12_fa92_xor1 u_wallace_cla12_u_cla22_b[14]
1 1
.names u_wallace_cla12_fa93_xor1 u_wallace_cla12_u_cla22_b[15]
1 1
.names u_wallace_cla12_fa94_xor1 u_wallace_cla12_u_cla22_b[16]
1 1
.names u_wallace_cla12_fa95_xor1 u_wallace_cla12_u_cla22_b[17]
1 1
.names u_wallace_cla12_fa96_xor1 u_wallace_cla12_u_cla22_b[18]
1 1
.names u_wallace_cla12_fa97_xor1 u_wallace_cla12_u_cla22_b[19]
1 1
.names u_wallace_cla12_fa98_xor1 u_wallace_cla12_u_cla22_b[20]
1 1
.names u_wallace_cla12_and_11_11 u_wallace_cla12_u_cla22_b[21]
1 1
.subckt u_cla22 a[0]=u_wallace_cla12_u_cla22_a[0] a[1]=u_wallace_cla12_u_cla22_a[1] a[2]=u_wallace_cla12_u_cla22_a[2] a[3]=u_wallace_cla12_u_cla22_a[3] a[4]=u_wallace_cla12_u_cla22_a[4] a[5]=u_wallace_cla12_u_cla22_a[5] a[6]=u_wallace_cla12_u_cla22_a[6] a[7]=u_wallace_cla12_u_cla22_a[7] a[8]=u_wallace_cla12_u_cla22_a[8] a[9]=u_wallace_cla12_u_cla22_a[9] a[10]=u_wallace_cla12_u_cla22_a[10] a[11]=u_wallace_cla12_u_cla22_a[11] a[12]=u_wallace_cla12_u_cla22_a[12] a[13]=u_wallace_cla12_u_cla22_a[13] a[14]=u_wallace_cla12_u_cla22_a[14] a[15]=u_wallace_cla12_u_cla22_a[15] a[16]=u_wallace_cla12_u_cla22_a[16] a[17]=u_wallace_cla12_u_cla22_a[17] a[18]=u_wallace_cla12_u_cla22_a[18] a[19]=u_wallace_cla12_u_cla22_a[19] a[20]=u_wallace_cla12_u_cla22_a[20] a[21]=u_wallace_cla12_u_cla22_a[21] b[0]=u_wallace_cla12_u_cla22_b[0] b[1]=u_wallace_cla12_u_cla22_b[1] b[2]=u_wallace_cla12_u_cla22_b[2] b[3]=u_wallace_cla12_u_cla22_b[3] b[4]=u_wallace_cla12_u_cla22_b[4] b[5]=u_wallace_cla12_u_cla22_b[5] b[6]=u_wallace_cla12_u_cla22_b[6] b[7]=u_wallace_cla12_u_cla22_b[7] b[8]=u_wallace_cla12_u_cla22_b[8] b[9]=u_wallace_cla12_u_cla22_b[9] b[10]=u_wallace_cla12_u_cla22_b[10] b[11]=u_wallace_cla12_u_cla22_b[11] b[12]=u_wallace_cla12_u_cla22_b[12] b[13]=u_wallace_cla12_u_cla22_b[13] b[14]=u_wallace_cla12_u_cla22_b[14] b[15]=u_wallace_cla12_u_cla22_b[15] b[16]=u_wallace_cla12_u_cla22_b[16] b[17]=u_wallace_cla12_u_cla22_b[17] b[18]=u_wallace_cla12_u_cla22_b[18] b[19]=u_wallace_cla12_u_cla22_b[19] b[20]=u_wallace_cla12_u_cla22_b[20] b[21]=u_wallace_cla12_u_cla22_b[21] u_cla22_out[0]=u_wallace_cla12_u_cla22_pg_logic0_xor0 u_cla22_out[1]=u_wallace_cla12_u_cla22_xor1 u_cla22_out[2]=u_wallace_cla12_u_cla22_xor2 u_cla22_out[3]=u_wallace_cla12_u_cla22_xor3 u_cla22_out[4]=u_wallace_cla12_u_cla22_xor4 u_cla22_out[5]=u_wallace_cla12_u_cla22_xor5 u_cla22_out[6]=u_wallace_cla12_u_cla22_xor6 u_cla22_out[7]=u_wallace_cla12_u_cla22_xor7 u_cla22_out[8]=u_wallace_cla12_u_cla22_xor8 u_cla22_out[9]=u_wallace_cla12_u_cla22_xor9 u_cla22_out[10]=u_wallace_cla12_u_cla22_xor10 u_cla22_out[11]=u_wallace_cla12_u_cla22_xor11 u_cla22_out[12]=u_wallace_cla12_u_cla22_xor12 u_cla22_out[13]=u_wallace_cla12_u_cla22_xor13 u_cla22_out[14]=u_wallace_cla12_u_cla22_xor14 u_cla22_out[15]=u_wallace_cla12_u_cla22_xor15 u_cla22_out[16]=u_wallace_cla12_u_cla22_xor16 u_cla22_out[17]=u_wallace_cla12_u_cla22_xor17 u_cla22_out[18]=u_wallace_cla12_u_cla22_xor18 u_cla22_out[19]=u_wallace_cla12_u_cla22_xor19 u_cla22_out[20]=u_wallace_cla12_u_cla22_xor20 u_cla22_out[21]=u_wallace_cla12_u_cla22_xor21 u_cla22_out[22]=u_wallace_cla12_u_cla22_or48
.names u_wallace_cla12_and_0_0 u_wallace_cla12_out[0]
1 1
.names u_wallace_cla12_u_cla22_pg_logic0_xor0 u_wallace_cla12_out[1]
1 1
.names u_wallace_cla12_u_cla22_xor1 u_wallace_cla12_out[2]
1 1
.names u_wallace_cla12_u_cla22_xor2 u_wallace_cla12_out[3]
1 1
.names u_wallace_cla12_u_cla22_xor3 u_wallace_cla12_out[4]
1 1
.names u_wallace_cla12_u_cla22_xor4 u_wallace_cla12_out[5]
1 1
.names u_wallace_cla12_u_cla22_xor5 u_wallace_cla12_out[6]
1 1
.names u_wallace_cla12_u_cla22_xor6 u_wallace_cla12_out[7]
1 1
.names u_wallace_cla12_u_cla22_xor7 u_wallace_cla12_out[8]
1 1
.names u_wallace_cla12_u_cla22_xor8 u_wallace_cla12_out[9]
1 1
.names u_wallace_cla12_u_cla22_xor9 u_wallace_cla12_out[10]
1 1
.names u_wallace_cla12_u_cla22_xor10 u_wallace_cla12_out[11]
1 1
.names u_wallace_cla12_u_cla22_xor11 u_wallace_cla12_out[12]
1 1
.names u_wallace_cla12_u_cla22_xor12 u_wallace_cla12_out[13]
1 1
.names u_wallace_cla12_u_cla22_xor13 u_wallace_cla12_out[14]
1 1
.names u_wallace_cla12_u_cla22_xor14 u_wallace_cla12_out[15]
1 1
.names u_wallace_cla12_u_cla22_xor15 u_wallace_cla12_out[16]
1 1
.names u_wallace_cla12_u_cla22_xor16 u_wallace_cla12_out[17]
1 1
.names u_wallace_cla12_u_cla22_xor17 u_wallace_cla12_out[18]
1 1
.names u_wallace_cla12_u_cla22_xor18 u_wallace_cla12_out[19]
1 1
.names u_wallace_cla12_u_cla22_xor19 u_wallace_cla12_out[20]
1 1
.names u_wallace_cla12_u_cla22_xor20 u_wallace_cla12_out[21]
1 1
.names u_wallace_cla12_u_cla22_xor21 u_wallace_cla12_out[22]
1 1
.names u_wallace_cla12_u_cla22_or48 u_wallace_cla12_out[23]
1 1
.end

.model u_cla22
.inputs a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] a[8] a[9] a[10] a[11] a[12] a[13] a[14] a[15] a[16] a[17] a[18] a[19] a[20] a[21] b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9] b[10] b[11] b[12] b[13] b[14] b[15] b[16] b[17] b[18] b[19] b[20] b[21]
.outputs u_cla22_out[0] u_cla22_out[1] u_cla22_out[2] u_cla22_out[3] u_cla22_out[4] u_cla22_out[5] u_cla22_out[6] u_cla22_out[7] u_cla22_out[8] u_cla22_out[9] u_cla22_out[10] u_cla22_out[11] u_cla22_out[12] u_cla22_out[13] u_cla22_out[14] u_cla22_out[15] u_cla22_out[16] u_cla22_out[17] u_cla22_out[18] u_cla22_out[19] u_cla22_out[20] u_cla22_out[21] u_cla22_out[22]
.names vdd
1
.names gnd
0
.subckt pg_logic a=a[0] b=b[0] pg_logic_or0=u_cla22_pg_logic0_or0 pg_logic_and0=u_cla22_pg_logic0_and0 pg_logic_xor0=u_cla22_pg_logic0_xor0
.subckt pg_logic a=a[1] b=b[1] pg_logic_or0=u_cla22_pg_logic1_or0 pg_logic_and0=u_cla22_pg_logic1_and0 pg_logic_xor0=u_cla22_pg_logic1_xor0
.subckt xor_gate a=u_cla22_pg_logic1_xor0 b=u_cla22_pg_logic0_and0 out=u_cla22_xor1
.subckt and_gate a=u_cla22_pg_logic0_and0 b=u_cla22_pg_logic1_or0 out=u_cla22_and0
.subckt or_gate a=u_cla22_pg_logic1_and0 b=u_cla22_and0 out=u_cla22_or0
.subckt pg_logic a=a[2] b=b[2] pg_logic_or0=u_cla22_pg_logic2_or0 pg_logic_and0=u_cla22_pg_logic2_and0 pg_logic_xor0=u_cla22_pg_logic2_xor0
.subckt xor_gate a=u_cla22_pg_logic2_xor0 b=u_cla22_or0 out=u_cla22_xor2
.subckt and_gate a=u_cla22_pg_logic2_or0 b=u_cla22_pg_logic0_or0 out=u_cla22_and1
.subckt and_gate a=u_cla22_pg_logic0_and0 b=u_cla22_pg_logic2_or0 out=u_cla22_and2
.subckt and_gate a=u_cla22_and2 b=u_cla22_pg_logic1_or0 out=u_cla22_and3
.subckt and_gate a=u_cla22_pg_logic1_and0 b=u_cla22_pg_logic2_or0 out=u_cla22_and4
.subckt or_gate a=u_cla22_and3 b=u_cla22_and4 out=u_cla22_or1
.subckt or_gate a=u_cla22_pg_logic2_and0 b=u_cla22_or1 out=u_cla22_or2
.subckt pg_logic a=a[3] b=b[3] pg_logic_or0=u_cla22_pg_logic3_or0 pg_logic_and0=u_cla22_pg_logic3_and0 pg_logic_xor0=u_cla22_pg_logic3_xor0
.subckt xor_gate a=u_cla22_pg_logic3_xor0 b=u_cla22_or2 out=u_cla22_xor3
.subckt and_gate a=u_cla22_pg_logic3_or0 b=u_cla22_pg_logic1_or0 out=u_cla22_and5
.subckt and_gate a=u_cla22_pg_logic0_and0 b=u_cla22_pg_logic2_or0 out=u_cla22_and6
.subckt and_gate a=u_cla22_pg_logic3_or0 b=u_cla22_pg_logic1_or0 out=u_cla22_and7
.subckt and_gate a=u_cla22_and6 b=u_cla22_and7 out=u_cla22_and8
.subckt and_gate a=u_cla22_pg_logic1_and0 b=u_cla22_pg_logic3_or0 out=u_cla22_and9
.subckt and_gate a=u_cla22_and9 b=u_cla22_pg_logic2_or0 out=u_cla22_and10
.subckt and_gate a=u_cla22_pg_logic2_and0 b=u_cla22_pg_logic3_or0 out=u_cla22_and11
.subckt or_gate a=u_cla22_and8 b=u_cla22_and11 out=u_cla22_or3
.subckt or_gate a=u_cla22_and10 b=u_cla22_or3 out=u_cla22_or4
.subckt or_gate a=u_cla22_pg_logic3_and0 b=u_cla22_or4 out=u_cla22_or5
.subckt pg_logic a=a[4] b=b[4] pg_logic_or0=u_cla22_pg_logic4_or0 pg_logic_and0=u_cla22_pg_logic4_and0 pg_logic_xor0=u_cla22_pg_logic4_xor0
.subckt xor_gate a=u_cla22_pg_logic4_xor0 b=u_cla22_or5 out=u_cla22_xor4
.subckt and_gate a=u_cla22_or5 b=u_cla22_pg_logic4_or0 out=u_cla22_and12
.subckt or_gate a=u_cla22_pg_logic4_and0 b=u_cla22_and12 out=u_cla22_or6
.subckt pg_logic a=a[5] b=b[5] pg_logic_or0=u_cla22_pg_logic5_or0 pg_logic_and0=u_cla22_pg_logic5_and0 pg_logic_xor0=u_cla22_pg_logic5_xor0
.subckt xor_gate a=u_cla22_pg_logic5_xor0 b=u_cla22_or6 out=u_cla22_xor5
.subckt and_gate a=u_cla22_or5 b=u_cla22_pg_logic5_or0 out=u_cla22_and13
.subckt and_gate a=u_cla22_and13 b=u_cla22_pg_logic4_or0 out=u_cla22_and14
.subckt and_gate a=u_cla22_pg_logic4_and0 b=u_cla22_pg_logic5_or0 out=u_cla22_and15
.subckt or_gate a=u_cla22_and14 b=u_cla22_and15 out=u_cla22_or7
.subckt or_gate a=u_cla22_pg_logic5_and0 b=u_cla22_or7 out=u_cla22_or8
.subckt pg_logic a=a[6] b=b[6] pg_logic_or0=u_cla22_pg_logic6_or0 pg_logic_and0=u_cla22_pg_logic6_and0 pg_logic_xor0=u_cla22_pg_logic6_xor0
.subckt xor_gate a=u_cla22_pg_logic6_xor0 b=u_cla22_or8 out=u_cla22_xor6
.subckt and_gate a=u_cla22_or5 b=u_cla22_pg_logic5_or0 out=u_cla22_and16
.subckt and_gate a=u_cla22_pg_logic6_or0 b=u_cla22_pg_logic4_or0 out=u_cla22_and17
.subckt and_gate a=u_cla22_and16 b=u_cla22_and17 out=u_cla22_and18
.subckt and_gate a=u_cla22_pg_logic4_and0 b=u_cla22_pg_logic6_or0 out=u_cla22_and19
.subckt and_gate a=u_cla22_and19 b=u_cla22_pg_logic5_or0 out=u_cla22_and20
.subckt and_gate a=u_cla22_pg_logic5_and0 b=u_cla22_pg_logic6_or0 out=u_cla22_and21
.subckt or_gate a=u_cla22_and18 b=u_cla22_and20 out=u_cla22_or9
.subckt or_gate a=u_cla22_or9 b=u_cla22_and21 out=u_cla22_or10
.subckt or_gate a=u_cla22_pg_logic6_and0 b=u_cla22_or10 out=u_cla22_or11
.subckt pg_logic a=a[7] b=b[7] pg_logic_or0=u_cla22_pg_logic7_or0 pg_logic_and0=u_cla22_pg_logic7_and0 pg_logic_xor0=u_cla22_pg_logic7_xor0
.subckt xor_gate a=u_cla22_pg_logic7_xor0 b=u_cla22_or11 out=u_cla22_xor7
.subckt and_gate a=u_cla22_or5 b=u_cla22_pg_logic6_or0 out=u_cla22_and22
.subckt and_gate a=u_cla22_pg_logic7_or0 b=u_cla22_pg_logic5_or0 out=u_cla22_and23
.subckt and_gate a=u_cla22_and22 b=u_cla22_and23 out=u_cla22_and24
.subckt and_gate a=u_cla22_and24 b=u_cla22_pg_logic4_or0 out=u_cla22_and25
.subckt and_gate a=u_cla22_pg_logic4_and0 b=u_cla22_pg_logic6_or0 out=u_cla22_and26
.subckt and_gate a=u_cla22_pg_logic7_or0 b=u_cla22_pg_logic5_or0 out=u_cla22_and27
.subckt and_gate a=u_cla22_and26 b=u_cla22_and27 out=u_cla22_and28
.subckt and_gate a=u_cla22_pg_logic5_and0 b=u_cla22_pg_logic7_or0 out=u_cla22_and29
.subckt and_gate a=u_cla22_and29 b=u_cla22_pg_logic6_or0 out=u_cla22_and30
.subckt and_gate a=u_cla22_pg_logic6_and0 b=u_cla22_pg_logic7_or0 out=u_cla22_and31
.subckt or_gate a=u_cla22_and25 b=u_cla22_and30 out=u_cla22_or12
.subckt or_gate a=u_cla22_and28 b=u_cla22_and31 out=u_cla22_or13
.subckt or_gate a=u_cla22_or12 b=u_cla22_or13 out=u_cla22_or14
.subckt or_gate a=u_cla22_pg_logic7_and0 b=u_cla22_or14 out=u_cla22_or15
.subckt pg_logic a=a[8] b=b[8] pg_logic_or0=u_cla22_pg_logic8_or0 pg_logic_and0=u_cla22_pg_logic8_and0 pg_logic_xor0=u_cla22_pg_logic8_xor0
.subckt xor_gate a=u_cla22_pg_logic8_xor0 b=u_cla22_or15 out=u_cla22_xor8
.subckt and_gate a=u_cla22_or15 b=u_cla22_pg_logic8_or0 out=u_cla22_and32
.subckt or_gate a=u_cla22_pg_logic8_and0 b=u_cla22_and32 out=u_cla22_or16
.subckt pg_logic a=a[9] b=b[9] pg_logic_or0=u_cla22_pg_logic9_or0 pg_logic_and0=u_cla22_pg_logic9_and0 pg_logic_xor0=u_cla22_pg_logic9_xor0
.subckt xor_gate a=u_cla22_pg_logic9_xor0 b=u_cla22_or16 out=u_cla22_xor9
.subckt and_gate a=u_cla22_or15 b=u_cla22_pg_logic9_or0 out=u_cla22_and33
.subckt and_gate a=u_cla22_and33 b=u_cla22_pg_logic8_or0 out=u_cla22_and34
.subckt and_gate a=u_cla22_pg_logic8_and0 b=u_cla22_pg_logic9_or0 out=u_cla22_and35
.subckt or_gate a=u_cla22_and34 b=u_cla22_and35 out=u_cla22_or17
.subckt or_gate a=u_cla22_pg_logic9_and0 b=u_cla22_or17 out=u_cla22_or18
.subckt pg_logic a=a[10] b=b[10] pg_logic_or0=u_cla22_pg_logic10_or0 pg_logic_and0=u_cla22_pg_logic10_and0 pg_logic_xor0=u_cla22_pg_logic10_xor0
.subckt xor_gate a=u_cla22_pg_logic10_xor0 b=u_cla22_or18 out=u_cla22_xor10
.subckt and_gate a=u_cla22_or15 b=u_cla22_pg_logic9_or0 out=u_cla22_and36
.subckt and_gate a=u_cla22_pg_logic10_or0 b=u_cla22_pg_logic8_or0 out=u_cla22_and37
.subckt and_gate a=u_cla22_and36 b=u_cla22_and37 out=u_cla22_and38
.subckt and_gate a=u_cla22_pg_logic8_and0 b=u_cla22_pg_logic10_or0 out=u_cla22_and39
.subckt and_gate a=u_cla22_and39 b=u_cla22_pg_logic9_or0 out=u_cla22_and40
.subckt and_gate a=u_cla22_pg_logic9_and0 b=u_cla22_pg_logic10_or0 out=u_cla22_and41
.subckt or_gate a=u_cla22_and38 b=u_cla22_and40 out=u_cla22_or19
.subckt or_gate a=u_cla22_or19 b=u_cla22_and41 out=u_cla22_or20
.subckt or_gate a=u_cla22_pg_logic10_and0 b=u_cla22_or20 out=u_cla22_or21
.subckt pg_logic a=a[11] b=b[11] pg_logic_or0=u_cla22_pg_logic11_or0 pg_logic_and0=u_cla22_pg_logic11_and0 pg_logic_xor0=u_cla22_pg_logic11_xor0
.subckt xor_gate a=u_cla22_pg_logic11_xor0 b=u_cla22_or21 out=u_cla22_xor11
.subckt and_gate a=u_cla22_or15 b=u_cla22_pg_logic10_or0 out=u_cla22_and42
.subckt and_gate a=u_cla22_pg_logic11_or0 b=u_cla22_pg_logic9_or0 out=u_cla22_and43
.subckt and_gate a=u_cla22_and42 b=u_cla22_and43 out=u_cla22_and44
.subckt and_gate a=u_cla22_and44 b=u_cla22_pg_logic8_or0 out=u_cla22_and45
.subckt and_gate a=u_cla22_pg_logic8_and0 b=u_cla22_pg_logic10_or0 out=u_cla22_and46
.subckt and_gate a=u_cla22_pg_logic11_or0 b=u_cla22_pg_logic9_or0 out=u_cla22_and47
.subckt and_gate a=u_cla22_and46 b=u_cla22_and47 out=u_cla22_and48
.subckt and_gate a=u_cla22_pg_logic9_and0 b=u_cla22_pg_logic11_or0 out=u_cla22_and49
.subckt and_gate a=u_cla22_and49 b=u_cla22_pg_logic10_or0 out=u_cla22_and50
.subckt and_gate a=u_cla22_pg_logic10_and0 b=u_cla22_pg_logic11_or0 out=u_cla22_and51
.subckt or_gate a=u_cla22_and45 b=u_cla22_and50 out=u_cla22_or22
.subckt or_gate a=u_cla22_and48 b=u_cla22_and51 out=u_cla22_or23
.subckt or_gate a=u_cla22_or22 b=u_cla22_or23 out=u_cla22_or24
.subckt or_gate a=u_cla22_pg_logic11_and0 b=u_cla22_or24 out=u_cla22_or25
.subckt pg_logic a=a[12] b=b[12] pg_logic_or0=u_cla22_pg_logic12_or0 pg_logic_and0=u_cla22_pg_logic12_and0 pg_logic_xor0=u_cla22_pg_logic12_xor0
.subckt xor_gate a=u_cla22_pg_logic12_xor0 b=u_cla22_or25 out=u_cla22_xor12
.subckt and_gate a=u_cla22_or25 b=u_cla22_pg_logic12_or0 out=u_cla22_and52
.subckt or_gate a=u_cla22_pg_logic12_and0 b=u_cla22_and52 out=u_cla22_or26
.subckt pg_logic a=a[13] b=b[13] pg_logic_or0=u_cla22_pg_logic13_or0 pg_logic_and0=u_cla22_pg_logic13_and0 pg_logic_xor0=u_cla22_pg_logic13_xor0
.subckt xor_gate a=u_cla22_pg_logic13_xor0 b=u_cla22_or26 out=u_cla22_xor13
.subckt and_gate a=u_cla22_or25 b=u_cla22_pg_logic13_or0 out=u_cla22_and53
.subckt and_gate a=u_cla22_and53 b=u_cla22_pg_logic12_or0 out=u_cla22_and54
.subckt and_gate a=u_cla22_pg_logic12_and0 b=u_cla22_pg_logic13_or0 out=u_cla22_and55
.subckt or_gate a=u_cla22_and54 b=u_cla22_and55 out=u_cla22_or27
.subckt or_gate a=u_cla22_pg_logic13_and0 b=u_cla22_or27 out=u_cla22_or28
.subckt pg_logic a=a[14] b=b[14] pg_logic_or0=u_cla22_pg_logic14_or0 pg_logic_and0=u_cla22_pg_logic14_and0 pg_logic_xor0=u_cla22_pg_logic14_xor0
.subckt xor_gate a=u_cla22_pg_logic14_xor0 b=u_cla22_or28 out=u_cla22_xor14
.subckt and_gate a=u_cla22_or25 b=u_cla22_pg_logic13_or0 out=u_cla22_and56
.subckt and_gate a=u_cla22_pg_logic14_or0 b=u_cla22_pg_logic12_or0 out=u_cla22_and57
.subckt and_gate a=u_cla22_and56 b=u_cla22_and57 out=u_cla22_and58
.subckt and_gate a=u_cla22_pg_logic12_and0 b=u_cla22_pg_logic14_or0 out=u_cla22_and59
.subckt and_gate a=u_cla22_and59 b=u_cla22_pg_logic13_or0 out=u_cla22_and60
.subckt and_gate a=u_cla22_pg_logic13_and0 b=u_cla22_pg_logic14_or0 out=u_cla22_and61
.subckt or_gate a=u_cla22_and58 b=u_cla22_and60 out=u_cla22_or29
.subckt or_gate a=u_cla22_or29 b=u_cla22_and61 out=u_cla22_or30
.subckt or_gate a=u_cla22_pg_logic14_and0 b=u_cla22_or30 out=u_cla22_or31
.subckt pg_logic a=a[15] b=b[15] pg_logic_or0=u_cla22_pg_logic15_or0 pg_logic_and0=u_cla22_pg_logic15_and0 pg_logic_xor0=u_cla22_pg_logic15_xor0
.subckt xor_gate a=u_cla22_pg_logic15_xor0 b=u_cla22_or31 out=u_cla22_xor15
.subckt and_gate a=u_cla22_or25 b=u_cla22_pg_logic14_or0 out=u_cla22_and62
.subckt and_gate a=u_cla22_pg_logic15_or0 b=u_cla22_pg_logic13_or0 out=u_cla22_and63
.subckt and_gate a=u_cla22_and62 b=u_cla22_and63 out=u_cla22_and64
.subckt and_gate a=u_cla22_and64 b=u_cla22_pg_logic12_or0 out=u_cla22_and65
.subckt and_gate a=u_cla22_pg_logic12_and0 b=u_cla22_pg_logic14_or0 out=u_cla22_and66
.subckt and_gate a=u_cla22_pg_logic15_or0 b=u_cla22_pg_logic13_or0 out=u_cla22_and67
.subckt and_gate a=u_cla22_and66 b=u_cla22_and67 out=u_cla22_and68
.subckt and_gate a=u_cla22_pg_logic13_and0 b=u_cla22_pg_logic15_or0 out=u_cla22_and69
.subckt and_gate a=u_cla22_and69 b=u_cla22_pg_logic14_or0 out=u_cla22_and70
.subckt and_gate a=u_cla22_pg_logic14_and0 b=u_cla22_pg_logic15_or0 out=u_cla22_and71
.subckt or_gate a=u_cla22_and65 b=u_cla22_and70 out=u_cla22_or32
.subckt or_gate a=u_cla22_and68 b=u_cla22_and71 out=u_cla22_or33
.subckt or_gate a=u_cla22_or32 b=u_cla22_or33 out=u_cla22_or34
.subckt or_gate a=u_cla22_pg_logic15_and0 b=u_cla22_or34 out=u_cla22_or35
.subckt pg_logic a=a[16] b=b[16] pg_logic_or0=u_cla22_pg_logic16_or0 pg_logic_and0=u_cla22_pg_logic16_and0 pg_logic_xor0=u_cla22_pg_logic16_xor0
.subckt xor_gate a=u_cla22_pg_logic16_xor0 b=u_cla22_or35 out=u_cla22_xor16
.subckt and_gate a=u_cla22_or35 b=u_cla22_pg_logic16_or0 out=u_cla22_and72
.subckt or_gate a=u_cla22_pg_logic16_and0 b=u_cla22_and72 out=u_cla22_or36
.subckt pg_logic a=a[17] b=b[17] pg_logic_or0=u_cla22_pg_logic17_or0 pg_logic_and0=u_cla22_pg_logic17_and0 pg_logic_xor0=u_cla22_pg_logic17_xor0
.subckt xor_gate a=u_cla22_pg_logic17_xor0 b=u_cla22_or36 out=u_cla22_xor17
.subckt and_gate a=u_cla22_or35 b=u_cla22_pg_logic17_or0 out=u_cla22_and73
.subckt and_gate a=u_cla22_and73 b=u_cla22_pg_logic16_or0 out=u_cla22_and74
.subckt and_gate a=u_cla22_pg_logic16_and0 b=u_cla22_pg_logic17_or0 out=u_cla22_and75
.subckt or_gate a=u_cla22_and74 b=u_cla22_and75 out=u_cla22_or37
.subckt or_gate a=u_cla22_pg_logic17_and0 b=u_cla22_or37 out=u_cla22_or38
.subckt pg_logic a=a[18] b=b[18] pg_logic_or0=u_cla22_pg_logic18_or0 pg_logic_and0=u_cla22_pg_logic18_and0 pg_logic_xor0=u_cla22_pg_logic18_xor0
.subckt xor_gate a=u_cla22_pg_logic18_xor0 b=u_cla22_or38 out=u_cla22_xor18
.subckt and_gate a=u_cla22_or35 b=u_cla22_pg_logic17_or0 out=u_cla22_and76
.subckt and_gate a=u_cla22_pg_logic18_or0 b=u_cla22_pg_logic16_or0 out=u_cla22_and77
.subckt and_gate a=u_cla22_and76 b=u_cla22_and77 out=u_cla22_and78
.subckt and_gate a=u_cla22_pg_logic16_and0 b=u_cla22_pg_logic18_or0 out=u_cla22_and79
.subckt and_gate a=u_cla22_and79 b=u_cla22_pg_logic17_or0 out=u_cla22_and80
.subckt and_gate a=u_cla22_pg_logic17_and0 b=u_cla22_pg_logic18_or0 out=u_cla22_and81
.subckt or_gate a=u_cla22_and78 b=u_cla22_and80 out=u_cla22_or39
.subckt or_gate a=u_cla22_or39 b=u_cla22_and81 out=u_cla22_or40
.subckt or_gate a=u_cla22_pg_logic18_and0 b=u_cla22_or40 out=u_cla22_or41
.subckt pg_logic a=a[19] b=b[19] pg_logic_or0=u_cla22_pg_logic19_or0 pg_logic_and0=u_cla22_pg_logic19_and0 pg_logic_xor0=u_cla22_pg_logic19_xor0
.subckt xor_gate a=u_cla22_pg_logic19_xor0 b=u_cla22_or41 out=u_cla22_xor19
.subckt and_gate a=u_cla22_or35 b=u_cla22_pg_logic18_or0 out=u_cla22_and82
.subckt and_gate a=u_cla22_pg_logic19_or0 b=u_cla22_pg_logic17_or0 out=u_cla22_and83
.subckt and_gate a=u_cla22_and82 b=u_cla22_and83 out=u_cla22_and84
.subckt and_gate a=u_cla22_and84 b=u_cla22_pg_logic16_or0 out=u_cla22_and85
.subckt and_gate a=u_cla22_pg_logic16_and0 b=u_cla22_pg_logic18_or0 out=u_cla22_and86
.subckt and_gate a=u_cla22_pg_logic19_or0 b=u_cla22_pg_logic17_or0 out=u_cla22_and87
.subckt and_gate a=u_cla22_and86 b=u_cla22_and87 out=u_cla22_and88
.subckt and_gate a=u_cla22_pg_logic17_and0 b=u_cla22_pg_logic19_or0 out=u_cla22_and89
.subckt and_gate a=u_cla22_and89 b=u_cla22_pg_logic18_or0 out=u_cla22_and90
.subckt and_gate a=u_cla22_pg_logic18_and0 b=u_cla22_pg_logic19_or0 out=u_cla22_and91
.subckt or_gate a=u_cla22_and85 b=u_cla22_and90 out=u_cla22_or42
.subckt or_gate a=u_cla22_and88 b=u_cla22_and91 out=u_cla22_or43
.subckt or_gate a=u_cla22_or42 b=u_cla22_or43 out=u_cla22_or44
.subckt or_gate a=u_cla22_pg_logic19_and0 b=u_cla22_or44 out=u_cla22_or45
.subckt pg_logic a=a[20] b=b[20] pg_logic_or0=u_cla22_pg_logic20_or0 pg_logic_and0=u_cla22_pg_logic20_and0 pg_logic_xor0=u_cla22_pg_logic20_xor0
.subckt xor_gate a=u_cla22_pg_logic20_xor0 b=u_cla22_or45 out=u_cla22_xor20
.subckt and_gate a=u_cla22_or45 b=u_cla22_pg_logic20_or0 out=u_cla22_and92
.subckt or_gate a=u_cla22_pg_logic20_and0 b=u_cla22_and92 out=u_cla22_or46
.subckt pg_logic a=a[21] b=b[21] pg_logic_or0=u_cla22_pg_logic21_or0 pg_logic_and0=u_cla22_pg_logic21_and0 pg_logic_xor0=u_cla22_pg_logic21_xor0
.subckt xor_gate a=u_cla22_pg_logic21_xor0 b=u_cla22_or46 out=u_cla22_xor21
.subckt and_gate a=u_cla22_or45 b=u_cla22_pg_logic21_or0 out=u_cla22_and93
.subckt and_gate a=u_cla22_and93 b=u_cla22_pg_logic20_or0 out=u_cla22_and94
.subckt and_gate a=u_cla22_pg_logic20_and0 b=u_cla22_pg_logic21_or0 out=u_cla22_and95
.subckt or_gate a=u_cla22_and94 b=u_cla22_and95 out=u_cla22_or47
.subckt or_gate a=u_cla22_pg_logic21_and0 b=u_cla22_or47 out=u_cla22_or48
.names u_cla22_pg_logic0_xor0 u_cla22_out[0]
1 1
.names u_cla22_xor1 u_cla22_out[1]
1 1
.names u_cla22_xor2 u_cla22_out[2]
1 1
.names u_cla22_xor3 u_cla22_out[3]
1 1
.names u_cla22_xor4 u_cla22_out[4]
1 1
.names u_cla22_xor5 u_cla22_out[5]
1 1
.names u_cla22_xor6 u_cla22_out[6]
1 1
.names u_cla22_xor7 u_cla22_out[7]
1 1
.names u_cla22_xor8 u_cla22_out[8]
1 1
.names u_cla22_xor9 u_cla22_out[9]
1 1
.names u_cla22_xor10 u_cla22_out[10]
1 1
.names u_cla22_xor11 u_cla22_out[11]
1 1
.names u_cla22_xor12 u_cla22_out[12]
1 1
.names u_cla22_xor13 u_cla22_out[13]
1 1
.names u_cla22_xor14 u_cla22_out[14]
1 1
.names u_cla22_xor15 u_cla22_out[15]
1 1
.names u_cla22_xor16 u_cla22_out[16]
1 1
.names u_cla22_xor17 u_cla22_out[17]
1 1
.names u_cla22_xor18 u_cla22_out[18]
1 1
.names u_cla22_xor19 u_cla22_out[19]
1 1
.names u_cla22_xor20 u_cla22_out[20]
1 1
.names u_cla22_xor21 u_cla22_out[21]
1 1
.names u_cla22_or48 u_cla22_out[22]
1 1
.end

.model pg_logic
.inputs a b
.outputs pg_logic_or0 pg_logic_and0 pg_logic_xor0
.names vdd
1
.names gnd
0
.subckt or_gate a=a b=b out=pg_logic_or0
.subckt and_gate a=a b=b out=pg_logic_and0
.subckt xor_gate a=a b=b out=pg_logic_xor0
.end

.model fa
.inputs a b cin
.outputs fa_xor1 fa_or0
.names vdd
1
.names gnd
0
.subckt xor_gate a=a b=b out=fa_xor0
.subckt and_gate a=a b=b out=fa_and0
.subckt xor_gate a=fa_xor0 b=cin out=fa_xor1
.subckt and_gate a=fa_xor0 b=cin out=fa_and1
.subckt or_gate a=fa_and0 b=fa_and1 out=fa_or0
.end

.model ha
.inputs a b
.outputs ha_xor0 ha_and0
.names vdd
1
.names gnd
0
.subckt xor_gate a=a b=b out=ha_xor0
.subckt and_gate a=a b=b out=ha_and0
.end

.model or_gate
.inputs a b
.outputs out
.names vdd
1
.names gnd
0
.names a b out
1- 1
-1 1
.end

.model xor_gate
.inputs a b
.outputs out
.names vdd
1
.names gnd
0
.names a b out
01 1
10 1
.end

.model and_gate
.inputs a b
.outputs out
.names vdd
1
.names gnd
0
.names a b out
11 1
.end