.model s_wallace_cla32
.inputs a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] a[8] a[9] a[10] a[11] a[12] a[13] a[14] a[15] a[16] a[17] a[18] a[19] a[20] a[21] a[22] a[23] a[24] a[25] a[26] a[27] a[28] a[29] a[30] a[31] b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9] b[10] b[11] b[12] b[13] b[14] b[15] b[16] b[17] b[18] b[19] b[20] b[21] b[22] b[23] b[24] b[25] b[26] b[27] b[28] b[29] b[30] b[31]
.outputs s_wallace_cla32_out[0] s_wallace_cla32_out[1] s_wallace_cla32_out[2] s_wallace_cla32_out[3] s_wallace_cla32_out[4] s_wallace_cla32_out[5] s_wallace_cla32_out[6] s_wallace_cla32_out[7] s_wallace_cla32_out[8] s_wallace_cla32_out[9] s_wallace_cla32_out[10] s_wallace_cla32_out[11] s_wallace_cla32_out[12] s_wallace_cla32_out[13] s_wallace_cla32_out[14] s_wallace_cla32_out[15] s_wallace_cla32_out[16] s_wallace_cla32_out[17] s_wallace_cla32_out[18] s_wallace_cla32_out[19] s_wallace_cla32_out[20] s_wallace_cla32_out[21] s_wallace_cla32_out[22] s_wallace_cla32_out[23] s_wallace_cla32_out[24] s_wallace_cla32_out[25] s_wallace_cla32_out[26] s_wallace_cla32_out[27] s_wallace_cla32_out[28] s_wallace_cla32_out[29] s_wallace_cla32_out[30] s_wallace_cla32_out[31] s_wallace_cla32_out[32] s_wallace_cla32_out[33] s_wallace_cla32_out[34] s_wallace_cla32_out[35] s_wallace_cla32_out[36] s_wallace_cla32_out[37] s_wallace_cla32_out[38] s_wallace_cla32_out[39] s_wallace_cla32_out[40] s_wallace_cla32_out[41] s_wallace_cla32_out[42] s_wallace_cla32_out[43] s_wallace_cla32_out[44] s_wallace_cla32_out[45] s_wallace_cla32_out[46] s_wallace_cla32_out[47] s_wallace_cla32_out[48] s_wallace_cla32_out[49] s_wallace_cla32_out[50] s_wallace_cla32_out[51] s_wallace_cla32_out[52] s_wallace_cla32_out[53] s_wallace_cla32_out[54] s_wallace_cla32_out[55] s_wallace_cla32_out[56] s_wallace_cla32_out[57] s_wallace_cla32_out[58] s_wallace_cla32_out[59] s_wallace_cla32_out[60] s_wallace_cla32_out[61] s_wallace_cla32_out[62] s_wallace_cla32_out[63]
.names vdd
1
.names gnd
0
.subckt and_gate a=a[2] b=b[0] out=s_wallace_cla32_and_2_0
.subckt and_gate a=a[1] b=b[1] out=s_wallace_cla32_and_1_1
.subckt ha a=s_wallace_cla32_and_2_0 b=s_wallace_cla32_and_1_1 ha_xor0=s_wallace_cla32_ha0_xor0 ha_and0=s_wallace_cla32_ha0_and0
.subckt and_gate a=a[3] b=b[0] out=s_wallace_cla32_and_3_0
.subckt and_gate a=a[2] b=b[1] out=s_wallace_cla32_and_2_1
.subckt fa a=s_wallace_cla32_ha0_and0 b=s_wallace_cla32_and_3_0 cin=s_wallace_cla32_and_2_1 fa_xor1=s_wallace_cla32_fa0_xor1 fa_or0=s_wallace_cla32_fa0_or0
.subckt and_gate a=a[4] b=b[0] out=s_wallace_cla32_and_4_0
.subckt and_gate a=a[3] b=b[1] out=s_wallace_cla32_and_3_1
.subckt fa a=s_wallace_cla32_fa0_or0 b=s_wallace_cla32_and_4_0 cin=s_wallace_cla32_and_3_1 fa_xor1=s_wallace_cla32_fa1_xor1 fa_or0=s_wallace_cla32_fa1_or0
.subckt and_gate a=a[5] b=b[0] out=s_wallace_cla32_and_5_0
.subckt and_gate a=a[4] b=b[1] out=s_wallace_cla32_and_4_1
.subckt fa a=s_wallace_cla32_fa1_or0 b=s_wallace_cla32_and_5_0 cin=s_wallace_cla32_and_4_1 fa_xor1=s_wallace_cla32_fa2_xor1 fa_or0=s_wallace_cla32_fa2_or0
.subckt and_gate a=a[6] b=b[0] out=s_wallace_cla32_and_6_0
.subckt and_gate a=a[5] b=b[1] out=s_wallace_cla32_and_5_1
.subckt fa a=s_wallace_cla32_fa2_or0 b=s_wallace_cla32_and_6_0 cin=s_wallace_cla32_and_5_1 fa_xor1=s_wallace_cla32_fa3_xor1 fa_or0=s_wallace_cla32_fa3_or0
.subckt and_gate a=a[7] b=b[0] out=s_wallace_cla32_and_7_0
.subckt and_gate a=a[6] b=b[1] out=s_wallace_cla32_and_6_1
.subckt fa a=s_wallace_cla32_fa3_or0 b=s_wallace_cla32_and_7_0 cin=s_wallace_cla32_and_6_1 fa_xor1=s_wallace_cla32_fa4_xor1 fa_or0=s_wallace_cla32_fa4_or0
.subckt and_gate a=a[8] b=b[0] out=s_wallace_cla32_and_8_0
.subckt and_gate a=a[7] b=b[1] out=s_wallace_cla32_and_7_1
.subckt fa a=s_wallace_cla32_fa4_or0 b=s_wallace_cla32_and_8_0 cin=s_wallace_cla32_and_7_1 fa_xor1=s_wallace_cla32_fa5_xor1 fa_or0=s_wallace_cla32_fa5_or0
.subckt and_gate a=a[9] b=b[0] out=s_wallace_cla32_and_9_0
.subckt and_gate a=a[8] b=b[1] out=s_wallace_cla32_and_8_1
.subckt fa a=s_wallace_cla32_fa5_or0 b=s_wallace_cla32_and_9_0 cin=s_wallace_cla32_and_8_1 fa_xor1=s_wallace_cla32_fa6_xor1 fa_or0=s_wallace_cla32_fa6_or0
.subckt and_gate a=a[10] b=b[0] out=s_wallace_cla32_and_10_0
.subckt and_gate a=a[9] b=b[1] out=s_wallace_cla32_and_9_1
.subckt fa a=s_wallace_cla32_fa6_or0 b=s_wallace_cla32_and_10_0 cin=s_wallace_cla32_and_9_1 fa_xor1=s_wallace_cla32_fa7_xor1 fa_or0=s_wallace_cla32_fa7_or0
.subckt and_gate a=a[11] b=b[0] out=s_wallace_cla32_and_11_0
.subckt and_gate a=a[10] b=b[1] out=s_wallace_cla32_and_10_1
.subckt fa a=s_wallace_cla32_fa7_or0 b=s_wallace_cla32_and_11_0 cin=s_wallace_cla32_and_10_1 fa_xor1=s_wallace_cla32_fa8_xor1 fa_or0=s_wallace_cla32_fa8_or0
.subckt and_gate a=a[12] b=b[0] out=s_wallace_cla32_and_12_0
.subckt and_gate a=a[11] b=b[1] out=s_wallace_cla32_and_11_1
.subckt fa a=s_wallace_cla32_fa8_or0 b=s_wallace_cla32_and_12_0 cin=s_wallace_cla32_and_11_1 fa_xor1=s_wallace_cla32_fa9_xor1 fa_or0=s_wallace_cla32_fa9_or0
.subckt and_gate a=a[13] b=b[0] out=s_wallace_cla32_and_13_0
.subckt and_gate a=a[12] b=b[1] out=s_wallace_cla32_and_12_1
.subckt fa a=s_wallace_cla32_fa9_or0 b=s_wallace_cla32_and_13_0 cin=s_wallace_cla32_and_12_1 fa_xor1=s_wallace_cla32_fa10_xor1 fa_or0=s_wallace_cla32_fa10_or0
.subckt and_gate a=a[14] b=b[0] out=s_wallace_cla32_and_14_0
.subckt and_gate a=a[13] b=b[1] out=s_wallace_cla32_and_13_1
.subckt fa a=s_wallace_cla32_fa10_or0 b=s_wallace_cla32_and_14_0 cin=s_wallace_cla32_and_13_1 fa_xor1=s_wallace_cla32_fa11_xor1 fa_or0=s_wallace_cla32_fa11_or0
.subckt and_gate a=a[15] b=b[0] out=s_wallace_cla32_and_15_0
.subckt and_gate a=a[14] b=b[1] out=s_wallace_cla32_and_14_1
.subckt fa a=s_wallace_cla32_fa11_or0 b=s_wallace_cla32_and_15_0 cin=s_wallace_cla32_and_14_1 fa_xor1=s_wallace_cla32_fa12_xor1 fa_or0=s_wallace_cla32_fa12_or0
.subckt and_gate a=a[16] b=b[0] out=s_wallace_cla32_and_16_0
.subckt and_gate a=a[15] b=b[1] out=s_wallace_cla32_and_15_1
.subckt fa a=s_wallace_cla32_fa12_or0 b=s_wallace_cla32_and_16_0 cin=s_wallace_cla32_and_15_1 fa_xor1=s_wallace_cla32_fa13_xor1 fa_or0=s_wallace_cla32_fa13_or0
.subckt and_gate a=a[17] b=b[0] out=s_wallace_cla32_and_17_0
.subckt and_gate a=a[16] b=b[1] out=s_wallace_cla32_and_16_1
.subckt fa a=s_wallace_cla32_fa13_or0 b=s_wallace_cla32_and_17_0 cin=s_wallace_cla32_and_16_1 fa_xor1=s_wallace_cla32_fa14_xor1 fa_or0=s_wallace_cla32_fa14_or0
.subckt and_gate a=a[18] b=b[0] out=s_wallace_cla32_and_18_0
.subckt and_gate a=a[17] b=b[1] out=s_wallace_cla32_and_17_1
.subckt fa a=s_wallace_cla32_fa14_or0 b=s_wallace_cla32_and_18_0 cin=s_wallace_cla32_and_17_1 fa_xor1=s_wallace_cla32_fa15_xor1 fa_or0=s_wallace_cla32_fa15_or0
.subckt and_gate a=a[19] b=b[0] out=s_wallace_cla32_and_19_0
.subckt and_gate a=a[18] b=b[1] out=s_wallace_cla32_and_18_1
.subckt fa a=s_wallace_cla32_fa15_or0 b=s_wallace_cla32_and_19_0 cin=s_wallace_cla32_and_18_1 fa_xor1=s_wallace_cla32_fa16_xor1 fa_or0=s_wallace_cla32_fa16_or0
.subckt and_gate a=a[20] b=b[0] out=s_wallace_cla32_and_20_0
.subckt and_gate a=a[19] b=b[1] out=s_wallace_cla32_and_19_1
.subckt fa a=s_wallace_cla32_fa16_or0 b=s_wallace_cla32_and_20_0 cin=s_wallace_cla32_and_19_1 fa_xor1=s_wallace_cla32_fa17_xor1 fa_or0=s_wallace_cla32_fa17_or0
.subckt and_gate a=a[21] b=b[0] out=s_wallace_cla32_and_21_0
.subckt and_gate a=a[20] b=b[1] out=s_wallace_cla32_and_20_1
.subckt fa a=s_wallace_cla32_fa17_or0 b=s_wallace_cla32_and_21_0 cin=s_wallace_cla32_and_20_1 fa_xor1=s_wallace_cla32_fa18_xor1 fa_or0=s_wallace_cla32_fa18_or0
.subckt and_gate a=a[22] b=b[0] out=s_wallace_cla32_and_22_0
.subckt and_gate a=a[21] b=b[1] out=s_wallace_cla32_and_21_1
.subckt fa a=s_wallace_cla32_fa18_or0 b=s_wallace_cla32_and_22_0 cin=s_wallace_cla32_and_21_1 fa_xor1=s_wallace_cla32_fa19_xor1 fa_or0=s_wallace_cla32_fa19_or0
.subckt and_gate a=a[23] b=b[0] out=s_wallace_cla32_and_23_0
.subckt and_gate a=a[22] b=b[1] out=s_wallace_cla32_and_22_1
.subckt fa a=s_wallace_cla32_fa19_or0 b=s_wallace_cla32_and_23_0 cin=s_wallace_cla32_and_22_1 fa_xor1=s_wallace_cla32_fa20_xor1 fa_or0=s_wallace_cla32_fa20_or0
.subckt and_gate a=a[24] b=b[0] out=s_wallace_cla32_and_24_0
.subckt and_gate a=a[23] b=b[1] out=s_wallace_cla32_and_23_1
.subckt fa a=s_wallace_cla32_fa20_or0 b=s_wallace_cla32_and_24_0 cin=s_wallace_cla32_and_23_1 fa_xor1=s_wallace_cla32_fa21_xor1 fa_or0=s_wallace_cla32_fa21_or0
.subckt and_gate a=a[25] b=b[0] out=s_wallace_cla32_and_25_0
.subckt and_gate a=a[24] b=b[1] out=s_wallace_cla32_and_24_1
.subckt fa a=s_wallace_cla32_fa21_or0 b=s_wallace_cla32_and_25_0 cin=s_wallace_cla32_and_24_1 fa_xor1=s_wallace_cla32_fa22_xor1 fa_or0=s_wallace_cla32_fa22_or0
.subckt and_gate a=a[26] b=b[0] out=s_wallace_cla32_and_26_0
.subckt and_gate a=a[25] b=b[1] out=s_wallace_cla32_and_25_1
.subckt fa a=s_wallace_cla32_fa22_or0 b=s_wallace_cla32_and_26_0 cin=s_wallace_cla32_and_25_1 fa_xor1=s_wallace_cla32_fa23_xor1 fa_or0=s_wallace_cla32_fa23_or0
.subckt and_gate a=a[27] b=b[0] out=s_wallace_cla32_and_27_0
.subckt and_gate a=a[26] b=b[1] out=s_wallace_cla32_and_26_1
.subckt fa a=s_wallace_cla32_fa23_or0 b=s_wallace_cla32_and_27_0 cin=s_wallace_cla32_and_26_1 fa_xor1=s_wallace_cla32_fa24_xor1 fa_or0=s_wallace_cla32_fa24_or0
.subckt and_gate a=a[28] b=b[0] out=s_wallace_cla32_and_28_0
.subckt and_gate a=a[27] b=b[1] out=s_wallace_cla32_and_27_1
.subckt fa a=s_wallace_cla32_fa24_or0 b=s_wallace_cla32_and_28_0 cin=s_wallace_cla32_and_27_1 fa_xor1=s_wallace_cla32_fa25_xor1 fa_or0=s_wallace_cla32_fa25_or0
.subckt and_gate a=a[29] b=b[0] out=s_wallace_cla32_and_29_0
.subckt and_gate a=a[28] b=b[1] out=s_wallace_cla32_and_28_1
.subckt fa a=s_wallace_cla32_fa25_or0 b=s_wallace_cla32_and_29_0 cin=s_wallace_cla32_and_28_1 fa_xor1=s_wallace_cla32_fa26_xor1 fa_or0=s_wallace_cla32_fa26_or0
.subckt and_gate a=a[30] b=b[0] out=s_wallace_cla32_and_30_0
.subckt and_gate a=a[29] b=b[1] out=s_wallace_cla32_and_29_1
.subckt fa a=s_wallace_cla32_fa26_or0 b=s_wallace_cla32_and_30_0 cin=s_wallace_cla32_and_29_1 fa_xor1=s_wallace_cla32_fa27_xor1 fa_or0=s_wallace_cla32_fa27_or0
.subckt nand_gate a=a[31] b=b[0] out=s_wallace_cla32_nand_31_0
.subckt and_gate a=a[30] b=b[1] out=s_wallace_cla32_and_30_1
.subckt fa a=s_wallace_cla32_fa27_or0 b=s_wallace_cla32_nand_31_0 cin=s_wallace_cla32_and_30_1 fa_xor1=s_wallace_cla32_fa28_xor1 fa_or0=s_wallace_cla32_fa28_or0
.subckt nand_gate a=a[31] b=b[1] out=s_wallace_cla32_nand_31_1
.subckt fa a=s_wallace_cla32_fa28_or0 b=vdd cin=s_wallace_cla32_nand_31_1 fa_xor1=s_wallace_cla32_fa29_xor1 fa_or0=s_wallace_cla32_fa29_or0
.subckt nand_gate a=a[31] b=b[2] out=s_wallace_cla32_nand_31_2
.subckt and_gate a=a[30] b=b[3] out=s_wallace_cla32_and_30_3
.subckt fa a=s_wallace_cla32_fa29_or0 b=s_wallace_cla32_nand_31_2 cin=s_wallace_cla32_and_30_3 fa_xor1=s_wallace_cla32_fa30_xor1 fa_or0=s_wallace_cla32_fa30_or0
.subckt nand_gate a=a[31] b=b[3] out=s_wallace_cla32_nand_31_3
.subckt and_gate a=a[30] b=b[4] out=s_wallace_cla32_and_30_4
.subckt fa a=s_wallace_cla32_fa30_or0 b=s_wallace_cla32_nand_31_3 cin=s_wallace_cla32_and_30_4 fa_xor1=s_wallace_cla32_fa31_xor1 fa_or0=s_wallace_cla32_fa31_or0
.subckt nand_gate a=a[31] b=b[4] out=s_wallace_cla32_nand_31_4
.subckt and_gate a=a[30] b=b[5] out=s_wallace_cla32_and_30_5
.subckt fa a=s_wallace_cla32_fa31_or0 b=s_wallace_cla32_nand_31_4 cin=s_wallace_cla32_and_30_5 fa_xor1=s_wallace_cla32_fa32_xor1 fa_or0=s_wallace_cla32_fa32_or0
.subckt nand_gate a=a[31] b=b[5] out=s_wallace_cla32_nand_31_5
.subckt and_gate a=a[30] b=b[6] out=s_wallace_cla32_and_30_6
.subckt fa a=s_wallace_cla32_fa32_or0 b=s_wallace_cla32_nand_31_5 cin=s_wallace_cla32_and_30_6 fa_xor1=s_wallace_cla32_fa33_xor1 fa_or0=s_wallace_cla32_fa33_or0
.subckt nand_gate a=a[31] b=b[6] out=s_wallace_cla32_nand_31_6
.subckt and_gate a=a[30] b=b[7] out=s_wallace_cla32_and_30_7
.subckt fa a=s_wallace_cla32_fa33_or0 b=s_wallace_cla32_nand_31_6 cin=s_wallace_cla32_and_30_7 fa_xor1=s_wallace_cla32_fa34_xor1 fa_or0=s_wallace_cla32_fa34_or0
.subckt nand_gate a=a[31] b=b[7] out=s_wallace_cla32_nand_31_7
.subckt and_gate a=a[30] b=b[8] out=s_wallace_cla32_and_30_8
.subckt fa a=s_wallace_cla32_fa34_or0 b=s_wallace_cla32_nand_31_7 cin=s_wallace_cla32_and_30_8 fa_xor1=s_wallace_cla32_fa35_xor1 fa_or0=s_wallace_cla32_fa35_or0
.subckt nand_gate a=a[31] b=b[8] out=s_wallace_cla32_nand_31_8
.subckt and_gate a=a[30] b=b[9] out=s_wallace_cla32_and_30_9
.subckt fa a=s_wallace_cla32_fa35_or0 b=s_wallace_cla32_nand_31_8 cin=s_wallace_cla32_and_30_9 fa_xor1=s_wallace_cla32_fa36_xor1 fa_or0=s_wallace_cla32_fa36_or0
.subckt nand_gate a=a[31] b=b[9] out=s_wallace_cla32_nand_31_9
.subckt and_gate a=a[30] b=b[10] out=s_wallace_cla32_and_30_10
.subckt fa a=s_wallace_cla32_fa36_or0 b=s_wallace_cla32_nand_31_9 cin=s_wallace_cla32_and_30_10 fa_xor1=s_wallace_cla32_fa37_xor1 fa_or0=s_wallace_cla32_fa37_or0
.subckt nand_gate a=a[31] b=b[10] out=s_wallace_cla32_nand_31_10
.subckt and_gate a=a[30] b=b[11] out=s_wallace_cla32_and_30_11
.subckt fa a=s_wallace_cla32_fa37_or0 b=s_wallace_cla32_nand_31_10 cin=s_wallace_cla32_and_30_11 fa_xor1=s_wallace_cla32_fa38_xor1 fa_or0=s_wallace_cla32_fa38_or0
.subckt nand_gate a=a[31] b=b[11] out=s_wallace_cla32_nand_31_11
.subckt and_gate a=a[30] b=b[12] out=s_wallace_cla32_and_30_12
.subckt fa a=s_wallace_cla32_fa38_or0 b=s_wallace_cla32_nand_31_11 cin=s_wallace_cla32_and_30_12 fa_xor1=s_wallace_cla32_fa39_xor1 fa_or0=s_wallace_cla32_fa39_or0
.subckt nand_gate a=a[31] b=b[12] out=s_wallace_cla32_nand_31_12
.subckt and_gate a=a[30] b=b[13] out=s_wallace_cla32_and_30_13
.subckt fa a=s_wallace_cla32_fa39_or0 b=s_wallace_cla32_nand_31_12 cin=s_wallace_cla32_and_30_13 fa_xor1=s_wallace_cla32_fa40_xor1 fa_or0=s_wallace_cla32_fa40_or0
.subckt nand_gate a=a[31] b=b[13] out=s_wallace_cla32_nand_31_13
.subckt and_gate a=a[30] b=b[14] out=s_wallace_cla32_and_30_14
.subckt fa a=s_wallace_cla32_fa40_or0 b=s_wallace_cla32_nand_31_13 cin=s_wallace_cla32_and_30_14 fa_xor1=s_wallace_cla32_fa41_xor1 fa_or0=s_wallace_cla32_fa41_or0
.subckt nand_gate a=a[31] b=b[14] out=s_wallace_cla32_nand_31_14
.subckt and_gate a=a[30] b=b[15] out=s_wallace_cla32_and_30_15
.subckt fa a=s_wallace_cla32_fa41_or0 b=s_wallace_cla32_nand_31_14 cin=s_wallace_cla32_and_30_15 fa_xor1=s_wallace_cla32_fa42_xor1 fa_or0=s_wallace_cla32_fa42_or0
.subckt nand_gate a=a[31] b=b[15] out=s_wallace_cla32_nand_31_15
.subckt and_gate a=a[30] b=b[16] out=s_wallace_cla32_and_30_16
.subckt fa a=s_wallace_cla32_fa42_or0 b=s_wallace_cla32_nand_31_15 cin=s_wallace_cla32_and_30_16 fa_xor1=s_wallace_cla32_fa43_xor1 fa_or0=s_wallace_cla32_fa43_or0
.subckt nand_gate a=a[31] b=b[16] out=s_wallace_cla32_nand_31_16
.subckt and_gate a=a[30] b=b[17] out=s_wallace_cla32_and_30_17
.subckt fa a=s_wallace_cla32_fa43_or0 b=s_wallace_cla32_nand_31_16 cin=s_wallace_cla32_and_30_17 fa_xor1=s_wallace_cla32_fa44_xor1 fa_or0=s_wallace_cla32_fa44_or0
.subckt nand_gate a=a[31] b=b[17] out=s_wallace_cla32_nand_31_17
.subckt and_gate a=a[30] b=b[18] out=s_wallace_cla32_and_30_18
.subckt fa a=s_wallace_cla32_fa44_or0 b=s_wallace_cla32_nand_31_17 cin=s_wallace_cla32_and_30_18 fa_xor1=s_wallace_cla32_fa45_xor1 fa_or0=s_wallace_cla32_fa45_or0
.subckt nand_gate a=a[31] b=b[18] out=s_wallace_cla32_nand_31_18
.subckt and_gate a=a[30] b=b[19] out=s_wallace_cla32_and_30_19
.subckt fa a=s_wallace_cla32_fa45_or0 b=s_wallace_cla32_nand_31_18 cin=s_wallace_cla32_and_30_19 fa_xor1=s_wallace_cla32_fa46_xor1 fa_or0=s_wallace_cla32_fa46_or0
.subckt nand_gate a=a[31] b=b[19] out=s_wallace_cla32_nand_31_19
.subckt and_gate a=a[30] b=b[20] out=s_wallace_cla32_and_30_20
.subckt fa a=s_wallace_cla32_fa46_or0 b=s_wallace_cla32_nand_31_19 cin=s_wallace_cla32_and_30_20 fa_xor1=s_wallace_cla32_fa47_xor1 fa_or0=s_wallace_cla32_fa47_or0
.subckt nand_gate a=a[31] b=b[20] out=s_wallace_cla32_nand_31_20
.subckt and_gate a=a[30] b=b[21] out=s_wallace_cla32_and_30_21
.subckt fa a=s_wallace_cla32_fa47_or0 b=s_wallace_cla32_nand_31_20 cin=s_wallace_cla32_and_30_21 fa_xor1=s_wallace_cla32_fa48_xor1 fa_or0=s_wallace_cla32_fa48_or0
.subckt nand_gate a=a[31] b=b[21] out=s_wallace_cla32_nand_31_21
.subckt and_gate a=a[30] b=b[22] out=s_wallace_cla32_and_30_22
.subckt fa a=s_wallace_cla32_fa48_or0 b=s_wallace_cla32_nand_31_21 cin=s_wallace_cla32_and_30_22 fa_xor1=s_wallace_cla32_fa49_xor1 fa_or0=s_wallace_cla32_fa49_or0
.subckt nand_gate a=a[31] b=b[22] out=s_wallace_cla32_nand_31_22
.subckt and_gate a=a[30] b=b[23] out=s_wallace_cla32_and_30_23
.subckt fa a=s_wallace_cla32_fa49_or0 b=s_wallace_cla32_nand_31_22 cin=s_wallace_cla32_and_30_23 fa_xor1=s_wallace_cla32_fa50_xor1 fa_or0=s_wallace_cla32_fa50_or0
.subckt nand_gate a=a[31] b=b[23] out=s_wallace_cla32_nand_31_23
.subckt and_gate a=a[30] b=b[24] out=s_wallace_cla32_and_30_24
.subckt fa a=s_wallace_cla32_fa50_or0 b=s_wallace_cla32_nand_31_23 cin=s_wallace_cla32_and_30_24 fa_xor1=s_wallace_cla32_fa51_xor1 fa_or0=s_wallace_cla32_fa51_or0
.subckt nand_gate a=a[31] b=b[24] out=s_wallace_cla32_nand_31_24
.subckt and_gate a=a[30] b=b[25] out=s_wallace_cla32_and_30_25
.subckt fa a=s_wallace_cla32_fa51_or0 b=s_wallace_cla32_nand_31_24 cin=s_wallace_cla32_and_30_25 fa_xor1=s_wallace_cla32_fa52_xor1 fa_or0=s_wallace_cla32_fa52_or0
.subckt nand_gate a=a[31] b=b[25] out=s_wallace_cla32_nand_31_25
.subckt and_gate a=a[30] b=b[26] out=s_wallace_cla32_and_30_26
.subckt fa a=s_wallace_cla32_fa52_or0 b=s_wallace_cla32_nand_31_25 cin=s_wallace_cla32_and_30_26 fa_xor1=s_wallace_cla32_fa53_xor1 fa_or0=s_wallace_cla32_fa53_or0
.subckt nand_gate a=a[31] b=b[26] out=s_wallace_cla32_nand_31_26
.subckt and_gate a=a[30] b=b[27] out=s_wallace_cla32_and_30_27
.subckt fa a=s_wallace_cla32_fa53_or0 b=s_wallace_cla32_nand_31_26 cin=s_wallace_cla32_and_30_27 fa_xor1=s_wallace_cla32_fa54_xor1 fa_or0=s_wallace_cla32_fa54_or0
.subckt nand_gate a=a[31] b=b[27] out=s_wallace_cla32_nand_31_27
.subckt and_gate a=a[30] b=b[28] out=s_wallace_cla32_and_30_28
.subckt fa a=s_wallace_cla32_fa54_or0 b=s_wallace_cla32_nand_31_27 cin=s_wallace_cla32_and_30_28 fa_xor1=s_wallace_cla32_fa55_xor1 fa_or0=s_wallace_cla32_fa55_or0
.subckt nand_gate a=a[31] b=b[28] out=s_wallace_cla32_nand_31_28
.subckt and_gate a=a[30] b=b[29] out=s_wallace_cla32_and_30_29
.subckt fa a=s_wallace_cla32_fa55_or0 b=s_wallace_cla32_nand_31_28 cin=s_wallace_cla32_and_30_29 fa_xor1=s_wallace_cla32_fa56_xor1 fa_or0=s_wallace_cla32_fa56_or0
.subckt nand_gate a=a[31] b=b[29] out=s_wallace_cla32_nand_31_29
.subckt and_gate a=a[30] b=b[30] out=s_wallace_cla32_and_30_30
.subckt fa a=s_wallace_cla32_fa56_or0 b=s_wallace_cla32_nand_31_29 cin=s_wallace_cla32_and_30_30 fa_xor1=s_wallace_cla32_fa57_xor1 fa_or0=s_wallace_cla32_fa57_or0
.subckt and_gate a=a[1] b=b[2] out=s_wallace_cla32_and_1_2
.subckt and_gate a=a[0] b=b[3] out=s_wallace_cla32_and_0_3
.subckt ha a=s_wallace_cla32_and_1_2 b=s_wallace_cla32_and_0_3 ha_xor0=s_wallace_cla32_ha1_xor0 ha_and0=s_wallace_cla32_ha1_and0
.subckt and_gate a=a[2] b=b[2] out=s_wallace_cla32_and_2_2
.subckt and_gate a=a[1] b=b[3] out=s_wallace_cla32_and_1_3
.subckt fa a=s_wallace_cla32_ha1_and0 b=s_wallace_cla32_and_2_2 cin=s_wallace_cla32_and_1_3 fa_xor1=s_wallace_cla32_fa58_xor1 fa_or0=s_wallace_cla32_fa58_or0
.subckt and_gate a=a[3] b=b[2] out=s_wallace_cla32_and_3_2
.subckt and_gate a=a[2] b=b[3] out=s_wallace_cla32_and_2_3
.subckt fa a=s_wallace_cla32_fa58_or0 b=s_wallace_cla32_and_3_2 cin=s_wallace_cla32_and_2_3 fa_xor1=s_wallace_cla32_fa59_xor1 fa_or0=s_wallace_cla32_fa59_or0
.subckt and_gate a=a[4] b=b[2] out=s_wallace_cla32_and_4_2
.subckt and_gate a=a[3] b=b[3] out=s_wallace_cla32_and_3_3
.subckt fa a=s_wallace_cla32_fa59_or0 b=s_wallace_cla32_and_4_2 cin=s_wallace_cla32_and_3_3 fa_xor1=s_wallace_cla32_fa60_xor1 fa_or0=s_wallace_cla32_fa60_or0
.subckt and_gate a=a[5] b=b[2] out=s_wallace_cla32_and_5_2
.subckt and_gate a=a[4] b=b[3] out=s_wallace_cla32_and_4_3
.subckt fa a=s_wallace_cla32_fa60_or0 b=s_wallace_cla32_and_5_2 cin=s_wallace_cla32_and_4_3 fa_xor1=s_wallace_cla32_fa61_xor1 fa_or0=s_wallace_cla32_fa61_or0
.subckt and_gate a=a[6] b=b[2] out=s_wallace_cla32_and_6_2
.subckt and_gate a=a[5] b=b[3] out=s_wallace_cla32_and_5_3
.subckt fa a=s_wallace_cla32_fa61_or0 b=s_wallace_cla32_and_6_2 cin=s_wallace_cla32_and_5_3 fa_xor1=s_wallace_cla32_fa62_xor1 fa_or0=s_wallace_cla32_fa62_or0
.subckt and_gate a=a[7] b=b[2] out=s_wallace_cla32_and_7_2
.subckt and_gate a=a[6] b=b[3] out=s_wallace_cla32_and_6_3
.subckt fa a=s_wallace_cla32_fa62_or0 b=s_wallace_cla32_and_7_2 cin=s_wallace_cla32_and_6_3 fa_xor1=s_wallace_cla32_fa63_xor1 fa_or0=s_wallace_cla32_fa63_or0
.subckt and_gate a=a[8] b=b[2] out=s_wallace_cla32_and_8_2
.subckt and_gate a=a[7] b=b[3] out=s_wallace_cla32_and_7_3
.subckt fa a=s_wallace_cla32_fa63_or0 b=s_wallace_cla32_and_8_2 cin=s_wallace_cla32_and_7_3 fa_xor1=s_wallace_cla32_fa64_xor1 fa_or0=s_wallace_cla32_fa64_or0
.subckt and_gate a=a[9] b=b[2] out=s_wallace_cla32_and_9_2
.subckt and_gate a=a[8] b=b[3] out=s_wallace_cla32_and_8_3
.subckt fa a=s_wallace_cla32_fa64_or0 b=s_wallace_cla32_and_9_2 cin=s_wallace_cla32_and_8_3 fa_xor1=s_wallace_cla32_fa65_xor1 fa_or0=s_wallace_cla32_fa65_or0
.subckt and_gate a=a[10] b=b[2] out=s_wallace_cla32_and_10_2
.subckt and_gate a=a[9] b=b[3] out=s_wallace_cla32_and_9_3
.subckt fa a=s_wallace_cla32_fa65_or0 b=s_wallace_cla32_and_10_2 cin=s_wallace_cla32_and_9_3 fa_xor1=s_wallace_cla32_fa66_xor1 fa_or0=s_wallace_cla32_fa66_or0
.subckt and_gate a=a[11] b=b[2] out=s_wallace_cla32_and_11_2
.subckt and_gate a=a[10] b=b[3] out=s_wallace_cla32_and_10_3
.subckt fa a=s_wallace_cla32_fa66_or0 b=s_wallace_cla32_and_11_2 cin=s_wallace_cla32_and_10_3 fa_xor1=s_wallace_cla32_fa67_xor1 fa_or0=s_wallace_cla32_fa67_or0
.subckt and_gate a=a[12] b=b[2] out=s_wallace_cla32_and_12_2
.subckt and_gate a=a[11] b=b[3] out=s_wallace_cla32_and_11_3
.subckt fa a=s_wallace_cla32_fa67_or0 b=s_wallace_cla32_and_12_2 cin=s_wallace_cla32_and_11_3 fa_xor1=s_wallace_cla32_fa68_xor1 fa_or0=s_wallace_cla32_fa68_or0
.subckt and_gate a=a[13] b=b[2] out=s_wallace_cla32_and_13_2
.subckt and_gate a=a[12] b=b[3] out=s_wallace_cla32_and_12_3
.subckt fa a=s_wallace_cla32_fa68_or0 b=s_wallace_cla32_and_13_2 cin=s_wallace_cla32_and_12_3 fa_xor1=s_wallace_cla32_fa69_xor1 fa_or0=s_wallace_cla32_fa69_or0
.subckt and_gate a=a[14] b=b[2] out=s_wallace_cla32_and_14_2
.subckt and_gate a=a[13] b=b[3] out=s_wallace_cla32_and_13_3
.subckt fa a=s_wallace_cla32_fa69_or0 b=s_wallace_cla32_and_14_2 cin=s_wallace_cla32_and_13_3 fa_xor1=s_wallace_cla32_fa70_xor1 fa_or0=s_wallace_cla32_fa70_or0
.subckt and_gate a=a[15] b=b[2] out=s_wallace_cla32_and_15_2
.subckt and_gate a=a[14] b=b[3] out=s_wallace_cla32_and_14_3
.subckt fa a=s_wallace_cla32_fa70_or0 b=s_wallace_cla32_and_15_2 cin=s_wallace_cla32_and_14_3 fa_xor1=s_wallace_cla32_fa71_xor1 fa_or0=s_wallace_cla32_fa71_or0
.subckt and_gate a=a[16] b=b[2] out=s_wallace_cla32_and_16_2
.subckt and_gate a=a[15] b=b[3] out=s_wallace_cla32_and_15_3
.subckt fa a=s_wallace_cla32_fa71_or0 b=s_wallace_cla32_and_16_2 cin=s_wallace_cla32_and_15_3 fa_xor1=s_wallace_cla32_fa72_xor1 fa_or0=s_wallace_cla32_fa72_or0
.subckt and_gate a=a[17] b=b[2] out=s_wallace_cla32_and_17_2
.subckt and_gate a=a[16] b=b[3] out=s_wallace_cla32_and_16_3
.subckt fa a=s_wallace_cla32_fa72_or0 b=s_wallace_cla32_and_17_2 cin=s_wallace_cla32_and_16_3 fa_xor1=s_wallace_cla32_fa73_xor1 fa_or0=s_wallace_cla32_fa73_or0
.subckt and_gate a=a[18] b=b[2] out=s_wallace_cla32_and_18_2
.subckt and_gate a=a[17] b=b[3] out=s_wallace_cla32_and_17_3
.subckt fa a=s_wallace_cla32_fa73_or0 b=s_wallace_cla32_and_18_2 cin=s_wallace_cla32_and_17_3 fa_xor1=s_wallace_cla32_fa74_xor1 fa_or0=s_wallace_cla32_fa74_or0
.subckt and_gate a=a[19] b=b[2] out=s_wallace_cla32_and_19_2
.subckt and_gate a=a[18] b=b[3] out=s_wallace_cla32_and_18_3
.subckt fa a=s_wallace_cla32_fa74_or0 b=s_wallace_cla32_and_19_2 cin=s_wallace_cla32_and_18_3 fa_xor1=s_wallace_cla32_fa75_xor1 fa_or0=s_wallace_cla32_fa75_or0
.subckt and_gate a=a[20] b=b[2] out=s_wallace_cla32_and_20_2
.subckt and_gate a=a[19] b=b[3] out=s_wallace_cla32_and_19_3
.subckt fa a=s_wallace_cla32_fa75_or0 b=s_wallace_cla32_and_20_2 cin=s_wallace_cla32_and_19_3 fa_xor1=s_wallace_cla32_fa76_xor1 fa_or0=s_wallace_cla32_fa76_or0
.subckt and_gate a=a[21] b=b[2] out=s_wallace_cla32_and_21_2
.subckt and_gate a=a[20] b=b[3] out=s_wallace_cla32_and_20_3
.subckt fa a=s_wallace_cla32_fa76_or0 b=s_wallace_cla32_and_21_2 cin=s_wallace_cla32_and_20_3 fa_xor1=s_wallace_cla32_fa77_xor1 fa_or0=s_wallace_cla32_fa77_or0
.subckt and_gate a=a[22] b=b[2] out=s_wallace_cla32_and_22_2
.subckt and_gate a=a[21] b=b[3] out=s_wallace_cla32_and_21_3
.subckt fa a=s_wallace_cla32_fa77_or0 b=s_wallace_cla32_and_22_2 cin=s_wallace_cla32_and_21_3 fa_xor1=s_wallace_cla32_fa78_xor1 fa_or0=s_wallace_cla32_fa78_or0
.subckt and_gate a=a[23] b=b[2] out=s_wallace_cla32_and_23_2
.subckt and_gate a=a[22] b=b[3] out=s_wallace_cla32_and_22_3
.subckt fa a=s_wallace_cla32_fa78_or0 b=s_wallace_cla32_and_23_2 cin=s_wallace_cla32_and_22_3 fa_xor1=s_wallace_cla32_fa79_xor1 fa_or0=s_wallace_cla32_fa79_or0
.subckt and_gate a=a[24] b=b[2] out=s_wallace_cla32_and_24_2
.subckt and_gate a=a[23] b=b[3] out=s_wallace_cla32_and_23_3
.subckt fa a=s_wallace_cla32_fa79_or0 b=s_wallace_cla32_and_24_2 cin=s_wallace_cla32_and_23_3 fa_xor1=s_wallace_cla32_fa80_xor1 fa_or0=s_wallace_cla32_fa80_or0
.subckt and_gate a=a[25] b=b[2] out=s_wallace_cla32_and_25_2
.subckt and_gate a=a[24] b=b[3] out=s_wallace_cla32_and_24_3
.subckt fa a=s_wallace_cla32_fa80_or0 b=s_wallace_cla32_and_25_2 cin=s_wallace_cla32_and_24_3 fa_xor1=s_wallace_cla32_fa81_xor1 fa_or0=s_wallace_cla32_fa81_or0
.subckt and_gate a=a[26] b=b[2] out=s_wallace_cla32_and_26_2
.subckt and_gate a=a[25] b=b[3] out=s_wallace_cla32_and_25_3
.subckt fa a=s_wallace_cla32_fa81_or0 b=s_wallace_cla32_and_26_2 cin=s_wallace_cla32_and_25_3 fa_xor1=s_wallace_cla32_fa82_xor1 fa_or0=s_wallace_cla32_fa82_or0
.subckt and_gate a=a[27] b=b[2] out=s_wallace_cla32_and_27_2
.subckt and_gate a=a[26] b=b[3] out=s_wallace_cla32_and_26_3
.subckt fa a=s_wallace_cla32_fa82_or0 b=s_wallace_cla32_and_27_2 cin=s_wallace_cla32_and_26_3 fa_xor1=s_wallace_cla32_fa83_xor1 fa_or0=s_wallace_cla32_fa83_or0
.subckt and_gate a=a[28] b=b[2] out=s_wallace_cla32_and_28_2
.subckt and_gate a=a[27] b=b[3] out=s_wallace_cla32_and_27_3
.subckt fa a=s_wallace_cla32_fa83_or0 b=s_wallace_cla32_and_28_2 cin=s_wallace_cla32_and_27_3 fa_xor1=s_wallace_cla32_fa84_xor1 fa_or0=s_wallace_cla32_fa84_or0
.subckt and_gate a=a[29] b=b[2] out=s_wallace_cla32_and_29_2
.subckt and_gate a=a[28] b=b[3] out=s_wallace_cla32_and_28_3
.subckt fa a=s_wallace_cla32_fa84_or0 b=s_wallace_cla32_and_29_2 cin=s_wallace_cla32_and_28_3 fa_xor1=s_wallace_cla32_fa85_xor1 fa_or0=s_wallace_cla32_fa85_or0
.subckt and_gate a=a[30] b=b[2] out=s_wallace_cla32_and_30_2
.subckt and_gate a=a[29] b=b[3] out=s_wallace_cla32_and_29_3
.subckt fa a=s_wallace_cla32_fa85_or0 b=s_wallace_cla32_and_30_2 cin=s_wallace_cla32_and_29_3 fa_xor1=s_wallace_cla32_fa86_xor1 fa_or0=s_wallace_cla32_fa86_or0
.subckt and_gate a=a[29] b=b[4] out=s_wallace_cla32_and_29_4
.subckt and_gate a=a[28] b=b[5] out=s_wallace_cla32_and_28_5
.subckt fa a=s_wallace_cla32_fa86_or0 b=s_wallace_cla32_and_29_4 cin=s_wallace_cla32_and_28_5 fa_xor1=s_wallace_cla32_fa87_xor1 fa_or0=s_wallace_cla32_fa87_or0
.subckt and_gate a=a[29] b=b[5] out=s_wallace_cla32_and_29_5
.subckt and_gate a=a[28] b=b[6] out=s_wallace_cla32_and_28_6
.subckt fa a=s_wallace_cla32_fa87_or0 b=s_wallace_cla32_and_29_5 cin=s_wallace_cla32_and_28_6 fa_xor1=s_wallace_cla32_fa88_xor1 fa_or0=s_wallace_cla32_fa88_or0
.subckt and_gate a=a[29] b=b[6] out=s_wallace_cla32_and_29_6
.subckt and_gate a=a[28] b=b[7] out=s_wallace_cla32_and_28_7
.subckt fa a=s_wallace_cla32_fa88_or0 b=s_wallace_cla32_and_29_6 cin=s_wallace_cla32_and_28_7 fa_xor1=s_wallace_cla32_fa89_xor1 fa_or0=s_wallace_cla32_fa89_or0
.subckt and_gate a=a[29] b=b[7] out=s_wallace_cla32_and_29_7
.subckt and_gate a=a[28] b=b[8] out=s_wallace_cla32_and_28_8
.subckt fa a=s_wallace_cla32_fa89_or0 b=s_wallace_cla32_and_29_7 cin=s_wallace_cla32_and_28_8 fa_xor1=s_wallace_cla32_fa90_xor1 fa_or0=s_wallace_cla32_fa90_or0
.subckt and_gate a=a[29] b=b[8] out=s_wallace_cla32_and_29_8
.subckt and_gate a=a[28] b=b[9] out=s_wallace_cla32_and_28_9
.subckt fa a=s_wallace_cla32_fa90_or0 b=s_wallace_cla32_and_29_8 cin=s_wallace_cla32_and_28_9 fa_xor1=s_wallace_cla32_fa91_xor1 fa_or0=s_wallace_cla32_fa91_or0
.subckt and_gate a=a[29] b=b[9] out=s_wallace_cla32_and_29_9
.subckt and_gate a=a[28] b=b[10] out=s_wallace_cla32_and_28_10
.subckt fa a=s_wallace_cla32_fa91_or0 b=s_wallace_cla32_and_29_9 cin=s_wallace_cla32_and_28_10 fa_xor1=s_wallace_cla32_fa92_xor1 fa_or0=s_wallace_cla32_fa92_or0
.subckt and_gate a=a[29] b=b[10] out=s_wallace_cla32_and_29_10
.subckt and_gate a=a[28] b=b[11] out=s_wallace_cla32_and_28_11
.subckt fa a=s_wallace_cla32_fa92_or0 b=s_wallace_cla32_and_29_10 cin=s_wallace_cla32_and_28_11 fa_xor1=s_wallace_cla32_fa93_xor1 fa_or0=s_wallace_cla32_fa93_or0
.subckt and_gate a=a[29] b=b[11] out=s_wallace_cla32_and_29_11
.subckt and_gate a=a[28] b=b[12] out=s_wallace_cla32_and_28_12
.subckt fa a=s_wallace_cla32_fa93_or0 b=s_wallace_cla32_and_29_11 cin=s_wallace_cla32_and_28_12 fa_xor1=s_wallace_cla32_fa94_xor1 fa_or0=s_wallace_cla32_fa94_or0
.subckt and_gate a=a[29] b=b[12] out=s_wallace_cla32_and_29_12
.subckt and_gate a=a[28] b=b[13] out=s_wallace_cla32_and_28_13
.subckt fa a=s_wallace_cla32_fa94_or0 b=s_wallace_cla32_and_29_12 cin=s_wallace_cla32_and_28_13 fa_xor1=s_wallace_cla32_fa95_xor1 fa_or0=s_wallace_cla32_fa95_or0
.subckt and_gate a=a[29] b=b[13] out=s_wallace_cla32_and_29_13
.subckt and_gate a=a[28] b=b[14] out=s_wallace_cla32_and_28_14
.subckt fa a=s_wallace_cla32_fa95_or0 b=s_wallace_cla32_and_29_13 cin=s_wallace_cla32_and_28_14 fa_xor1=s_wallace_cla32_fa96_xor1 fa_or0=s_wallace_cla32_fa96_or0
.subckt and_gate a=a[29] b=b[14] out=s_wallace_cla32_and_29_14
.subckt and_gate a=a[28] b=b[15] out=s_wallace_cla32_and_28_15
.subckt fa a=s_wallace_cla32_fa96_or0 b=s_wallace_cla32_and_29_14 cin=s_wallace_cla32_and_28_15 fa_xor1=s_wallace_cla32_fa97_xor1 fa_or0=s_wallace_cla32_fa97_or0
.subckt and_gate a=a[29] b=b[15] out=s_wallace_cla32_and_29_15
.subckt and_gate a=a[28] b=b[16] out=s_wallace_cla32_and_28_16
.subckt fa a=s_wallace_cla32_fa97_or0 b=s_wallace_cla32_and_29_15 cin=s_wallace_cla32_and_28_16 fa_xor1=s_wallace_cla32_fa98_xor1 fa_or0=s_wallace_cla32_fa98_or0
.subckt and_gate a=a[29] b=b[16] out=s_wallace_cla32_and_29_16
.subckt and_gate a=a[28] b=b[17] out=s_wallace_cla32_and_28_17
.subckt fa a=s_wallace_cla32_fa98_or0 b=s_wallace_cla32_and_29_16 cin=s_wallace_cla32_and_28_17 fa_xor1=s_wallace_cla32_fa99_xor1 fa_or0=s_wallace_cla32_fa99_or0
.subckt and_gate a=a[29] b=b[17] out=s_wallace_cla32_and_29_17
.subckt and_gate a=a[28] b=b[18] out=s_wallace_cla32_and_28_18
.subckt fa a=s_wallace_cla32_fa99_or0 b=s_wallace_cla32_and_29_17 cin=s_wallace_cla32_and_28_18 fa_xor1=s_wallace_cla32_fa100_xor1 fa_or0=s_wallace_cla32_fa100_or0
.subckt and_gate a=a[29] b=b[18] out=s_wallace_cla32_and_29_18
.subckt and_gate a=a[28] b=b[19] out=s_wallace_cla32_and_28_19
.subckt fa a=s_wallace_cla32_fa100_or0 b=s_wallace_cla32_and_29_18 cin=s_wallace_cla32_and_28_19 fa_xor1=s_wallace_cla32_fa101_xor1 fa_or0=s_wallace_cla32_fa101_or0
.subckt and_gate a=a[29] b=b[19] out=s_wallace_cla32_and_29_19
.subckt and_gate a=a[28] b=b[20] out=s_wallace_cla32_and_28_20
.subckt fa a=s_wallace_cla32_fa101_or0 b=s_wallace_cla32_and_29_19 cin=s_wallace_cla32_and_28_20 fa_xor1=s_wallace_cla32_fa102_xor1 fa_or0=s_wallace_cla32_fa102_or0
.subckt and_gate a=a[29] b=b[20] out=s_wallace_cla32_and_29_20
.subckt and_gate a=a[28] b=b[21] out=s_wallace_cla32_and_28_21
.subckt fa a=s_wallace_cla32_fa102_or0 b=s_wallace_cla32_and_29_20 cin=s_wallace_cla32_and_28_21 fa_xor1=s_wallace_cla32_fa103_xor1 fa_or0=s_wallace_cla32_fa103_or0
.subckt and_gate a=a[29] b=b[21] out=s_wallace_cla32_and_29_21
.subckt and_gate a=a[28] b=b[22] out=s_wallace_cla32_and_28_22
.subckt fa a=s_wallace_cla32_fa103_or0 b=s_wallace_cla32_and_29_21 cin=s_wallace_cla32_and_28_22 fa_xor1=s_wallace_cla32_fa104_xor1 fa_or0=s_wallace_cla32_fa104_or0
.subckt and_gate a=a[29] b=b[22] out=s_wallace_cla32_and_29_22
.subckt and_gate a=a[28] b=b[23] out=s_wallace_cla32_and_28_23
.subckt fa a=s_wallace_cla32_fa104_or0 b=s_wallace_cla32_and_29_22 cin=s_wallace_cla32_and_28_23 fa_xor1=s_wallace_cla32_fa105_xor1 fa_or0=s_wallace_cla32_fa105_or0
.subckt and_gate a=a[29] b=b[23] out=s_wallace_cla32_and_29_23
.subckt and_gate a=a[28] b=b[24] out=s_wallace_cla32_and_28_24
.subckt fa a=s_wallace_cla32_fa105_or0 b=s_wallace_cla32_and_29_23 cin=s_wallace_cla32_and_28_24 fa_xor1=s_wallace_cla32_fa106_xor1 fa_or0=s_wallace_cla32_fa106_or0
.subckt and_gate a=a[29] b=b[24] out=s_wallace_cla32_and_29_24
.subckt and_gate a=a[28] b=b[25] out=s_wallace_cla32_and_28_25
.subckt fa a=s_wallace_cla32_fa106_or0 b=s_wallace_cla32_and_29_24 cin=s_wallace_cla32_and_28_25 fa_xor1=s_wallace_cla32_fa107_xor1 fa_or0=s_wallace_cla32_fa107_or0
.subckt and_gate a=a[29] b=b[25] out=s_wallace_cla32_and_29_25
.subckt and_gate a=a[28] b=b[26] out=s_wallace_cla32_and_28_26
.subckt fa a=s_wallace_cla32_fa107_or0 b=s_wallace_cla32_and_29_25 cin=s_wallace_cla32_and_28_26 fa_xor1=s_wallace_cla32_fa108_xor1 fa_or0=s_wallace_cla32_fa108_or0
.subckt and_gate a=a[29] b=b[26] out=s_wallace_cla32_and_29_26
.subckt and_gate a=a[28] b=b[27] out=s_wallace_cla32_and_28_27
.subckt fa a=s_wallace_cla32_fa108_or0 b=s_wallace_cla32_and_29_26 cin=s_wallace_cla32_and_28_27 fa_xor1=s_wallace_cla32_fa109_xor1 fa_or0=s_wallace_cla32_fa109_or0
.subckt and_gate a=a[29] b=b[27] out=s_wallace_cla32_and_29_27
.subckt and_gate a=a[28] b=b[28] out=s_wallace_cla32_and_28_28
.subckt fa a=s_wallace_cla32_fa109_or0 b=s_wallace_cla32_and_29_27 cin=s_wallace_cla32_and_28_28 fa_xor1=s_wallace_cla32_fa110_xor1 fa_or0=s_wallace_cla32_fa110_or0
.subckt and_gate a=a[29] b=b[28] out=s_wallace_cla32_and_29_28
.subckt and_gate a=a[28] b=b[29] out=s_wallace_cla32_and_28_29
.subckt fa a=s_wallace_cla32_fa110_or0 b=s_wallace_cla32_and_29_28 cin=s_wallace_cla32_and_28_29 fa_xor1=s_wallace_cla32_fa111_xor1 fa_or0=s_wallace_cla32_fa111_or0
.subckt and_gate a=a[29] b=b[29] out=s_wallace_cla32_and_29_29
.subckt and_gate a=a[28] b=b[30] out=s_wallace_cla32_and_28_30
.subckt fa a=s_wallace_cla32_fa111_or0 b=s_wallace_cla32_and_29_29 cin=s_wallace_cla32_and_28_30 fa_xor1=s_wallace_cla32_fa112_xor1 fa_or0=s_wallace_cla32_fa112_or0
.subckt and_gate a=a[29] b=b[30] out=s_wallace_cla32_and_29_30
.subckt nand_gate a=a[28] b=b[31] out=s_wallace_cla32_nand_28_31
.subckt fa a=s_wallace_cla32_fa112_or0 b=s_wallace_cla32_and_29_30 cin=s_wallace_cla32_nand_28_31 fa_xor1=s_wallace_cla32_fa113_xor1 fa_or0=s_wallace_cla32_fa113_or0
.subckt and_gate a=a[0] b=b[4] out=s_wallace_cla32_and_0_4
.subckt ha a=s_wallace_cla32_and_0_4 b=s_wallace_cla32_fa1_xor1 ha_xor0=s_wallace_cla32_ha2_xor0 ha_and0=s_wallace_cla32_ha2_and0
.subckt and_gate a=a[1] b=b[4] out=s_wallace_cla32_and_1_4
.subckt and_gate a=a[0] b=b[5] out=s_wallace_cla32_and_0_5
.subckt fa a=s_wallace_cla32_ha2_and0 b=s_wallace_cla32_and_1_4 cin=s_wallace_cla32_and_0_5 fa_xor1=s_wallace_cla32_fa114_xor1 fa_or0=s_wallace_cla32_fa114_or0
.subckt and_gate a=a[2] b=b[4] out=s_wallace_cla32_and_2_4
.subckt and_gate a=a[1] b=b[5] out=s_wallace_cla32_and_1_5
.subckt fa a=s_wallace_cla32_fa114_or0 b=s_wallace_cla32_and_2_4 cin=s_wallace_cla32_and_1_5 fa_xor1=s_wallace_cla32_fa115_xor1 fa_or0=s_wallace_cla32_fa115_or0
.subckt and_gate a=a[3] b=b[4] out=s_wallace_cla32_and_3_4
.subckt and_gate a=a[2] b=b[5] out=s_wallace_cla32_and_2_5
.subckt fa a=s_wallace_cla32_fa115_or0 b=s_wallace_cla32_and_3_4 cin=s_wallace_cla32_and_2_5 fa_xor1=s_wallace_cla32_fa116_xor1 fa_or0=s_wallace_cla32_fa116_or0
.subckt and_gate a=a[4] b=b[4] out=s_wallace_cla32_and_4_4
.subckt and_gate a=a[3] b=b[5] out=s_wallace_cla32_and_3_5
.subckt fa a=s_wallace_cla32_fa116_or0 b=s_wallace_cla32_and_4_4 cin=s_wallace_cla32_and_3_5 fa_xor1=s_wallace_cla32_fa117_xor1 fa_or0=s_wallace_cla32_fa117_or0
.subckt and_gate a=a[5] b=b[4] out=s_wallace_cla32_and_5_4
.subckt and_gate a=a[4] b=b[5] out=s_wallace_cla32_and_4_5
.subckt fa a=s_wallace_cla32_fa117_or0 b=s_wallace_cla32_and_5_4 cin=s_wallace_cla32_and_4_5 fa_xor1=s_wallace_cla32_fa118_xor1 fa_or0=s_wallace_cla32_fa118_or0
.subckt and_gate a=a[6] b=b[4] out=s_wallace_cla32_and_6_4
.subckt and_gate a=a[5] b=b[5] out=s_wallace_cla32_and_5_5
.subckt fa a=s_wallace_cla32_fa118_or0 b=s_wallace_cla32_and_6_4 cin=s_wallace_cla32_and_5_5 fa_xor1=s_wallace_cla32_fa119_xor1 fa_or0=s_wallace_cla32_fa119_or0
.subckt and_gate a=a[7] b=b[4] out=s_wallace_cla32_and_7_4
.subckt and_gate a=a[6] b=b[5] out=s_wallace_cla32_and_6_5
.subckt fa a=s_wallace_cla32_fa119_or0 b=s_wallace_cla32_and_7_4 cin=s_wallace_cla32_and_6_5 fa_xor1=s_wallace_cla32_fa120_xor1 fa_or0=s_wallace_cla32_fa120_or0
.subckt and_gate a=a[8] b=b[4] out=s_wallace_cla32_and_8_4
.subckt and_gate a=a[7] b=b[5] out=s_wallace_cla32_and_7_5
.subckt fa a=s_wallace_cla32_fa120_or0 b=s_wallace_cla32_and_8_4 cin=s_wallace_cla32_and_7_5 fa_xor1=s_wallace_cla32_fa121_xor1 fa_or0=s_wallace_cla32_fa121_or0
.subckt and_gate a=a[9] b=b[4] out=s_wallace_cla32_and_9_4
.subckt and_gate a=a[8] b=b[5] out=s_wallace_cla32_and_8_5
.subckt fa a=s_wallace_cla32_fa121_or0 b=s_wallace_cla32_and_9_4 cin=s_wallace_cla32_and_8_5 fa_xor1=s_wallace_cla32_fa122_xor1 fa_or0=s_wallace_cla32_fa122_or0
.subckt and_gate a=a[10] b=b[4] out=s_wallace_cla32_and_10_4
.subckt and_gate a=a[9] b=b[5] out=s_wallace_cla32_and_9_5
.subckt fa a=s_wallace_cla32_fa122_or0 b=s_wallace_cla32_and_10_4 cin=s_wallace_cla32_and_9_5 fa_xor1=s_wallace_cla32_fa123_xor1 fa_or0=s_wallace_cla32_fa123_or0
.subckt and_gate a=a[11] b=b[4] out=s_wallace_cla32_and_11_4
.subckt and_gate a=a[10] b=b[5] out=s_wallace_cla32_and_10_5
.subckt fa a=s_wallace_cla32_fa123_or0 b=s_wallace_cla32_and_11_4 cin=s_wallace_cla32_and_10_5 fa_xor1=s_wallace_cla32_fa124_xor1 fa_or0=s_wallace_cla32_fa124_or0
.subckt and_gate a=a[12] b=b[4] out=s_wallace_cla32_and_12_4
.subckt and_gate a=a[11] b=b[5] out=s_wallace_cla32_and_11_5
.subckt fa a=s_wallace_cla32_fa124_or0 b=s_wallace_cla32_and_12_4 cin=s_wallace_cla32_and_11_5 fa_xor1=s_wallace_cla32_fa125_xor1 fa_or0=s_wallace_cla32_fa125_or0
.subckt and_gate a=a[13] b=b[4] out=s_wallace_cla32_and_13_4
.subckt and_gate a=a[12] b=b[5] out=s_wallace_cla32_and_12_5
.subckt fa a=s_wallace_cla32_fa125_or0 b=s_wallace_cla32_and_13_4 cin=s_wallace_cla32_and_12_5 fa_xor1=s_wallace_cla32_fa126_xor1 fa_or0=s_wallace_cla32_fa126_or0
.subckt and_gate a=a[14] b=b[4] out=s_wallace_cla32_and_14_4
.subckt and_gate a=a[13] b=b[5] out=s_wallace_cla32_and_13_5
.subckt fa a=s_wallace_cla32_fa126_or0 b=s_wallace_cla32_and_14_4 cin=s_wallace_cla32_and_13_5 fa_xor1=s_wallace_cla32_fa127_xor1 fa_or0=s_wallace_cla32_fa127_or0
.subckt and_gate a=a[15] b=b[4] out=s_wallace_cla32_and_15_4
.subckt and_gate a=a[14] b=b[5] out=s_wallace_cla32_and_14_5
.subckt fa a=s_wallace_cla32_fa127_or0 b=s_wallace_cla32_and_15_4 cin=s_wallace_cla32_and_14_5 fa_xor1=s_wallace_cla32_fa128_xor1 fa_or0=s_wallace_cla32_fa128_or0
.subckt and_gate a=a[16] b=b[4] out=s_wallace_cla32_and_16_4
.subckt and_gate a=a[15] b=b[5] out=s_wallace_cla32_and_15_5
.subckt fa a=s_wallace_cla32_fa128_or0 b=s_wallace_cla32_and_16_4 cin=s_wallace_cla32_and_15_5 fa_xor1=s_wallace_cla32_fa129_xor1 fa_or0=s_wallace_cla32_fa129_or0
.subckt and_gate a=a[17] b=b[4] out=s_wallace_cla32_and_17_4
.subckt and_gate a=a[16] b=b[5] out=s_wallace_cla32_and_16_5
.subckt fa a=s_wallace_cla32_fa129_or0 b=s_wallace_cla32_and_17_4 cin=s_wallace_cla32_and_16_5 fa_xor1=s_wallace_cla32_fa130_xor1 fa_or0=s_wallace_cla32_fa130_or0
.subckt and_gate a=a[18] b=b[4] out=s_wallace_cla32_and_18_4
.subckt and_gate a=a[17] b=b[5] out=s_wallace_cla32_and_17_5
.subckt fa a=s_wallace_cla32_fa130_or0 b=s_wallace_cla32_and_18_4 cin=s_wallace_cla32_and_17_5 fa_xor1=s_wallace_cla32_fa131_xor1 fa_or0=s_wallace_cla32_fa131_or0
.subckt and_gate a=a[19] b=b[4] out=s_wallace_cla32_and_19_4
.subckt and_gate a=a[18] b=b[5] out=s_wallace_cla32_and_18_5
.subckt fa a=s_wallace_cla32_fa131_or0 b=s_wallace_cla32_and_19_4 cin=s_wallace_cla32_and_18_5 fa_xor1=s_wallace_cla32_fa132_xor1 fa_or0=s_wallace_cla32_fa132_or0
.subckt and_gate a=a[20] b=b[4] out=s_wallace_cla32_and_20_4
.subckt and_gate a=a[19] b=b[5] out=s_wallace_cla32_and_19_5
.subckt fa a=s_wallace_cla32_fa132_or0 b=s_wallace_cla32_and_20_4 cin=s_wallace_cla32_and_19_5 fa_xor1=s_wallace_cla32_fa133_xor1 fa_or0=s_wallace_cla32_fa133_or0
.subckt and_gate a=a[21] b=b[4] out=s_wallace_cla32_and_21_4
.subckt and_gate a=a[20] b=b[5] out=s_wallace_cla32_and_20_5
.subckt fa a=s_wallace_cla32_fa133_or0 b=s_wallace_cla32_and_21_4 cin=s_wallace_cla32_and_20_5 fa_xor1=s_wallace_cla32_fa134_xor1 fa_or0=s_wallace_cla32_fa134_or0
.subckt and_gate a=a[22] b=b[4] out=s_wallace_cla32_and_22_4
.subckt and_gate a=a[21] b=b[5] out=s_wallace_cla32_and_21_5
.subckt fa a=s_wallace_cla32_fa134_or0 b=s_wallace_cla32_and_22_4 cin=s_wallace_cla32_and_21_5 fa_xor1=s_wallace_cla32_fa135_xor1 fa_or0=s_wallace_cla32_fa135_or0
.subckt and_gate a=a[23] b=b[4] out=s_wallace_cla32_and_23_4
.subckt and_gate a=a[22] b=b[5] out=s_wallace_cla32_and_22_5
.subckt fa a=s_wallace_cla32_fa135_or0 b=s_wallace_cla32_and_23_4 cin=s_wallace_cla32_and_22_5 fa_xor1=s_wallace_cla32_fa136_xor1 fa_or0=s_wallace_cla32_fa136_or0
.subckt and_gate a=a[24] b=b[4] out=s_wallace_cla32_and_24_4
.subckt and_gate a=a[23] b=b[5] out=s_wallace_cla32_and_23_5
.subckt fa a=s_wallace_cla32_fa136_or0 b=s_wallace_cla32_and_24_4 cin=s_wallace_cla32_and_23_5 fa_xor1=s_wallace_cla32_fa137_xor1 fa_or0=s_wallace_cla32_fa137_or0
.subckt and_gate a=a[25] b=b[4] out=s_wallace_cla32_and_25_4
.subckt and_gate a=a[24] b=b[5] out=s_wallace_cla32_and_24_5
.subckt fa a=s_wallace_cla32_fa137_or0 b=s_wallace_cla32_and_25_4 cin=s_wallace_cla32_and_24_5 fa_xor1=s_wallace_cla32_fa138_xor1 fa_or0=s_wallace_cla32_fa138_or0
.subckt and_gate a=a[26] b=b[4] out=s_wallace_cla32_and_26_4
.subckt and_gate a=a[25] b=b[5] out=s_wallace_cla32_and_25_5
.subckt fa a=s_wallace_cla32_fa138_or0 b=s_wallace_cla32_and_26_4 cin=s_wallace_cla32_and_25_5 fa_xor1=s_wallace_cla32_fa139_xor1 fa_or0=s_wallace_cla32_fa139_or0
.subckt and_gate a=a[27] b=b[4] out=s_wallace_cla32_and_27_4
.subckt and_gate a=a[26] b=b[5] out=s_wallace_cla32_and_26_5
.subckt fa a=s_wallace_cla32_fa139_or0 b=s_wallace_cla32_and_27_4 cin=s_wallace_cla32_and_26_5 fa_xor1=s_wallace_cla32_fa140_xor1 fa_or0=s_wallace_cla32_fa140_or0
.subckt and_gate a=a[28] b=b[4] out=s_wallace_cla32_and_28_4
.subckt and_gate a=a[27] b=b[5] out=s_wallace_cla32_and_27_5
.subckt fa a=s_wallace_cla32_fa140_or0 b=s_wallace_cla32_and_28_4 cin=s_wallace_cla32_and_27_5 fa_xor1=s_wallace_cla32_fa141_xor1 fa_or0=s_wallace_cla32_fa141_or0
.subckt and_gate a=a[27] b=b[6] out=s_wallace_cla32_and_27_6
.subckt and_gate a=a[26] b=b[7] out=s_wallace_cla32_and_26_7
.subckt fa a=s_wallace_cla32_fa141_or0 b=s_wallace_cla32_and_27_6 cin=s_wallace_cla32_and_26_7 fa_xor1=s_wallace_cla32_fa142_xor1 fa_or0=s_wallace_cla32_fa142_or0
.subckt and_gate a=a[27] b=b[7] out=s_wallace_cla32_and_27_7
.subckt and_gate a=a[26] b=b[8] out=s_wallace_cla32_and_26_8
.subckt fa a=s_wallace_cla32_fa142_or0 b=s_wallace_cla32_and_27_7 cin=s_wallace_cla32_and_26_8 fa_xor1=s_wallace_cla32_fa143_xor1 fa_or0=s_wallace_cla32_fa143_or0
.subckt and_gate a=a[27] b=b[8] out=s_wallace_cla32_and_27_8
.subckt and_gate a=a[26] b=b[9] out=s_wallace_cla32_and_26_9
.subckt fa a=s_wallace_cla32_fa143_or0 b=s_wallace_cla32_and_27_8 cin=s_wallace_cla32_and_26_9 fa_xor1=s_wallace_cla32_fa144_xor1 fa_or0=s_wallace_cla32_fa144_or0
.subckt and_gate a=a[27] b=b[9] out=s_wallace_cla32_and_27_9
.subckt and_gate a=a[26] b=b[10] out=s_wallace_cla32_and_26_10
.subckt fa a=s_wallace_cla32_fa144_or0 b=s_wallace_cla32_and_27_9 cin=s_wallace_cla32_and_26_10 fa_xor1=s_wallace_cla32_fa145_xor1 fa_or0=s_wallace_cla32_fa145_or0
.subckt and_gate a=a[27] b=b[10] out=s_wallace_cla32_and_27_10
.subckt and_gate a=a[26] b=b[11] out=s_wallace_cla32_and_26_11
.subckt fa a=s_wallace_cla32_fa145_or0 b=s_wallace_cla32_and_27_10 cin=s_wallace_cla32_and_26_11 fa_xor1=s_wallace_cla32_fa146_xor1 fa_or0=s_wallace_cla32_fa146_or0
.subckt and_gate a=a[27] b=b[11] out=s_wallace_cla32_and_27_11
.subckt and_gate a=a[26] b=b[12] out=s_wallace_cla32_and_26_12
.subckt fa a=s_wallace_cla32_fa146_or0 b=s_wallace_cla32_and_27_11 cin=s_wallace_cla32_and_26_12 fa_xor1=s_wallace_cla32_fa147_xor1 fa_or0=s_wallace_cla32_fa147_or0
.subckt and_gate a=a[27] b=b[12] out=s_wallace_cla32_and_27_12
.subckt and_gate a=a[26] b=b[13] out=s_wallace_cla32_and_26_13
.subckt fa a=s_wallace_cla32_fa147_or0 b=s_wallace_cla32_and_27_12 cin=s_wallace_cla32_and_26_13 fa_xor1=s_wallace_cla32_fa148_xor1 fa_or0=s_wallace_cla32_fa148_or0
.subckt and_gate a=a[27] b=b[13] out=s_wallace_cla32_and_27_13
.subckt and_gate a=a[26] b=b[14] out=s_wallace_cla32_and_26_14
.subckt fa a=s_wallace_cla32_fa148_or0 b=s_wallace_cla32_and_27_13 cin=s_wallace_cla32_and_26_14 fa_xor1=s_wallace_cla32_fa149_xor1 fa_or0=s_wallace_cla32_fa149_or0
.subckt and_gate a=a[27] b=b[14] out=s_wallace_cla32_and_27_14
.subckt and_gate a=a[26] b=b[15] out=s_wallace_cla32_and_26_15
.subckt fa a=s_wallace_cla32_fa149_or0 b=s_wallace_cla32_and_27_14 cin=s_wallace_cla32_and_26_15 fa_xor1=s_wallace_cla32_fa150_xor1 fa_or0=s_wallace_cla32_fa150_or0
.subckt and_gate a=a[27] b=b[15] out=s_wallace_cla32_and_27_15
.subckt and_gate a=a[26] b=b[16] out=s_wallace_cla32_and_26_16
.subckt fa a=s_wallace_cla32_fa150_or0 b=s_wallace_cla32_and_27_15 cin=s_wallace_cla32_and_26_16 fa_xor1=s_wallace_cla32_fa151_xor1 fa_or0=s_wallace_cla32_fa151_or0
.subckt and_gate a=a[27] b=b[16] out=s_wallace_cla32_and_27_16
.subckt and_gate a=a[26] b=b[17] out=s_wallace_cla32_and_26_17
.subckt fa a=s_wallace_cla32_fa151_or0 b=s_wallace_cla32_and_27_16 cin=s_wallace_cla32_and_26_17 fa_xor1=s_wallace_cla32_fa152_xor1 fa_or0=s_wallace_cla32_fa152_or0
.subckt and_gate a=a[27] b=b[17] out=s_wallace_cla32_and_27_17
.subckt and_gate a=a[26] b=b[18] out=s_wallace_cla32_and_26_18
.subckt fa a=s_wallace_cla32_fa152_or0 b=s_wallace_cla32_and_27_17 cin=s_wallace_cla32_and_26_18 fa_xor1=s_wallace_cla32_fa153_xor1 fa_or0=s_wallace_cla32_fa153_or0
.subckt and_gate a=a[27] b=b[18] out=s_wallace_cla32_and_27_18
.subckt and_gate a=a[26] b=b[19] out=s_wallace_cla32_and_26_19
.subckt fa a=s_wallace_cla32_fa153_or0 b=s_wallace_cla32_and_27_18 cin=s_wallace_cla32_and_26_19 fa_xor1=s_wallace_cla32_fa154_xor1 fa_or0=s_wallace_cla32_fa154_or0
.subckt and_gate a=a[27] b=b[19] out=s_wallace_cla32_and_27_19
.subckt and_gate a=a[26] b=b[20] out=s_wallace_cla32_and_26_20
.subckt fa a=s_wallace_cla32_fa154_or0 b=s_wallace_cla32_and_27_19 cin=s_wallace_cla32_and_26_20 fa_xor1=s_wallace_cla32_fa155_xor1 fa_or0=s_wallace_cla32_fa155_or0
.subckt and_gate a=a[27] b=b[20] out=s_wallace_cla32_and_27_20
.subckt and_gate a=a[26] b=b[21] out=s_wallace_cla32_and_26_21
.subckt fa a=s_wallace_cla32_fa155_or0 b=s_wallace_cla32_and_27_20 cin=s_wallace_cla32_and_26_21 fa_xor1=s_wallace_cla32_fa156_xor1 fa_or0=s_wallace_cla32_fa156_or0
.subckt and_gate a=a[27] b=b[21] out=s_wallace_cla32_and_27_21
.subckt and_gate a=a[26] b=b[22] out=s_wallace_cla32_and_26_22
.subckt fa a=s_wallace_cla32_fa156_or0 b=s_wallace_cla32_and_27_21 cin=s_wallace_cla32_and_26_22 fa_xor1=s_wallace_cla32_fa157_xor1 fa_or0=s_wallace_cla32_fa157_or0
.subckt and_gate a=a[27] b=b[22] out=s_wallace_cla32_and_27_22
.subckt and_gate a=a[26] b=b[23] out=s_wallace_cla32_and_26_23
.subckt fa a=s_wallace_cla32_fa157_or0 b=s_wallace_cla32_and_27_22 cin=s_wallace_cla32_and_26_23 fa_xor1=s_wallace_cla32_fa158_xor1 fa_or0=s_wallace_cla32_fa158_or0
.subckt and_gate a=a[27] b=b[23] out=s_wallace_cla32_and_27_23
.subckt and_gate a=a[26] b=b[24] out=s_wallace_cla32_and_26_24
.subckt fa a=s_wallace_cla32_fa158_or0 b=s_wallace_cla32_and_27_23 cin=s_wallace_cla32_and_26_24 fa_xor1=s_wallace_cla32_fa159_xor1 fa_or0=s_wallace_cla32_fa159_or0
.subckt and_gate a=a[27] b=b[24] out=s_wallace_cla32_and_27_24
.subckt and_gate a=a[26] b=b[25] out=s_wallace_cla32_and_26_25
.subckt fa a=s_wallace_cla32_fa159_or0 b=s_wallace_cla32_and_27_24 cin=s_wallace_cla32_and_26_25 fa_xor1=s_wallace_cla32_fa160_xor1 fa_or0=s_wallace_cla32_fa160_or0
.subckt and_gate a=a[27] b=b[25] out=s_wallace_cla32_and_27_25
.subckt and_gate a=a[26] b=b[26] out=s_wallace_cla32_and_26_26
.subckt fa a=s_wallace_cla32_fa160_or0 b=s_wallace_cla32_and_27_25 cin=s_wallace_cla32_and_26_26 fa_xor1=s_wallace_cla32_fa161_xor1 fa_or0=s_wallace_cla32_fa161_or0
.subckt and_gate a=a[27] b=b[26] out=s_wallace_cla32_and_27_26
.subckt and_gate a=a[26] b=b[27] out=s_wallace_cla32_and_26_27
.subckt fa a=s_wallace_cla32_fa161_or0 b=s_wallace_cla32_and_27_26 cin=s_wallace_cla32_and_26_27 fa_xor1=s_wallace_cla32_fa162_xor1 fa_or0=s_wallace_cla32_fa162_or0
.subckt and_gate a=a[27] b=b[27] out=s_wallace_cla32_and_27_27
.subckt and_gate a=a[26] b=b[28] out=s_wallace_cla32_and_26_28
.subckt fa a=s_wallace_cla32_fa162_or0 b=s_wallace_cla32_and_27_27 cin=s_wallace_cla32_and_26_28 fa_xor1=s_wallace_cla32_fa163_xor1 fa_or0=s_wallace_cla32_fa163_or0
.subckt and_gate a=a[27] b=b[28] out=s_wallace_cla32_and_27_28
.subckt and_gate a=a[26] b=b[29] out=s_wallace_cla32_and_26_29
.subckt fa a=s_wallace_cla32_fa163_or0 b=s_wallace_cla32_and_27_28 cin=s_wallace_cla32_and_26_29 fa_xor1=s_wallace_cla32_fa164_xor1 fa_or0=s_wallace_cla32_fa164_or0
.subckt and_gate a=a[27] b=b[29] out=s_wallace_cla32_and_27_29
.subckt and_gate a=a[26] b=b[30] out=s_wallace_cla32_and_26_30
.subckt fa a=s_wallace_cla32_fa164_or0 b=s_wallace_cla32_and_27_29 cin=s_wallace_cla32_and_26_30 fa_xor1=s_wallace_cla32_fa165_xor1 fa_or0=s_wallace_cla32_fa165_or0
.subckt and_gate a=a[27] b=b[30] out=s_wallace_cla32_and_27_30
.subckt nand_gate a=a[26] b=b[31] out=s_wallace_cla32_nand_26_31
.subckt fa a=s_wallace_cla32_fa165_or0 b=s_wallace_cla32_and_27_30 cin=s_wallace_cla32_nand_26_31 fa_xor1=s_wallace_cla32_fa166_xor1 fa_or0=s_wallace_cla32_fa166_or0
.subckt nand_gate a=a[27] b=b[31] out=s_wallace_cla32_nand_27_31
.subckt fa a=s_wallace_cla32_fa166_or0 b=s_wallace_cla32_nand_27_31 cin=s_wallace_cla32_fa55_xor1 fa_xor1=s_wallace_cla32_fa167_xor1 fa_or0=s_wallace_cla32_fa167_or0
.subckt ha a=s_wallace_cla32_fa2_xor1 b=s_wallace_cla32_fa59_xor1 ha_xor0=s_wallace_cla32_ha3_xor0 ha_and0=s_wallace_cla32_ha3_and0
.subckt and_gate a=a[0] b=b[6] out=s_wallace_cla32_and_0_6
.subckt fa a=s_wallace_cla32_ha3_and0 b=s_wallace_cla32_and_0_6 cin=s_wallace_cla32_fa3_xor1 fa_xor1=s_wallace_cla32_fa168_xor1 fa_or0=s_wallace_cla32_fa168_or0
.subckt and_gate a=a[1] b=b[6] out=s_wallace_cla32_and_1_6
.subckt and_gate a=a[0] b=b[7] out=s_wallace_cla32_and_0_7
.subckt fa a=s_wallace_cla32_fa168_or0 b=s_wallace_cla32_and_1_6 cin=s_wallace_cla32_and_0_7 fa_xor1=s_wallace_cla32_fa169_xor1 fa_or0=s_wallace_cla32_fa169_or0
.subckt and_gate a=a[2] b=b[6] out=s_wallace_cla32_and_2_6
.subckt and_gate a=a[1] b=b[7] out=s_wallace_cla32_and_1_7
.subckt fa a=s_wallace_cla32_fa169_or0 b=s_wallace_cla32_and_2_6 cin=s_wallace_cla32_and_1_7 fa_xor1=s_wallace_cla32_fa170_xor1 fa_or0=s_wallace_cla32_fa170_or0
.subckt and_gate a=a[3] b=b[6] out=s_wallace_cla32_and_3_6
.subckt and_gate a=a[2] b=b[7] out=s_wallace_cla32_and_2_7
.subckt fa a=s_wallace_cla32_fa170_or0 b=s_wallace_cla32_and_3_6 cin=s_wallace_cla32_and_2_7 fa_xor1=s_wallace_cla32_fa171_xor1 fa_or0=s_wallace_cla32_fa171_or0
.subckt and_gate a=a[4] b=b[6] out=s_wallace_cla32_and_4_6
.subckt and_gate a=a[3] b=b[7] out=s_wallace_cla32_and_3_7
.subckt fa a=s_wallace_cla32_fa171_or0 b=s_wallace_cla32_and_4_6 cin=s_wallace_cla32_and_3_7 fa_xor1=s_wallace_cla32_fa172_xor1 fa_or0=s_wallace_cla32_fa172_or0
.subckt and_gate a=a[5] b=b[6] out=s_wallace_cla32_and_5_6
.subckt and_gate a=a[4] b=b[7] out=s_wallace_cla32_and_4_7
.subckt fa a=s_wallace_cla32_fa172_or0 b=s_wallace_cla32_and_5_6 cin=s_wallace_cla32_and_4_7 fa_xor1=s_wallace_cla32_fa173_xor1 fa_or0=s_wallace_cla32_fa173_or0
.subckt and_gate a=a[6] b=b[6] out=s_wallace_cla32_and_6_6
.subckt and_gate a=a[5] b=b[7] out=s_wallace_cla32_and_5_7
.subckt fa a=s_wallace_cla32_fa173_or0 b=s_wallace_cla32_and_6_6 cin=s_wallace_cla32_and_5_7 fa_xor1=s_wallace_cla32_fa174_xor1 fa_or0=s_wallace_cla32_fa174_or0
.subckt and_gate a=a[7] b=b[6] out=s_wallace_cla32_and_7_6
.subckt and_gate a=a[6] b=b[7] out=s_wallace_cla32_and_6_7
.subckt fa a=s_wallace_cla32_fa174_or0 b=s_wallace_cla32_and_7_6 cin=s_wallace_cla32_and_6_7 fa_xor1=s_wallace_cla32_fa175_xor1 fa_or0=s_wallace_cla32_fa175_or0
.subckt and_gate a=a[8] b=b[6] out=s_wallace_cla32_and_8_6
.subckt and_gate a=a[7] b=b[7] out=s_wallace_cla32_and_7_7
.subckt fa a=s_wallace_cla32_fa175_or0 b=s_wallace_cla32_and_8_6 cin=s_wallace_cla32_and_7_7 fa_xor1=s_wallace_cla32_fa176_xor1 fa_or0=s_wallace_cla32_fa176_or0
.subckt and_gate a=a[9] b=b[6] out=s_wallace_cla32_and_9_6
.subckt and_gate a=a[8] b=b[7] out=s_wallace_cla32_and_8_7
.subckt fa a=s_wallace_cla32_fa176_or0 b=s_wallace_cla32_and_9_6 cin=s_wallace_cla32_and_8_7 fa_xor1=s_wallace_cla32_fa177_xor1 fa_or0=s_wallace_cla32_fa177_or0
.subckt and_gate a=a[10] b=b[6] out=s_wallace_cla32_and_10_6
.subckt and_gate a=a[9] b=b[7] out=s_wallace_cla32_and_9_7
.subckt fa a=s_wallace_cla32_fa177_or0 b=s_wallace_cla32_and_10_6 cin=s_wallace_cla32_and_9_7 fa_xor1=s_wallace_cla32_fa178_xor1 fa_or0=s_wallace_cla32_fa178_or0
.subckt and_gate a=a[11] b=b[6] out=s_wallace_cla32_and_11_6
.subckt and_gate a=a[10] b=b[7] out=s_wallace_cla32_and_10_7
.subckt fa a=s_wallace_cla32_fa178_or0 b=s_wallace_cla32_and_11_6 cin=s_wallace_cla32_and_10_7 fa_xor1=s_wallace_cla32_fa179_xor1 fa_or0=s_wallace_cla32_fa179_or0
.subckt and_gate a=a[12] b=b[6] out=s_wallace_cla32_and_12_6
.subckt and_gate a=a[11] b=b[7] out=s_wallace_cla32_and_11_7
.subckt fa a=s_wallace_cla32_fa179_or0 b=s_wallace_cla32_and_12_6 cin=s_wallace_cla32_and_11_7 fa_xor1=s_wallace_cla32_fa180_xor1 fa_or0=s_wallace_cla32_fa180_or0
.subckt and_gate a=a[13] b=b[6] out=s_wallace_cla32_and_13_6
.subckt and_gate a=a[12] b=b[7] out=s_wallace_cla32_and_12_7
.subckt fa a=s_wallace_cla32_fa180_or0 b=s_wallace_cla32_and_13_6 cin=s_wallace_cla32_and_12_7 fa_xor1=s_wallace_cla32_fa181_xor1 fa_or0=s_wallace_cla32_fa181_or0
.subckt and_gate a=a[14] b=b[6] out=s_wallace_cla32_and_14_6
.subckt and_gate a=a[13] b=b[7] out=s_wallace_cla32_and_13_7
.subckt fa a=s_wallace_cla32_fa181_or0 b=s_wallace_cla32_and_14_6 cin=s_wallace_cla32_and_13_7 fa_xor1=s_wallace_cla32_fa182_xor1 fa_or0=s_wallace_cla32_fa182_or0
.subckt and_gate a=a[15] b=b[6] out=s_wallace_cla32_and_15_6
.subckt and_gate a=a[14] b=b[7] out=s_wallace_cla32_and_14_7
.subckt fa a=s_wallace_cla32_fa182_or0 b=s_wallace_cla32_and_15_6 cin=s_wallace_cla32_and_14_7 fa_xor1=s_wallace_cla32_fa183_xor1 fa_or0=s_wallace_cla32_fa183_or0
.subckt and_gate a=a[16] b=b[6] out=s_wallace_cla32_and_16_6
.subckt and_gate a=a[15] b=b[7] out=s_wallace_cla32_and_15_7
.subckt fa a=s_wallace_cla32_fa183_or0 b=s_wallace_cla32_and_16_6 cin=s_wallace_cla32_and_15_7 fa_xor1=s_wallace_cla32_fa184_xor1 fa_or0=s_wallace_cla32_fa184_or0
.subckt and_gate a=a[17] b=b[6] out=s_wallace_cla32_and_17_6
.subckt and_gate a=a[16] b=b[7] out=s_wallace_cla32_and_16_7
.subckt fa a=s_wallace_cla32_fa184_or0 b=s_wallace_cla32_and_17_6 cin=s_wallace_cla32_and_16_7 fa_xor1=s_wallace_cla32_fa185_xor1 fa_or0=s_wallace_cla32_fa185_or0
.subckt and_gate a=a[18] b=b[6] out=s_wallace_cla32_and_18_6
.subckt and_gate a=a[17] b=b[7] out=s_wallace_cla32_and_17_7
.subckt fa a=s_wallace_cla32_fa185_or0 b=s_wallace_cla32_and_18_6 cin=s_wallace_cla32_and_17_7 fa_xor1=s_wallace_cla32_fa186_xor1 fa_or0=s_wallace_cla32_fa186_or0
.subckt and_gate a=a[19] b=b[6] out=s_wallace_cla32_and_19_6
.subckt and_gate a=a[18] b=b[7] out=s_wallace_cla32_and_18_7
.subckt fa a=s_wallace_cla32_fa186_or0 b=s_wallace_cla32_and_19_6 cin=s_wallace_cla32_and_18_7 fa_xor1=s_wallace_cla32_fa187_xor1 fa_or0=s_wallace_cla32_fa187_or0
.subckt and_gate a=a[20] b=b[6] out=s_wallace_cla32_and_20_6
.subckt and_gate a=a[19] b=b[7] out=s_wallace_cla32_and_19_7
.subckt fa a=s_wallace_cla32_fa187_or0 b=s_wallace_cla32_and_20_6 cin=s_wallace_cla32_and_19_7 fa_xor1=s_wallace_cla32_fa188_xor1 fa_or0=s_wallace_cla32_fa188_or0
.subckt and_gate a=a[21] b=b[6] out=s_wallace_cla32_and_21_6
.subckt and_gate a=a[20] b=b[7] out=s_wallace_cla32_and_20_7
.subckt fa a=s_wallace_cla32_fa188_or0 b=s_wallace_cla32_and_21_6 cin=s_wallace_cla32_and_20_7 fa_xor1=s_wallace_cla32_fa189_xor1 fa_or0=s_wallace_cla32_fa189_or0
.subckt and_gate a=a[22] b=b[6] out=s_wallace_cla32_and_22_6
.subckt and_gate a=a[21] b=b[7] out=s_wallace_cla32_and_21_7
.subckt fa a=s_wallace_cla32_fa189_or0 b=s_wallace_cla32_and_22_6 cin=s_wallace_cla32_and_21_7 fa_xor1=s_wallace_cla32_fa190_xor1 fa_or0=s_wallace_cla32_fa190_or0
.subckt and_gate a=a[23] b=b[6] out=s_wallace_cla32_and_23_6
.subckt and_gate a=a[22] b=b[7] out=s_wallace_cla32_and_22_7
.subckt fa a=s_wallace_cla32_fa190_or0 b=s_wallace_cla32_and_23_6 cin=s_wallace_cla32_and_22_7 fa_xor1=s_wallace_cla32_fa191_xor1 fa_or0=s_wallace_cla32_fa191_or0
.subckt and_gate a=a[24] b=b[6] out=s_wallace_cla32_and_24_6
.subckt and_gate a=a[23] b=b[7] out=s_wallace_cla32_and_23_7
.subckt fa a=s_wallace_cla32_fa191_or0 b=s_wallace_cla32_and_24_6 cin=s_wallace_cla32_and_23_7 fa_xor1=s_wallace_cla32_fa192_xor1 fa_or0=s_wallace_cla32_fa192_or0
.subckt and_gate a=a[25] b=b[6] out=s_wallace_cla32_and_25_6
.subckt and_gate a=a[24] b=b[7] out=s_wallace_cla32_and_24_7
.subckt fa a=s_wallace_cla32_fa192_or0 b=s_wallace_cla32_and_25_6 cin=s_wallace_cla32_and_24_7 fa_xor1=s_wallace_cla32_fa193_xor1 fa_or0=s_wallace_cla32_fa193_or0
.subckt and_gate a=a[26] b=b[6] out=s_wallace_cla32_and_26_6
.subckt and_gate a=a[25] b=b[7] out=s_wallace_cla32_and_25_7
.subckt fa a=s_wallace_cla32_fa193_or0 b=s_wallace_cla32_and_26_6 cin=s_wallace_cla32_and_25_7 fa_xor1=s_wallace_cla32_fa194_xor1 fa_or0=s_wallace_cla32_fa194_or0
.subckt and_gate a=a[25] b=b[8] out=s_wallace_cla32_and_25_8
.subckt and_gate a=a[24] b=b[9] out=s_wallace_cla32_and_24_9
.subckt fa a=s_wallace_cla32_fa194_or0 b=s_wallace_cla32_and_25_8 cin=s_wallace_cla32_and_24_9 fa_xor1=s_wallace_cla32_fa195_xor1 fa_or0=s_wallace_cla32_fa195_or0
.subckt and_gate a=a[25] b=b[9] out=s_wallace_cla32_and_25_9
.subckt and_gate a=a[24] b=b[10] out=s_wallace_cla32_and_24_10
.subckt fa a=s_wallace_cla32_fa195_or0 b=s_wallace_cla32_and_25_9 cin=s_wallace_cla32_and_24_10 fa_xor1=s_wallace_cla32_fa196_xor1 fa_or0=s_wallace_cla32_fa196_or0
.subckt and_gate a=a[25] b=b[10] out=s_wallace_cla32_and_25_10
.subckt and_gate a=a[24] b=b[11] out=s_wallace_cla32_and_24_11
.subckt fa a=s_wallace_cla32_fa196_or0 b=s_wallace_cla32_and_25_10 cin=s_wallace_cla32_and_24_11 fa_xor1=s_wallace_cla32_fa197_xor1 fa_or0=s_wallace_cla32_fa197_or0
.subckt and_gate a=a[25] b=b[11] out=s_wallace_cla32_and_25_11
.subckt and_gate a=a[24] b=b[12] out=s_wallace_cla32_and_24_12
.subckt fa a=s_wallace_cla32_fa197_or0 b=s_wallace_cla32_and_25_11 cin=s_wallace_cla32_and_24_12 fa_xor1=s_wallace_cla32_fa198_xor1 fa_or0=s_wallace_cla32_fa198_or0
.subckt and_gate a=a[25] b=b[12] out=s_wallace_cla32_and_25_12
.subckt and_gate a=a[24] b=b[13] out=s_wallace_cla32_and_24_13
.subckt fa a=s_wallace_cla32_fa198_or0 b=s_wallace_cla32_and_25_12 cin=s_wallace_cla32_and_24_13 fa_xor1=s_wallace_cla32_fa199_xor1 fa_or0=s_wallace_cla32_fa199_or0
.subckt and_gate a=a[25] b=b[13] out=s_wallace_cla32_and_25_13
.subckt and_gate a=a[24] b=b[14] out=s_wallace_cla32_and_24_14
.subckt fa a=s_wallace_cla32_fa199_or0 b=s_wallace_cla32_and_25_13 cin=s_wallace_cla32_and_24_14 fa_xor1=s_wallace_cla32_fa200_xor1 fa_or0=s_wallace_cla32_fa200_or0
.subckt and_gate a=a[25] b=b[14] out=s_wallace_cla32_and_25_14
.subckt and_gate a=a[24] b=b[15] out=s_wallace_cla32_and_24_15
.subckt fa a=s_wallace_cla32_fa200_or0 b=s_wallace_cla32_and_25_14 cin=s_wallace_cla32_and_24_15 fa_xor1=s_wallace_cla32_fa201_xor1 fa_or0=s_wallace_cla32_fa201_or0
.subckt and_gate a=a[25] b=b[15] out=s_wallace_cla32_and_25_15
.subckt and_gate a=a[24] b=b[16] out=s_wallace_cla32_and_24_16
.subckt fa a=s_wallace_cla32_fa201_or0 b=s_wallace_cla32_and_25_15 cin=s_wallace_cla32_and_24_16 fa_xor1=s_wallace_cla32_fa202_xor1 fa_or0=s_wallace_cla32_fa202_or0
.subckt and_gate a=a[25] b=b[16] out=s_wallace_cla32_and_25_16
.subckt and_gate a=a[24] b=b[17] out=s_wallace_cla32_and_24_17
.subckt fa a=s_wallace_cla32_fa202_or0 b=s_wallace_cla32_and_25_16 cin=s_wallace_cla32_and_24_17 fa_xor1=s_wallace_cla32_fa203_xor1 fa_or0=s_wallace_cla32_fa203_or0
.subckt and_gate a=a[25] b=b[17] out=s_wallace_cla32_and_25_17
.subckt and_gate a=a[24] b=b[18] out=s_wallace_cla32_and_24_18
.subckt fa a=s_wallace_cla32_fa203_or0 b=s_wallace_cla32_and_25_17 cin=s_wallace_cla32_and_24_18 fa_xor1=s_wallace_cla32_fa204_xor1 fa_or0=s_wallace_cla32_fa204_or0
.subckt and_gate a=a[25] b=b[18] out=s_wallace_cla32_and_25_18
.subckt and_gate a=a[24] b=b[19] out=s_wallace_cla32_and_24_19
.subckt fa a=s_wallace_cla32_fa204_or0 b=s_wallace_cla32_and_25_18 cin=s_wallace_cla32_and_24_19 fa_xor1=s_wallace_cla32_fa205_xor1 fa_or0=s_wallace_cla32_fa205_or0
.subckt and_gate a=a[25] b=b[19] out=s_wallace_cla32_and_25_19
.subckt and_gate a=a[24] b=b[20] out=s_wallace_cla32_and_24_20
.subckt fa a=s_wallace_cla32_fa205_or0 b=s_wallace_cla32_and_25_19 cin=s_wallace_cla32_and_24_20 fa_xor1=s_wallace_cla32_fa206_xor1 fa_or0=s_wallace_cla32_fa206_or0
.subckt and_gate a=a[25] b=b[20] out=s_wallace_cla32_and_25_20
.subckt and_gate a=a[24] b=b[21] out=s_wallace_cla32_and_24_21
.subckt fa a=s_wallace_cla32_fa206_or0 b=s_wallace_cla32_and_25_20 cin=s_wallace_cla32_and_24_21 fa_xor1=s_wallace_cla32_fa207_xor1 fa_or0=s_wallace_cla32_fa207_or0
.subckt and_gate a=a[25] b=b[21] out=s_wallace_cla32_and_25_21
.subckt and_gate a=a[24] b=b[22] out=s_wallace_cla32_and_24_22
.subckt fa a=s_wallace_cla32_fa207_or0 b=s_wallace_cla32_and_25_21 cin=s_wallace_cla32_and_24_22 fa_xor1=s_wallace_cla32_fa208_xor1 fa_or0=s_wallace_cla32_fa208_or0
.subckt and_gate a=a[25] b=b[22] out=s_wallace_cla32_and_25_22
.subckt and_gate a=a[24] b=b[23] out=s_wallace_cla32_and_24_23
.subckt fa a=s_wallace_cla32_fa208_or0 b=s_wallace_cla32_and_25_22 cin=s_wallace_cla32_and_24_23 fa_xor1=s_wallace_cla32_fa209_xor1 fa_or0=s_wallace_cla32_fa209_or0
.subckt and_gate a=a[25] b=b[23] out=s_wallace_cla32_and_25_23
.subckt and_gate a=a[24] b=b[24] out=s_wallace_cla32_and_24_24
.subckt fa a=s_wallace_cla32_fa209_or0 b=s_wallace_cla32_and_25_23 cin=s_wallace_cla32_and_24_24 fa_xor1=s_wallace_cla32_fa210_xor1 fa_or0=s_wallace_cla32_fa210_or0
.subckt and_gate a=a[25] b=b[24] out=s_wallace_cla32_and_25_24
.subckt and_gate a=a[24] b=b[25] out=s_wallace_cla32_and_24_25
.subckt fa a=s_wallace_cla32_fa210_or0 b=s_wallace_cla32_and_25_24 cin=s_wallace_cla32_and_24_25 fa_xor1=s_wallace_cla32_fa211_xor1 fa_or0=s_wallace_cla32_fa211_or0
.subckt and_gate a=a[25] b=b[25] out=s_wallace_cla32_and_25_25
.subckt and_gate a=a[24] b=b[26] out=s_wallace_cla32_and_24_26
.subckt fa a=s_wallace_cla32_fa211_or0 b=s_wallace_cla32_and_25_25 cin=s_wallace_cla32_and_24_26 fa_xor1=s_wallace_cla32_fa212_xor1 fa_or0=s_wallace_cla32_fa212_or0
.subckt and_gate a=a[25] b=b[26] out=s_wallace_cla32_and_25_26
.subckt and_gate a=a[24] b=b[27] out=s_wallace_cla32_and_24_27
.subckt fa a=s_wallace_cla32_fa212_or0 b=s_wallace_cla32_and_25_26 cin=s_wallace_cla32_and_24_27 fa_xor1=s_wallace_cla32_fa213_xor1 fa_or0=s_wallace_cla32_fa213_or0
.subckt and_gate a=a[25] b=b[27] out=s_wallace_cla32_and_25_27
.subckt and_gate a=a[24] b=b[28] out=s_wallace_cla32_and_24_28
.subckt fa a=s_wallace_cla32_fa213_or0 b=s_wallace_cla32_and_25_27 cin=s_wallace_cla32_and_24_28 fa_xor1=s_wallace_cla32_fa214_xor1 fa_or0=s_wallace_cla32_fa214_or0
.subckt and_gate a=a[25] b=b[28] out=s_wallace_cla32_and_25_28
.subckt and_gate a=a[24] b=b[29] out=s_wallace_cla32_and_24_29
.subckt fa a=s_wallace_cla32_fa214_or0 b=s_wallace_cla32_and_25_28 cin=s_wallace_cla32_and_24_29 fa_xor1=s_wallace_cla32_fa215_xor1 fa_or0=s_wallace_cla32_fa215_or0
.subckt and_gate a=a[25] b=b[29] out=s_wallace_cla32_and_25_29
.subckt and_gate a=a[24] b=b[30] out=s_wallace_cla32_and_24_30
.subckt fa a=s_wallace_cla32_fa215_or0 b=s_wallace_cla32_and_25_29 cin=s_wallace_cla32_and_24_30 fa_xor1=s_wallace_cla32_fa216_xor1 fa_or0=s_wallace_cla32_fa216_or0
.subckt and_gate a=a[25] b=b[30] out=s_wallace_cla32_and_25_30
.subckt nand_gate a=a[24] b=b[31] out=s_wallace_cla32_nand_24_31
.subckt fa a=s_wallace_cla32_fa216_or0 b=s_wallace_cla32_and_25_30 cin=s_wallace_cla32_nand_24_31 fa_xor1=s_wallace_cla32_fa217_xor1 fa_or0=s_wallace_cla32_fa217_or0
.subckt nand_gate a=a[25] b=b[31] out=s_wallace_cla32_nand_25_31
.subckt fa a=s_wallace_cla32_fa217_or0 b=s_wallace_cla32_nand_25_31 cin=s_wallace_cla32_fa53_xor1 fa_xor1=s_wallace_cla32_fa218_xor1 fa_or0=s_wallace_cla32_fa218_or0
.subckt fa a=s_wallace_cla32_fa218_or0 b=s_wallace_cla32_fa54_xor1 cin=s_wallace_cla32_fa111_xor1 fa_xor1=s_wallace_cla32_fa219_xor1 fa_or0=s_wallace_cla32_fa219_or0
.subckt ha a=s_wallace_cla32_fa60_xor1 b=s_wallace_cla32_fa115_xor1 ha_xor0=s_wallace_cla32_ha4_xor0 ha_and0=s_wallace_cla32_ha4_and0
.subckt fa a=s_wallace_cla32_ha4_and0 b=s_wallace_cla32_fa4_xor1 cin=s_wallace_cla32_fa61_xor1 fa_xor1=s_wallace_cla32_fa220_xor1 fa_or0=s_wallace_cla32_fa220_or0
.subckt and_gate a=a[0] b=b[8] out=s_wallace_cla32_and_0_8
.subckt fa a=s_wallace_cla32_fa220_or0 b=s_wallace_cla32_and_0_8 cin=s_wallace_cla32_fa5_xor1 fa_xor1=s_wallace_cla32_fa221_xor1 fa_or0=s_wallace_cla32_fa221_or0
.subckt and_gate a=a[1] b=b[8] out=s_wallace_cla32_and_1_8
.subckt and_gate a=a[0] b=b[9] out=s_wallace_cla32_and_0_9
.subckt fa a=s_wallace_cla32_fa221_or0 b=s_wallace_cla32_and_1_8 cin=s_wallace_cla32_and_0_9 fa_xor1=s_wallace_cla32_fa222_xor1 fa_or0=s_wallace_cla32_fa222_or0
.subckt and_gate a=a[2] b=b[8] out=s_wallace_cla32_and_2_8
.subckt and_gate a=a[1] b=b[9] out=s_wallace_cla32_and_1_9
.subckt fa a=s_wallace_cla32_fa222_or0 b=s_wallace_cla32_and_2_8 cin=s_wallace_cla32_and_1_9 fa_xor1=s_wallace_cla32_fa223_xor1 fa_or0=s_wallace_cla32_fa223_or0
.subckt and_gate a=a[3] b=b[8] out=s_wallace_cla32_and_3_8
.subckt and_gate a=a[2] b=b[9] out=s_wallace_cla32_and_2_9
.subckt fa a=s_wallace_cla32_fa223_or0 b=s_wallace_cla32_and_3_8 cin=s_wallace_cla32_and_2_9 fa_xor1=s_wallace_cla32_fa224_xor1 fa_or0=s_wallace_cla32_fa224_or0
.subckt and_gate a=a[4] b=b[8] out=s_wallace_cla32_and_4_8
.subckt and_gate a=a[3] b=b[9] out=s_wallace_cla32_and_3_9
.subckt fa a=s_wallace_cla32_fa224_or0 b=s_wallace_cla32_and_4_8 cin=s_wallace_cla32_and_3_9 fa_xor1=s_wallace_cla32_fa225_xor1 fa_or0=s_wallace_cla32_fa225_or0
.subckt and_gate a=a[5] b=b[8] out=s_wallace_cla32_and_5_8
.subckt and_gate a=a[4] b=b[9] out=s_wallace_cla32_and_4_9
.subckt fa a=s_wallace_cla32_fa225_or0 b=s_wallace_cla32_and_5_8 cin=s_wallace_cla32_and_4_9 fa_xor1=s_wallace_cla32_fa226_xor1 fa_or0=s_wallace_cla32_fa226_or0
.subckt and_gate a=a[6] b=b[8] out=s_wallace_cla32_and_6_8
.subckt and_gate a=a[5] b=b[9] out=s_wallace_cla32_and_5_9
.subckt fa a=s_wallace_cla32_fa226_or0 b=s_wallace_cla32_and_6_8 cin=s_wallace_cla32_and_5_9 fa_xor1=s_wallace_cla32_fa227_xor1 fa_or0=s_wallace_cla32_fa227_or0
.subckt and_gate a=a[7] b=b[8] out=s_wallace_cla32_and_7_8
.subckt and_gate a=a[6] b=b[9] out=s_wallace_cla32_and_6_9
.subckt fa a=s_wallace_cla32_fa227_or0 b=s_wallace_cla32_and_7_8 cin=s_wallace_cla32_and_6_9 fa_xor1=s_wallace_cla32_fa228_xor1 fa_or0=s_wallace_cla32_fa228_or0
.subckt and_gate a=a[8] b=b[8] out=s_wallace_cla32_and_8_8
.subckt and_gate a=a[7] b=b[9] out=s_wallace_cla32_and_7_9
.subckt fa a=s_wallace_cla32_fa228_or0 b=s_wallace_cla32_and_8_8 cin=s_wallace_cla32_and_7_9 fa_xor1=s_wallace_cla32_fa229_xor1 fa_or0=s_wallace_cla32_fa229_or0
.subckt and_gate a=a[9] b=b[8] out=s_wallace_cla32_and_9_8
.subckt and_gate a=a[8] b=b[9] out=s_wallace_cla32_and_8_9
.subckt fa a=s_wallace_cla32_fa229_or0 b=s_wallace_cla32_and_9_8 cin=s_wallace_cla32_and_8_9 fa_xor1=s_wallace_cla32_fa230_xor1 fa_or0=s_wallace_cla32_fa230_or0
.subckt and_gate a=a[10] b=b[8] out=s_wallace_cla32_and_10_8
.subckt and_gate a=a[9] b=b[9] out=s_wallace_cla32_and_9_9
.subckt fa a=s_wallace_cla32_fa230_or0 b=s_wallace_cla32_and_10_8 cin=s_wallace_cla32_and_9_9 fa_xor1=s_wallace_cla32_fa231_xor1 fa_or0=s_wallace_cla32_fa231_or0
.subckt and_gate a=a[11] b=b[8] out=s_wallace_cla32_and_11_8
.subckt and_gate a=a[10] b=b[9] out=s_wallace_cla32_and_10_9
.subckt fa a=s_wallace_cla32_fa231_or0 b=s_wallace_cla32_and_11_8 cin=s_wallace_cla32_and_10_9 fa_xor1=s_wallace_cla32_fa232_xor1 fa_or0=s_wallace_cla32_fa232_or0
.subckt and_gate a=a[12] b=b[8] out=s_wallace_cla32_and_12_8
.subckt and_gate a=a[11] b=b[9] out=s_wallace_cla32_and_11_9
.subckt fa a=s_wallace_cla32_fa232_or0 b=s_wallace_cla32_and_12_8 cin=s_wallace_cla32_and_11_9 fa_xor1=s_wallace_cla32_fa233_xor1 fa_or0=s_wallace_cla32_fa233_or0
.subckt and_gate a=a[13] b=b[8] out=s_wallace_cla32_and_13_8
.subckt and_gate a=a[12] b=b[9] out=s_wallace_cla32_and_12_9
.subckt fa a=s_wallace_cla32_fa233_or0 b=s_wallace_cla32_and_13_8 cin=s_wallace_cla32_and_12_9 fa_xor1=s_wallace_cla32_fa234_xor1 fa_or0=s_wallace_cla32_fa234_or0
.subckt and_gate a=a[14] b=b[8] out=s_wallace_cla32_and_14_8
.subckt and_gate a=a[13] b=b[9] out=s_wallace_cla32_and_13_9
.subckt fa a=s_wallace_cla32_fa234_or0 b=s_wallace_cla32_and_14_8 cin=s_wallace_cla32_and_13_9 fa_xor1=s_wallace_cla32_fa235_xor1 fa_or0=s_wallace_cla32_fa235_or0
.subckt and_gate a=a[15] b=b[8] out=s_wallace_cla32_and_15_8
.subckt and_gate a=a[14] b=b[9] out=s_wallace_cla32_and_14_9
.subckt fa a=s_wallace_cla32_fa235_or0 b=s_wallace_cla32_and_15_8 cin=s_wallace_cla32_and_14_9 fa_xor1=s_wallace_cla32_fa236_xor1 fa_or0=s_wallace_cla32_fa236_or0
.subckt and_gate a=a[16] b=b[8] out=s_wallace_cla32_and_16_8
.subckt and_gate a=a[15] b=b[9] out=s_wallace_cla32_and_15_9
.subckt fa a=s_wallace_cla32_fa236_or0 b=s_wallace_cla32_and_16_8 cin=s_wallace_cla32_and_15_9 fa_xor1=s_wallace_cla32_fa237_xor1 fa_or0=s_wallace_cla32_fa237_or0
.subckt and_gate a=a[17] b=b[8] out=s_wallace_cla32_and_17_8
.subckt and_gate a=a[16] b=b[9] out=s_wallace_cla32_and_16_9
.subckt fa a=s_wallace_cla32_fa237_or0 b=s_wallace_cla32_and_17_8 cin=s_wallace_cla32_and_16_9 fa_xor1=s_wallace_cla32_fa238_xor1 fa_or0=s_wallace_cla32_fa238_or0
.subckt and_gate a=a[18] b=b[8] out=s_wallace_cla32_and_18_8
.subckt and_gate a=a[17] b=b[9] out=s_wallace_cla32_and_17_9
.subckt fa a=s_wallace_cla32_fa238_or0 b=s_wallace_cla32_and_18_8 cin=s_wallace_cla32_and_17_9 fa_xor1=s_wallace_cla32_fa239_xor1 fa_or0=s_wallace_cla32_fa239_or0
.subckt and_gate a=a[19] b=b[8] out=s_wallace_cla32_and_19_8
.subckt and_gate a=a[18] b=b[9] out=s_wallace_cla32_and_18_9
.subckt fa a=s_wallace_cla32_fa239_or0 b=s_wallace_cla32_and_19_8 cin=s_wallace_cla32_and_18_9 fa_xor1=s_wallace_cla32_fa240_xor1 fa_or0=s_wallace_cla32_fa240_or0
.subckt and_gate a=a[20] b=b[8] out=s_wallace_cla32_and_20_8
.subckt and_gate a=a[19] b=b[9] out=s_wallace_cla32_and_19_9
.subckt fa a=s_wallace_cla32_fa240_or0 b=s_wallace_cla32_and_20_8 cin=s_wallace_cla32_and_19_9 fa_xor1=s_wallace_cla32_fa241_xor1 fa_or0=s_wallace_cla32_fa241_or0
.subckt and_gate a=a[21] b=b[8] out=s_wallace_cla32_and_21_8
.subckt and_gate a=a[20] b=b[9] out=s_wallace_cla32_and_20_9
.subckt fa a=s_wallace_cla32_fa241_or0 b=s_wallace_cla32_and_21_8 cin=s_wallace_cla32_and_20_9 fa_xor1=s_wallace_cla32_fa242_xor1 fa_or0=s_wallace_cla32_fa242_or0
.subckt and_gate a=a[22] b=b[8] out=s_wallace_cla32_and_22_8
.subckt and_gate a=a[21] b=b[9] out=s_wallace_cla32_and_21_9
.subckt fa a=s_wallace_cla32_fa242_or0 b=s_wallace_cla32_and_22_8 cin=s_wallace_cla32_and_21_9 fa_xor1=s_wallace_cla32_fa243_xor1 fa_or0=s_wallace_cla32_fa243_or0
.subckt and_gate a=a[23] b=b[8] out=s_wallace_cla32_and_23_8
.subckt and_gate a=a[22] b=b[9] out=s_wallace_cla32_and_22_9
.subckt fa a=s_wallace_cla32_fa243_or0 b=s_wallace_cla32_and_23_8 cin=s_wallace_cla32_and_22_9 fa_xor1=s_wallace_cla32_fa244_xor1 fa_or0=s_wallace_cla32_fa244_or0
.subckt and_gate a=a[24] b=b[8] out=s_wallace_cla32_and_24_8
.subckt and_gate a=a[23] b=b[9] out=s_wallace_cla32_and_23_9
.subckt fa a=s_wallace_cla32_fa244_or0 b=s_wallace_cla32_and_24_8 cin=s_wallace_cla32_and_23_9 fa_xor1=s_wallace_cla32_fa245_xor1 fa_or0=s_wallace_cla32_fa245_or0
.subckt and_gate a=a[23] b=b[10] out=s_wallace_cla32_and_23_10
.subckt and_gate a=a[22] b=b[11] out=s_wallace_cla32_and_22_11
.subckt fa a=s_wallace_cla32_fa245_or0 b=s_wallace_cla32_and_23_10 cin=s_wallace_cla32_and_22_11 fa_xor1=s_wallace_cla32_fa246_xor1 fa_or0=s_wallace_cla32_fa246_or0
.subckt and_gate a=a[23] b=b[11] out=s_wallace_cla32_and_23_11
.subckt and_gate a=a[22] b=b[12] out=s_wallace_cla32_and_22_12
.subckt fa a=s_wallace_cla32_fa246_or0 b=s_wallace_cla32_and_23_11 cin=s_wallace_cla32_and_22_12 fa_xor1=s_wallace_cla32_fa247_xor1 fa_or0=s_wallace_cla32_fa247_or0
.subckt and_gate a=a[23] b=b[12] out=s_wallace_cla32_and_23_12
.subckt and_gate a=a[22] b=b[13] out=s_wallace_cla32_and_22_13
.subckt fa a=s_wallace_cla32_fa247_or0 b=s_wallace_cla32_and_23_12 cin=s_wallace_cla32_and_22_13 fa_xor1=s_wallace_cla32_fa248_xor1 fa_or0=s_wallace_cla32_fa248_or0
.subckt and_gate a=a[23] b=b[13] out=s_wallace_cla32_and_23_13
.subckt and_gate a=a[22] b=b[14] out=s_wallace_cla32_and_22_14
.subckt fa a=s_wallace_cla32_fa248_or0 b=s_wallace_cla32_and_23_13 cin=s_wallace_cla32_and_22_14 fa_xor1=s_wallace_cla32_fa249_xor1 fa_or0=s_wallace_cla32_fa249_or0
.subckt and_gate a=a[23] b=b[14] out=s_wallace_cla32_and_23_14
.subckt and_gate a=a[22] b=b[15] out=s_wallace_cla32_and_22_15
.subckt fa a=s_wallace_cla32_fa249_or0 b=s_wallace_cla32_and_23_14 cin=s_wallace_cla32_and_22_15 fa_xor1=s_wallace_cla32_fa250_xor1 fa_or0=s_wallace_cla32_fa250_or0
.subckt and_gate a=a[23] b=b[15] out=s_wallace_cla32_and_23_15
.subckt and_gate a=a[22] b=b[16] out=s_wallace_cla32_and_22_16
.subckt fa a=s_wallace_cla32_fa250_or0 b=s_wallace_cla32_and_23_15 cin=s_wallace_cla32_and_22_16 fa_xor1=s_wallace_cla32_fa251_xor1 fa_or0=s_wallace_cla32_fa251_or0
.subckt and_gate a=a[23] b=b[16] out=s_wallace_cla32_and_23_16
.subckt and_gate a=a[22] b=b[17] out=s_wallace_cla32_and_22_17
.subckt fa a=s_wallace_cla32_fa251_or0 b=s_wallace_cla32_and_23_16 cin=s_wallace_cla32_and_22_17 fa_xor1=s_wallace_cla32_fa252_xor1 fa_or0=s_wallace_cla32_fa252_or0
.subckt and_gate a=a[23] b=b[17] out=s_wallace_cla32_and_23_17
.subckt and_gate a=a[22] b=b[18] out=s_wallace_cla32_and_22_18
.subckt fa a=s_wallace_cla32_fa252_or0 b=s_wallace_cla32_and_23_17 cin=s_wallace_cla32_and_22_18 fa_xor1=s_wallace_cla32_fa253_xor1 fa_or0=s_wallace_cla32_fa253_or0
.subckt and_gate a=a[23] b=b[18] out=s_wallace_cla32_and_23_18
.subckt and_gate a=a[22] b=b[19] out=s_wallace_cla32_and_22_19
.subckt fa a=s_wallace_cla32_fa253_or0 b=s_wallace_cla32_and_23_18 cin=s_wallace_cla32_and_22_19 fa_xor1=s_wallace_cla32_fa254_xor1 fa_or0=s_wallace_cla32_fa254_or0
.subckt and_gate a=a[23] b=b[19] out=s_wallace_cla32_and_23_19
.subckt and_gate a=a[22] b=b[20] out=s_wallace_cla32_and_22_20
.subckt fa a=s_wallace_cla32_fa254_or0 b=s_wallace_cla32_and_23_19 cin=s_wallace_cla32_and_22_20 fa_xor1=s_wallace_cla32_fa255_xor1 fa_or0=s_wallace_cla32_fa255_or0
.subckt and_gate a=a[23] b=b[20] out=s_wallace_cla32_and_23_20
.subckt and_gate a=a[22] b=b[21] out=s_wallace_cla32_and_22_21
.subckt fa a=s_wallace_cla32_fa255_or0 b=s_wallace_cla32_and_23_20 cin=s_wallace_cla32_and_22_21 fa_xor1=s_wallace_cla32_fa256_xor1 fa_or0=s_wallace_cla32_fa256_or0
.subckt and_gate a=a[23] b=b[21] out=s_wallace_cla32_and_23_21
.subckt and_gate a=a[22] b=b[22] out=s_wallace_cla32_and_22_22
.subckt fa a=s_wallace_cla32_fa256_or0 b=s_wallace_cla32_and_23_21 cin=s_wallace_cla32_and_22_22 fa_xor1=s_wallace_cla32_fa257_xor1 fa_or0=s_wallace_cla32_fa257_or0
.subckt and_gate a=a[23] b=b[22] out=s_wallace_cla32_and_23_22
.subckt and_gate a=a[22] b=b[23] out=s_wallace_cla32_and_22_23
.subckt fa a=s_wallace_cla32_fa257_or0 b=s_wallace_cla32_and_23_22 cin=s_wallace_cla32_and_22_23 fa_xor1=s_wallace_cla32_fa258_xor1 fa_or0=s_wallace_cla32_fa258_or0
.subckt and_gate a=a[23] b=b[23] out=s_wallace_cla32_and_23_23
.subckt and_gate a=a[22] b=b[24] out=s_wallace_cla32_and_22_24
.subckt fa a=s_wallace_cla32_fa258_or0 b=s_wallace_cla32_and_23_23 cin=s_wallace_cla32_and_22_24 fa_xor1=s_wallace_cla32_fa259_xor1 fa_or0=s_wallace_cla32_fa259_or0
.subckt and_gate a=a[23] b=b[24] out=s_wallace_cla32_and_23_24
.subckt and_gate a=a[22] b=b[25] out=s_wallace_cla32_and_22_25
.subckt fa a=s_wallace_cla32_fa259_or0 b=s_wallace_cla32_and_23_24 cin=s_wallace_cla32_and_22_25 fa_xor1=s_wallace_cla32_fa260_xor1 fa_or0=s_wallace_cla32_fa260_or0
.subckt and_gate a=a[23] b=b[25] out=s_wallace_cla32_and_23_25
.subckt and_gate a=a[22] b=b[26] out=s_wallace_cla32_and_22_26
.subckt fa a=s_wallace_cla32_fa260_or0 b=s_wallace_cla32_and_23_25 cin=s_wallace_cla32_and_22_26 fa_xor1=s_wallace_cla32_fa261_xor1 fa_or0=s_wallace_cla32_fa261_or0
.subckt and_gate a=a[23] b=b[26] out=s_wallace_cla32_and_23_26
.subckt and_gate a=a[22] b=b[27] out=s_wallace_cla32_and_22_27
.subckt fa a=s_wallace_cla32_fa261_or0 b=s_wallace_cla32_and_23_26 cin=s_wallace_cla32_and_22_27 fa_xor1=s_wallace_cla32_fa262_xor1 fa_or0=s_wallace_cla32_fa262_or0
.subckt and_gate a=a[23] b=b[27] out=s_wallace_cla32_and_23_27
.subckt and_gate a=a[22] b=b[28] out=s_wallace_cla32_and_22_28
.subckt fa a=s_wallace_cla32_fa262_or0 b=s_wallace_cla32_and_23_27 cin=s_wallace_cla32_and_22_28 fa_xor1=s_wallace_cla32_fa263_xor1 fa_or0=s_wallace_cla32_fa263_or0
.subckt and_gate a=a[23] b=b[28] out=s_wallace_cla32_and_23_28
.subckt and_gate a=a[22] b=b[29] out=s_wallace_cla32_and_22_29
.subckt fa a=s_wallace_cla32_fa263_or0 b=s_wallace_cla32_and_23_28 cin=s_wallace_cla32_and_22_29 fa_xor1=s_wallace_cla32_fa264_xor1 fa_or0=s_wallace_cla32_fa264_or0
.subckt and_gate a=a[23] b=b[29] out=s_wallace_cla32_and_23_29
.subckt and_gate a=a[22] b=b[30] out=s_wallace_cla32_and_22_30
.subckt fa a=s_wallace_cla32_fa264_or0 b=s_wallace_cla32_and_23_29 cin=s_wallace_cla32_and_22_30 fa_xor1=s_wallace_cla32_fa265_xor1 fa_or0=s_wallace_cla32_fa265_or0
.subckt and_gate a=a[23] b=b[30] out=s_wallace_cla32_and_23_30
.subckt nand_gate a=a[22] b=b[31] out=s_wallace_cla32_nand_22_31
.subckt fa a=s_wallace_cla32_fa265_or0 b=s_wallace_cla32_and_23_30 cin=s_wallace_cla32_nand_22_31 fa_xor1=s_wallace_cla32_fa266_xor1 fa_or0=s_wallace_cla32_fa266_or0
.subckt nand_gate a=a[23] b=b[31] out=s_wallace_cla32_nand_23_31
.subckt fa a=s_wallace_cla32_fa266_or0 b=s_wallace_cla32_nand_23_31 cin=s_wallace_cla32_fa51_xor1 fa_xor1=s_wallace_cla32_fa267_xor1 fa_or0=s_wallace_cla32_fa267_or0
.subckt fa a=s_wallace_cla32_fa267_or0 b=s_wallace_cla32_fa52_xor1 cin=s_wallace_cla32_fa109_xor1 fa_xor1=s_wallace_cla32_fa268_xor1 fa_or0=s_wallace_cla32_fa268_or0
.subckt fa a=s_wallace_cla32_fa268_or0 b=s_wallace_cla32_fa110_xor1 cin=s_wallace_cla32_fa165_xor1 fa_xor1=s_wallace_cla32_fa269_xor1 fa_or0=s_wallace_cla32_fa269_or0
.subckt ha a=s_wallace_cla32_fa116_xor1 b=s_wallace_cla32_fa169_xor1 ha_xor0=s_wallace_cla32_ha5_xor0 ha_and0=s_wallace_cla32_ha5_and0
.subckt fa a=s_wallace_cla32_ha5_and0 b=s_wallace_cla32_fa62_xor1 cin=s_wallace_cla32_fa117_xor1 fa_xor1=s_wallace_cla32_fa270_xor1 fa_or0=s_wallace_cla32_fa270_or0
.subckt fa a=s_wallace_cla32_fa270_or0 b=s_wallace_cla32_fa6_xor1 cin=s_wallace_cla32_fa63_xor1 fa_xor1=s_wallace_cla32_fa271_xor1 fa_or0=s_wallace_cla32_fa271_or0
.subckt and_gate a=a[0] b=b[10] out=s_wallace_cla32_and_0_10
.subckt fa a=s_wallace_cla32_fa271_or0 b=s_wallace_cla32_and_0_10 cin=s_wallace_cla32_fa7_xor1 fa_xor1=s_wallace_cla32_fa272_xor1 fa_or0=s_wallace_cla32_fa272_or0
.subckt and_gate a=a[1] b=b[10] out=s_wallace_cla32_and_1_10
.subckt and_gate a=a[0] b=b[11] out=s_wallace_cla32_and_0_11
.subckt fa a=s_wallace_cla32_fa272_or0 b=s_wallace_cla32_and_1_10 cin=s_wallace_cla32_and_0_11 fa_xor1=s_wallace_cla32_fa273_xor1 fa_or0=s_wallace_cla32_fa273_or0
.subckt and_gate a=a[2] b=b[10] out=s_wallace_cla32_and_2_10
.subckt and_gate a=a[1] b=b[11] out=s_wallace_cla32_and_1_11
.subckt fa a=s_wallace_cla32_fa273_or0 b=s_wallace_cla32_and_2_10 cin=s_wallace_cla32_and_1_11 fa_xor1=s_wallace_cla32_fa274_xor1 fa_or0=s_wallace_cla32_fa274_or0
.subckt and_gate a=a[3] b=b[10] out=s_wallace_cla32_and_3_10
.subckt and_gate a=a[2] b=b[11] out=s_wallace_cla32_and_2_11
.subckt fa a=s_wallace_cla32_fa274_or0 b=s_wallace_cla32_and_3_10 cin=s_wallace_cla32_and_2_11 fa_xor1=s_wallace_cla32_fa275_xor1 fa_or0=s_wallace_cla32_fa275_or0
.subckt and_gate a=a[4] b=b[10] out=s_wallace_cla32_and_4_10
.subckt and_gate a=a[3] b=b[11] out=s_wallace_cla32_and_3_11
.subckt fa a=s_wallace_cla32_fa275_or0 b=s_wallace_cla32_and_4_10 cin=s_wallace_cla32_and_3_11 fa_xor1=s_wallace_cla32_fa276_xor1 fa_or0=s_wallace_cla32_fa276_or0
.subckt and_gate a=a[5] b=b[10] out=s_wallace_cla32_and_5_10
.subckt and_gate a=a[4] b=b[11] out=s_wallace_cla32_and_4_11
.subckt fa a=s_wallace_cla32_fa276_or0 b=s_wallace_cla32_and_5_10 cin=s_wallace_cla32_and_4_11 fa_xor1=s_wallace_cla32_fa277_xor1 fa_or0=s_wallace_cla32_fa277_or0
.subckt and_gate a=a[6] b=b[10] out=s_wallace_cla32_and_6_10
.subckt and_gate a=a[5] b=b[11] out=s_wallace_cla32_and_5_11
.subckt fa a=s_wallace_cla32_fa277_or0 b=s_wallace_cla32_and_6_10 cin=s_wallace_cla32_and_5_11 fa_xor1=s_wallace_cla32_fa278_xor1 fa_or0=s_wallace_cla32_fa278_or0
.subckt and_gate a=a[7] b=b[10] out=s_wallace_cla32_and_7_10
.subckt and_gate a=a[6] b=b[11] out=s_wallace_cla32_and_6_11
.subckt fa a=s_wallace_cla32_fa278_or0 b=s_wallace_cla32_and_7_10 cin=s_wallace_cla32_and_6_11 fa_xor1=s_wallace_cla32_fa279_xor1 fa_or0=s_wallace_cla32_fa279_or0
.subckt and_gate a=a[8] b=b[10] out=s_wallace_cla32_and_8_10
.subckt and_gate a=a[7] b=b[11] out=s_wallace_cla32_and_7_11
.subckt fa a=s_wallace_cla32_fa279_or0 b=s_wallace_cla32_and_8_10 cin=s_wallace_cla32_and_7_11 fa_xor1=s_wallace_cla32_fa280_xor1 fa_or0=s_wallace_cla32_fa280_or0
.subckt and_gate a=a[9] b=b[10] out=s_wallace_cla32_and_9_10
.subckt and_gate a=a[8] b=b[11] out=s_wallace_cla32_and_8_11
.subckt fa a=s_wallace_cla32_fa280_or0 b=s_wallace_cla32_and_9_10 cin=s_wallace_cla32_and_8_11 fa_xor1=s_wallace_cla32_fa281_xor1 fa_or0=s_wallace_cla32_fa281_or0
.subckt and_gate a=a[10] b=b[10] out=s_wallace_cla32_and_10_10
.subckt and_gate a=a[9] b=b[11] out=s_wallace_cla32_and_9_11
.subckt fa a=s_wallace_cla32_fa281_or0 b=s_wallace_cla32_and_10_10 cin=s_wallace_cla32_and_9_11 fa_xor1=s_wallace_cla32_fa282_xor1 fa_or0=s_wallace_cla32_fa282_or0
.subckt and_gate a=a[11] b=b[10] out=s_wallace_cla32_and_11_10
.subckt and_gate a=a[10] b=b[11] out=s_wallace_cla32_and_10_11
.subckt fa a=s_wallace_cla32_fa282_or0 b=s_wallace_cla32_and_11_10 cin=s_wallace_cla32_and_10_11 fa_xor1=s_wallace_cla32_fa283_xor1 fa_or0=s_wallace_cla32_fa283_or0
.subckt and_gate a=a[12] b=b[10] out=s_wallace_cla32_and_12_10
.subckt and_gate a=a[11] b=b[11] out=s_wallace_cla32_and_11_11
.subckt fa a=s_wallace_cla32_fa283_or0 b=s_wallace_cla32_and_12_10 cin=s_wallace_cla32_and_11_11 fa_xor1=s_wallace_cla32_fa284_xor1 fa_or0=s_wallace_cla32_fa284_or0
.subckt and_gate a=a[13] b=b[10] out=s_wallace_cla32_and_13_10
.subckt and_gate a=a[12] b=b[11] out=s_wallace_cla32_and_12_11
.subckt fa a=s_wallace_cla32_fa284_or0 b=s_wallace_cla32_and_13_10 cin=s_wallace_cla32_and_12_11 fa_xor1=s_wallace_cla32_fa285_xor1 fa_or0=s_wallace_cla32_fa285_or0
.subckt and_gate a=a[14] b=b[10] out=s_wallace_cla32_and_14_10
.subckt and_gate a=a[13] b=b[11] out=s_wallace_cla32_and_13_11
.subckt fa a=s_wallace_cla32_fa285_or0 b=s_wallace_cla32_and_14_10 cin=s_wallace_cla32_and_13_11 fa_xor1=s_wallace_cla32_fa286_xor1 fa_or0=s_wallace_cla32_fa286_or0
.subckt and_gate a=a[15] b=b[10] out=s_wallace_cla32_and_15_10
.subckt and_gate a=a[14] b=b[11] out=s_wallace_cla32_and_14_11
.subckt fa a=s_wallace_cla32_fa286_or0 b=s_wallace_cla32_and_15_10 cin=s_wallace_cla32_and_14_11 fa_xor1=s_wallace_cla32_fa287_xor1 fa_or0=s_wallace_cla32_fa287_or0
.subckt and_gate a=a[16] b=b[10] out=s_wallace_cla32_and_16_10
.subckt and_gate a=a[15] b=b[11] out=s_wallace_cla32_and_15_11
.subckt fa a=s_wallace_cla32_fa287_or0 b=s_wallace_cla32_and_16_10 cin=s_wallace_cla32_and_15_11 fa_xor1=s_wallace_cla32_fa288_xor1 fa_or0=s_wallace_cla32_fa288_or0
.subckt and_gate a=a[17] b=b[10] out=s_wallace_cla32_and_17_10
.subckt and_gate a=a[16] b=b[11] out=s_wallace_cla32_and_16_11
.subckt fa a=s_wallace_cla32_fa288_or0 b=s_wallace_cla32_and_17_10 cin=s_wallace_cla32_and_16_11 fa_xor1=s_wallace_cla32_fa289_xor1 fa_or0=s_wallace_cla32_fa289_or0
.subckt and_gate a=a[18] b=b[10] out=s_wallace_cla32_and_18_10
.subckt and_gate a=a[17] b=b[11] out=s_wallace_cla32_and_17_11
.subckt fa a=s_wallace_cla32_fa289_or0 b=s_wallace_cla32_and_18_10 cin=s_wallace_cla32_and_17_11 fa_xor1=s_wallace_cla32_fa290_xor1 fa_or0=s_wallace_cla32_fa290_or0
.subckt and_gate a=a[19] b=b[10] out=s_wallace_cla32_and_19_10
.subckt and_gate a=a[18] b=b[11] out=s_wallace_cla32_and_18_11
.subckt fa a=s_wallace_cla32_fa290_or0 b=s_wallace_cla32_and_19_10 cin=s_wallace_cla32_and_18_11 fa_xor1=s_wallace_cla32_fa291_xor1 fa_or0=s_wallace_cla32_fa291_or0
.subckt and_gate a=a[20] b=b[10] out=s_wallace_cla32_and_20_10
.subckt and_gate a=a[19] b=b[11] out=s_wallace_cla32_and_19_11
.subckt fa a=s_wallace_cla32_fa291_or0 b=s_wallace_cla32_and_20_10 cin=s_wallace_cla32_and_19_11 fa_xor1=s_wallace_cla32_fa292_xor1 fa_or0=s_wallace_cla32_fa292_or0
.subckt and_gate a=a[21] b=b[10] out=s_wallace_cla32_and_21_10
.subckt and_gate a=a[20] b=b[11] out=s_wallace_cla32_and_20_11
.subckt fa a=s_wallace_cla32_fa292_or0 b=s_wallace_cla32_and_21_10 cin=s_wallace_cla32_and_20_11 fa_xor1=s_wallace_cla32_fa293_xor1 fa_or0=s_wallace_cla32_fa293_or0
.subckt and_gate a=a[22] b=b[10] out=s_wallace_cla32_and_22_10
.subckt and_gate a=a[21] b=b[11] out=s_wallace_cla32_and_21_11
.subckt fa a=s_wallace_cla32_fa293_or0 b=s_wallace_cla32_and_22_10 cin=s_wallace_cla32_and_21_11 fa_xor1=s_wallace_cla32_fa294_xor1 fa_or0=s_wallace_cla32_fa294_or0
.subckt and_gate a=a[21] b=b[12] out=s_wallace_cla32_and_21_12
.subckt and_gate a=a[20] b=b[13] out=s_wallace_cla32_and_20_13
.subckt fa a=s_wallace_cla32_fa294_or0 b=s_wallace_cla32_and_21_12 cin=s_wallace_cla32_and_20_13 fa_xor1=s_wallace_cla32_fa295_xor1 fa_or0=s_wallace_cla32_fa295_or0
.subckt and_gate a=a[21] b=b[13] out=s_wallace_cla32_and_21_13
.subckt and_gate a=a[20] b=b[14] out=s_wallace_cla32_and_20_14
.subckt fa a=s_wallace_cla32_fa295_or0 b=s_wallace_cla32_and_21_13 cin=s_wallace_cla32_and_20_14 fa_xor1=s_wallace_cla32_fa296_xor1 fa_or0=s_wallace_cla32_fa296_or0
.subckt and_gate a=a[21] b=b[14] out=s_wallace_cla32_and_21_14
.subckt and_gate a=a[20] b=b[15] out=s_wallace_cla32_and_20_15
.subckt fa a=s_wallace_cla32_fa296_or0 b=s_wallace_cla32_and_21_14 cin=s_wallace_cla32_and_20_15 fa_xor1=s_wallace_cla32_fa297_xor1 fa_or0=s_wallace_cla32_fa297_or0
.subckt and_gate a=a[21] b=b[15] out=s_wallace_cla32_and_21_15
.subckt and_gate a=a[20] b=b[16] out=s_wallace_cla32_and_20_16
.subckt fa a=s_wallace_cla32_fa297_or0 b=s_wallace_cla32_and_21_15 cin=s_wallace_cla32_and_20_16 fa_xor1=s_wallace_cla32_fa298_xor1 fa_or0=s_wallace_cla32_fa298_or0
.subckt and_gate a=a[21] b=b[16] out=s_wallace_cla32_and_21_16
.subckt and_gate a=a[20] b=b[17] out=s_wallace_cla32_and_20_17
.subckt fa a=s_wallace_cla32_fa298_or0 b=s_wallace_cla32_and_21_16 cin=s_wallace_cla32_and_20_17 fa_xor1=s_wallace_cla32_fa299_xor1 fa_or0=s_wallace_cla32_fa299_or0
.subckt and_gate a=a[21] b=b[17] out=s_wallace_cla32_and_21_17
.subckt and_gate a=a[20] b=b[18] out=s_wallace_cla32_and_20_18
.subckt fa a=s_wallace_cla32_fa299_or0 b=s_wallace_cla32_and_21_17 cin=s_wallace_cla32_and_20_18 fa_xor1=s_wallace_cla32_fa300_xor1 fa_or0=s_wallace_cla32_fa300_or0
.subckt and_gate a=a[21] b=b[18] out=s_wallace_cla32_and_21_18
.subckt and_gate a=a[20] b=b[19] out=s_wallace_cla32_and_20_19
.subckt fa a=s_wallace_cla32_fa300_or0 b=s_wallace_cla32_and_21_18 cin=s_wallace_cla32_and_20_19 fa_xor1=s_wallace_cla32_fa301_xor1 fa_or0=s_wallace_cla32_fa301_or0
.subckt and_gate a=a[21] b=b[19] out=s_wallace_cla32_and_21_19
.subckt and_gate a=a[20] b=b[20] out=s_wallace_cla32_and_20_20
.subckt fa a=s_wallace_cla32_fa301_or0 b=s_wallace_cla32_and_21_19 cin=s_wallace_cla32_and_20_20 fa_xor1=s_wallace_cla32_fa302_xor1 fa_or0=s_wallace_cla32_fa302_or0
.subckt and_gate a=a[21] b=b[20] out=s_wallace_cla32_and_21_20
.subckt and_gate a=a[20] b=b[21] out=s_wallace_cla32_and_20_21
.subckt fa a=s_wallace_cla32_fa302_or0 b=s_wallace_cla32_and_21_20 cin=s_wallace_cla32_and_20_21 fa_xor1=s_wallace_cla32_fa303_xor1 fa_or0=s_wallace_cla32_fa303_or0
.subckt and_gate a=a[21] b=b[21] out=s_wallace_cla32_and_21_21
.subckt and_gate a=a[20] b=b[22] out=s_wallace_cla32_and_20_22
.subckt fa a=s_wallace_cla32_fa303_or0 b=s_wallace_cla32_and_21_21 cin=s_wallace_cla32_and_20_22 fa_xor1=s_wallace_cla32_fa304_xor1 fa_or0=s_wallace_cla32_fa304_or0
.subckt and_gate a=a[21] b=b[22] out=s_wallace_cla32_and_21_22
.subckt and_gate a=a[20] b=b[23] out=s_wallace_cla32_and_20_23
.subckt fa a=s_wallace_cla32_fa304_or0 b=s_wallace_cla32_and_21_22 cin=s_wallace_cla32_and_20_23 fa_xor1=s_wallace_cla32_fa305_xor1 fa_or0=s_wallace_cla32_fa305_or0
.subckt and_gate a=a[21] b=b[23] out=s_wallace_cla32_and_21_23
.subckt and_gate a=a[20] b=b[24] out=s_wallace_cla32_and_20_24
.subckt fa a=s_wallace_cla32_fa305_or0 b=s_wallace_cla32_and_21_23 cin=s_wallace_cla32_and_20_24 fa_xor1=s_wallace_cla32_fa306_xor1 fa_or0=s_wallace_cla32_fa306_or0
.subckt and_gate a=a[21] b=b[24] out=s_wallace_cla32_and_21_24
.subckt and_gate a=a[20] b=b[25] out=s_wallace_cla32_and_20_25
.subckt fa a=s_wallace_cla32_fa306_or0 b=s_wallace_cla32_and_21_24 cin=s_wallace_cla32_and_20_25 fa_xor1=s_wallace_cla32_fa307_xor1 fa_or0=s_wallace_cla32_fa307_or0
.subckt and_gate a=a[21] b=b[25] out=s_wallace_cla32_and_21_25
.subckt and_gate a=a[20] b=b[26] out=s_wallace_cla32_and_20_26
.subckt fa a=s_wallace_cla32_fa307_or0 b=s_wallace_cla32_and_21_25 cin=s_wallace_cla32_and_20_26 fa_xor1=s_wallace_cla32_fa308_xor1 fa_or0=s_wallace_cla32_fa308_or0
.subckt and_gate a=a[21] b=b[26] out=s_wallace_cla32_and_21_26
.subckt and_gate a=a[20] b=b[27] out=s_wallace_cla32_and_20_27
.subckt fa a=s_wallace_cla32_fa308_or0 b=s_wallace_cla32_and_21_26 cin=s_wallace_cla32_and_20_27 fa_xor1=s_wallace_cla32_fa309_xor1 fa_or0=s_wallace_cla32_fa309_or0
.subckt and_gate a=a[21] b=b[27] out=s_wallace_cla32_and_21_27
.subckt and_gate a=a[20] b=b[28] out=s_wallace_cla32_and_20_28
.subckt fa a=s_wallace_cla32_fa309_or0 b=s_wallace_cla32_and_21_27 cin=s_wallace_cla32_and_20_28 fa_xor1=s_wallace_cla32_fa310_xor1 fa_or0=s_wallace_cla32_fa310_or0
.subckt and_gate a=a[21] b=b[28] out=s_wallace_cla32_and_21_28
.subckt and_gate a=a[20] b=b[29] out=s_wallace_cla32_and_20_29
.subckt fa a=s_wallace_cla32_fa310_or0 b=s_wallace_cla32_and_21_28 cin=s_wallace_cla32_and_20_29 fa_xor1=s_wallace_cla32_fa311_xor1 fa_or0=s_wallace_cla32_fa311_or0
.subckt and_gate a=a[21] b=b[29] out=s_wallace_cla32_and_21_29
.subckt and_gate a=a[20] b=b[30] out=s_wallace_cla32_and_20_30
.subckt fa a=s_wallace_cla32_fa311_or0 b=s_wallace_cla32_and_21_29 cin=s_wallace_cla32_and_20_30 fa_xor1=s_wallace_cla32_fa312_xor1 fa_or0=s_wallace_cla32_fa312_or0
.subckt and_gate a=a[21] b=b[30] out=s_wallace_cla32_and_21_30
.subckt nand_gate a=a[20] b=b[31] out=s_wallace_cla32_nand_20_31
.subckt fa a=s_wallace_cla32_fa312_or0 b=s_wallace_cla32_and_21_30 cin=s_wallace_cla32_nand_20_31 fa_xor1=s_wallace_cla32_fa313_xor1 fa_or0=s_wallace_cla32_fa313_or0
.subckt nand_gate a=a[21] b=b[31] out=s_wallace_cla32_nand_21_31
.subckt fa a=s_wallace_cla32_fa313_or0 b=s_wallace_cla32_nand_21_31 cin=s_wallace_cla32_fa49_xor1 fa_xor1=s_wallace_cla32_fa314_xor1 fa_or0=s_wallace_cla32_fa314_or0
.subckt fa a=s_wallace_cla32_fa314_or0 b=s_wallace_cla32_fa50_xor1 cin=s_wallace_cla32_fa107_xor1 fa_xor1=s_wallace_cla32_fa315_xor1 fa_or0=s_wallace_cla32_fa315_or0
.subckt fa a=s_wallace_cla32_fa315_or0 b=s_wallace_cla32_fa108_xor1 cin=s_wallace_cla32_fa163_xor1 fa_xor1=s_wallace_cla32_fa316_xor1 fa_or0=s_wallace_cla32_fa316_or0
.subckt fa a=s_wallace_cla32_fa316_or0 b=s_wallace_cla32_fa164_xor1 cin=s_wallace_cla32_fa217_xor1 fa_xor1=s_wallace_cla32_fa317_xor1 fa_or0=s_wallace_cla32_fa317_or0
.subckt ha a=s_wallace_cla32_fa170_xor1 b=s_wallace_cla32_fa221_xor1 ha_xor0=s_wallace_cla32_ha6_xor0 ha_and0=s_wallace_cla32_ha6_and0
.subckt fa a=s_wallace_cla32_ha6_and0 b=s_wallace_cla32_fa118_xor1 cin=s_wallace_cla32_fa171_xor1 fa_xor1=s_wallace_cla32_fa318_xor1 fa_or0=s_wallace_cla32_fa318_or0
.subckt fa a=s_wallace_cla32_fa318_or0 b=s_wallace_cla32_fa64_xor1 cin=s_wallace_cla32_fa119_xor1 fa_xor1=s_wallace_cla32_fa319_xor1 fa_or0=s_wallace_cla32_fa319_or0
.subckt fa a=s_wallace_cla32_fa319_or0 b=s_wallace_cla32_fa8_xor1 cin=s_wallace_cla32_fa65_xor1 fa_xor1=s_wallace_cla32_fa320_xor1 fa_or0=s_wallace_cla32_fa320_or0
.subckt and_gate a=a[0] b=b[12] out=s_wallace_cla32_and_0_12
.subckt fa a=s_wallace_cla32_fa320_or0 b=s_wallace_cla32_and_0_12 cin=s_wallace_cla32_fa9_xor1 fa_xor1=s_wallace_cla32_fa321_xor1 fa_or0=s_wallace_cla32_fa321_or0
.subckt and_gate a=a[1] b=b[12] out=s_wallace_cla32_and_1_12
.subckt and_gate a=a[0] b=b[13] out=s_wallace_cla32_and_0_13
.subckt fa a=s_wallace_cla32_fa321_or0 b=s_wallace_cla32_and_1_12 cin=s_wallace_cla32_and_0_13 fa_xor1=s_wallace_cla32_fa322_xor1 fa_or0=s_wallace_cla32_fa322_or0
.subckt and_gate a=a[2] b=b[12] out=s_wallace_cla32_and_2_12
.subckt and_gate a=a[1] b=b[13] out=s_wallace_cla32_and_1_13
.subckt fa a=s_wallace_cla32_fa322_or0 b=s_wallace_cla32_and_2_12 cin=s_wallace_cla32_and_1_13 fa_xor1=s_wallace_cla32_fa323_xor1 fa_or0=s_wallace_cla32_fa323_or0
.subckt and_gate a=a[3] b=b[12] out=s_wallace_cla32_and_3_12
.subckt and_gate a=a[2] b=b[13] out=s_wallace_cla32_and_2_13
.subckt fa a=s_wallace_cla32_fa323_or0 b=s_wallace_cla32_and_3_12 cin=s_wallace_cla32_and_2_13 fa_xor1=s_wallace_cla32_fa324_xor1 fa_or0=s_wallace_cla32_fa324_or0
.subckt and_gate a=a[4] b=b[12] out=s_wallace_cla32_and_4_12
.subckt and_gate a=a[3] b=b[13] out=s_wallace_cla32_and_3_13
.subckt fa a=s_wallace_cla32_fa324_or0 b=s_wallace_cla32_and_4_12 cin=s_wallace_cla32_and_3_13 fa_xor1=s_wallace_cla32_fa325_xor1 fa_or0=s_wallace_cla32_fa325_or0
.subckt and_gate a=a[5] b=b[12] out=s_wallace_cla32_and_5_12
.subckt and_gate a=a[4] b=b[13] out=s_wallace_cla32_and_4_13
.subckt fa a=s_wallace_cla32_fa325_or0 b=s_wallace_cla32_and_5_12 cin=s_wallace_cla32_and_4_13 fa_xor1=s_wallace_cla32_fa326_xor1 fa_or0=s_wallace_cla32_fa326_or0
.subckt and_gate a=a[6] b=b[12] out=s_wallace_cla32_and_6_12
.subckt and_gate a=a[5] b=b[13] out=s_wallace_cla32_and_5_13
.subckt fa a=s_wallace_cla32_fa326_or0 b=s_wallace_cla32_and_6_12 cin=s_wallace_cla32_and_5_13 fa_xor1=s_wallace_cla32_fa327_xor1 fa_or0=s_wallace_cla32_fa327_or0
.subckt and_gate a=a[7] b=b[12] out=s_wallace_cla32_and_7_12
.subckt and_gate a=a[6] b=b[13] out=s_wallace_cla32_and_6_13
.subckt fa a=s_wallace_cla32_fa327_or0 b=s_wallace_cla32_and_7_12 cin=s_wallace_cla32_and_6_13 fa_xor1=s_wallace_cla32_fa328_xor1 fa_or0=s_wallace_cla32_fa328_or0
.subckt and_gate a=a[8] b=b[12] out=s_wallace_cla32_and_8_12
.subckt and_gate a=a[7] b=b[13] out=s_wallace_cla32_and_7_13
.subckt fa a=s_wallace_cla32_fa328_or0 b=s_wallace_cla32_and_8_12 cin=s_wallace_cla32_and_7_13 fa_xor1=s_wallace_cla32_fa329_xor1 fa_or0=s_wallace_cla32_fa329_or0
.subckt and_gate a=a[9] b=b[12] out=s_wallace_cla32_and_9_12
.subckt and_gate a=a[8] b=b[13] out=s_wallace_cla32_and_8_13
.subckt fa a=s_wallace_cla32_fa329_or0 b=s_wallace_cla32_and_9_12 cin=s_wallace_cla32_and_8_13 fa_xor1=s_wallace_cla32_fa330_xor1 fa_or0=s_wallace_cla32_fa330_or0
.subckt and_gate a=a[10] b=b[12] out=s_wallace_cla32_and_10_12
.subckt and_gate a=a[9] b=b[13] out=s_wallace_cla32_and_9_13
.subckt fa a=s_wallace_cla32_fa330_or0 b=s_wallace_cla32_and_10_12 cin=s_wallace_cla32_and_9_13 fa_xor1=s_wallace_cla32_fa331_xor1 fa_or0=s_wallace_cla32_fa331_or0
.subckt and_gate a=a[11] b=b[12] out=s_wallace_cla32_and_11_12
.subckt and_gate a=a[10] b=b[13] out=s_wallace_cla32_and_10_13
.subckt fa a=s_wallace_cla32_fa331_or0 b=s_wallace_cla32_and_11_12 cin=s_wallace_cla32_and_10_13 fa_xor1=s_wallace_cla32_fa332_xor1 fa_or0=s_wallace_cla32_fa332_or0
.subckt and_gate a=a[12] b=b[12] out=s_wallace_cla32_and_12_12
.subckt and_gate a=a[11] b=b[13] out=s_wallace_cla32_and_11_13
.subckt fa a=s_wallace_cla32_fa332_or0 b=s_wallace_cla32_and_12_12 cin=s_wallace_cla32_and_11_13 fa_xor1=s_wallace_cla32_fa333_xor1 fa_or0=s_wallace_cla32_fa333_or0
.subckt and_gate a=a[13] b=b[12] out=s_wallace_cla32_and_13_12
.subckt and_gate a=a[12] b=b[13] out=s_wallace_cla32_and_12_13
.subckt fa a=s_wallace_cla32_fa333_or0 b=s_wallace_cla32_and_13_12 cin=s_wallace_cla32_and_12_13 fa_xor1=s_wallace_cla32_fa334_xor1 fa_or0=s_wallace_cla32_fa334_or0
.subckt and_gate a=a[14] b=b[12] out=s_wallace_cla32_and_14_12
.subckt and_gate a=a[13] b=b[13] out=s_wallace_cla32_and_13_13
.subckt fa a=s_wallace_cla32_fa334_or0 b=s_wallace_cla32_and_14_12 cin=s_wallace_cla32_and_13_13 fa_xor1=s_wallace_cla32_fa335_xor1 fa_or0=s_wallace_cla32_fa335_or0
.subckt and_gate a=a[15] b=b[12] out=s_wallace_cla32_and_15_12
.subckt and_gate a=a[14] b=b[13] out=s_wallace_cla32_and_14_13
.subckt fa a=s_wallace_cla32_fa335_or0 b=s_wallace_cla32_and_15_12 cin=s_wallace_cla32_and_14_13 fa_xor1=s_wallace_cla32_fa336_xor1 fa_or0=s_wallace_cla32_fa336_or0
.subckt and_gate a=a[16] b=b[12] out=s_wallace_cla32_and_16_12
.subckt and_gate a=a[15] b=b[13] out=s_wallace_cla32_and_15_13
.subckt fa a=s_wallace_cla32_fa336_or0 b=s_wallace_cla32_and_16_12 cin=s_wallace_cla32_and_15_13 fa_xor1=s_wallace_cla32_fa337_xor1 fa_or0=s_wallace_cla32_fa337_or0
.subckt and_gate a=a[17] b=b[12] out=s_wallace_cla32_and_17_12
.subckt and_gate a=a[16] b=b[13] out=s_wallace_cla32_and_16_13
.subckt fa a=s_wallace_cla32_fa337_or0 b=s_wallace_cla32_and_17_12 cin=s_wallace_cla32_and_16_13 fa_xor1=s_wallace_cla32_fa338_xor1 fa_or0=s_wallace_cla32_fa338_or0
.subckt and_gate a=a[18] b=b[12] out=s_wallace_cla32_and_18_12
.subckt and_gate a=a[17] b=b[13] out=s_wallace_cla32_and_17_13
.subckt fa a=s_wallace_cla32_fa338_or0 b=s_wallace_cla32_and_18_12 cin=s_wallace_cla32_and_17_13 fa_xor1=s_wallace_cla32_fa339_xor1 fa_or0=s_wallace_cla32_fa339_or0
.subckt and_gate a=a[19] b=b[12] out=s_wallace_cla32_and_19_12
.subckt and_gate a=a[18] b=b[13] out=s_wallace_cla32_and_18_13
.subckt fa a=s_wallace_cla32_fa339_or0 b=s_wallace_cla32_and_19_12 cin=s_wallace_cla32_and_18_13 fa_xor1=s_wallace_cla32_fa340_xor1 fa_or0=s_wallace_cla32_fa340_or0
.subckt and_gate a=a[20] b=b[12] out=s_wallace_cla32_and_20_12
.subckt and_gate a=a[19] b=b[13] out=s_wallace_cla32_and_19_13
.subckt fa a=s_wallace_cla32_fa340_or0 b=s_wallace_cla32_and_20_12 cin=s_wallace_cla32_and_19_13 fa_xor1=s_wallace_cla32_fa341_xor1 fa_or0=s_wallace_cla32_fa341_or0
.subckt and_gate a=a[19] b=b[14] out=s_wallace_cla32_and_19_14
.subckt and_gate a=a[18] b=b[15] out=s_wallace_cla32_and_18_15
.subckt fa a=s_wallace_cla32_fa341_or0 b=s_wallace_cla32_and_19_14 cin=s_wallace_cla32_and_18_15 fa_xor1=s_wallace_cla32_fa342_xor1 fa_or0=s_wallace_cla32_fa342_or0
.subckt and_gate a=a[19] b=b[15] out=s_wallace_cla32_and_19_15
.subckt and_gate a=a[18] b=b[16] out=s_wallace_cla32_and_18_16
.subckt fa a=s_wallace_cla32_fa342_or0 b=s_wallace_cla32_and_19_15 cin=s_wallace_cla32_and_18_16 fa_xor1=s_wallace_cla32_fa343_xor1 fa_or0=s_wallace_cla32_fa343_or0
.subckt and_gate a=a[19] b=b[16] out=s_wallace_cla32_and_19_16
.subckt and_gate a=a[18] b=b[17] out=s_wallace_cla32_and_18_17
.subckt fa a=s_wallace_cla32_fa343_or0 b=s_wallace_cla32_and_19_16 cin=s_wallace_cla32_and_18_17 fa_xor1=s_wallace_cla32_fa344_xor1 fa_or0=s_wallace_cla32_fa344_or0
.subckt and_gate a=a[19] b=b[17] out=s_wallace_cla32_and_19_17
.subckt and_gate a=a[18] b=b[18] out=s_wallace_cla32_and_18_18
.subckt fa a=s_wallace_cla32_fa344_or0 b=s_wallace_cla32_and_19_17 cin=s_wallace_cla32_and_18_18 fa_xor1=s_wallace_cla32_fa345_xor1 fa_or0=s_wallace_cla32_fa345_or0
.subckt and_gate a=a[19] b=b[18] out=s_wallace_cla32_and_19_18
.subckt and_gate a=a[18] b=b[19] out=s_wallace_cla32_and_18_19
.subckt fa a=s_wallace_cla32_fa345_or0 b=s_wallace_cla32_and_19_18 cin=s_wallace_cla32_and_18_19 fa_xor1=s_wallace_cla32_fa346_xor1 fa_or0=s_wallace_cla32_fa346_or0
.subckt and_gate a=a[19] b=b[19] out=s_wallace_cla32_and_19_19
.subckt and_gate a=a[18] b=b[20] out=s_wallace_cla32_and_18_20
.subckt fa a=s_wallace_cla32_fa346_or0 b=s_wallace_cla32_and_19_19 cin=s_wallace_cla32_and_18_20 fa_xor1=s_wallace_cla32_fa347_xor1 fa_or0=s_wallace_cla32_fa347_or0
.subckt and_gate a=a[19] b=b[20] out=s_wallace_cla32_and_19_20
.subckt and_gate a=a[18] b=b[21] out=s_wallace_cla32_and_18_21
.subckt fa a=s_wallace_cla32_fa347_or0 b=s_wallace_cla32_and_19_20 cin=s_wallace_cla32_and_18_21 fa_xor1=s_wallace_cla32_fa348_xor1 fa_or0=s_wallace_cla32_fa348_or0
.subckt and_gate a=a[19] b=b[21] out=s_wallace_cla32_and_19_21
.subckt and_gate a=a[18] b=b[22] out=s_wallace_cla32_and_18_22
.subckt fa a=s_wallace_cla32_fa348_or0 b=s_wallace_cla32_and_19_21 cin=s_wallace_cla32_and_18_22 fa_xor1=s_wallace_cla32_fa349_xor1 fa_or0=s_wallace_cla32_fa349_or0
.subckt and_gate a=a[19] b=b[22] out=s_wallace_cla32_and_19_22
.subckt and_gate a=a[18] b=b[23] out=s_wallace_cla32_and_18_23
.subckt fa a=s_wallace_cla32_fa349_or0 b=s_wallace_cla32_and_19_22 cin=s_wallace_cla32_and_18_23 fa_xor1=s_wallace_cla32_fa350_xor1 fa_or0=s_wallace_cla32_fa350_or0
.subckt and_gate a=a[19] b=b[23] out=s_wallace_cla32_and_19_23
.subckt and_gate a=a[18] b=b[24] out=s_wallace_cla32_and_18_24
.subckt fa a=s_wallace_cla32_fa350_or0 b=s_wallace_cla32_and_19_23 cin=s_wallace_cla32_and_18_24 fa_xor1=s_wallace_cla32_fa351_xor1 fa_or0=s_wallace_cla32_fa351_or0
.subckt and_gate a=a[19] b=b[24] out=s_wallace_cla32_and_19_24
.subckt and_gate a=a[18] b=b[25] out=s_wallace_cla32_and_18_25
.subckt fa a=s_wallace_cla32_fa351_or0 b=s_wallace_cla32_and_19_24 cin=s_wallace_cla32_and_18_25 fa_xor1=s_wallace_cla32_fa352_xor1 fa_or0=s_wallace_cla32_fa352_or0
.subckt and_gate a=a[19] b=b[25] out=s_wallace_cla32_and_19_25
.subckt and_gate a=a[18] b=b[26] out=s_wallace_cla32_and_18_26
.subckt fa a=s_wallace_cla32_fa352_or0 b=s_wallace_cla32_and_19_25 cin=s_wallace_cla32_and_18_26 fa_xor1=s_wallace_cla32_fa353_xor1 fa_or0=s_wallace_cla32_fa353_or0
.subckt and_gate a=a[19] b=b[26] out=s_wallace_cla32_and_19_26
.subckt and_gate a=a[18] b=b[27] out=s_wallace_cla32_and_18_27
.subckt fa a=s_wallace_cla32_fa353_or0 b=s_wallace_cla32_and_19_26 cin=s_wallace_cla32_and_18_27 fa_xor1=s_wallace_cla32_fa354_xor1 fa_or0=s_wallace_cla32_fa354_or0
.subckt and_gate a=a[19] b=b[27] out=s_wallace_cla32_and_19_27
.subckt and_gate a=a[18] b=b[28] out=s_wallace_cla32_and_18_28
.subckt fa a=s_wallace_cla32_fa354_or0 b=s_wallace_cla32_and_19_27 cin=s_wallace_cla32_and_18_28 fa_xor1=s_wallace_cla32_fa355_xor1 fa_or0=s_wallace_cla32_fa355_or0
.subckt and_gate a=a[19] b=b[28] out=s_wallace_cla32_and_19_28
.subckt and_gate a=a[18] b=b[29] out=s_wallace_cla32_and_18_29
.subckt fa a=s_wallace_cla32_fa355_or0 b=s_wallace_cla32_and_19_28 cin=s_wallace_cla32_and_18_29 fa_xor1=s_wallace_cla32_fa356_xor1 fa_or0=s_wallace_cla32_fa356_or0
.subckt and_gate a=a[19] b=b[29] out=s_wallace_cla32_and_19_29
.subckt and_gate a=a[18] b=b[30] out=s_wallace_cla32_and_18_30
.subckt fa a=s_wallace_cla32_fa356_or0 b=s_wallace_cla32_and_19_29 cin=s_wallace_cla32_and_18_30 fa_xor1=s_wallace_cla32_fa357_xor1 fa_or0=s_wallace_cla32_fa357_or0
.subckt and_gate a=a[19] b=b[30] out=s_wallace_cla32_and_19_30
.subckt nand_gate a=a[18] b=b[31] out=s_wallace_cla32_nand_18_31
.subckt fa a=s_wallace_cla32_fa357_or0 b=s_wallace_cla32_and_19_30 cin=s_wallace_cla32_nand_18_31 fa_xor1=s_wallace_cla32_fa358_xor1 fa_or0=s_wallace_cla32_fa358_or0
.subckt nand_gate a=a[19] b=b[31] out=s_wallace_cla32_nand_19_31
.subckt fa a=s_wallace_cla32_fa358_or0 b=s_wallace_cla32_nand_19_31 cin=s_wallace_cla32_fa47_xor1 fa_xor1=s_wallace_cla32_fa359_xor1 fa_or0=s_wallace_cla32_fa359_or0
.subckt fa a=s_wallace_cla32_fa359_or0 b=s_wallace_cla32_fa48_xor1 cin=s_wallace_cla32_fa105_xor1 fa_xor1=s_wallace_cla32_fa360_xor1 fa_or0=s_wallace_cla32_fa360_or0
.subckt fa a=s_wallace_cla32_fa360_or0 b=s_wallace_cla32_fa106_xor1 cin=s_wallace_cla32_fa161_xor1 fa_xor1=s_wallace_cla32_fa361_xor1 fa_or0=s_wallace_cla32_fa361_or0
.subckt fa a=s_wallace_cla32_fa361_or0 b=s_wallace_cla32_fa162_xor1 cin=s_wallace_cla32_fa215_xor1 fa_xor1=s_wallace_cla32_fa362_xor1 fa_or0=s_wallace_cla32_fa362_or0
.subckt fa a=s_wallace_cla32_fa362_or0 b=s_wallace_cla32_fa216_xor1 cin=s_wallace_cla32_fa267_xor1 fa_xor1=s_wallace_cla32_fa363_xor1 fa_or0=s_wallace_cla32_fa363_or0
.subckt ha a=s_wallace_cla32_fa222_xor1 b=s_wallace_cla32_fa271_xor1 ha_xor0=s_wallace_cla32_ha7_xor0 ha_and0=s_wallace_cla32_ha7_and0
.subckt fa a=s_wallace_cla32_ha7_and0 b=s_wallace_cla32_fa172_xor1 cin=s_wallace_cla32_fa223_xor1 fa_xor1=s_wallace_cla32_fa364_xor1 fa_or0=s_wallace_cla32_fa364_or0
.subckt fa a=s_wallace_cla32_fa364_or0 b=s_wallace_cla32_fa120_xor1 cin=s_wallace_cla32_fa173_xor1 fa_xor1=s_wallace_cla32_fa365_xor1 fa_or0=s_wallace_cla32_fa365_or0
.subckt fa a=s_wallace_cla32_fa365_or0 b=s_wallace_cla32_fa66_xor1 cin=s_wallace_cla32_fa121_xor1 fa_xor1=s_wallace_cla32_fa366_xor1 fa_or0=s_wallace_cla32_fa366_or0
.subckt fa a=s_wallace_cla32_fa366_or0 b=s_wallace_cla32_fa10_xor1 cin=s_wallace_cla32_fa67_xor1 fa_xor1=s_wallace_cla32_fa367_xor1 fa_or0=s_wallace_cla32_fa367_or0
.subckt and_gate a=a[0] b=b[14] out=s_wallace_cla32_and_0_14
.subckt fa a=s_wallace_cla32_fa367_or0 b=s_wallace_cla32_and_0_14 cin=s_wallace_cla32_fa11_xor1 fa_xor1=s_wallace_cla32_fa368_xor1 fa_or0=s_wallace_cla32_fa368_or0
.subckt and_gate a=a[1] b=b[14] out=s_wallace_cla32_and_1_14
.subckt and_gate a=a[0] b=b[15] out=s_wallace_cla32_and_0_15
.subckt fa a=s_wallace_cla32_fa368_or0 b=s_wallace_cla32_and_1_14 cin=s_wallace_cla32_and_0_15 fa_xor1=s_wallace_cla32_fa369_xor1 fa_or0=s_wallace_cla32_fa369_or0
.subckt and_gate a=a[2] b=b[14] out=s_wallace_cla32_and_2_14
.subckt and_gate a=a[1] b=b[15] out=s_wallace_cla32_and_1_15
.subckt fa a=s_wallace_cla32_fa369_or0 b=s_wallace_cla32_and_2_14 cin=s_wallace_cla32_and_1_15 fa_xor1=s_wallace_cla32_fa370_xor1 fa_or0=s_wallace_cla32_fa370_or0
.subckt and_gate a=a[3] b=b[14] out=s_wallace_cla32_and_3_14
.subckt and_gate a=a[2] b=b[15] out=s_wallace_cla32_and_2_15
.subckt fa a=s_wallace_cla32_fa370_or0 b=s_wallace_cla32_and_3_14 cin=s_wallace_cla32_and_2_15 fa_xor1=s_wallace_cla32_fa371_xor1 fa_or0=s_wallace_cla32_fa371_or0
.subckt and_gate a=a[4] b=b[14] out=s_wallace_cla32_and_4_14
.subckt and_gate a=a[3] b=b[15] out=s_wallace_cla32_and_3_15
.subckt fa a=s_wallace_cla32_fa371_or0 b=s_wallace_cla32_and_4_14 cin=s_wallace_cla32_and_3_15 fa_xor1=s_wallace_cla32_fa372_xor1 fa_or0=s_wallace_cla32_fa372_or0
.subckt and_gate a=a[5] b=b[14] out=s_wallace_cla32_and_5_14
.subckt and_gate a=a[4] b=b[15] out=s_wallace_cla32_and_4_15
.subckt fa a=s_wallace_cla32_fa372_or0 b=s_wallace_cla32_and_5_14 cin=s_wallace_cla32_and_4_15 fa_xor1=s_wallace_cla32_fa373_xor1 fa_or0=s_wallace_cla32_fa373_or0
.subckt and_gate a=a[6] b=b[14] out=s_wallace_cla32_and_6_14
.subckt and_gate a=a[5] b=b[15] out=s_wallace_cla32_and_5_15
.subckt fa a=s_wallace_cla32_fa373_or0 b=s_wallace_cla32_and_6_14 cin=s_wallace_cla32_and_5_15 fa_xor1=s_wallace_cla32_fa374_xor1 fa_or0=s_wallace_cla32_fa374_or0
.subckt and_gate a=a[7] b=b[14] out=s_wallace_cla32_and_7_14
.subckt and_gate a=a[6] b=b[15] out=s_wallace_cla32_and_6_15
.subckt fa a=s_wallace_cla32_fa374_or0 b=s_wallace_cla32_and_7_14 cin=s_wallace_cla32_and_6_15 fa_xor1=s_wallace_cla32_fa375_xor1 fa_or0=s_wallace_cla32_fa375_or0
.subckt and_gate a=a[8] b=b[14] out=s_wallace_cla32_and_8_14
.subckt and_gate a=a[7] b=b[15] out=s_wallace_cla32_and_7_15
.subckt fa a=s_wallace_cla32_fa375_or0 b=s_wallace_cla32_and_8_14 cin=s_wallace_cla32_and_7_15 fa_xor1=s_wallace_cla32_fa376_xor1 fa_or0=s_wallace_cla32_fa376_or0
.subckt and_gate a=a[9] b=b[14] out=s_wallace_cla32_and_9_14
.subckt and_gate a=a[8] b=b[15] out=s_wallace_cla32_and_8_15
.subckt fa a=s_wallace_cla32_fa376_or0 b=s_wallace_cla32_and_9_14 cin=s_wallace_cla32_and_8_15 fa_xor1=s_wallace_cla32_fa377_xor1 fa_or0=s_wallace_cla32_fa377_or0
.subckt and_gate a=a[10] b=b[14] out=s_wallace_cla32_and_10_14
.subckt and_gate a=a[9] b=b[15] out=s_wallace_cla32_and_9_15
.subckt fa a=s_wallace_cla32_fa377_or0 b=s_wallace_cla32_and_10_14 cin=s_wallace_cla32_and_9_15 fa_xor1=s_wallace_cla32_fa378_xor1 fa_or0=s_wallace_cla32_fa378_or0
.subckt and_gate a=a[11] b=b[14] out=s_wallace_cla32_and_11_14
.subckt and_gate a=a[10] b=b[15] out=s_wallace_cla32_and_10_15
.subckt fa a=s_wallace_cla32_fa378_or0 b=s_wallace_cla32_and_11_14 cin=s_wallace_cla32_and_10_15 fa_xor1=s_wallace_cla32_fa379_xor1 fa_or0=s_wallace_cla32_fa379_or0
.subckt and_gate a=a[12] b=b[14] out=s_wallace_cla32_and_12_14
.subckt and_gate a=a[11] b=b[15] out=s_wallace_cla32_and_11_15
.subckt fa a=s_wallace_cla32_fa379_or0 b=s_wallace_cla32_and_12_14 cin=s_wallace_cla32_and_11_15 fa_xor1=s_wallace_cla32_fa380_xor1 fa_or0=s_wallace_cla32_fa380_or0
.subckt and_gate a=a[13] b=b[14] out=s_wallace_cla32_and_13_14
.subckt and_gate a=a[12] b=b[15] out=s_wallace_cla32_and_12_15
.subckt fa a=s_wallace_cla32_fa380_or0 b=s_wallace_cla32_and_13_14 cin=s_wallace_cla32_and_12_15 fa_xor1=s_wallace_cla32_fa381_xor1 fa_or0=s_wallace_cla32_fa381_or0
.subckt and_gate a=a[14] b=b[14] out=s_wallace_cla32_and_14_14
.subckt and_gate a=a[13] b=b[15] out=s_wallace_cla32_and_13_15
.subckt fa a=s_wallace_cla32_fa381_or0 b=s_wallace_cla32_and_14_14 cin=s_wallace_cla32_and_13_15 fa_xor1=s_wallace_cla32_fa382_xor1 fa_or0=s_wallace_cla32_fa382_or0
.subckt and_gate a=a[15] b=b[14] out=s_wallace_cla32_and_15_14
.subckt and_gate a=a[14] b=b[15] out=s_wallace_cla32_and_14_15
.subckt fa a=s_wallace_cla32_fa382_or0 b=s_wallace_cla32_and_15_14 cin=s_wallace_cla32_and_14_15 fa_xor1=s_wallace_cla32_fa383_xor1 fa_or0=s_wallace_cla32_fa383_or0
.subckt and_gate a=a[16] b=b[14] out=s_wallace_cla32_and_16_14
.subckt and_gate a=a[15] b=b[15] out=s_wallace_cla32_and_15_15
.subckt fa a=s_wallace_cla32_fa383_or0 b=s_wallace_cla32_and_16_14 cin=s_wallace_cla32_and_15_15 fa_xor1=s_wallace_cla32_fa384_xor1 fa_or0=s_wallace_cla32_fa384_or0
.subckt and_gate a=a[17] b=b[14] out=s_wallace_cla32_and_17_14
.subckt and_gate a=a[16] b=b[15] out=s_wallace_cla32_and_16_15
.subckt fa a=s_wallace_cla32_fa384_or0 b=s_wallace_cla32_and_17_14 cin=s_wallace_cla32_and_16_15 fa_xor1=s_wallace_cla32_fa385_xor1 fa_or0=s_wallace_cla32_fa385_or0
.subckt and_gate a=a[18] b=b[14] out=s_wallace_cla32_and_18_14
.subckt and_gate a=a[17] b=b[15] out=s_wallace_cla32_and_17_15
.subckt fa a=s_wallace_cla32_fa385_or0 b=s_wallace_cla32_and_18_14 cin=s_wallace_cla32_and_17_15 fa_xor1=s_wallace_cla32_fa386_xor1 fa_or0=s_wallace_cla32_fa386_or0
.subckt and_gate a=a[17] b=b[16] out=s_wallace_cla32_and_17_16
.subckt and_gate a=a[16] b=b[17] out=s_wallace_cla32_and_16_17
.subckt fa a=s_wallace_cla32_fa386_or0 b=s_wallace_cla32_and_17_16 cin=s_wallace_cla32_and_16_17 fa_xor1=s_wallace_cla32_fa387_xor1 fa_or0=s_wallace_cla32_fa387_or0
.subckt and_gate a=a[17] b=b[17] out=s_wallace_cla32_and_17_17
.subckt and_gate a=a[16] b=b[18] out=s_wallace_cla32_and_16_18
.subckt fa a=s_wallace_cla32_fa387_or0 b=s_wallace_cla32_and_17_17 cin=s_wallace_cla32_and_16_18 fa_xor1=s_wallace_cla32_fa388_xor1 fa_or0=s_wallace_cla32_fa388_or0
.subckt and_gate a=a[17] b=b[18] out=s_wallace_cla32_and_17_18
.subckt and_gate a=a[16] b=b[19] out=s_wallace_cla32_and_16_19
.subckt fa a=s_wallace_cla32_fa388_or0 b=s_wallace_cla32_and_17_18 cin=s_wallace_cla32_and_16_19 fa_xor1=s_wallace_cla32_fa389_xor1 fa_or0=s_wallace_cla32_fa389_or0
.subckt and_gate a=a[17] b=b[19] out=s_wallace_cla32_and_17_19
.subckt and_gate a=a[16] b=b[20] out=s_wallace_cla32_and_16_20
.subckt fa a=s_wallace_cla32_fa389_or0 b=s_wallace_cla32_and_17_19 cin=s_wallace_cla32_and_16_20 fa_xor1=s_wallace_cla32_fa390_xor1 fa_or0=s_wallace_cla32_fa390_or0
.subckt and_gate a=a[17] b=b[20] out=s_wallace_cla32_and_17_20
.subckt and_gate a=a[16] b=b[21] out=s_wallace_cla32_and_16_21
.subckt fa a=s_wallace_cla32_fa390_or0 b=s_wallace_cla32_and_17_20 cin=s_wallace_cla32_and_16_21 fa_xor1=s_wallace_cla32_fa391_xor1 fa_or0=s_wallace_cla32_fa391_or0
.subckt and_gate a=a[17] b=b[21] out=s_wallace_cla32_and_17_21
.subckt and_gate a=a[16] b=b[22] out=s_wallace_cla32_and_16_22
.subckt fa a=s_wallace_cla32_fa391_or0 b=s_wallace_cla32_and_17_21 cin=s_wallace_cla32_and_16_22 fa_xor1=s_wallace_cla32_fa392_xor1 fa_or0=s_wallace_cla32_fa392_or0
.subckt and_gate a=a[17] b=b[22] out=s_wallace_cla32_and_17_22
.subckt and_gate a=a[16] b=b[23] out=s_wallace_cla32_and_16_23
.subckt fa a=s_wallace_cla32_fa392_or0 b=s_wallace_cla32_and_17_22 cin=s_wallace_cla32_and_16_23 fa_xor1=s_wallace_cla32_fa393_xor1 fa_or0=s_wallace_cla32_fa393_or0
.subckt and_gate a=a[17] b=b[23] out=s_wallace_cla32_and_17_23
.subckt and_gate a=a[16] b=b[24] out=s_wallace_cla32_and_16_24
.subckt fa a=s_wallace_cla32_fa393_or0 b=s_wallace_cla32_and_17_23 cin=s_wallace_cla32_and_16_24 fa_xor1=s_wallace_cla32_fa394_xor1 fa_or0=s_wallace_cla32_fa394_or0
.subckt and_gate a=a[17] b=b[24] out=s_wallace_cla32_and_17_24
.subckt and_gate a=a[16] b=b[25] out=s_wallace_cla32_and_16_25
.subckt fa a=s_wallace_cla32_fa394_or0 b=s_wallace_cla32_and_17_24 cin=s_wallace_cla32_and_16_25 fa_xor1=s_wallace_cla32_fa395_xor1 fa_or0=s_wallace_cla32_fa395_or0
.subckt and_gate a=a[17] b=b[25] out=s_wallace_cla32_and_17_25
.subckt and_gate a=a[16] b=b[26] out=s_wallace_cla32_and_16_26
.subckt fa a=s_wallace_cla32_fa395_or0 b=s_wallace_cla32_and_17_25 cin=s_wallace_cla32_and_16_26 fa_xor1=s_wallace_cla32_fa396_xor1 fa_or0=s_wallace_cla32_fa396_or0
.subckt and_gate a=a[17] b=b[26] out=s_wallace_cla32_and_17_26
.subckt and_gate a=a[16] b=b[27] out=s_wallace_cla32_and_16_27
.subckt fa a=s_wallace_cla32_fa396_or0 b=s_wallace_cla32_and_17_26 cin=s_wallace_cla32_and_16_27 fa_xor1=s_wallace_cla32_fa397_xor1 fa_or0=s_wallace_cla32_fa397_or0
.subckt and_gate a=a[17] b=b[27] out=s_wallace_cla32_and_17_27
.subckt and_gate a=a[16] b=b[28] out=s_wallace_cla32_and_16_28
.subckt fa a=s_wallace_cla32_fa397_or0 b=s_wallace_cla32_and_17_27 cin=s_wallace_cla32_and_16_28 fa_xor1=s_wallace_cla32_fa398_xor1 fa_or0=s_wallace_cla32_fa398_or0
.subckt and_gate a=a[17] b=b[28] out=s_wallace_cla32_and_17_28
.subckt and_gate a=a[16] b=b[29] out=s_wallace_cla32_and_16_29
.subckt fa a=s_wallace_cla32_fa398_or0 b=s_wallace_cla32_and_17_28 cin=s_wallace_cla32_and_16_29 fa_xor1=s_wallace_cla32_fa399_xor1 fa_or0=s_wallace_cla32_fa399_or0
.subckt and_gate a=a[17] b=b[29] out=s_wallace_cla32_and_17_29
.subckt and_gate a=a[16] b=b[30] out=s_wallace_cla32_and_16_30
.subckt fa a=s_wallace_cla32_fa399_or0 b=s_wallace_cla32_and_17_29 cin=s_wallace_cla32_and_16_30 fa_xor1=s_wallace_cla32_fa400_xor1 fa_or0=s_wallace_cla32_fa400_or0
.subckt and_gate a=a[17] b=b[30] out=s_wallace_cla32_and_17_30
.subckt nand_gate a=a[16] b=b[31] out=s_wallace_cla32_nand_16_31
.subckt fa a=s_wallace_cla32_fa400_or0 b=s_wallace_cla32_and_17_30 cin=s_wallace_cla32_nand_16_31 fa_xor1=s_wallace_cla32_fa401_xor1 fa_or0=s_wallace_cla32_fa401_or0
.subckt nand_gate a=a[17] b=b[31] out=s_wallace_cla32_nand_17_31
.subckt fa a=s_wallace_cla32_fa401_or0 b=s_wallace_cla32_nand_17_31 cin=s_wallace_cla32_fa45_xor1 fa_xor1=s_wallace_cla32_fa402_xor1 fa_or0=s_wallace_cla32_fa402_or0
.subckt fa a=s_wallace_cla32_fa402_or0 b=s_wallace_cla32_fa46_xor1 cin=s_wallace_cla32_fa103_xor1 fa_xor1=s_wallace_cla32_fa403_xor1 fa_or0=s_wallace_cla32_fa403_or0
.subckt fa a=s_wallace_cla32_fa403_or0 b=s_wallace_cla32_fa104_xor1 cin=s_wallace_cla32_fa159_xor1 fa_xor1=s_wallace_cla32_fa404_xor1 fa_or0=s_wallace_cla32_fa404_or0
.subckt fa a=s_wallace_cla32_fa404_or0 b=s_wallace_cla32_fa160_xor1 cin=s_wallace_cla32_fa213_xor1 fa_xor1=s_wallace_cla32_fa405_xor1 fa_or0=s_wallace_cla32_fa405_or0
.subckt fa a=s_wallace_cla32_fa405_or0 b=s_wallace_cla32_fa214_xor1 cin=s_wallace_cla32_fa265_xor1 fa_xor1=s_wallace_cla32_fa406_xor1 fa_or0=s_wallace_cla32_fa406_or0
.subckt fa a=s_wallace_cla32_fa406_or0 b=s_wallace_cla32_fa266_xor1 cin=s_wallace_cla32_fa315_xor1 fa_xor1=s_wallace_cla32_fa407_xor1 fa_or0=s_wallace_cla32_fa407_or0
.subckt ha a=s_wallace_cla32_fa272_xor1 b=s_wallace_cla32_fa319_xor1 ha_xor0=s_wallace_cla32_ha8_xor0 ha_and0=s_wallace_cla32_ha8_and0
.subckt fa a=s_wallace_cla32_ha8_and0 b=s_wallace_cla32_fa224_xor1 cin=s_wallace_cla32_fa273_xor1 fa_xor1=s_wallace_cla32_fa408_xor1 fa_or0=s_wallace_cla32_fa408_or0
.subckt fa a=s_wallace_cla32_fa408_or0 b=s_wallace_cla32_fa174_xor1 cin=s_wallace_cla32_fa225_xor1 fa_xor1=s_wallace_cla32_fa409_xor1 fa_or0=s_wallace_cla32_fa409_or0
.subckt fa a=s_wallace_cla32_fa409_or0 b=s_wallace_cla32_fa122_xor1 cin=s_wallace_cla32_fa175_xor1 fa_xor1=s_wallace_cla32_fa410_xor1 fa_or0=s_wallace_cla32_fa410_or0
.subckt fa a=s_wallace_cla32_fa410_or0 b=s_wallace_cla32_fa68_xor1 cin=s_wallace_cla32_fa123_xor1 fa_xor1=s_wallace_cla32_fa411_xor1 fa_or0=s_wallace_cla32_fa411_or0
.subckt fa a=s_wallace_cla32_fa411_or0 b=s_wallace_cla32_fa12_xor1 cin=s_wallace_cla32_fa69_xor1 fa_xor1=s_wallace_cla32_fa412_xor1 fa_or0=s_wallace_cla32_fa412_or0
.subckt and_gate a=a[0] b=b[16] out=s_wallace_cla32_and_0_16
.subckt fa a=s_wallace_cla32_fa412_or0 b=s_wallace_cla32_and_0_16 cin=s_wallace_cla32_fa13_xor1 fa_xor1=s_wallace_cla32_fa413_xor1 fa_or0=s_wallace_cla32_fa413_or0
.subckt and_gate a=a[1] b=b[16] out=s_wallace_cla32_and_1_16
.subckt and_gate a=a[0] b=b[17] out=s_wallace_cla32_and_0_17
.subckt fa a=s_wallace_cla32_fa413_or0 b=s_wallace_cla32_and_1_16 cin=s_wallace_cla32_and_0_17 fa_xor1=s_wallace_cla32_fa414_xor1 fa_or0=s_wallace_cla32_fa414_or0
.subckt and_gate a=a[2] b=b[16] out=s_wallace_cla32_and_2_16
.subckt and_gate a=a[1] b=b[17] out=s_wallace_cla32_and_1_17
.subckt fa a=s_wallace_cla32_fa414_or0 b=s_wallace_cla32_and_2_16 cin=s_wallace_cla32_and_1_17 fa_xor1=s_wallace_cla32_fa415_xor1 fa_or0=s_wallace_cla32_fa415_or0
.subckt and_gate a=a[3] b=b[16] out=s_wallace_cla32_and_3_16
.subckt and_gate a=a[2] b=b[17] out=s_wallace_cla32_and_2_17
.subckt fa a=s_wallace_cla32_fa415_or0 b=s_wallace_cla32_and_3_16 cin=s_wallace_cla32_and_2_17 fa_xor1=s_wallace_cla32_fa416_xor1 fa_or0=s_wallace_cla32_fa416_or0
.subckt and_gate a=a[4] b=b[16] out=s_wallace_cla32_and_4_16
.subckt and_gate a=a[3] b=b[17] out=s_wallace_cla32_and_3_17
.subckt fa a=s_wallace_cla32_fa416_or0 b=s_wallace_cla32_and_4_16 cin=s_wallace_cla32_and_3_17 fa_xor1=s_wallace_cla32_fa417_xor1 fa_or0=s_wallace_cla32_fa417_or0
.subckt and_gate a=a[5] b=b[16] out=s_wallace_cla32_and_5_16
.subckt and_gate a=a[4] b=b[17] out=s_wallace_cla32_and_4_17
.subckt fa a=s_wallace_cla32_fa417_or0 b=s_wallace_cla32_and_5_16 cin=s_wallace_cla32_and_4_17 fa_xor1=s_wallace_cla32_fa418_xor1 fa_or0=s_wallace_cla32_fa418_or0
.subckt and_gate a=a[6] b=b[16] out=s_wallace_cla32_and_6_16
.subckt and_gate a=a[5] b=b[17] out=s_wallace_cla32_and_5_17
.subckt fa a=s_wallace_cla32_fa418_or0 b=s_wallace_cla32_and_6_16 cin=s_wallace_cla32_and_5_17 fa_xor1=s_wallace_cla32_fa419_xor1 fa_or0=s_wallace_cla32_fa419_or0
.subckt and_gate a=a[7] b=b[16] out=s_wallace_cla32_and_7_16
.subckt and_gate a=a[6] b=b[17] out=s_wallace_cla32_and_6_17
.subckt fa a=s_wallace_cla32_fa419_or0 b=s_wallace_cla32_and_7_16 cin=s_wallace_cla32_and_6_17 fa_xor1=s_wallace_cla32_fa420_xor1 fa_or0=s_wallace_cla32_fa420_or0
.subckt and_gate a=a[8] b=b[16] out=s_wallace_cla32_and_8_16
.subckt and_gate a=a[7] b=b[17] out=s_wallace_cla32_and_7_17
.subckt fa a=s_wallace_cla32_fa420_or0 b=s_wallace_cla32_and_8_16 cin=s_wallace_cla32_and_7_17 fa_xor1=s_wallace_cla32_fa421_xor1 fa_or0=s_wallace_cla32_fa421_or0
.subckt and_gate a=a[9] b=b[16] out=s_wallace_cla32_and_9_16
.subckt and_gate a=a[8] b=b[17] out=s_wallace_cla32_and_8_17
.subckt fa a=s_wallace_cla32_fa421_or0 b=s_wallace_cla32_and_9_16 cin=s_wallace_cla32_and_8_17 fa_xor1=s_wallace_cla32_fa422_xor1 fa_or0=s_wallace_cla32_fa422_or0
.subckt and_gate a=a[10] b=b[16] out=s_wallace_cla32_and_10_16
.subckt and_gate a=a[9] b=b[17] out=s_wallace_cla32_and_9_17
.subckt fa a=s_wallace_cla32_fa422_or0 b=s_wallace_cla32_and_10_16 cin=s_wallace_cla32_and_9_17 fa_xor1=s_wallace_cla32_fa423_xor1 fa_or0=s_wallace_cla32_fa423_or0
.subckt and_gate a=a[11] b=b[16] out=s_wallace_cla32_and_11_16
.subckt and_gate a=a[10] b=b[17] out=s_wallace_cla32_and_10_17
.subckt fa a=s_wallace_cla32_fa423_or0 b=s_wallace_cla32_and_11_16 cin=s_wallace_cla32_and_10_17 fa_xor1=s_wallace_cla32_fa424_xor1 fa_or0=s_wallace_cla32_fa424_or0
.subckt and_gate a=a[12] b=b[16] out=s_wallace_cla32_and_12_16
.subckt and_gate a=a[11] b=b[17] out=s_wallace_cla32_and_11_17
.subckt fa a=s_wallace_cla32_fa424_or0 b=s_wallace_cla32_and_12_16 cin=s_wallace_cla32_and_11_17 fa_xor1=s_wallace_cla32_fa425_xor1 fa_or0=s_wallace_cla32_fa425_or0
.subckt and_gate a=a[13] b=b[16] out=s_wallace_cla32_and_13_16
.subckt and_gate a=a[12] b=b[17] out=s_wallace_cla32_and_12_17
.subckt fa a=s_wallace_cla32_fa425_or0 b=s_wallace_cla32_and_13_16 cin=s_wallace_cla32_and_12_17 fa_xor1=s_wallace_cla32_fa426_xor1 fa_or0=s_wallace_cla32_fa426_or0
.subckt and_gate a=a[14] b=b[16] out=s_wallace_cla32_and_14_16
.subckt and_gate a=a[13] b=b[17] out=s_wallace_cla32_and_13_17
.subckt fa a=s_wallace_cla32_fa426_or0 b=s_wallace_cla32_and_14_16 cin=s_wallace_cla32_and_13_17 fa_xor1=s_wallace_cla32_fa427_xor1 fa_or0=s_wallace_cla32_fa427_or0
.subckt and_gate a=a[15] b=b[16] out=s_wallace_cla32_and_15_16
.subckt and_gate a=a[14] b=b[17] out=s_wallace_cla32_and_14_17
.subckt fa a=s_wallace_cla32_fa427_or0 b=s_wallace_cla32_and_15_16 cin=s_wallace_cla32_and_14_17 fa_xor1=s_wallace_cla32_fa428_xor1 fa_or0=s_wallace_cla32_fa428_or0
.subckt and_gate a=a[16] b=b[16] out=s_wallace_cla32_and_16_16
.subckt and_gate a=a[15] b=b[17] out=s_wallace_cla32_and_15_17
.subckt fa a=s_wallace_cla32_fa428_or0 b=s_wallace_cla32_and_16_16 cin=s_wallace_cla32_and_15_17 fa_xor1=s_wallace_cla32_fa429_xor1 fa_or0=s_wallace_cla32_fa429_or0
.subckt and_gate a=a[15] b=b[18] out=s_wallace_cla32_and_15_18
.subckt and_gate a=a[14] b=b[19] out=s_wallace_cla32_and_14_19
.subckt fa a=s_wallace_cla32_fa429_or0 b=s_wallace_cla32_and_15_18 cin=s_wallace_cla32_and_14_19 fa_xor1=s_wallace_cla32_fa430_xor1 fa_or0=s_wallace_cla32_fa430_or0
.subckt and_gate a=a[15] b=b[19] out=s_wallace_cla32_and_15_19
.subckt and_gate a=a[14] b=b[20] out=s_wallace_cla32_and_14_20
.subckt fa a=s_wallace_cla32_fa430_or0 b=s_wallace_cla32_and_15_19 cin=s_wallace_cla32_and_14_20 fa_xor1=s_wallace_cla32_fa431_xor1 fa_or0=s_wallace_cla32_fa431_or0
.subckt and_gate a=a[15] b=b[20] out=s_wallace_cla32_and_15_20
.subckt and_gate a=a[14] b=b[21] out=s_wallace_cla32_and_14_21
.subckt fa a=s_wallace_cla32_fa431_or0 b=s_wallace_cla32_and_15_20 cin=s_wallace_cla32_and_14_21 fa_xor1=s_wallace_cla32_fa432_xor1 fa_or0=s_wallace_cla32_fa432_or0
.subckt and_gate a=a[15] b=b[21] out=s_wallace_cla32_and_15_21
.subckt and_gate a=a[14] b=b[22] out=s_wallace_cla32_and_14_22
.subckt fa a=s_wallace_cla32_fa432_or0 b=s_wallace_cla32_and_15_21 cin=s_wallace_cla32_and_14_22 fa_xor1=s_wallace_cla32_fa433_xor1 fa_or0=s_wallace_cla32_fa433_or0
.subckt and_gate a=a[15] b=b[22] out=s_wallace_cla32_and_15_22
.subckt and_gate a=a[14] b=b[23] out=s_wallace_cla32_and_14_23
.subckt fa a=s_wallace_cla32_fa433_or0 b=s_wallace_cla32_and_15_22 cin=s_wallace_cla32_and_14_23 fa_xor1=s_wallace_cla32_fa434_xor1 fa_or0=s_wallace_cla32_fa434_or0
.subckt and_gate a=a[15] b=b[23] out=s_wallace_cla32_and_15_23
.subckt and_gate a=a[14] b=b[24] out=s_wallace_cla32_and_14_24
.subckt fa a=s_wallace_cla32_fa434_or0 b=s_wallace_cla32_and_15_23 cin=s_wallace_cla32_and_14_24 fa_xor1=s_wallace_cla32_fa435_xor1 fa_or0=s_wallace_cla32_fa435_or0
.subckt and_gate a=a[15] b=b[24] out=s_wallace_cla32_and_15_24
.subckt and_gate a=a[14] b=b[25] out=s_wallace_cla32_and_14_25
.subckt fa a=s_wallace_cla32_fa435_or0 b=s_wallace_cla32_and_15_24 cin=s_wallace_cla32_and_14_25 fa_xor1=s_wallace_cla32_fa436_xor1 fa_or0=s_wallace_cla32_fa436_or0
.subckt and_gate a=a[15] b=b[25] out=s_wallace_cla32_and_15_25
.subckt and_gate a=a[14] b=b[26] out=s_wallace_cla32_and_14_26
.subckt fa a=s_wallace_cla32_fa436_or0 b=s_wallace_cla32_and_15_25 cin=s_wallace_cla32_and_14_26 fa_xor1=s_wallace_cla32_fa437_xor1 fa_or0=s_wallace_cla32_fa437_or0
.subckt and_gate a=a[15] b=b[26] out=s_wallace_cla32_and_15_26
.subckt and_gate a=a[14] b=b[27] out=s_wallace_cla32_and_14_27
.subckt fa a=s_wallace_cla32_fa437_or0 b=s_wallace_cla32_and_15_26 cin=s_wallace_cla32_and_14_27 fa_xor1=s_wallace_cla32_fa438_xor1 fa_or0=s_wallace_cla32_fa438_or0
.subckt and_gate a=a[15] b=b[27] out=s_wallace_cla32_and_15_27
.subckt and_gate a=a[14] b=b[28] out=s_wallace_cla32_and_14_28
.subckt fa a=s_wallace_cla32_fa438_or0 b=s_wallace_cla32_and_15_27 cin=s_wallace_cla32_and_14_28 fa_xor1=s_wallace_cla32_fa439_xor1 fa_or0=s_wallace_cla32_fa439_or0
.subckt and_gate a=a[15] b=b[28] out=s_wallace_cla32_and_15_28
.subckt and_gate a=a[14] b=b[29] out=s_wallace_cla32_and_14_29
.subckt fa a=s_wallace_cla32_fa439_or0 b=s_wallace_cla32_and_15_28 cin=s_wallace_cla32_and_14_29 fa_xor1=s_wallace_cla32_fa440_xor1 fa_or0=s_wallace_cla32_fa440_or0
.subckt and_gate a=a[15] b=b[29] out=s_wallace_cla32_and_15_29
.subckt and_gate a=a[14] b=b[30] out=s_wallace_cla32_and_14_30
.subckt fa a=s_wallace_cla32_fa440_or0 b=s_wallace_cla32_and_15_29 cin=s_wallace_cla32_and_14_30 fa_xor1=s_wallace_cla32_fa441_xor1 fa_or0=s_wallace_cla32_fa441_or0
.subckt and_gate a=a[15] b=b[30] out=s_wallace_cla32_and_15_30
.subckt nand_gate a=a[14] b=b[31] out=s_wallace_cla32_nand_14_31
.subckt fa a=s_wallace_cla32_fa441_or0 b=s_wallace_cla32_and_15_30 cin=s_wallace_cla32_nand_14_31 fa_xor1=s_wallace_cla32_fa442_xor1 fa_or0=s_wallace_cla32_fa442_or0
.subckt nand_gate a=a[15] b=b[31] out=s_wallace_cla32_nand_15_31
.subckt fa a=s_wallace_cla32_fa442_or0 b=s_wallace_cla32_nand_15_31 cin=s_wallace_cla32_fa43_xor1 fa_xor1=s_wallace_cla32_fa443_xor1 fa_or0=s_wallace_cla32_fa443_or0
.subckt fa a=s_wallace_cla32_fa443_or0 b=s_wallace_cla32_fa44_xor1 cin=s_wallace_cla32_fa101_xor1 fa_xor1=s_wallace_cla32_fa444_xor1 fa_or0=s_wallace_cla32_fa444_or0
.subckt fa a=s_wallace_cla32_fa444_or0 b=s_wallace_cla32_fa102_xor1 cin=s_wallace_cla32_fa157_xor1 fa_xor1=s_wallace_cla32_fa445_xor1 fa_or0=s_wallace_cla32_fa445_or0
.subckt fa a=s_wallace_cla32_fa445_or0 b=s_wallace_cla32_fa158_xor1 cin=s_wallace_cla32_fa211_xor1 fa_xor1=s_wallace_cla32_fa446_xor1 fa_or0=s_wallace_cla32_fa446_or0
.subckt fa a=s_wallace_cla32_fa446_or0 b=s_wallace_cla32_fa212_xor1 cin=s_wallace_cla32_fa263_xor1 fa_xor1=s_wallace_cla32_fa447_xor1 fa_or0=s_wallace_cla32_fa447_or0
.subckt fa a=s_wallace_cla32_fa447_or0 b=s_wallace_cla32_fa264_xor1 cin=s_wallace_cla32_fa313_xor1 fa_xor1=s_wallace_cla32_fa448_xor1 fa_or0=s_wallace_cla32_fa448_or0
.subckt fa a=s_wallace_cla32_fa448_or0 b=s_wallace_cla32_fa314_xor1 cin=s_wallace_cla32_fa361_xor1 fa_xor1=s_wallace_cla32_fa449_xor1 fa_or0=s_wallace_cla32_fa449_or0
.subckt ha a=s_wallace_cla32_fa320_xor1 b=s_wallace_cla32_fa365_xor1 ha_xor0=s_wallace_cla32_ha9_xor0 ha_and0=s_wallace_cla32_ha9_and0
.subckt fa a=s_wallace_cla32_ha9_and0 b=s_wallace_cla32_fa274_xor1 cin=s_wallace_cla32_fa321_xor1 fa_xor1=s_wallace_cla32_fa450_xor1 fa_or0=s_wallace_cla32_fa450_or0
.subckt fa a=s_wallace_cla32_fa450_or0 b=s_wallace_cla32_fa226_xor1 cin=s_wallace_cla32_fa275_xor1 fa_xor1=s_wallace_cla32_fa451_xor1 fa_or0=s_wallace_cla32_fa451_or0
.subckt fa a=s_wallace_cla32_fa451_or0 b=s_wallace_cla32_fa176_xor1 cin=s_wallace_cla32_fa227_xor1 fa_xor1=s_wallace_cla32_fa452_xor1 fa_or0=s_wallace_cla32_fa452_or0
.subckt fa a=s_wallace_cla32_fa452_or0 b=s_wallace_cla32_fa124_xor1 cin=s_wallace_cla32_fa177_xor1 fa_xor1=s_wallace_cla32_fa453_xor1 fa_or0=s_wallace_cla32_fa453_or0
.subckt fa a=s_wallace_cla32_fa453_or0 b=s_wallace_cla32_fa70_xor1 cin=s_wallace_cla32_fa125_xor1 fa_xor1=s_wallace_cla32_fa454_xor1 fa_or0=s_wallace_cla32_fa454_or0
.subckt fa a=s_wallace_cla32_fa454_or0 b=s_wallace_cla32_fa14_xor1 cin=s_wallace_cla32_fa71_xor1 fa_xor1=s_wallace_cla32_fa455_xor1 fa_or0=s_wallace_cla32_fa455_or0
.subckt and_gate a=a[0] b=b[18] out=s_wallace_cla32_and_0_18
.subckt fa a=s_wallace_cla32_fa455_or0 b=s_wallace_cla32_and_0_18 cin=s_wallace_cla32_fa15_xor1 fa_xor1=s_wallace_cla32_fa456_xor1 fa_or0=s_wallace_cla32_fa456_or0
.subckt and_gate a=a[1] b=b[18] out=s_wallace_cla32_and_1_18
.subckt and_gate a=a[0] b=b[19] out=s_wallace_cla32_and_0_19
.subckt fa a=s_wallace_cla32_fa456_or0 b=s_wallace_cla32_and_1_18 cin=s_wallace_cla32_and_0_19 fa_xor1=s_wallace_cla32_fa457_xor1 fa_or0=s_wallace_cla32_fa457_or0
.subckt and_gate a=a[2] b=b[18] out=s_wallace_cla32_and_2_18
.subckt and_gate a=a[1] b=b[19] out=s_wallace_cla32_and_1_19
.subckt fa a=s_wallace_cla32_fa457_or0 b=s_wallace_cla32_and_2_18 cin=s_wallace_cla32_and_1_19 fa_xor1=s_wallace_cla32_fa458_xor1 fa_or0=s_wallace_cla32_fa458_or0
.subckt and_gate a=a[3] b=b[18] out=s_wallace_cla32_and_3_18
.subckt and_gate a=a[2] b=b[19] out=s_wallace_cla32_and_2_19
.subckt fa a=s_wallace_cla32_fa458_or0 b=s_wallace_cla32_and_3_18 cin=s_wallace_cla32_and_2_19 fa_xor1=s_wallace_cla32_fa459_xor1 fa_or0=s_wallace_cla32_fa459_or0
.subckt and_gate a=a[4] b=b[18] out=s_wallace_cla32_and_4_18
.subckt and_gate a=a[3] b=b[19] out=s_wallace_cla32_and_3_19
.subckt fa a=s_wallace_cla32_fa459_or0 b=s_wallace_cla32_and_4_18 cin=s_wallace_cla32_and_3_19 fa_xor1=s_wallace_cla32_fa460_xor1 fa_or0=s_wallace_cla32_fa460_or0
.subckt and_gate a=a[5] b=b[18] out=s_wallace_cla32_and_5_18
.subckt and_gate a=a[4] b=b[19] out=s_wallace_cla32_and_4_19
.subckt fa a=s_wallace_cla32_fa460_or0 b=s_wallace_cla32_and_5_18 cin=s_wallace_cla32_and_4_19 fa_xor1=s_wallace_cla32_fa461_xor1 fa_or0=s_wallace_cla32_fa461_or0
.subckt and_gate a=a[6] b=b[18] out=s_wallace_cla32_and_6_18
.subckt and_gate a=a[5] b=b[19] out=s_wallace_cla32_and_5_19
.subckt fa a=s_wallace_cla32_fa461_or0 b=s_wallace_cla32_and_6_18 cin=s_wallace_cla32_and_5_19 fa_xor1=s_wallace_cla32_fa462_xor1 fa_or0=s_wallace_cla32_fa462_or0
.subckt and_gate a=a[7] b=b[18] out=s_wallace_cla32_and_7_18
.subckt and_gate a=a[6] b=b[19] out=s_wallace_cla32_and_6_19
.subckt fa a=s_wallace_cla32_fa462_or0 b=s_wallace_cla32_and_7_18 cin=s_wallace_cla32_and_6_19 fa_xor1=s_wallace_cla32_fa463_xor1 fa_or0=s_wallace_cla32_fa463_or0
.subckt and_gate a=a[8] b=b[18] out=s_wallace_cla32_and_8_18
.subckt and_gate a=a[7] b=b[19] out=s_wallace_cla32_and_7_19
.subckt fa a=s_wallace_cla32_fa463_or0 b=s_wallace_cla32_and_8_18 cin=s_wallace_cla32_and_7_19 fa_xor1=s_wallace_cla32_fa464_xor1 fa_or0=s_wallace_cla32_fa464_or0
.subckt and_gate a=a[9] b=b[18] out=s_wallace_cla32_and_9_18
.subckt and_gate a=a[8] b=b[19] out=s_wallace_cla32_and_8_19
.subckt fa a=s_wallace_cla32_fa464_or0 b=s_wallace_cla32_and_9_18 cin=s_wallace_cla32_and_8_19 fa_xor1=s_wallace_cla32_fa465_xor1 fa_or0=s_wallace_cla32_fa465_or0
.subckt and_gate a=a[10] b=b[18] out=s_wallace_cla32_and_10_18
.subckt and_gate a=a[9] b=b[19] out=s_wallace_cla32_and_9_19
.subckt fa a=s_wallace_cla32_fa465_or0 b=s_wallace_cla32_and_10_18 cin=s_wallace_cla32_and_9_19 fa_xor1=s_wallace_cla32_fa466_xor1 fa_or0=s_wallace_cla32_fa466_or0
.subckt and_gate a=a[11] b=b[18] out=s_wallace_cla32_and_11_18
.subckt and_gate a=a[10] b=b[19] out=s_wallace_cla32_and_10_19
.subckt fa a=s_wallace_cla32_fa466_or0 b=s_wallace_cla32_and_11_18 cin=s_wallace_cla32_and_10_19 fa_xor1=s_wallace_cla32_fa467_xor1 fa_or0=s_wallace_cla32_fa467_or0
.subckt and_gate a=a[12] b=b[18] out=s_wallace_cla32_and_12_18
.subckt and_gate a=a[11] b=b[19] out=s_wallace_cla32_and_11_19
.subckt fa a=s_wallace_cla32_fa467_or0 b=s_wallace_cla32_and_12_18 cin=s_wallace_cla32_and_11_19 fa_xor1=s_wallace_cla32_fa468_xor1 fa_or0=s_wallace_cla32_fa468_or0
.subckt and_gate a=a[13] b=b[18] out=s_wallace_cla32_and_13_18
.subckt and_gate a=a[12] b=b[19] out=s_wallace_cla32_and_12_19
.subckt fa a=s_wallace_cla32_fa468_or0 b=s_wallace_cla32_and_13_18 cin=s_wallace_cla32_and_12_19 fa_xor1=s_wallace_cla32_fa469_xor1 fa_or0=s_wallace_cla32_fa469_or0
.subckt and_gate a=a[14] b=b[18] out=s_wallace_cla32_and_14_18
.subckt and_gate a=a[13] b=b[19] out=s_wallace_cla32_and_13_19
.subckt fa a=s_wallace_cla32_fa469_or0 b=s_wallace_cla32_and_14_18 cin=s_wallace_cla32_and_13_19 fa_xor1=s_wallace_cla32_fa470_xor1 fa_or0=s_wallace_cla32_fa470_or0
.subckt and_gate a=a[13] b=b[20] out=s_wallace_cla32_and_13_20
.subckt and_gate a=a[12] b=b[21] out=s_wallace_cla32_and_12_21
.subckt fa a=s_wallace_cla32_fa470_or0 b=s_wallace_cla32_and_13_20 cin=s_wallace_cla32_and_12_21 fa_xor1=s_wallace_cla32_fa471_xor1 fa_or0=s_wallace_cla32_fa471_or0
.subckt and_gate a=a[13] b=b[21] out=s_wallace_cla32_and_13_21
.subckt and_gate a=a[12] b=b[22] out=s_wallace_cla32_and_12_22
.subckt fa a=s_wallace_cla32_fa471_or0 b=s_wallace_cla32_and_13_21 cin=s_wallace_cla32_and_12_22 fa_xor1=s_wallace_cla32_fa472_xor1 fa_or0=s_wallace_cla32_fa472_or0
.subckt and_gate a=a[13] b=b[22] out=s_wallace_cla32_and_13_22
.subckt and_gate a=a[12] b=b[23] out=s_wallace_cla32_and_12_23
.subckt fa a=s_wallace_cla32_fa472_or0 b=s_wallace_cla32_and_13_22 cin=s_wallace_cla32_and_12_23 fa_xor1=s_wallace_cla32_fa473_xor1 fa_or0=s_wallace_cla32_fa473_or0
.subckt and_gate a=a[13] b=b[23] out=s_wallace_cla32_and_13_23
.subckt and_gate a=a[12] b=b[24] out=s_wallace_cla32_and_12_24
.subckt fa a=s_wallace_cla32_fa473_or0 b=s_wallace_cla32_and_13_23 cin=s_wallace_cla32_and_12_24 fa_xor1=s_wallace_cla32_fa474_xor1 fa_or0=s_wallace_cla32_fa474_or0
.subckt and_gate a=a[13] b=b[24] out=s_wallace_cla32_and_13_24
.subckt and_gate a=a[12] b=b[25] out=s_wallace_cla32_and_12_25
.subckt fa a=s_wallace_cla32_fa474_or0 b=s_wallace_cla32_and_13_24 cin=s_wallace_cla32_and_12_25 fa_xor1=s_wallace_cla32_fa475_xor1 fa_or0=s_wallace_cla32_fa475_or0
.subckt and_gate a=a[13] b=b[25] out=s_wallace_cla32_and_13_25
.subckt and_gate a=a[12] b=b[26] out=s_wallace_cla32_and_12_26
.subckt fa a=s_wallace_cla32_fa475_or0 b=s_wallace_cla32_and_13_25 cin=s_wallace_cla32_and_12_26 fa_xor1=s_wallace_cla32_fa476_xor1 fa_or0=s_wallace_cla32_fa476_or0
.subckt and_gate a=a[13] b=b[26] out=s_wallace_cla32_and_13_26
.subckt and_gate a=a[12] b=b[27] out=s_wallace_cla32_and_12_27
.subckt fa a=s_wallace_cla32_fa476_or0 b=s_wallace_cla32_and_13_26 cin=s_wallace_cla32_and_12_27 fa_xor1=s_wallace_cla32_fa477_xor1 fa_or0=s_wallace_cla32_fa477_or0
.subckt and_gate a=a[13] b=b[27] out=s_wallace_cla32_and_13_27
.subckt and_gate a=a[12] b=b[28] out=s_wallace_cla32_and_12_28
.subckt fa a=s_wallace_cla32_fa477_or0 b=s_wallace_cla32_and_13_27 cin=s_wallace_cla32_and_12_28 fa_xor1=s_wallace_cla32_fa478_xor1 fa_or0=s_wallace_cla32_fa478_or0
.subckt and_gate a=a[13] b=b[28] out=s_wallace_cla32_and_13_28
.subckt and_gate a=a[12] b=b[29] out=s_wallace_cla32_and_12_29
.subckt fa a=s_wallace_cla32_fa478_or0 b=s_wallace_cla32_and_13_28 cin=s_wallace_cla32_and_12_29 fa_xor1=s_wallace_cla32_fa479_xor1 fa_or0=s_wallace_cla32_fa479_or0
.subckt and_gate a=a[13] b=b[29] out=s_wallace_cla32_and_13_29
.subckt and_gate a=a[12] b=b[30] out=s_wallace_cla32_and_12_30
.subckt fa a=s_wallace_cla32_fa479_or0 b=s_wallace_cla32_and_13_29 cin=s_wallace_cla32_and_12_30 fa_xor1=s_wallace_cla32_fa480_xor1 fa_or0=s_wallace_cla32_fa480_or0
.subckt and_gate a=a[13] b=b[30] out=s_wallace_cla32_and_13_30
.subckt nand_gate a=a[12] b=b[31] out=s_wallace_cla32_nand_12_31
.subckt fa a=s_wallace_cla32_fa480_or0 b=s_wallace_cla32_and_13_30 cin=s_wallace_cla32_nand_12_31 fa_xor1=s_wallace_cla32_fa481_xor1 fa_or0=s_wallace_cla32_fa481_or0
.subckt nand_gate a=a[13] b=b[31] out=s_wallace_cla32_nand_13_31
.subckt fa a=s_wallace_cla32_fa481_or0 b=s_wallace_cla32_nand_13_31 cin=s_wallace_cla32_fa41_xor1 fa_xor1=s_wallace_cla32_fa482_xor1 fa_or0=s_wallace_cla32_fa482_or0
.subckt fa a=s_wallace_cla32_fa482_or0 b=s_wallace_cla32_fa42_xor1 cin=s_wallace_cla32_fa99_xor1 fa_xor1=s_wallace_cla32_fa483_xor1 fa_or0=s_wallace_cla32_fa483_or0
.subckt fa a=s_wallace_cla32_fa483_or0 b=s_wallace_cla32_fa100_xor1 cin=s_wallace_cla32_fa155_xor1 fa_xor1=s_wallace_cla32_fa484_xor1 fa_or0=s_wallace_cla32_fa484_or0
.subckt fa a=s_wallace_cla32_fa484_or0 b=s_wallace_cla32_fa156_xor1 cin=s_wallace_cla32_fa209_xor1 fa_xor1=s_wallace_cla32_fa485_xor1 fa_or0=s_wallace_cla32_fa485_or0
.subckt fa a=s_wallace_cla32_fa485_or0 b=s_wallace_cla32_fa210_xor1 cin=s_wallace_cla32_fa261_xor1 fa_xor1=s_wallace_cla32_fa486_xor1 fa_or0=s_wallace_cla32_fa486_or0
.subckt fa a=s_wallace_cla32_fa486_or0 b=s_wallace_cla32_fa262_xor1 cin=s_wallace_cla32_fa311_xor1 fa_xor1=s_wallace_cla32_fa487_xor1 fa_or0=s_wallace_cla32_fa487_or0
.subckt fa a=s_wallace_cla32_fa487_or0 b=s_wallace_cla32_fa312_xor1 cin=s_wallace_cla32_fa359_xor1 fa_xor1=s_wallace_cla32_fa488_xor1 fa_or0=s_wallace_cla32_fa488_or0
.subckt fa a=s_wallace_cla32_fa488_or0 b=s_wallace_cla32_fa360_xor1 cin=s_wallace_cla32_fa405_xor1 fa_xor1=s_wallace_cla32_fa489_xor1 fa_or0=s_wallace_cla32_fa489_or0
.subckt ha a=s_wallace_cla32_fa366_xor1 b=s_wallace_cla32_fa409_xor1 ha_xor0=s_wallace_cla32_ha10_xor0 ha_and0=s_wallace_cla32_ha10_and0
.subckt fa a=s_wallace_cla32_ha10_and0 b=s_wallace_cla32_fa322_xor1 cin=s_wallace_cla32_fa367_xor1 fa_xor1=s_wallace_cla32_fa490_xor1 fa_or0=s_wallace_cla32_fa490_or0
.subckt fa a=s_wallace_cla32_fa490_or0 b=s_wallace_cla32_fa276_xor1 cin=s_wallace_cla32_fa323_xor1 fa_xor1=s_wallace_cla32_fa491_xor1 fa_or0=s_wallace_cla32_fa491_or0
.subckt fa a=s_wallace_cla32_fa491_or0 b=s_wallace_cla32_fa228_xor1 cin=s_wallace_cla32_fa277_xor1 fa_xor1=s_wallace_cla32_fa492_xor1 fa_or0=s_wallace_cla32_fa492_or0
.subckt fa a=s_wallace_cla32_fa492_or0 b=s_wallace_cla32_fa178_xor1 cin=s_wallace_cla32_fa229_xor1 fa_xor1=s_wallace_cla32_fa493_xor1 fa_or0=s_wallace_cla32_fa493_or0
.subckt fa a=s_wallace_cla32_fa493_or0 b=s_wallace_cla32_fa126_xor1 cin=s_wallace_cla32_fa179_xor1 fa_xor1=s_wallace_cla32_fa494_xor1 fa_or0=s_wallace_cla32_fa494_or0
.subckt fa a=s_wallace_cla32_fa494_or0 b=s_wallace_cla32_fa72_xor1 cin=s_wallace_cla32_fa127_xor1 fa_xor1=s_wallace_cla32_fa495_xor1 fa_or0=s_wallace_cla32_fa495_or0
.subckt fa a=s_wallace_cla32_fa495_or0 b=s_wallace_cla32_fa16_xor1 cin=s_wallace_cla32_fa73_xor1 fa_xor1=s_wallace_cla32_fa496_xor1 fa_or0=s_wallace_cla32_fa496_or0
.subckt and_gate a=a[0] b=b[20] out=s_wallace_cla32_and_0_20
.subckt fa a=s_wallace_cla32_fa496_or0 b=s_wallace_cla32_and_0_20 cin=s_wallace_cla32_fa17_xor1 fa_xor1=s_wallace_cla32_fa497_xor1 fa_or0=s_wallace_cla32_fa497_or0
.subckt and_gate a=a[1] b=b[20] out=s_wallace_cla32_and_1_20
.subckt and_gate a=a[0] b=b[21] out=s_wallace_cla32_and_0_21
.subckt fa a=s_wallace_cla32_fa497_or0 b=s_wallace_cla32_and_1_20 cin=s_wallace_cla32_and_0_21 fa_xor1=s_wallace_cla32_fa498_xor1 fa_or0=s_wallace_cla32_fa498_or0
.subckt and_gate a=a[2] b=b[20] out=s_wallace_cla32_and_2_20
.subckt and_gate a=a[1] b=b[21] out=s_wallace_cla32_and_1_21
.subckt fa a=s_wallace_cla32_fa498_or0 b=s_wallace_cla32_and_2_20 cin=s_wallace_cla32_and_1_21 fa_xor1=s_wallace_cla32_fa499_xor1 fa_or0=s_wallace_cla32_fa499_or0
.subckt and_gate a=a[3] b=b[20] out=s_wallace_cla32_and_3_20
.subckt and_gate a=a[2] b=b[21] out=s_wallace_cla32_and_2_21
.subckt fa a=s_wallace_cla32_fa499_or0 b=s_wallace_cla32_and_3_20 cin=s_wallace_cla32_and_2_21 fa_xor1=s_wallace_cla32_fa500_xor1 fa_or0=s_wallace_cla32_fa500_or0
.subckt and_gate a=a[4] b=b[20] out=s_wallace_cla32_and_4_20
.subckt and_gate a=a[3] b=b[21] out=s_wallace_cla32_and_3_21
.subckt fa a=s_wallace_cla32_fa500_or0 b=s_wallace_cla32_and_4_20 cin=s_wallace_cla32_and_3_21 fa_xor1=s_wallace_cla32_fa501_xor1 fa_or0=s_wallace_cla32_fa501_or0
.subckt and_gate a=a[5] b=b[20] out=s_wallace_cla32_and_5_20
.subckt and_gate a=a[4] b=b[21] out=s_wallace_cla32_and_4_21
.subckt fa a=s_wallace_cla32_fa501_or0 b=s_wallace_cla32_and_5_20 cin=s_wallace_cla32_and_4_21 fa_xor1=s_wallace_cla32_fa502_xor1 fa_or0=s_wallace_cla32_fa502_or0
.subckt and_gate a=a[6] b=b[20] out=s_wallace_cla32_and_6_20
.subckt and_gate a=a[5] b=b[21] out=s_wallace_cla32_and_5_21
.subckt fa a=s_wallace_cla32_fa502_or0 b=s_wallace_cla32_and_6_20 cin=s_wallace_cla32_and_5_21 fa_xor1=s_wallace_cla32_fa503_xor1 fa_or0=s_wallace_cla32_fa503_or0
.subckt and_gate a=a[7] b=b[20] out=s_wallace_cla32_and_7_20
.subckt and_gate a=a[6] b=b[21] out=s_wallace_cla32_and_6_21
.subckt fa a=s_wallace_cla32_fa503_or0 b=s_wallace_cla32_and_7_20 cin=s_wallace_cla32_and_6_21 fa_xor1=s_wallace_cla32_fa504_xor1 fa_or0=s_wallace_cla32_fa504_or0
.subckt and_gate a=a[8] b=b[20] out=s_wallace_cla32_and_8_20
.subckt and_gate a=a[7] b=b[21] out=s_wallace_cla32_and_7_21
.subckt fa a=s_wallace_cla32_fa504_or0 b=s_wallace_cla32_and_8_20 cin=s_wallace_cla32_and_7_21 fa_xor1=s_wallace_cla32_fa505_xor1 fa_or0=s_wallace_cla32_fa505_or0
.subckt and_gate a=a[9] b=b[20] out=s_wallace_cla32_and_9_20
.subckt and_gate a=a[8] b=b[21] out=s_wallace_cla32_and_8_21
.subckt fa a=s_wallace_cla32_fa505_or0 b=s_wallace_cla32_and_9_20 cin=s_wallace_cla32_and_8_21 fa_xor1=s_wallace_cla32_fa506_xor1 fa_or0=s_wallace_cla32_fa506_or0
.subckt and_gate a=a[10] b=b[20] out=s_wallace_cla32_and_10_20
.subckt and_gate a=a[9] b=b[21] out=s_wallace_cla32_and_9_21
.subckt fa a=s_wallace_cla32_fa506_or0 b=s_wallace_cla32_and_10_20 cin=s_wallace_cla32_and_9_21 fa_xor1=s_wallace_cla32_fa507_xor1 fa_or0=s_wallace_cla32_fa507_or0
.subckt and_gate a=a[11] b=b[20] out=s_wallace_cla32_and_11_20
.subckt and_gate a=a[10] b=b[21] out=s_wallace_cla32_and_10_21
.subckt fa a=s_wallace_cla32_fa507_or0 b=s_wallace_cla32_and_11_20 cin=s_wallace_cla32_and_10_21 fa_xor1=s_wallace_cla32_fa508_xor1 fa_or0=s_wallace_cla32_fa508_or0
.subckt and_gate a=a[12] b=b[20] out=s_wallace_cla32_and_12_20
.subckt and_gate a=a[11] b=b[21] out=s_wallace_cla32_and_11_21
.subckt fa a=s_wallace_cla32_fa508_or0 b=s_wallace_cla32_and_12_20 cin=s_wallace_cla32_and_11_21 fa_xor1=s_wallace_cla32_fa509_xor1 fa_or0=s_wallace_cla32_fa509_or0
.subckt and_gate a=a[11] b=b[22] out=s_wallace_cla32_and_11_22
.subckt and_gate a=a[10] b=b[23] out=s_wallace_cla32_and_10_23
.subckt fa a=s_wallace_cla32_fa509_or0 b=s_wallace_cla32_and_11_22 cin=s_wallace_cla32_and_10_23 fa_xor1=s_wallace_cla32_fa510_xor1 fa_or0=s_wallace_cla32_fa510_or0
.subckt and_gate a=a[11] b=b[23] out=s_wallace_cla32_and_11_23
.subckt and_gate a=a[10] b=b[24] out=s_wallace_cla32_and_10_24
.subckt fa a=s_wallace_cla32_fa510_or0 b=s_wallace_cla32_and_11_23 cin=s_wallace_cla32_and_10_24 fa_xor1=s_wallace_cla32_fa511_xor1 fa_or0=s_wallace_cla32_fa511_or0
.subckt and_gate a=a[11] b=b[24] out=s_wallace_cla32_and_11_24
.subckt and_gate a=a[10] b=b[25] out=s_wallace_cla32_and_10_25
.subckt fa a=s_wallace_cla32_fa511_or0 b=s_wallace_cla32_and_11_24 cin=s_wallace_cla32_and_10_25 fa_xor1=s_wallace_cla32_fa512_xor1 fa_or0=s_wallace_cla32_fa512_or0
.subckt and_gate a=a[11] b=b[25] out=s_wallace_cla32_and_11_25
.subckt and_gate a=a[10] b=b[26] out=s_wallace_cla32_and_10_26
.subckt fa a=s_wallace_cla32_fa512_or0 b=s_wallace_cla32_and_11_25 cin=s_wallace_cla32_and_10_26 fa_xor1=s_wallace_cla32_fa513_xor1 fa_or0=s_wallace_cla32_fa513_or0
.subckt and_gate a=a[11] b=b[26] out=s_wallace_cla32_and_11_26
.subckt and_gate a=a[10] b=b[27] out=s_wallace_cla32_and_10_27
.subckt fa a=s_wallace_cla32_fa513_or0 b=s_wallace_cla32_and_11_26 cin=s_wallace_cla32_and_10_27 fa_xor1=s_wallace_cla32_fa514_xor1 fa_or0=s_wallace_cla32_fa514_or0
.subckt and_gate a=a[11] b=b[27] out=s_wallace_cla32_and_11_27
.subckt and_gate a=a[10] b=b[28] out=s_wallace_cla32_and_10_28
.subckt fa a=s_wallace_cla32_fa514_or0 b=s_wallace_cla32_and_11_27 cin=s_wallace_cla32_and_10_28 fa_xor1=s_wallace_cla32_fa515_xor1 fa_or0=s_wallace_cla32_fa515_or0
.subckt and_gate a=a[11] b=b[28] out=s_wallace_cla32_and_11_28
.subckt and_gate a=a[10] b=b[29] out=s_wallace_cla32_and_10_29
.subckt fa a=s_wallace_cla32_fa515_or0 b=s_wallace_cla32_and_11_28 cin=s_wallace_cla32_and_10_29 fa_xor1=s_wallace_cla32_fa516_xor1 fa_or0=s_wallace_cla32_fa516_or0
.subckt and_gate a=a[11] b=b[29] out=s_wallace_cla32_and_11_29
.subckt and_gate a=a[10] b=b[30] out=s_wallace_cla32_and_10_30
.subckt fa a=s_wallace_cla32_fa516_or0 b=s_wallace_cla32_and_11_29 cin=s_wallace_cla32_and_10_30 fa_xor1=s_wallace_cla32_fa517_xor1 fa_or0=s_wallace_cla32_fa517_or0
.subckt and_gate a=a[11] b=b[30] out=s_wallace_cla32_and_11_30
.subckt nand_gate a=a[10] b=b[31] out=s_wallace_cla32_nand_10_31
.subckt fa a=s_wallace_cla32_fa517_or0 b=s_wallace_cla32_and_11_30 cin=s_wallace_cla32_nand_10_31 fa_xor1=s_wallace_cla32_fa518_xor1 fa_or0=s_wallace_cla32_fa518_or0
.subckt nand_gate a=a[11] b=b[31] out=s_wallace_cla32_nand_11_31
.subckt fa a=s_wallace_cla32_fa518_or0 b=s_wallace_cla32_nand_11_31 cin=s_wallace_cla32_fa39_xor1 fa_xor1=s_wallace_cla32_fa519_xor1 fa_or0=s_wallace_cla32_fa519_or0
.subckt fa a=s_wallace_cla32_fa519_or0 b=s_wallace_cla32_fa40_xor1 cin=s_wallace_cla32_fa97_xor1 fa_xor1=s_wallace_cla32_fa520_xor1 fa_or0=s_wallace_cla32_fa520_or0
.subckt fa a=s_wallace_cla32_fa520_or0 b=s_wallace_cla32_fa98_xor1 cin=s_wallace_cla32_fa153_xor1 fa_xor1=s_wallace_cla32_fa521_xor1 fa_or0=s_wallace_cla32_fa521_or0
.subckt fa a=s_wallace_cla32_fa521_or0 b=s_wallace_cla32_fa154_xor1 cin=s_wallace_cla32_fa207_xor1 fa_xor1=s_wallace_cla32_fa522_xor1 fa_or0=s_wallace_cla32_fa522_or0
.subckt fa a=s_wallace_cla32_fa522_or0 b=s_wallace_cla32_fa208_xor1 cin=s_wallace_cla32_fa259_xor1 fa_xor1=s_wallace_cla32_fa523_xor1 fa_or0=s_wallace_cla32_fa523_or0
.subckt fa a=s_wallace_cla32_fa523_or0 b=s_wallace_cla32_fa260_xor1 cin=s_wallace_cla32_fa309_xor1 fa_xor1=s_wallace_cla32_fa524_xor1 fa_or0=s_wallace_cla32_fa524_or0
.subckt fa a=s_wallace_cla32_fa524_or0 b=s_wallace_cla32_fa310_xor1 cin=s_wallace_cla32_fa357_xor1 fa_xor1=s_wallace_cla32_fa525_xor1 fa_or0=s_wallace_cla32_fa525_or0
.subckt fa a=s_wallace_cla32_fa525_or0 b=s_wallace_cla32_fa358_xor1 cin=s_wallace_cla32_fa403_xor1 fa_xor1=s_wallace_cla32_fa526_xor1 fa_or0=s_wallace_cla32_fa526_or0
.subckt fa a=s_wallace_cla32_fa526_or0 b=s_wallace_cla32_fa404_xor1 cin=s_wallace_cla32_fa447_xor1 fa_xor1=s_wallace_cla32_fa527_xor1 fa_or0=s_wallace_cla32_fa527_or0
.subckt ha a=s_wallace_cla32_fa410_xor1 b=s_wallace_cla32_fa451_xor1 ha_xor0=s_wallace_cla32_ha11_xor0 ha_and0=s_wallace_cla32_ha11_and0
.subckt fa a=s_wallace_cla32_ha11_and0 b=s_wallace_cla32_fa368_xor1 cin=s_wallace_cla32_fa411_xor1 fa_xor1=s_wallace_cla32_fa528_xor1 fa_or0=s_wallace_cla32_fa528_or0
.subckt fa a=s_wallace_cla32_fa528_or0 b=s_wallace_cla32_fa324_xor1 cin=s_wallace_cla32_fa369_xor1 fa_xor1=s_wallace_cla32_fa529_xor1 fa_or0=s_wallace_cla32_fa529_or0
.subckt fa a=s_wallace_cla32_fa529_or0 b=s_wallace_cla32_fa278_xor1 cin=s_wallace_cla32_fa325_xor1 fa_xor1=s_wallace_cla32_fa530_xor1 fa_or0=s_wallace_cla32_fa530_or0
.subckt fa a=s_wallace_cla32_fa530_or0 b=s_wallace_cla32_fa230_xor1 cin=s_wallace_cla32_fa279_xor1 fa_xor1=s_wallace_cla32_fa531_xor1 fa_or0=s_wallace_cla32_fa531_or0
.subckt fa a=s_wallace_cla32_fa531_or0 b=s_wallace_cla32_fa180_xor1 cin=s_wallace_cla32_fa231_xor1 fa_xor1=s_wallace_cla32_fa532_xor1 fa_or0=s_wallace_cla32_fa532_or0
.subckt fa a=s_wallace_cla32_fa532_or0 b=s_wallace_cla32_fa128_xor1 cin=s_wallace_cla32_fa181_xor1 fa_xor1=s_wallace_cla32_fa533_xor1 fa_or0=s_wallace_cla32_fa533_or0
.subckt fa a=s_wallace_cla32_fa533_or0 b=s_wallace_cla32_fa74_xor1 cin=s_wallace_cla32_fa129_xor1 fa_xor1=s_wallace_cla32_fa534_xor1 fa_or0=s_wallace_cla32_fa534_or0
.subckt fa a=s_wallace_cla32_fa534_or0 b=s_wallace_cla32_fa18_xor1 cin=s_wallace_cla32_fa75_xor1 fa_xor1=s_wallace_cla32_fa535_xor1 fa_or0=s_wallace_cla32_fa535_or0
.subckt and_gate a=a[0] b=b[22] out=s_wallace_cla32_and_0_22
.subckt fa a=s_wallace_cla32_fa535_or0 b=s_wallace_cla32_and_0_22 cin=s_wallace_cla32_fa19_xor1 fa_xor1=s_wallace_cla32_fa536_xor1 fa_or0=s_wallace_cla32_fa536_or0
.subckt and_gate a=a[1] b=b[22] out=s_wallace_cla32_and_1_22
.subckt and_gate a=a[0] b=b[23] out=s_wallace_cla32_and_0_23
.subckt fa a=s_wallace_cla32_fa536_or0 b=s_wallace_cla32_and_1_22 cin=s_wallace_cla32_and_0_23 fa_xor1=s_wallace_cla32_fa537_xor1 fa_or0=s_wallace_cla32_fa537_or0
.subckt and_gate a=a[2] b=b[22] out=s_wallace_cla32_and_2_22
.subckt and_gate a=a[1] b=b[23] out=s_wallace_cla32_and_1_23
.subckt fa a=s_wallace_cla32_fa537_or0 b=s_wallace_cla32_and_2_22 cin=s_wallace_cla32_and_1_23 fa_xor1=s_wallace_cla32_fa538_xor1 fa_or0=s_wallace_cla32_fa538_or0
.subckt and_gate a=a[3] b=b[22] out=s_wallace_cla32_and_3_22
.subckt and_gate a=a[2] b=b[23] out=s_wallace_cla32_and_2_23
.subckt fa a=s_wallace_cla32_fa538_or0 b=s_wallace_cla32_and_3_22 cin=s_wallace_cla32_and_2_23 fa_xor1=s_wallace_cla32_fa539_xor1 fa_or0=s_wallace_cla32_fa539_or0
.subckt and_gate a=a[4] b=b[22] out=s_wallace_cla32_and_4_22
.subckt and_gate a=a[3] b=b[23] out=s_wallace_cla32_and_3_23
.subckt fa a=s_wallace_cla32_fa539_or0 b=s_wallace_cla32_and_4_22 cin=s_wallace_cla32_and_3_23 fa_xor1=s_wallace_cla32_fa540_xor1 fa_or0=s_wallace_cla32_fa540_or0
.subckt and_gate a=a[5] b=b[22] out=s_wallace_cla32_and_5_22
.subckt and_gate a=a[4] b=b[23] out=s_wallace_cla32_and_4_23
.subckt fa a=s_wallace_cla32_fa540_or0 b=s_wallace_cla32_and_5_22 cin=s_wallace_cla32_and_4_23 fa_xor1=s_wallace_cla32_fa541_xor1 fa_or0=s_wallace_cla32_fa541_or0
.subckt and_gate a=a[6] b=b[22] out=s_wallace_cla32_and_6_22
.subckt and_gate a=a[5] b=b[23] out=s_wallace_cla32_and_5_23
.subckt fa a=s_wallace_cla32_fa541_or0 b=s_wallace_cla32_and_6_22 cin=s_wallace_cla32_and_5_23 fa_xor1=s_wallace_cla32_fa542_xor1 fa_or0=s_wallace_cla32_fa542_or0
.subckt and_gate a=a[7] b=b[22] out=s_wallace_cla32_and_7_22
.subckt and_gate a=a[6] b=b[23] out=s_wallace_cla32_and_6_23
.subckt fa a=s_wallace_cla32_fa542_or0 b=s_wallace_cla32_and_7_22 cin=s_wallace_cla32_and_6_23 fa_xor1=s_wallace_cla32_fa543_xor1 fa_or0=s_wallace_cla32_fa543_or0
.subckt and_gate a=a[8] b=b[22] out=s_wallace_cla32_and_8_22
.subckt and_gate a=a[7] b=b[23] out=s_wallace_cla32_and_7_23
.subckt fa a=s_wallace_cla32_fa543_or0 b=s_wallace_cla32_and_8_22 cin=s_wallace_cla32_and_7_23 fa_xor1=s_wallace_cla32_fa544_xor1 fa_or0=s_wallace_cla32_fa544_or0
.subckt and_gate a=a[9] b=b[22] out=s_wallace_cla32_and_9_22
.subckt and_gate a=a[8] b=b[23] out=s_wallace_cla32_and_8_23
.subckt fa a=s_wallace_cla32_fa544_or0 b=s_wallace_cla32_and_9_22 cin=s_wallace_cla32_and_8_23 fa_xor1=s_wallace_cla32_fa545_xor1 fa_or0=s_wallace_cla32_fa545_or0
.subckt and_gate a=a[10] b=b[22] out=s_wallace_cla32_and_10_22
.subckt and_gate a=a[9] b=b[23] out=s_wallace_cla32_and_9_23
.subckt fa a=s_wallace_cla32_fa545_or0 b=s_wallace_cla32_and_10_22 cin=s_wallace_cla32_and_9_23 fa_xor1=s_wallace_cla32_fa546_xor1 fa_or0=s_wallace_cla32_fa546_or0
.subckt and_gate a=a[9] b=b[24] out=s_wallace_cla32_and_9_24
.subckt and_gate a=a[8] b=b[25] out=s_wallace_cla32_and_8_25
.subckt fa a=s_wallace_cla32_fa546_or0 b=s_wallace_cla32_and_9_24 cin=s_wallace_cla32_and_8_25 fa_xor1=s_wallace_cla32_fa547_xor1 fa_or0=s_wallace_cla32_fa547_or0
.subckt and_gate a=a[9] b=b[25] out=s_wallace_cla32_and_9_25
.subckt and_gate a=a[8] b=b[26] out=s_wallace_cla32_and_8_26
.subckt fa a=s_wallace_cla32_fa547_or0 b=s_wallace_cla32_and_9_25 cin=s_wallace_cla32_and_8_26 fa_xor1=s_wallace_cla32_fa548_xor1 fa_or0=s_wallace_cla32_fa548_or0
.subckt and_gate a=a[9] b=b[26] out=s_wallace_cla32_and_9_26
.subckt and_gate a=a[8] b=b[27] out=s_wallace_cla32_and_8_27
.subckt fa a=s_wallace_cla32_fa548_or0 b=s_wallace_cla32_and_9_26 cin=s_wallace_cla32_and_8_27 fa_xor1=s_wallace_cla32_fa549_xor1 fa_or0=s_wallace_cla32_fa549_or0
.subckt and_gate a=a[9] b=b[27] out=s_wallace_cla32_and_9_27
.subckt and_gate a=a[8] b=b[28] out=s_wallace_cla32_and_8_28
.subckt fa a=s_wallace_cla32_fa549_or0 b=s_wallace_cla32_and_9_27 cin=s_wallace_cla32_and_8_28 fa_xor1=s_wallace_cla32_fa550_xor1 fa_or0=s_wallace_cla32_fa550_or0
.subckt and_gate a=a[9] b=b[28] out=s_wallace_cla32_and_9_28
.subckt and_gate a=a[8] b=b[29] out=s_wallace_cla32_and_8_29
.subckt fa a=s_wallace_cla32_fa550_or0 b=s_wallace_cla32_and_9_28 cin=s_wallace_cla32_and_8_29 fa_xor1=s_wallace_cla32_fa551_xor1 fa_or0=s_wallace_cla32_fa551_or0
.subckt and_gate a=a[9] b=b[29] out=s_wallace_cla32_and_9_29
.subckt and_gate a=a[8] b=b[30] out=s_wallace_cla32_and_8_30
.subckt fa a=s_wallace_cla32_fa551_or0 b=s_wallace_cla32_and_9_29 cin=s_wallace_cla32_and_8_30 fa_xor1=s_wallace_cla32_fa552_xor1 fa_or0=s_wallace_cla32_fa552_or0
.subckt and_gate a=a[9] b=b[30] out=s_wallace_cla32_and_9_30
.subckt nand_gate a=a[8] b=b[31] out=s_wallace_cla32_nand_8_31
.subckt fa a=s_wallace_cla32_fa552_or0 b=s_wallace_cla32_and_9_30 cin=s_wallace_cla32_nand_8_31 fa_xor1=s_wallace_cla32_fa553_xor1 fa_or0=s_wallace_cla32_fa553_or0
.subckt nand_gate a=a[9] b=b[31] out=s_wallace_cla32_nand_9_31
.subckt fa a=s_wallace_cla32_fa553_or0 b=s_wallace_cla32_nand_9_31 cin=s_wallace_cla32_fa37_xor1 fa_xor1=s_wallace_cla32_fa554_xor1 fa_or0=s_wallace_cla32_fa554_or0
.subckt fa a=s_wallace_cla32_fa554_or0 b=s_wallace_cla32_fa38_xor1 cin=s_wallace_cla32_fa95_xor1 fa_xor1=s_wallace_cla32_fa555_xor1 fa_or0=s_wallace_cla32_fa555_or0
.subckt fa a=s_wallace_cla32_fa555_or0 b=s_wallace_cla32_fa96_xor1 cin=s_wallace_cla32_fa151_xor1 fa_xor1=s_wallace_cla32_fa556_xor1 fa_or0=s_wallace_cla32_fa556_or0
.subckt fa a=s_wallace_cla32_fa556_or0 b=s_wallace_cla32_fa152_xor1 cin=s_wallace_cla32_fa205_xor1 fa_xor1=s_wallace_cla32_fa557_xor1 fa_or0=s_wallace_cla32_fa557_or0
.subckt fa a=s_wallace_cla32_fa557_or0 b=s_wallace_cla32_fa206_xor1 cin=s_wallace_cla32_fa257_xor1 fa_xor1=s_wallace_cla32_fa558_xor1 fa_or0=s_wallace_cla32_fa558_or0
.subckt fa a=s_wallace_cla32_fa558_or0 b=s_wallace_cla32_fa258_xor1 cin=s_wallace_cla32_fa307_xor1 fa_xor1=s_wallace_cla32_fa559_xor1 fa_or0=s_wallace_cla32_fa559_or0
.subckt fa a=s_wallace_cla32_fa559_or0 b=s_wallace_cla32_fa308_xor1 cin=s_wallace_cla32_fa355_xor1 fa_xor1=s_wallace_cla32_fa560_xor1 fa_or0=s_wallace_cla32_fa560_or0
.subckt fa a=s_wallace_cla32_fa560_or0 b=s_wallace_cla32_fa356_xor1 cin=s_wallace_cla32_fa401_xor1 fa_xor1=s_wallace_cla32_fa561_xor1 fa_or0=s_wallace_cla32_fa561_or0
.subckt fa a=s_wallace_cla32_fa561_or0 b=s_wallace_cla32_fa402_xor1 cin=s_wallace_cla32_fa445_xor1 fa_xor1=s_wallace_cla32_fa562_xor1 fa_or0=s_wallace_cla32_fa562_or0
.subckt fa a=s_wallace_cla32_fa562_or0 b=s_wallace_cla32_fa446_xor1 cin=s_wallace_cla32_fa487_xor1 fa_xor1=s_wallace_cla32_fa563_xor1 fa_or0=s_wallace_cla32_fa563_or0
.subckt ha a=s_wallace_cla32_fa452_xor1 b=s_wallace_cla32_fa491_xor1 ha_xor0=s_wallace_cla32_ha12_xor0 ha_and0=s_wallace_cla32_ha12_and0
.subckt fa a=s_wallace_cla32_ha12_and0 b=s_wallace_cla32_fa412_xor1 cin=s_wallace_cla32_fa453_xor1 fa_xor1=s_wallace_cla32_fa564_xor1 fa_or0=s_wallace_cla32_fa564_or0
.subckt fa a=s_wallace_cla32_fa564_or0 b=s_wallace_cla32_fa370_xor1 cin=s_wallace_cla32_fa413_xor1 fa_xor1=s_wallace_cla32_fa565_xor1 fa_or0=s_wallace_cla32_fa565_or0
.subckt fa a=s_wallace_cla32_fa565_or0 b=s_wallace_cla32_fa326_xor1 cin=s_wallace_cla32_fa371_xor1 fa_xor1=s_wallace_cla32_fa566_xor1 fa_or0=s_wallace_cla32_fa566_or0
.subckt fa a=s_wallace_cla32_fa566_or0 b=s_wallace_cla32_fa280_xor1 cin=s_wallace_cla32_fa327_xor1 fa_xor1=s_wallace_cla32_fa567_xor1 fa_or0=s_wallace_cla32_fa567_or0
.subckt fa a=s_wallace_cla32_fa567_or0 b=s_wallace_cla32_fa232_xor1 cin=s_wallace_cla32_fa281_xor1 fa_xor1=s_wallace_cla32_fa568_xor1 fa_or0=s_wallace_cla32_fa568_or0
.subckt fa a=s_wallace_cla32_fa568_or0 b=s_wallace_cla32_fa182_xor1 cin=s_wallace_cla32_fa233_xor1 fa_xor1=s_wallace_cla32_fa569_xor1 fa_or0=s_wallace_cla32_fa569_or0
.subckt fa a=s_wallace_cla32_fa569_or0 b=s_wallace_cla32_fa130_xor1 cin=s_wallace_cla32_fa183_xor1 fa_xor1=s_wallace_cla32_fa570_xor1 fa_or0=s_wallace_cla32_fa570_or0
.subckt fa a=s_wallace_cla32_fa570_or0 b=s_wallace_cla32_fa76_xor1 cin=s_wallace_cla32_fa131_xor1 fa_xor1=s_wallace_cla32_fa571_xor1 fa_or0=s_wallace_cla32_fa571_or0
.subckt fa a=s_wallace_cla32_fa571_or0 b=s_wallace_cla32_fa20_xor1 cin=s_wallace_cla32_fa77_xor1 fa_xor1=s_wallace_cla32_fa572_xor1 fa_or0=s_wallace_cla32_fa572_or0
.subckt and_gate a=a[0] b=b[24] out=s_wallace_cla32_and_0_24
.subckt fa a=s_wallace_cla32_fa572_or0 b=s_wallace_cla32_and_0_24 cin=s_wallace_cla32_fa21_xor1 fa_xor1=s_wallace_cla32_fa573_xor1 fa_or0=s_wallace_cla32_fa573_or0
.subckt and_gate a=a[1] b=b[24] out=s_wallace_cla32_and_1_24
.subckt and_gate a=a[0] b=b[25] out=s_wallace_cla32_and_0_25
.subckt fa a=s_wallace_cla32_fa573_or0 b=s_wallace_cla32_and_1_24 cin=s_wallace_cla32_and_0_25 fa_xor1=s_wallace_cla32_fa574_xor1 fa_or0=s_wallace_cla32_fa574_or0
.subckt and_gate a=a[2] b=b[24] out=s_wallace_cla32_and_2_24
.subckt and_gate a=a[1] b=b[25] out=s_wallace_cla32_and_1_25
.subckt fa a=s_wallace_cla32_fa574_or0 b=s_wallace_cla32_and_2_24 cin=s_wallace_cla32_and_1_25 fa_xor1=s_wallace_cla32_fa575_xor1 fa_or0=s_wallace_cla32_fa575_or0
.subckt and_gate a=a[3] b=b[24] out=s_wallace_cla32_and_3_24
.subckt and_gate a=a[2] b=b[25] out=s_wallace_cla32_and_2_25
.subckt fa a=s_wallace_cla32_fa575_or0 b=s_wallace_cla32_and_3_24 cin=s_wallace_cla32_and_2_25 fa_xor1=s_wallace_cla32_fa576_xor1 fa_or0=s_wallace_cla32_fa576_or0
.subckt and_gate a=a[4] b=b[24] out=s_wallace_cla32_and_4_24
.subckt and_gate a=a[3] b=b[25] out=s_wallace_cla32_and_3_25
.subckt fa a=s_wallace_cla32_fa576_or0 b=s_wallace_cla32_and_4_24 cin=s_wallace_cla32_and_3_25 fa_xor1=s_wallace_cla32_fa577_xor1 fa_or0=s_wallace_cla32_fa577_or0
.subckt and_gate a=a[5] b=b[24] out=s_wallace_cla32_and_5_24
.subckt and_gate a=a[4] b=b[25] out=s_wallace_cla32_and_4_25
.subckt fa a=s_wallace_cla32_fa577_or0 b=s_wallace_cla32_and_5_24 cin=s_wallace_cla32_and_4_25 fa_xor1=s_wallace_cla32_fa578_xor1 fa_or0=s_wallace_cla32_fa578_or0
.subckt and_gate a=a[6] b=b[24] out=s_wallace_cla32_and_6_24
.subckt and_gate a=a[5] b=b[25] out=s_wallace_cla32_and_5_25
.subckt fa a=s_wallace_cla32_fa578_or0 b=s_wallace_cla32_and_6_24 cin=s_wallace_cla32_and_5_25 fa_xor1=s_wallace_cla32_fa579_xor1 fa_or0=s_wallace_cla32_fa579_or0
.subckt and_gate a=a[7] b=b[24] out=s_wallace_cla32_and_7_24
.subckt and_gate a=a[6] b=b[25] out=s_wallace_cla32_and_6_25
.subckt fa a=s_wallace_cla32_fa579_or0 b=s_wallace_cla32_and_7_24 cin=s_wallace_cla32_and_6_25 fa_xor1=s_wallace_cla32_fa580_xor1 fa_or0=s_wallace_cla32_fa580_or0
.subckt and_gate a=a[8] b=b[24] out=s_wallace_cla32_and_8_24
.subckt and_gate a=a[7] b=b[25] out=s_wallace_cla32_and_7_25
.subckt fa a=s_wallace_cla32_fa580_or0 b=s_wallace_cla32_and_8_24 cin=s_wallace_cla32_and_7_25 fa_xor1=s_wallace_cla32_fa581_xor1 fa_or0=s_wallace_cla32_fa581_or0
.subckt and_gate a=a[7] b=b[26] out=s_wallace_cla32_and_7_26
.subckt and_gate a=a[6] b=b[27] out=s_wallace_cla32_and_6_27
.subckt fa a=s_wallace_cla32_fa581_or0 b=s_wallace_cla32_and_7_26 cin=s_wallace_cla32_and_6_27 fa_xor1=s_wallace_cla32_fa582_xor1 fa_or0=s_wallace_cla32_fa582_or0
.subckt and_gate a=a[7] b=b[27] out=s_wallace_cla32_and_7_27
.subckt and_gate a=a[6] b=b[28] out=s_wallace_cla32_and_6_28
.subckt fa a=s_wallace_cla32_fa582_or0 b=s_wallace_cla32_and_7_27 cin=s_wallace_cla32_and_6_28 fa_xor1=s_wallace_cla32_fa583_xor1 fa_or0=s_wallace_cla32_fa583_or0
.subckt and_gate a=a[7] b=b[28] out=s_wallace_cla32_and_7_28
.subckt and_gate a=a[6] b=b[29] out=s_wallace_cla32_and_6_29
.subckt fa a=s_wallace_cla32_fa583_or0 b=s_wallace_cla32_and_7_28 cin=s_wallace_cla32_and_6_29 fa_xor1=s_wallace_cla32_fa584_xor1 fa_or0=s_wallace_cla32_fa584_or0
.subckt and_gate a=a[7] b=b[29] out=s_wallace_cla32_and_7_29
.subckt and_gate a=a[6] b=b[30] out=s_wallace_cla32_and_6_30
.subckt fa a=s_wallace_cla32_fa584_or0 b=s_wallace_cla32_and_7_29 cin=s_wallace_cla32_and_6_30 fa_xor1=s_wallace_cla32_fa585_xor1 fa_or0=s_wallace_cla32_fa585_or0
.subckt and_gate a=a[7] b=b[30] out=s_wallace_cla32_and_7_30
.subckt nand_gate a=a[6] b=b[31] out=s_wallace_cla32_nand_6_31
.subckt fa a=s_wallace_cla32_fa585_or0 b=s_wallace_cla32_and_7_30 cin=s_wallace_cla32_nand_6_31 fa_xor1=s_wallace_cla32_fa586_xor1 fa_or0=s_wallace_cla32_fa586_or0
.subckt nand_gate a=a[7] b=b[31] out=s_wallace_cla32_nand_7_31
.subckt fa a=s_wallace_cla32_fa586_or0 b=s_wallace_cla32_nand_7_31 cin=s_wallace_cla32_fa35_xor1 fa_xor1=s_wallace_cla32_fa587_xor1 fa_or0=s_wallace_cla32_fa587_or0
.subckt fa a=s_wallace_cla32_fa587_or0 b=s_wallace_cla32_fa36_xor1 cin=s_wallace_cla32_fa93_xor1 fa_xor1=s_wallace_cla32_fa588_xor1 fa_or0=s_wallace_cla32_fa588_or0
.subckt fa a=s_wallace_cla32_fa588_or0 b=s_wallace_cla32_fa94_xor1 cin=s_wallace_cla32_fa149_xor1 fa_xor1=s_wallace_cla32_fa589_xor1 fa_or0=s_wallace_cla32_fa589_or0
.subckt fa a=s_wallace_cla32_fa589_or0 b=s_wallace_cla32_fa150_xor1 cin=s_wallace_cla32_fa203_xor1 fa_xor1=s_wallace_cla32_fa590_xor1 fa_or0=s_wallace_cla32_fa590_or0
.subckt fa a=s_wallace_cla32_fa590_or0 b=s_wallace_cla32_fa204_xor1 cin=s_wallace_cla32_fa255_xor1 fa_xor1=s_wallace_cla32_fa591_xor1 fa_or0=s_wallace_cla32_fa591_or0
.subckt fa a=s_wallace_cla32_fa591_or0 b=s_wallace_cla32_fa256_xor1 cin=s_wallace_cla32_fa305_xor1 fa_xor1=s_wallace_cla32_fa592_xor1 fa_or0=s_wallace_cla32_fa592_or0
.subckt fa a=s_wallace_cla32_fa592_or0 b=s_wallace_cla32_fa306_xor1 cin=s_wallace_cla32_fa353_xor1 fa_xor1=s_wallace_cla32_fa593_xor1 fa_or0=s_wallace_cla32_fa593_or0
.subckt fa a=s_wallace_cla32_fa593_or0 b=s_wallace_cla32_fa354_xor1 cin=s_wallace_cla32_fa399_xor1 fa_xor1=s_wallace_cla32_fa594_xor1 fa_or0=s_wallace_cla32_fa594_or0
.subckt fa a=s_wallace_cla32_fa594_or0 b=s_wallace_cla32_fa400_xor1 cin=s_wallace_cla32_fa443_xor1 fa_xor1=s_wallace_cla32_fa595_xor1 fa_or0=s_wallace_cla32_fa595_or0
.subckt fa a=s_wallace_cla32_fa595_or0 b=s_wallace_cla32_fa444_xor1 cin=s_wallace_cla32_fa485_xor1 fa_xor1=s_wallace_cla32_fa596_xor1 fa_or0=s_wallace_cla32_fa596_or0
.subckt fa a=s_wallace_cla32_fa596_or0 b=s_wallace_cla32_fa486_xor1 cin=s_wallace_cla32_fa525_xor1 fa_xor1=s_wallace_cla32_fa597_xor1 fa_or0=s_wallace_cla32_fa597_or0
.subckt ha a=s_wallace_cla32_fa492_xor1 b=s_wallace_cla32_fa529_xor1 ha_xor0=s_wallace_cla32_ha13_xor0 ha_and0=s_wallace_cla32_ha13_and0
.subckt fa a=s_wallace_cla32_ha13_and0 b=s_wallace_cla32_fa454_xor1 cin=s_wallace_cla32_fa493_xor1 fa_xor1=s_wallace_cla32_fa598_xor1 fa_or0=s_wallace_cla32_fa598_or0
.subckt fa a=s_wallace_cla32_fa598_or0 b=s_wallace_cla32_fa414_xor1 cin=s_wallace_cla32_fa455_xor1 fa_xor1=s_wallace_cla32_fa599_xor1 fa_or0=s_wallace_cla32_fa599_or0
.subckt fa a=s_wallace_cla32_fa599_or0 b=s_wallace_cla32_fa372_xor1 cin=s_wallace_cla32_fa415_xor1 fa_xor1=s_wallace_cla32_fa600_xor1 fa_or0=s_wallace_cla32_fa600_or0
.subckt fa a=s_wallace_cla32_fa600_or0 b=s_wallace_cla32_fa328_xor1 cin=s_wallace_cla32_fa373_xor1 fa_xor1=s_wallace_cla32_fa601_xor1 fa_or0=s_wallace_cla32_fa601_or0
.subckt fa a=s_wallace_cla32_fa601_or0 b=s_wallace_cla32_fa282_xor1 cin=s_wallace_cla32_fa329_xor1 fa_xor1=s_wallace_cla32_fa602_xor1 fa_or0=s_wallace_cla32_fa602_or0
.subckt fa a=s_wallace_cla32_fa602_or0 b=s_wallace_cla32_fa234_xor1 cin=s_wallace_cla32_fa283_xor1 fa_xor1=s_wallace_cla32_fa603_xor1 fa_or0=s_wallace_cla32_fa603_or0
.subckt fa a=s_wallace_cla32_fa603_or0 b=s_wallace_cla32_fa184_xor1 cin=s_wallace_cla32_fa235_xor1 fa_xor1=s_wallace_cla32_fa604_xor1 fa_or0=s_wallace_cla32_fa604_or0
.subckt fa a=s_wallace_cla32_fa604_or0 b=s_wallace_cla32_fa132_xor1 cin=s_wallace_cla32_fa185_xor1 fa_xor1=s_wallace_cla32_fa605_xor1 fa_or0=s_wallace_cla32_fa605_or0
.subckt fa a=s_wallace_cla32_fa605_or0 b=s_wallace_cla32_fa78_xor1 cin=s_wallace_cla32_fa133_xor1 fa_xor1=s_wallace_cla32_fa606_xor1 fa_or0=s_wallace_cla32_fa606_or0
.subckt fa a=s_wallace_cla32_fa606_or0 b=s_wallace_cla32_fa22_xor1 cin=s_wallace_cla32_fa79_xor1 fa_xor1=s_wallace_cla32_fa607_xor1 fa_or0=s_wallace_cla32_fa607_or0
.subckt and_gate a=a[0] b=b[26] out=s_wallace_cla32_and_0_26
.subckt fa a=s_wallace_cla32_fa607_or0 b=s_wallace_cla32_and_0_26 cin=s_wallace_cla32_fa23_xor1 fa_xor1=s_wallace_cla32_fa608_xor1 fa_or0=s_wallace_cla32_fa608_or0
.subckt and_gate a=a[1] b=b[26] out=s_wallace_cla32_and_1_26
.subckt and_gate a=a[0] b=b[27] out=s_wallace_cla32_and_0_27
.subckt fa a=s_wallace_cla32_fa608_or0 b=s_wallace_cla32_and_1_26 cin=s_wallace_cla32_and_0_27 fa_xor1=s_wallace_cla32_fa609_xor1 fa_or0=s_wallace_cla32_fa609_or0
.subckt and_gate a=a[2] b=b[26] out=s_wallace_cla32_and_2_26
.subckt and_gate a=a[1] b=b[27] out=s_wallace_cla32_and_1_27
.subckt fa a=s_wallace_cla32_fa609_or0 b=s_wallace_cla32_and_2_26 cin=s_wallace_cla32_and_1_27 fa_xor1=s_wallace_cla32_fa610_xor1 fa_or0=s_wallace_cla32_fa610_or0
.subckt and_gate a=a[3] b=b[26] out=s_wallace_cla32_and_3_26
.subckt and_gate a=a[2] b=b[27] out=s_wallace_cla32_and_2_27
.subckt fa a=s_wallace_cla32_fa610_or0 b=s_wallace_cla32_and_3_26 cin=s_wallace_cla32_and_2_27 fa_xor1=s_wallace_cla32_fa611_xor1 fa_or0=s_wallace_cla32_fa611_or0
.subckt and_gate a=a[4] b=b[26] out=s_wallace_cla32_and_4_26
.subckt and_gate a=a[3] b=b[27] out=s_wallace_cla32_and_3_27
.subckt fa a=s_wallace_cla32_fa611_or0 b=s_wallace_cla32_and_4_26 cin=s_wallace_cla32_and_3_27 fa_xor1=s_wallace_cla32_fa612_xor1 fa_or0=s_wallace_cla32_fa612_or0
.subckt and_gate a=a[5] b=b[26] out=s_wallace_cla32_and_5_26
.subckt and_gate a=a[4] b=b[27] out=s_wallace_cla32_and_4_27
.subckt fa a=s_wallace_cla32_fa612_or0 b=s_wallace_cla32_and_5_26 cin=s_wallace_cla32_and_4_27 fa_xor1=s_wallace_cla32_fa613_xor1 fa_or0=s_wallace_cla32_fa613_or0
.subckt and_gate a=a[6] b=b[26] out=s_wallace_cla32_and_6_26
.subckt and_gate a=a[5] b=b[27] out=s_wallace_cla32_and_5_27
.subckt fa a=s_wallace_cla32_fa613_or0 b=s_wallace_cla32_and_6_26 cin=s_wallace_cla32_and_5_27 fa_xor1=s_wallace_cla32_fa614_xor1 fa_or0=s_wallace_cla32_fa614_or0
.subckt and_gate a=a[5] b=b[28] out=s_wallace_cla32_and_5_28
.subckt and_gate a=a[4] b=b[29] out=s_wallace_cla32_and_4_29
.subckt fa a=s_wallace_cla32_fa614_or0 b=s_wallace_cla32_and_5_28 cin=s_wallace_cla32_and_4_29 fa_xor1=s_wallace_cla32_fa615_xor1 fa_or0=s_wallace_cla32_fa615_or0
.subckt and_gate a=a[5] b=b[29] out=s_wallace_cla32_and_5_29
.subckt and_gate a=a[4] b=b[30] out=s_wallace_cla32_and_4_30
.subckt fa a=s_wallace_cla32_fa615_or0 b=s_wallace_cla32_and_5_29 cin=s_wallace_cla32_and_4_30 fa_xor1=s_wallace_cla32_fa616_xor1 fa_or0=s_wallace_cla32_fa616_or0
.subckt and_gate a=a[5] b=b[30] out=s_wallace_cla32_and_5_30
.subckt nand_gate a=a[4] b=b[31] out=s_wallace_cla32_nand_4_31
.subckt fa a=s_wallace_cla32_fa616_or0 b=s_wallace_cla32_and_5_30 cin=s_wallace_cla32_nand_4_31 fa_xor1=s_wallace_cla32_fa617_xor1 fa_or0=s_wallace_cla32_fa617_or0
.subckt nand_gate a=a[5] b=b[31] out=s_wallace_cla32_nand_5_31
.subckt fa a=s_wallace_cla32_fa617_or0 b=s_wallace_cla32_nand_5_31 cin=s_wallace_cla32_fa33_xor1 fa_xor1=s_wallace_cla32_fa618_xor1 fa_or0=s_wallace_cla32_fa618_or0
.subckt fa a=s_wallace_cla32_fa618_or0 b=s_wallace_cla32_fa34_xor1 cin=s_wallace_cla32_fa91_xor1 fa_xor1=s_wallace_cla32_fa619_xor1 fa_or0=s_wallace_cla32_fa619_or0
.subckt fa a=s_wallace_cla32_fa619_or0 b=s_wallace_cla32_fa92_xor1 cin=s_wallace_cla32_fa147_xor1 fa_xor1=s_wallace_cla32_fa620_xor1 fa_or0=s_wallace_cla32_fa620_or0
.subckt fa a=s_wallace_cla32_fa620_or0 b=s_wallace_cla32_fa148_xor1 cin=s_wallace_cla32_fa201_xor1 fa_xor1=s_wallace_cla32_fa621_xor1 fa_or0=s_wallace_cla32_fa621_or0
.subckt fa a=s_wallace_cla32_fa621_or0 b=s_wallace_cla32_fa202_xor1 cin=s_wallace_cla32_fa253_xor1 fa_xor1=s_wallace_cla32_fa622_xor1 fa_or0=s_wallace_cla32_fa622_or0
.subckt fa a=s_wallace_cla32_fa622_or0 b=s_wallace_cla32_fa254_xor1 cin=s_wallace_cla32_fa303_xor1 fa_xor1=s_wallace_cla32_fa623_xor1 fa_or0=s_wallace_cla32_fa623_or0
.subckt fa a=s_wallace_cla32_fa623_or0 b=s_wallace_cla32_fa304_xor1 cin=s_wallace_cla32_fa351_xor1 fa_xor1=s_wallace_cla32_fa624_xor1 fa_or0=s_wallace_cla32_fa624_or0
.subckt fa a=s_wallace_cla32_fa624_or0 b=s_wallace_cla32_fa352_xor1 cin=s_wallace_cla32_fa397_xor1 fa_xor1=s_wallace_cla32_fa625_xor1 fa_or0=s_wallace_cla32_fa625_or0
.subckt fa a=s_wallace_cla32_fa625_or0 b=s_wallace_cla32_fa398_xor1 cin=s_wallace_cla32_fa441_xor1 fa_xor1=s_wallace_cla32_fa626_xor1 fa_or0=s_wallace_cla32_fa626_or0
.subckt fa a=s_wallace_cla32_fa626_or0 b=s_wallace_cla32_fa442_xor1 cin=s_wallace_cla32_fa483_xor1 fa_xor1=s_wallace_cla32_fa627_xor1 fa_or0=s_wallace_cla32_fa627_or0
.subckt fa a=s_wallace_cla32_fa627_or0 b=s_wallace_cla32_fa484_xor1 cin=s_wallace_cla32_fa523_xor1 fa_xor1=s_wallace_cla32_fa628_xor1 fa_or0=s_wallace_cla32_fa628_or0
.subckt fa a=s_wallace_cla32_fa628_or0 b=s_wallace_cla32_fa524_xor1 cin=s_wallace_cla32_fa561_xor1 fa_xor1=s_wallace_cla32_fa629_xor1 fa_or0=s_wallace_cla32_fa629_or0
.subckt ha a=s_wallace_cla32_fa530_xor1 b=s_wallace_cla32_fa565_xor1 ha_xor0=s_wallace_cla32_ha14_xor0 ha_and0=s_wallace_cla32_ha14_and0
.subckt fa a=s_wallace_cla32_ha14_and0 b=s_wallace_cla32_fa494_xor1 cin=s_wallace_cla32_fa531_xor1 fa_xor1=s_wallace_cla32_fa630_xor1 fa_or0=s_wallace_cla32_fa630_or0
.subckt fa a=s_wallace_cla32_fa630_or0 b=s_wallace_cla32_fa456_xor1 cin=s_wallace_cla32_fa495_xor1 fa_xor1=s_wallace_cla32_fa631_xor1 fa_or0=s_wallace_cla32_fa631_or0
.subckt fa a=s_wallace_cla32_fa631_or0 b=s_wallace_cla32_fa416_xor1 cin=s_wallace_cla32_fa457_xor1 fa_xor1=s_wallace_cla32_fa632_xor1 fa_or0=s_wallace_cla32_fa632_or0
.subckt fa a=s_wallace_cla32_fa632_or0 b=s_wallace_cla32_fa374_xor1 cin=s_wallace_cla32_fa417_xor1 fa_xor1=s_wallace_cla32_fa633_xor1 fa_or0=s_wallace_cla32_fa633_or0
.subckt fa a=s_wallace_cla32_fa633_or0 b=s_wallace_cla32_fa330_xor1 cin=s_wallace_cla32_fa375_xor1 fa_xor1=s_wallace_cla32_fa634_xor1 fa_or0=s_wallace_cla32_fa634_or0
.subckt fa a=s_wallace_cla32_fa634_or0 b=s_wallace_cla32_fa284_xor1 cin=s_wallace_cla32_fa331_xor1 fa_xor1=s_wallace_cla32_fa635_xor1 fa_or0=s_wallace_cla32_fa635_or0
.subckt fa a=s_wallace_cla32_fa635_or0 b=s_wallace_cla32_fa236_xor1 cin=s_wallace_cla32_fa285_xor1 fa_xor1=s_wallace_cla32_fa636_xor1 fa_or0=s_wallace_cla32_fa636_or0
.subckt fa a=s_wallace_cla32_fa636_or0 b=s_wallace_cla32_fa186_xor1 cin=s_wallace_cla32_fa237_xor1 fa_xor1=s_wallace_cla32_fa637_xor1 fa_or0=s_wallace_cla32_fa637_or0
.subckt fa a=s_wallace_cla32_fa637_or0 b=s_wallace_cla32_fa134_xor1 cin=s_wallace_cla32_fa187_xor1 fa_xor1=s_wallace_cla32_fa638_xor1 fa_or0=s_wallace_cla32_fa638_or0
.subckt fa a=s_wallace_cla32_fa638_or0 b=s_wallace_cla32_fa80_xor1 cin=s_wallace_cla32_fa135_xor1 fa_xor1=s_wallace_cla32_fa639_xor1 fa_or0=s_wallace_cla32_fa639_or0
.subckt fa a=s_wallace_cla32_fa639_or0 b=s_wallace_cla32_fa24_xor1 cin=s_wallace_cla32_fa81_xor1 fa_xor1=s_wallace_cla32_fa640_xor1 fa_or0=s_wallace_cla32_fa640_or0
.subckt and_gate a=a[0] b=b[28] out=s_wallace_cla32_and_0_28
.subckt fa a=s_wallace_cla32_fa640_or0 b=s_wallace_cla32_and_0_28 cin=s_wallace_cla32_fa25_xor1 fa_xor1=s_wallace_cla32_fa641_xor1 fa_or0=s_wallace_cla32_fa641_or0
.subckt and_gate a=a[1] b=b[28] out=s_wallace_cla32_and_1_28
.subckt and_gate a=a[0] b=b[29] out=s_wallace_cla32_and_0_29
.subckt fa a=s_wallace_cla32_fa641_or0 b=s_wallace_cla32_and_1_28 cin=s_wallace_cla32_and_0_29 fa_xor1=s_wallace_cla32_fa642_xor1 fa_or0=s_wallace_cla32_fa642_or0
.subckt and_gate a=a[2] b=b[28] out=s_wallace_cla32_and_2_28
.subckt and_gate a=a[1] b=b[29] out=s_wallace_cla32_and_1_29
.subckt fa a=s_wallace_cla32_fa642_or0 b=s_wallace_cla32_and_2_28 cin=s_wallace_cla32_and_1_29 fa_xor1=s_wallace_cla32_fa643_xor1 fa_or0=s_wallace_cla32_fa643_or0
.subckt and_gate a=a[3] b=b[28] out=s_wallace_cla32_and_3_28
.subckt and_gate a=a[2] b=b[29] out=s_wallace_cla32_and_2_29
.subckt fa a=s_wallace_cla32_fa643_or0 b=s_wallace_cla32_and_3_28 cin=s_wallace_cla32_and_2_29 fa_xor1=s_wallace_cla32_fa644_xor1 fa_or0=s_wallace_cla32_fa644_or0
.subckt and_gate a=a[4] b=b[28] out=s_wallace_cla32_and_4_28
.subckt and_gate a=a[3] b=b[29] out=s_wallace_cla32_and_3_29
.subckt fa a=s_wallace_cla32_fa644_or0 b=s_wallace_cla32_and_4_28 cin=s_wallace_cla32_and_3_29 fa_xor1=s_wallace_cla32_fa645_xor1 fa_or0=s_wallace_cla32_fa645_or0
.subckt and_gate a=a[3] b=b[30] out=s_wallace_cla32_and_3_30
.subckt nand_gate a=a[2] b=b[31] out=s_wallace_cla32_nand_2_31
.subckt fa a=s_wallace_cla32_fa645_or0 b=s_wallace_cla32_and_3_30 cin=s_wallace_cla32_nand_2_31 fa_xor1=s_wallace_cla32_fa646_xor1 fa_or0=s_wallace_cla32_fa646_or0
.subckt nand_gate a=a[3] b=b[31] out=s_wallace_cla32_nand_3_31
.subckt fa a=s_wallace_cla32_fa646_or0 b=s_wallace_cla32_nand_3_31 cin=s_wallace_cla32_fa31_xor1 fa_xor1=s_wallace_cla32_fa647_xor1 fa_or0=s_wallace_cla32_fa647_or0
.subckt fa a=s_wallace_cla32_fa647_or0 b=s_wallace_cla32_fa32_xor1 cin=s_wallace_cla32_fa89_xor1 fa_xor1=s_wallace_cla32_fa648_xor1 fa_or0=s_wallace_cla32_fa648_or0
.subckt fa a=s_wallace_cla32_fa648_or0 b=s_wallace_cla32_fa90_xor1 cin=s_wallace_cla32_fa145_xor1 fa_xor1=s_wallace_cla32_fa649_xor1 fa_or0=s_wallace_cla32_fa649_or0
.subckt fa a=s_wallace_cla32_fa649_or0 b=s_wallace_cla32_fa146_xor1 cin=s_wallace_cla32_fa199_xor1 fa_xor1=s_wallace_cla32_fa650_xor1 fa_or0=s_wallace_cla32_fa650_or0
.subckt fa a=s_wallace_cla32_fa650_or0 b=s_wallace_cla32_fa200_xor1 cin=s_wallace_cla32_fa251_xor1 fa_xor1=s_wallace_cla32_fa651_xor1 fa_or0=s_wallace_cla32_fa651_or0
.subckt fa a=s_wallace_cla32_fa651_or0 b=s_wallace_cla32_fa252_xor1 cin=s_wallace_cla32_fa301_xor1 fa_xor1=s_wallace_cla32_fa652_xor1 fa_or0=s_wallace_cla32_fa652_or0
.subckt fa a=s_wallace_cla32_fa652_or0 b=s_wallace_cla32_fa302_xor1 cin=s_wallace_cla32_fa349_xor1 fa_xor1=s_wallace_cla32_fa653_xor1 fa_or0=s_wallace_cla32_fa653_or0
.subckt fa a=s_wallace_cla32_fa653_or0 b=s_wallace_cla32_fa350_xor1 cin=s_wallace_cla32_fa395_xor1 fa_xor1=s_wallace_cla32_fa654_xor1 fa_or0=s_wallace_cla32_fa654_or0
.subckt fa a=s_wallace_cla32_fa654_or0 b=s_wallace_cla32_fa396_xor1 cin=s_wallace_cla32_fa439_xor1 fa_xor1=s_wallace_cla32_fa655_xor1 fa_or0=s_wallace_cla32_fa655_or0
.subckt fa a=s_wallace_cla32_fa655_or0 b=s_wallace_cla32_fa440_xor1 cin=s_wallace_cla32_fa481_xor1 fa_xor1=s_wallace_cla32_fa656_xor1 fa_or0=s_wallace_cla32_fa656_or0
.subckt fa a=s_wallace_cla32_fa656_or0 b=s_wallace_cla32_fa482_xor1 cin=s_wallace_cla32_fa521_xor1 fa_xor1=s_wallace_cla32_fa657_xor1 fa_or0=s_wallace_cla32_fa657_or0
.subckt fa a=s_wallace_cla32_fa657_or0 b=s_wallace_cla32_fa522_xor1 cin=s_wallace_cla32_fa559_xor1 fa_xor1=s_wallace_cla32_fa658_xor1 fa_or0=s_wallace_cla32_fa658_or0
.subckt fa a=s_wallace_cla32_fa658_or0 b=s_wallace_cla32_fa560_xor1 cin=s_wallace_cla32_fa595_xor1 fa_xor1=s_wallace_cla32_fa659_xor1 fa_or0=s_wallace_cla32_fa659_or0
.subckt ha a=s_wallace_cla32_fa566_xor1 b=s_wallace_cla32_fa599_xor1 ha_xor0=s_wallace_cla32_ha15_xor0 ha_and0=s_wallace_cla32_ha15_and0
.subckt fa a=s_wallace_cla32_ha15_and0 b=s_wallace_cla32_fa532_xor1 cin=s_wallace_cla32_fa567_xor1 fa_xor1=s_wallace_cla32_fa660_xor1 fa_or0=s_wallace_cla32_fa660_or0
.subckt fa a=s_wallace_cla32_fa660_or0 b=s_wallace_cla32_fa496_xor1 cin=s_wallace_cla32_fa533_xor1 fa_xor1=s_wallace_cla32_fa661_xor1 fa_or0=s_wallace_cla32_fa661_or0
.subckt fa a=s_wallace_cla32_fa661_or0 b=s_wallace_cla32_fa458_xor1 cin=s_wallace_cla32_fa497_xor1 fa_xor1=s_wallace_cla32_fa662_xor1 fa_or0=s_wallace_cla32_fa662_or0
.subckt fa a=s_wallace_cla32_fa662_or0 b=s_wallace_cla32_fa418_xor1 cin=s_wallace_cla32_fa459_xor1 fa_xor1=s_wallace_cla32_fa663_xor1 fa_or0=s_wallace_cla32_fa663_or0
.subckt fa a=s_wallace_cla32_fa663_or0 b=s_wallace_cla32_fa376_xor1 cin=s_wallace_cla32_fa419_xor1 fa_xor1=s_wallace_cla32_fa664_xor1 fa_or0=s_wallace_cla32_fa664_or0
.subckt fa a=s_wallace_cla32_fa664_or0 b=s_wallace_cla32_fa332_xor1 cin=s_wallace_cla32_fa377_xor1 fa_xor1=s_wallace_cla32_fa665_xor1 fa_or0=s_wallace_cla32_fa665_or0
.subckt fa a=s_wallace_cla32_fa665_or0 b=s_wallace_cla32_fa286_xor1 cin=s_wallace_cla32_fa333_xor1 fa_xor1=s_wallace_cla32_fa666_xor1 fa_or0=s_wallace_cla32_fa666_or0
.subckt fa a=s_wallace_cla32_fa666_or0 b=s_wallace_cla32_fa238_xor1 cin=s_wallace_cla32_fa287_xor1 fa_xor1=s_wallace_cla32_fa667_xor1 fa_or0=s_wallace_cla32_fa667_or0
.subckt fa a=s_wallace_cla32_fa667_or0 b=s_wallace_cla32_fa188_xor1 cin=s_wallace_cla32_fa239_xor1 fa_xor1=s_wallace_cla32_fa668_xor1 fa_or0=s_wallace_cla32_fa668_or0
.subckt fa a=s_wallace_cla32_fa668_or0 b=s_wallace_cla32_fa136_xor1 cin=s_wallace_cla32_fa189_xor1 fa_xor1=s_wallace_cla32_fa669_xor1 fa_or0=s_wallace_cla32_fa669_or0
.subckt fa a=s_wallace_cla32_fa669_or0 b=s_wallace_cla32_fa82_xor1 cin=s_wallace_cla32_fa137_xor1 fa_xor1=s_wallace_cla32_fa670_xor1 fa_or0=s_wallace_cla32_fa670_or0
.subckt fa a=s_wallace_cla32_fa670_or0 b=s_wallace_cla32_fa26_xor1 cin=s_wallace_cla32_fa83_xor1 fa_xor1=s_wallace_cla32_fa671_xor1 fa_or0=s_wallace_cla32_fa671_or0
.subckt and_gate a=a[0] b=b[30] out=s_wallace_cla32_and_0_30
.subckt fa a=s_wallace_cla32_fa671_or0 b=s_wallace_cla32_and_0_30 cin=s_wallace_cla32_fa27_xor1 fa_xor1=s_wallace_cla32_fa672_xor1 fa_or0=s_wallace_cla32_fa672_or0
.subckt and_gate a=a[1] b=b[30] out=s_wallace_cla32_and_1_30
.subckt nand_gate a=a[0] b=b[31] out=s_wallace_cla32_nand_0_31
.subckt fa a=s_wallace_cla32_fa672_or0 b=s_wallace_cla32_and_1_30 cin=s_wallace_cla32_nand_0_31 fa_xor1=s_wallace_cla32_fa673_xor1 fa_or0=s_wallace_cla32_fa673_or0
.subckt and_gate a=a[2] b=b[30] out=s_wallace_cla32_and_2_30
.subckt nand_gate a=a[1] b=b[31] out=s_wallace_cla32_nand_1_31
.subckt fa a=s_wallace_cla32_fa673_or0 b=s_wallace_cla32_and_2_30 cin=s_wallace_cla32_nand_1_31 fa_xor1=s_wallace_cla32_fa674_xor1 fa_or0=s_wallace_cla32_fa674_or0
.subckt fa a=s_wallace_cla32_fa674_or0 b=s_wallace_cla32_fa30_xor1 cin=s_wallace_cla32_fa87_xor1 fa_xor1=s_wallace_cla32_fa675_xor1 fa_or0=s_wallace_cla32_fa675_or0
.subckt fa a=s_wallace_cla32_fa675_or0 b=s_wallace_cla32_fa88_xor1 cin=s_wallace_cla32_fa143_xor1 fa_xor1=s_wallace_cla32_fa676_xor1 fa_or0=s_wallace_cla32_fa676_or0
.subckt fa a=s_wallace_cla32_fa676_or0 b=s_wallace_cla32_fa144_xor1 cin=s_wallace_cla32_fa197_xor1 fa_xor1=s_wallace_cla32_fa677_xor1 fa_or0=s_wallace_cla32_fa677_or0
.subckt fa a=s_wallace_cla32_fa677_or0 b=s_wallace_cla32_fa198_xor1 cin=s_wallace_cla32_fa249_xor1 fa_xor1=s_wallace_cla32_fa678_xor1 fa_or0=s_wallace_cla32_fa678_or0
.subckt fa a=s_wallace_cla32_fa678_or0 b=s_wallace_cla32_fa250_xor1 cin=s_wallace_cla32_fa299_xor1 fa_xor1=s_wallace_cla32_fa679_xor1 fa_or0=s_wallace_cla32_fa679_or0
.subckt fa a=s_wallace_cla32_fa679_or0 b=s_wallace_cla32_fa300_xor1 cin=s_wallace_cla32_fa347_xor1 fa_xor1=s_wallace_cla32_fa680_xor1 fa_or0=s_wallace_cla32_fa680_or0
.subckt fa a=s_wallace_cla32_fa680_or0 b=s_wallace_cla32_fa348_xor1 cin=s_wallace_cla32_fa393_xor1 fa_xor1=s_wallace_cla32_fa681_xor1 fa_or0=s_wallace_cla32_fa681_or0
.subckt fa a=s_wallace_cla32_fa681_or0 b=s_wallace_cla32_fa394_xor1 cin=s_wallace_cla32_fa437_xor1 fa_xor1=s_wallace_cla32_fa682_xor1 fa_or0=s_wallace_cla32_fa682_or0
.subckt fa a=s_wallace_cla32_fa682_or0 b=s_wallace_cla32_fa438_xor1 cin=s_wallace_cla32_fa479_xor1 fa_xor1=s_wallace_cla32_fa683_xor1 fa_or0=s_wallace_cla32_fa683_or0
.subckt fa a=s_wallace_cla32_fa683_or0 b=s_wallace_cla32_fa480_xor1 cin=s_wallace_cla32_fa519_xor1 fa_xor1=s_wallace_cla32_fa684_xor1 fa_or0=s_wallace_cla32_fa684_or0
.subckt fa a=s_wallace_cla32_fa684_or0 b=s_wallace_cla32_fa520_xor1 cin=s_wallace_cla32_fa557_xor1 fa_xor1=s_wallace_cla32_fa685_xor1 fa_or0=s_wallace_cla32_fa685_or0
.subckt fa a=s_wallace_cla32_fa685_or0 b=s_wallace_cla32_fa558_xor1 cin=s_wallace_cla32_fa593_xor1 fa_xor1=s_wallace_cla32_fa686_xor1 fa_or0=s_wallace_cla32_fa686_or0
.subckt fa a=s_wallace_cla32_fa686_or0 b=s_wallace_cla32_fa594_xor1 cin=s_wallace_cla32_fa627_xor1 fa_xor1=s_wallace_cla32_fa687_xor1 fa_or0=s_wallace_cla32_fa687_or0
.subckt ha a=s_wallace_cla32_fa600_xor1 b=s_wallace_cla32_fa631_xor1 ha_xor0=s_wallace_cla32_ha16_xor0 ha_and0=s_wallace_cla32_ha16_and0
.subckt fa a=s_wallace_cla32_ha16_and0 b=s_wallace_cla32_fa568_xor1 cin=s_wallace_cla32_fa601_xor1 fa_xor1=s_wallace_cla32_fa688_xor1 fa_or0=s_wallace_cla32_fa688_or0
.subckt fa a=s_wallace_cla32_fa688_or0 b=s_wallace_cla32_fa534_xor1 cin=s_wallace_cla32_fa569_xor1 fa_xor1=s_wallace_cla32_fa689_xor1 fa_or0=s_wallace_cla32_fa689_or0
.subckt fa a=s_wallace_cla32_fa689_or0 b=s_wallace_cla32_fa498_xor1 cin=s_wallace_cla32_fa535_xor1 fa_xor1=s_wallace_cla32_fa690_xor1 fa_or0=s_wallace_cla32_fa690_or0
.subckt fa a=s_wallace_cla32_fa690_or0 b=s_wallace_cla32_fa460_xor1 cin=s_wallace_cla32_fa499_xor1 fa_xor1=s_wallace_cla32_fa691_xor1 fa_or0=s_wallace_cla32_fa691_or0
.subckt fa a=s_wallace_cla32_fa691_or0 b=s_wallace_cla32_fa420_xor1 cin=s_wallace_cla32_fa461_xor1 fa_xor1=s_wallace_cla32_fa692_xor1 fa_or0=s_wallace_cla32_fa692_or0
.subckt fa a=s_wallace_cla32_fa692_or0 b=s_wallace_cla32_fa378_xor1 cin=s_wallace_cla32_fa421_xor1 fa_xor1=s_wallace_cla32_fa693_xor1 fa_or0=s_wallace_cla32_fa693_or0
.subckt fa a=s_wallace_cla32_fa693_or0 b=s_wallace_cla32_fa334_xor1 cin=s_wallace_cla32_fa379_xor1 fa_xor1=s_wallace_cla32_fa694_xor1 fa_or0=s_wallace_cla32_fa694_or0
.subckt fa a=s_wallace_cla32_fa694_or0 b=s_wallace_cla32_fa288_xor1 cin=s_wallace_cla32_fa335_xor1 fa_xor1=s_wallace_cla32_fa695_xor1 fa_or0=s_wallace_cla32_fa695_or0
.subckt fa a=s_wallace_cla32_fa695_or0 b=s_wallace_cla32_fa240_xor1 cin=s_wallace_cla32_fa289_xor1 fa_xor1=s_wallace_cla32_fa696_xor1 fa_or0=s_wallace_cla32_fa696_or0
.subckt fa a=s_wallace_cla32_fa696_or0 b=s_wallace_cla32_fa190_xor1 cin=s_wallace_cla32_fa241_xor1 fa_xor1=s_wallace_cla32_fa697_xor1 fa_or0=s_wallace_cla32_fa697_or0
.subckt fa a=s_wallace_cla32_fa697_or0 b=s_wallace_cla32_fa138_xor1 cin=s_wallace_cla32_fa191_xor1 fa_xor1=s_wallace_cla32_fa698_xor1 fa_or0=s_wallace_cla32_fa698_or0
.subckt fa a=s_wallace_cla32_fa698_or0 b=s_wallace_cla32_fa84_xor1 cin=s_wallace_cla32_fa139_xor1 fa_xor1=s_wallace_cla32_fa699_xor1 fa_or0=s_wallace_cla32_fa699_or0
.subckt fa a=s_wallace_cla32_fa699_or0 b=s_wallace_cla32_fa28_xor1 cin=s_wallace_cla32_fa85_xor1 fa_xor1=s_wallace_cla32_fa700_xor1 fa_or0=s_wallace_cla32_fa700_or0
.subckt fa a=s_wallace_cla32_fa700_or0 b=s_wallace_cla32_fa29_xor1 cin=s_wallace_cla32_fa86_xor1 fa_xor1=s_wallace_cla32_fa701_xor1 fa_or0=s_wallace_cla32_fa701_or0
.subckt fa a=s_wallace_cla32_fa701_or0 b=s_wallace_cla32_fa142_xor1 cin=s_wallace_cla32_fa195_xor1 fa_xor1=s_wallace_cla32_fa702_xor1 fa_or0=s_wallace_cla32_fa702_or0
.subckt fa a=s_wallace_cla32_fa702_or0 b=s_wallace_cla32_fa196_xor1 cin=s_wallace_cla32_fa247_xor1 fa_xor1=s_wallace_cla32_fa703_xor1 fa_or0=s_wallace_cla32_fa703_or0
.subckt fa a=s_wallace_cla32_fa703_or0 b=s_wallace_cla32_fa248_xor1 cin=s_wallace_cla32_fa297_xor1 fa_xor1=s_wallace_cla32_fa704_xor1 fa_or0=s_wallace_cla32_fa704_or0
.subckt fa a=s_wallace_cla32_fa704_or0 b=s_wallace_cla32_fa298_xor1 cin=s_wallace_cla32_fa345_xor1 fa_xor1=s_wallace_cla32_fa705_xor1 fa_or0=s_wallace_cla32_fa705_or0
.subckt fa a=s_wallace_cla32_fa705_or0 b=s_wallace_cla32_fa346_xor1 cin=s_wallace_cla32_fa391_xor1 fa_xor1=s_wallace_cla32_fa706_xor1 fa_or0=s_wallace_cla32_fa706_or0
.subckt fa a=s_wallace_cla32_fa706_or0 b=s_wallace_cla32_fa392_xor1 cin=s_wallace_cla32_fa435_xor1 fa_xor1=s_wallace_cla32_fa707_xor1 fa_or0=s_wallace_cla32_fa707_or0
.subckt fa a=s_wallace_cla32_fa707_or0 b=s_wallace_cla32_fa436_xor1 cin=s_wallace_cla32_fa477_xor1 fa_xor1=s_wallace_cla32_fa708_xor1 fa_or0=s_wallace_cla32_fa708_or0
.subckt fa a=s_wallace_cla32_fa708_or0 b=s_wallace_cla32_fa478_xor1 cin=s_wallace_cla32_fa517_xor1 fa_xor1=s_wallace_cla32_fa709_xor1 fa_or0=s_wallace_cla32_fa709_or0
.subckt fa a=s_wallace_cla32_fa709_or0 b=s_wallace_cla32_fa518_xor1 cin=s_wallace_cla32_fa555_xor1 fa_xor1=s_wallace_cla32_fa710_xor1 fa_or0=s_wallace_cla32_fa710_or0
.subckt fa a=s_wallace_cla32_fa710_or0 b=s_wallace_cla32_fa556_xor1 cin=s_wallace_cla32_fa591_xor1 fa_xor1=s_wallace_cla32_fa711_xor1 fa_or0=s_wallace_cla32_fa711_or0
.subckt fa a=s_wallace_cla32_fa711_or0 b=s_wallace_cla32_fa592_xor1 cin=s_wallace_cla32_fa625_xor1 fa_xor1=s_wallace_cla32_fa712_xor1 fa_or0=s_wallace_cla32_fa712_or0
.subckt fa a=s_wallace_cla32_fa712_or0 b=s_wallace_cla32_fa626_xor1 cin=s_wallace_cla32_fa657_xor1 fa_xor1=s_wallace_cla32_fa713_xor1 fa_or0=s_wallace_cla32_fa713_or0
.subckt ha a=s_wallace_cla32_fa632_xor1 b=s_wallace_cla32_fa661_xor1 ha_xor0=s_wallace_cla32_ha17_xor0 ha_and0=s_wallace_cla32_ha17_and0
.subckt fa a=s_wallace_cla32_ha17_and0 b=s_wallace_cla32_fa602_xor1 cin=s_wallace_cla32_fa633_xor1 fa_xor1=s_wallace_cla32_fa714_xor1 fa_or0=s_wallace_cla32_fa714_or0
.subckt fa a=s_wallace_cla32_fa714_or0 b=s_wallace_cla32_fa570_xor1 cin=s_wallace_cla32_fa603_xor1 fa_xor1=s_wallace_cla32_fa715_xor1 fa_or0=s_wallace_cla32_fa715_or0
.subckt fa a=s_wallace_cla32_fa715_or0 b=s_wallace_cla32_fa536_xor1 cin=s_wallace_cla32_fa571_xor1 fa_xor1=s_wallace_cla32_fa716_xor1 fa_or0=s_wallace_cla32_fa716_or0
.subckt fa a=s_wallace_cla32_fa716_or0 b=s_wallace_cla32_fa500_xor1 cin=s_wallace_cla32_fa537_xor1 fa_xor1=s_wallace_cla32_fa717_xor1 fa_or0=s_wallace_cla32_fa717_or0
.subckt fa a=s_wallace_cla32_fa717_or0 b=s_wallace_cla32_fa462_xor1 cin=s_wallace_cla32_fa501_xor1 fa_xor1=s_wallace_cla32_fa718_xor1 fa_or0=s_wallace_cla32_fa718_or0
.subckt fa a=s_wallace_cla32_fa718_or0 b=s_wallace_cla32_fa422_xor1 cin=s_wallace_cla32_fa463_xor1 fa_xor1=s_wallace_cla32_fa719_xor1 fa_or0=s_wallace_cla32_fa719_or0
.subckt fa a=s_wallace_cla32_fa719_or0 b=s_wallace_cla32_fa380_xor1 cin=s_wallace_cla32_fa423_xor1 fa_xor1=s_wallace_cla32_fa720_xor1 fa_or0=s_wallace_cla32_fa720_or0
.subckt fa a=s_wallace_cla32_fa720_or0 b=s_wallace_cla32_fa336_xor1 cin=s_wallace_cla32_fa381_xor1 fa_xor1=s_wallace_cla32_fa721_xor1 fa_or0=s_wallace_cla32_fa721_or0
.subckt fa a=s_wallace_cla32_fa721_or0 b=s_wallace_cla32_fa290_xor1 cin=s_wallace_cla32_fa337_xor1 fa_xor1=s_wallace_cla32_fa722_xor1 fa_or0=s_wallace_cla32_fa722_or0
.subckt fa a=s_wallace_cla32_fa722_or0 b=s_wallace_cla32_fa242_xor1 cin=s_wallace_cla32_fa291_xor1 fa_xor1=s_wallace_cla32_fa723_xor1 fa_or0=s_wallace_cla32_fa723_or0
.subckt fa a=s_wallace_cla32_fa723_or0 b=s_wallace_cla32_fa192_xor1 cin=s_wallace_cla32_fa243_xor1 fa_xor1=s_wallace_cla32_fa724_xor1 fa_or0=s_wallace_cla32_fa724_or0
.subckt fa a=s_wallace_cla32_fa724_or0 b=s_wallace_cla32_fa140_xor1 cin=s_wallace_cla32_fa193_xor1 fa_xor1=s_wallace_cla32_fa725_xor1 fa_or0=s_wallace_cla32_fa725_or0
.subckt fa a=s_wallace_cla32_fa725_or0 b=s_wallace_cla32_fa141_xor1 cin=s_wallace_cla32_fa194_xor1 fa_xor1=s_wallace_cla32_fa726_xor1 fa_or0=s_wallace_cla32_fa726_or0
.subckt fa a=s_wallace_cla32_fa726_or0 b=s_wallace_cla32_fa246_xor1 cin=s_wallace_cla32_fa295_xor1 fa_xor1=s_wallace_cla32_fa727_xor1 fa_or0=s_wallace_cla32_fa727_or0
.subckt fa a=s_wallace_cla32_fa727_or0 b=s_wallace_cla32_fa296_xor1 cin=s_wallace_cla32_fa343_xor1 fa_xor1=s_wallace_cla32_fa728_xor1 fa_or0=s_wallace_cla32_fa728_or0
.subckt fa a=s_wallace_cla32_fa728_or0 b=s_wallace_cla32_fa344_xor1 cin=s_wallace_cla32_fa389_xor1 fa_xor1=s_wallace_cla32_fa729_xor1 fa_or0=s_wallace_cla32_fa729_or0
.subckt fa a=s_wallace_cla32_fa729_or0 b=s_wallace_cla32_fa390_xor1 cin=s_wallace_cla32_fa433_xor1 fa_xor1=s_wallace_cla32_fa730_xor1 fa_or0=s_wallace_cla32_fa730_or0
.subckt fa a=s_wallace_cla32_fa730_or0 b=s_wallace_cla32_fa434_xor1 cin=s_wallace_cla32_fa475_xor1 fa_xor1=s_wallace_cla32_fa731_xor1 fa_or0=s_wallace_cla32_fa731_or0
.subckt fa a=s_wallace_cla32_fa731_or0 b=s_wallace_cla32_fa476_xor1 cin=s_wallace_cla32_fa515_xor1 fa_xor1=s_wallace_cla32_fa732_xor1 fa_or0=s_wallace_cla32_fa732_or0
.subckt fa a=s_wallace_cla32_fa732_or0 b=s_wallace_cla32_fa516_xor1 cin=s_wallace_cla32_fa553_xor1 fa_xor1=s_wallace_cla32_fa733_xor1 fa_or0=s_wallace_cla32_fa733_or0
.subckt fa a=s_wallace_cla32_fa733_or0 b=s_wallace_cla32_fa554_xor1 cin=s_wallace_cla32_fa589_xor1 fa_xor1=s_wallace_cla32_fa734_xor1 fa_or0=s_wallace_cla32_fa734_or0
.subckt fa a=s_wallace_cla32_fa734_or0 b=s_wallace_cla32_fa590_xor1 cin=s_wallace_cla32_fa623_xor1 fa_xor1=s_wallace_cla32_fa735_xor1 fa_or0=s_wallace_cla32_fa735_or0
.subckt fa a=s_wallace_cla32_fa735_or0 b=s_wallace_cla32_fa624_xor1 cin=s_wallace_cla32_fa655_xor1 fa_xor1=s_wallace_cla32_fa736_xor1 fa_or0=s_wallace_cla32_fa736_or0
.subckt fa a=s_wallace_cla32_fa736_or0 b=s_wallace_cla32_fa656_xor1 cin=s_wallace_cla32_fa685_xor1 fa_xor1=s_wallace_cla32_fa737_xor1 fa_or0=s_wallace_cla32_fa737_or0
.subckt ha a=s_wallace_cla32_fa662_xor1 b=s_wallace_cla32_fa689_xor1 ha_xor0=s_wallace_cla32_ha18_xor0 ha_and0=s_wallace_cla32_ha18_and0
.subckt fa a=s_wallace_cla32_ha18_and0 b=s_wallace_cla32_fa634_xor1 cin=s_wallace_cla32_fa663_xor1 fa_xor1=s_wallace_cla32_fa738_xor1 fa_or0=s_wallace_cla32_fa738_or0
.subckt fa a=s_wallace_cla32_fa738_or0 b=s_wallace_cla32_fa604_xor1 cin=s_wallace_cla32_fa635_xor1 fa_xor1=s_wallace_cla32_fa739_xor1 fa_or0=s_wallace_cla32_fa739_or0
.subckt fa a=s_wallace_cla32_fa739_or0 b=s_wallace_cla32_fa572_xor1 cin=s_wallace_cla32_fa605_xor1 fa_xor1=s_wallace_cla32_fa740_xor1 fa_or0=s_wallace_cla32_fa740_or0
.subckt fa a=s_wallace_cla32_fa740_or0 b=s_wallace_cla32_fa538_xor1 cin=s_wallace_cla32_fa573_xor1 fa_xor1=s_wallace_cla32_fa741_xor1 fa_or0=s_wallace_cla32_fa741_or0
.subckt fa a=s_wallace_cla32_fa741_or0 b=s_wallace_cla32_fa502_xor1 cin=s_wallace_cla32_fa539_xor1 fa_xor1=s_wallace_cla32_fa742_xor1 fa_or0=s_wallace_cla32_fa742_or0
.subckt fa a=s_wallace_cla32_fa742_or0 b=s_wallace_cla32_fa464_xor1 cin=s_wallace_cla32_fa503_xor1 fa_xor1=s_wallace_cla32_fa743_xor1 fa_or0=s_wallace_cla32_fa743_or0
.subckt fa a=s_wallace_cla32_fa743_or0 b=s_wallace_cla32_fa424_xor1 cin=s_wallace_cla32_fa465_xor1 fa_xor1=s_wallace_cla32_fa744_xor1 fa_or0=s_wallace_cla32_fa744_or0
.subckt fa a=s_wallace_cla32_fa744_or0 b=s_wallace_cla32_fa382_xor1 cin=s_wallace_cla32_fa425_xor1 fa_xor1=s_wallace_cla32_fa745_xor1 fa_or0=s_wallace_cla32_fa745_or0
.subckt fa a=s_wallace_cla32_fa745_or0 b=s_wallace_cla32_fa338_xor1 cin=s_wallace_cla32_fa383_xor1 fa_xor1=s_wallace_cla32_fa746_xor1 fa_or0=s_wallace_cla32_fa746_or0
.subckt fa a=s_wallace_cla32_fa746_or0 b=s_wallace_cla32_fa292_xor1 cin=s_wallace_cla32_fa339_xor1 fa_xor1=s_wallace_cla32_fa747_xor1 fa_or0=s_wallace_cla32_fa747_or0
.subckt fa a=s_wallace_cla32_fa747_or0 b=s_wallace_cla32_fa244_xor1 cin=s_wallace_cla32_fa293_xor1 fa_xor1=s_wallace_cla32_fa748_xor1 fa_or0=s_wallace_cla32_fa748_or0
.subckt fa a=s_wallace_cla32_fa748_or0 b=s_wallace_cla32_fa245_xor1 cin=s_wallace_cla32_fa294_xor1 fa_xor1=s_wallace_cla32_fa749_xor1 fa_or0=s_wallace_cla32_fa749_or0
.subckt fa a=s_wallace_cla32_fa749_or0 b=s_wallace_cla32_fa342_xor1 cin=s_wallace_cla32_fa387_xor1 fa_xor1=s_wallace_cla32_fa750_xor1 fa_or0=s_wallace_cla32_fa750_or0
.subckt fa a=s_wallace_cla32_fa750_or0 b=s_wallace_cla32_fa388_xor1 cin=s_wallace_cla32_fa431_xor1 fa_xor1=s_wallace_cla32_fa751_xor1 fa_or0=s_wallace_cla32_fa751_or0
.subckt fa a=s_wallace_cla32_fa751_or0 b=s_wallace_cla32_fa432_xor1 cin=s_wallace_cla32_fa473_xor1 fa_xor1=s_wallace_cla32_fa752_xor1 fa_or0=s_wallace_cla32_fa752_or0
.subckt fa a=s_wallace_cla32_fa752_or0 b=s_wallace_cla32_fa474_xor1 cin=s_wallace_cla32_fa513_xor1 fa_xor1=s_wallace_cla32_fa753_xor1 fa_or0=s_wallace_cla32_fa753_or0
.subckt fa a=s_wallace_cla32_fa753_or0 b=s_wallace_cla32_fa514_xor1 cin=s_wallace_cla32_fa551_xor1 fa_xor1=s_wallace_cla32_fa754_xor1 fa_or0=s_wallace_cla32_fa754_or0
.subckt fa a=s_wallace_cla32_fa754_or0 b=s_wallace_cla32_fa552_xor1 cin=s_wallace_cla32_fa587_xor1 fa_xor1=s_wallace_cla32_fa755_xor1 fa_or0=s_wallace_cla32_fa755_or0
.subckt fa a=s_wallace_cla32_fa755_or0 b=s_wallace_cla32_fa588_xor1 cin=s_wallace_cla32_fa621_xor1 fa_xor1=s_wallace_cla32_fa756_xor1 fa_or0=s_wallace_cla32_fa756_or0
.subckt fa a=s_wallace_cla32_fa756_or0 b=s_wallace_cla32_fa622_xor1 cin=s_wallace_cla32_fa653_xor1 fa_xor1=s_wallace_cla32_fa757_xor1 fa_or0=s_wallace_cla32_fa757_or0
.subckt fa a=s_wallace_cla32_fa757_or0 b=s_wallace_cla32_fa654_xor1 cin=s_wallace_cla32_fa683_xor1 fa_xor1=s_wallace_cla32_fa758_xor1 fa_or0=s_wallace_cla32_fa758_or0
.subckt fa a=s_wallace_cla32_fa758_or0 b=s_wallace_cla32_fa684_xor1 cin=s_wallace_cla32_fa711_xor1 fa_xor1=s_wallace_cla32_fa759_xor1 fa_or0=s_wallace_cla32_fa759_or0
.subckt ha a=s_wallace_cla32_fa690_xor1 b=s_wallace_cla32_fa715_xor1 ha_xor0=s_wallace_cla32_ha19_xor0 ha_and0=s_wallace_cla32_ha19_and0
.subckt fa a=s_wallace_cla32_ha19_and0 b=s_wallace_cla32_fa664_xor1 cin=s_wallace_cla32_fa691_xor1 fa_xor1=s_wallace_cla32_fa760_xor1 fa_or0=s_wallace_cla32_fa760_or0
.subckt fa a=s_wallace_cla32_fa760_or0 b=s_wallace_cla32_fa636_xor1 cin=s_wallace_cla32_fa665_xor1 fa_xor1=s_wallace_cla32_fa761_xor1 fa_or0=s_wallace_cla32_fa761_or0
.subckt fa a=s_wallace_cla32_fa761_or0 b=s_wallace_cla32_fa606_xor1 cin=s_wallace_cla32_fa637_xor1 fa_xor1=s_wallace_cla32_fa762_xor1 fa_or0=s_wallace_cla32_fa762_or0
.subckt fa a=s_wallace_cla32_fa762_or0 b=s_wallace_cla32_fa574_xor1 cin=s_wallace_cla32_fa607_xor1 fa_xor1=s_wallace_cla32_fa763_xor1 fa_or0=s_wallace_cla32_fa763_or0
.subckt fa a=s_wallace_cla32_fa763_or0 b=s_wallace_cla32_fa540_xor1 cin=s_wallace_cla32_fa575_xor1 fa_xor1=s_wallace_cla32_fa764_xor1 fa_or0=s_wallace_cla32_fa764_or0
.subckt fa a=s_wallace_cla32_fa764_or0 b=s_wallace_cla32_fa504_xor1 cin=s_wallace_cla32_fa541_xor1 fa_xor1=s_wallace_cla32_fa765_xor1 fa_or0=s_wallace_cla32_fa765_or0
.subckt fa a=s_wallace_cla32_fa765_or0 b=s_wallace_cla32_fa466_xor1 cin=s_wallace_cla32_fa505_xor1 fa_xor1=s_wallace_cla32_fa766_xor1 fa_or0=s_wallace_cla32_fa766_or0
.subckt fa a=s_wallace_cla32_fa766_or0 b=s_wallace_cla32_fa426_xor1 cin=s_wallace_cla32_fa467_xor1 fa_xor1=s_wallace_cla32_fa767_xor1 fa_or0=s_wallace_cla32_fa767_or0
.subckt fa a=s_wallace_cla32_fa767_or0 b=s_wallace_cla32_fa384_xor1 cin=s_wallace_cla32_fa427_xor1 fa_xor1=s_wallace_cla32_fa768_xor1 fa_or0=s_wallace_cla32_fa768_or0
.subckt fa a=s_wallace_cla32_fa768_or0 b=s_wallace_cla32_fa340_xor1 cin=s_wallace_cla32_fa385_xor1 fa_xor1=s_wallace_cla32_fa769_xor1 fa_or0=s_wallace_cla32_fa769_or0
.subckt fa a=s_wallace_cla32_fa769_or0 b=s_wallace_cla32_fa341_xor1 cin=s_wallace_cla32_fa386_xor1 fa_xor1=s_wallace_cla32_fa770_xor1 fa_or0=s_wallace_cla32_fa770_or0
.subckt fa a=s_wallace_cla32_fa770_or0 b=s_wallace_cla32_fa430_xor1 cin=s_wallace_cla32_fa471_xor1 fa_xor1=s_wallace_cla32_fa771_xor1 fa_or0=s_wallace_cla32_fa771_or0
.subckt fa a=s_wallace_cla32_fa771_or0 b=s_wallace_cla32_fa472_xor1 cin=s_wallace_cla32_fa511_xor1 fa_xor1=s_wallace_cla32_fa772_xor1 fa_or0=s_wallace_cla32_fa772_or0
.subckt fa a=s_wallace_cla32_fa772_or0 b=s_wallace_cla32_fa512_xor1 cin=s_wallace_cla32_fa549_xor1 fa_xor1=s_wallace_cla32_fa773_xor1 fa_or0=s_wallace_cla32_fa773_or0
.subckt fa a=s_wallace_cla32_fa773_or0 b=s_wallace_cla32_fa550_xor1 cin=s_wallace_cla32_fa585_xor1 fa_xor1=s_wallace_cla32_fa774_xor1 fa_or0=s_wallace_cla32_fa774_or0
.subckt fa a=s_wallace_cla32_fa774_or0 b=s_wallace_cla32_fa586_xor1 cin=s_wallace_cla32_fa619_xor1 fa_xor1=s_wallace_cla32_fa775_xor1 fa_or0=s_wallace_cla32_fa775_or0
.subckt fa a=s_wallace_cla32_fa775_or0 b=s_wallace_cla32_fa620_xor1 cin=s_wallace_cla32_fa651_xor1 fa_xor1=s_wallace_cla32_fa776_xor1 fa_or0=s_wallace_cla32_fa776_or0
.subckt fa a=s_wallace_cla32_fa776_or0 b=s_wallace_cla32_fa652_xor1 cin=s_wallace_cla32_fa681_xor1 fa_xor1=s_wallace_cla32_fa777_xor1 fa_or0=s_wallace_cla32_fa777_or0
.subckt fa a=s_wallace_cla32_fa777_or0 b=s_wallace_cla32_fa682_xor1 cin=s_wallace_cla32_fa709_xor1 fa_xor1=s_wallace_cla32_fa778_xor1 fa_or0=s_wallace_cla32_fa778_or0
.subckt fa a=s_wallace_cla32_fa778_or0 b=s_wallace_cla32_fa710_xor1 cin=s_wallace_cla32_fa735_xor1 fa_xor1=s_wallace_cla32_fa779_xor1 fa_or0=s_wallace_cla32_fa779_or0
.subckt ha a=s_wallace_cla32_fa716_xor1 b=s_wallace_cla32_fa739_xor1 ha_xor0=s_wallace_cla32_ha20_xor0 ha_and0=s_wallace_cla32_ha20_and0
.subckt fa a=s_wallace_cla32_ha20_and0 b=s_wallace_cla32_fa692_xor1 cin=s_wallace_cla32_fa717_xor1 fa_xor1=s_wallace_cla32_fa780_xor1 fa_or0=s_wallace_cla32_fa780_or0
.subckt fa a=s_wallace_cla32_fa780_or0 b=s_wallace_cla32_fa666_xor1 cin=s_wallace_cla32_fa693_xor1 fa_xor1=s_wallace_cla32_fa781_xor1 fa_or0=s_wallace_cla32_fa781_or0
.subckt fa a=s_wallace_cla32_fa781_or0 b=s_wallace_cla32_fa638_xor1 cin=s_wallace_cla32_fa667_xor1 fa_xor1=s_wallace_cla32_fa782_xor1 fa_or0=s_wallace_cla32_fa782_or0
.subckt fa a=s_wallace_cla32_fa782_or0 b=s_wallace_cla32_fa608_xor1 cin=s_wallace_cla32_fa639_xor1 fa_xor1=s_wallace_cla32_fa783_xor1 fa_or0=s_wallace_cla32_fa783_or0
.subckt fa a=s_wallace_cla32_fa783_or0 b=s_wallace_cla32_fa576_xor1 cin=s_wallace_cla32_fa609_xor1 fa_xor1=s_wallace_cla32_fa784_xor1 fa_or0=s_wallace_cla32_fa784_or0
.subckt fa a=s_wallace_cla32_fa784_or0 b=s_wallace_cla32_fa542_xor1 cin=s_wallace_cla32_fa577_xor1 fa_xor1=s_wallace_cla32_fa785_xor1 fa_or0=s_wallace_cla32_fa785_or0
.subckt fa a=s_wallace_cla32_fa785_or0 b=s_wallace_cla32_fa506_xor1 cin=s_wallace_cla32_fa543_xor1 fa_xor1=s_wallace_cla32_fa786_xor1 fa_or0=s_wallace_cla32_fa786_or0
.subckt fa a=s_wallace_cla32_fa786_or0 b=s_wallace_cla32_fa468_xor1 cin=s_wallace_cla32_fa507_xor1 fa_xor1=s_wallace_cla32_fa787_xor1 fa_or0=s_wallace_cla32_fa787_or0
.subckt fa a=s_wallace_cla32_fa787_or0 b=s_wallace_cla32_fa428_xor1 cin=s_wallace_cla32_fa469_xor1 fa_xor1=s_wallace_cla32_fa788_xor1 fa_or0=s_wallace_cla32_fa788_or0
.subckt fa a=s_wallace_cla32_fa788_or0 b=s_wallace_cla32_fa429_xor1 cin=s_wallace_cla32_fa470_xor1 fa_xor1=s_wallace_cla32_fa789_xor1 fa_or0=s_wallace_cla32_fa789_or0
.subckt fa a=s_wallace_cla32_fa789_or0 b=s_wallace_cla32_fa510_xor1 cin=s_wallace_cla32_fa547_xor1 fa_xor1=s_wallace_cla32_fa790_xor1 fa_or0=s_wallace_cla32_fa790_or0
.subckt fa a=s_wallace_cla32_fa790_or0 b=s_wallace_cla32_fa548_xor1 cin=s_wallace_cla32_fa583_xor1 fa_xor1=s_wallace_cla32_fa791_xor1 fa_or0=s_wallace_cla32_fa791_or0
.subckt fa a=s_wallace_cla32_fa791_or0 b=s_wallace_cla32_fa584_xor1 cin=s_wallace_cla32_fa617_xor1 fa_xor1=s_wallace_cla32_fa792_xor1 fa_or0=s_wallace_cla32_fa792_or0
.subckt fa a=s_wallace_cla32_fa792_or0 b=s_wallace_cla32_fa618_xor1 cin=s_wallace_cla32_fa649_xor1 fa_xor1=s_wallace_cla32_fa793_xor1 fa_or0=s_wallace_cla32_fa793_or0
.subckt fa a=s_wallace_cla32_fa793_or0 b=s_wallace_cla32_fa650_xor1 cin=s_wallace_cla32_fa679_xor1 fa_xor1=s_wallace_cla32_fa794_xor1 fa_or0=s_wallace_cla32_fa794_or0
.subckt fa a=s_wallace_cla32_fa794_or0 b=s_wallace_cla32_fa680_xor1 cin=s_wallace_cla32_fa707_xor1 fa_xor1=s_wallace_cla32_fa795_xor1 fa_or0=s_wallace_cla32_fa795_or0
.subckt fa a=s_wallace_cla32_fa795_or0 b=s_wallace_cla32_fa708_xor1 cin=s_wallace_cla32_fa733_xor1 fa_xor1=s_wallace_cla32_fa796_xor1 fa_or0=s_wallace_cla32_fa796_or0
.subckt fa a=s_wallace_cla32_fa796_or0 b=s_wallace_cla32_fa734_xor1 cin=s_wallace_cla32_fa757_xor1 fa_xor1=s_wallace_cla32_fa797_xor1 fa_or0=s_wallace_cla32_fa797_or0
.subckt ha a=s_wallace_cla32_fa740_xor1 b=s_wallace_cla32_fa761_xor1 ha_xor0=s_wallace_cla32_ha21_xor0 ha_and0=s_wallace_cla32_ha21_and0
.subckt fa a=s_wallace_cla32_ha21_and0 b=s_wallace_cla32_fa718_xor1 cin=s_wallace_cla32_fa741_xor1 fa_xor1=s_wallace_cla32_fa798_xor1 fa_or0=s_wallace_cla32_fa798_or0
.subckt fa a=s_wallace_cla32_fa798_or0 b=s_wallace_cla32_fa694_xor1 cin=s_wallace_cla32_fa719_xor1 fa_xor1=s_wallace_cla32_fa799_xor1 fa_or0=s_wallace_cla32_fa799_or0
.subckt fa a=s_wallace_cla32_fa799_or0 b=s_wallace_cla32_fa668_xor1 cin=s_wallace_cla32_fa695_xor1 fa_xor1=s_wallace_cla32_fa800_xor1 fa_or0=s_wallace_cla32_fa800_or0
.subckt fa a=s_wallace_cla32_fa800_or0 b=s_wallace_cla32_fa640_xor1 cin=s_wallace_cla32_fa669_xor1 fa_xor1=s_wallace_cla32_fa801_xor1 fa_or0=s_wallace_cla32_fa801_or0
.subckt fa a=s_wallace_cla32_fa801_or0 b=s_wallace_cla32_fa610_xor1 cin=s_wallace_cla32_fa641_xor1 fa_xor1=s_wallace_cla32_fa802_xor1 fa_or0=s_wallace_cla32_fa802_or0
.subckt fa a=s_wallace_cla32_fa802_or0 b=s_wallace_cla32_fa578_xor1 cin=s_wallace_cla32_fa611_xor1 fa_xor1=s_wallace_cla32_fa803_xor1 fa_or0=s_wallace_cla32_fa803_or0
.subckt fa a=s_wallace_cla32_fa803_or0 b=s_wallace_cla32_fa544_xor1 cin=s_wallace_cla32_fa579_xor1 fa_xor1=s_wallace_cla32_fa804_xor1 fa_or0=s_wallace_cla32_fa804_or0
.subckt fa a=s_wallace_cla32_fa804_or0 b=s_wallace_cla32_fa508_xor1 cin=s_wallace_cla32_fa545_xor1 fa_xor1=s_wallace_cla32_fa805_xor1 fa_or0=s_wallace_cla32_fa805_or0
.subckt fa a=s_wallace_cla32_fa805_or0 b=s_wallace_cla32_fa509_xor1 cin=s_wallace_cla32_fa546_xor1 fa_xor1=s_wallace_cla32_fa806_xor1 fa_or0=s_wallace_cla32_fa806_or0
.subckt fa a=s_wallace_cla32_fa806_or0 b=s_wallace_cla32_fa582_xor1 cin=s_wallace_cla32_fa615_xor1 fa_xor1=s_wallace_cla32_fa807_xor1 fa_or0=s_wallace_cla32_fa807_or0
.subckt fa a=s_wallace_cla32_fa807_or0 b=s_wallace_cla32_fa616_xor1 cin=s_wallace_cla32_fa647_xor1 fa_xor1=s_wallace_cla32_fa808_xor1 fa_or0=s_wallace_cla32_fa808_or0
.subckt fa a=s_wallace_cla32_fa808_or0 b=s_wallace_cla32_fa648_xor1 cin=s_wallace_cla32_fa677_xor1 fa_xor1=s_wallace_cla32_fa809_xor1 fa_or0=s_wallace_cla32_fa809_or0
.subckt fa a=s_wallace_cla32_fa809_or0 b=s_wallace_cla32_fa678_xor1 cin=s_wallace_cla32_fa705_xor1 fa_xor1=s_wallace_cla32_fa810_xor1 fa_or0=s_wallace_cla32_fa810_or0
.subckt fa a=s_wallace_cla32_fa810_or0 b=s_wallace_cla32_fa706_xor1 cin=s_wallace_cla32_fa731_xor1 fa_xor1=s_wallace_cla32_fa811_xor1 fa_or0=s_wallace_cla32_fa811_or0
.subckt fa a=s_wallace_cla32_fa811_or0 b=s_wallace_cla32_fa732_xor1 cin=s_wallace_cla32_fa755_xor1 fa_xor1=s_wallace_cla32_fa812_xor1 fa_or0=s_wallace_cla32_fa812_or0
.subckt fa a=s_wallace_cla32_fa812_or0 b=s_wallace_cla32_fa756_xor1 cin=s_wallace_cla32_fa777_xor1 fa_xor1=s_wallace_cla32_fa813_xor1 fa_or0=s_wallace_cla32_fa813_or0
.subckt ha a=s_wallace_cla32_fa762_xor1 b=s_wallace_cla32_fa781_xor1 ha_xor0=s_wallace_cla32_ha22_xor0 ha_and0=s_wallace_cla32_ha22_and0
.subckt fa a=s_wallace_cla32_ha22_and0 b=s_wallace_cla32_fa742_xor1 cin=s_wallace_cla32_fa763_xor1 fa_xor1=s_wallace_cla32_fa814_xor1 fa_or0=s_wallace_cla32_fa814_or0
.subckt fa a=s_wallace_cla32_fa814_or0 b=s_wallace_cla32_fa720_xor1 cin=s_wallace_cla32_fa743_xor1 fa_xor1=s_wallace_cla32_fa815_xor1 fa_or0=s_wallace_cla32_fa815_or0
.subckt fa a=s_wallace_cla32_fa815_or0 b=s_wallace_cla32_fa696_xor1 cin=s_wallace_cla32_fa721_xor1 fa_xor1=s_wallace_cla32_fa816_xor1 fa_or0=s_wallace_cla32_fa816_or0
.subckt fa a=s_wallace_cla32_fa816_or0 b=s_wallace_cla32_fa670_xor1 cin=s_wallace_cla32_fa697_xor1 fa_xor1=s_wallace_cla32_fa817_xor1 fa_or0=s_wallace_cla32_fa817_or0
.subckt fa a=s_wallace_cla32_fa817_or0 b=s_wallace_cla32_fa642_xor1 cin=s_wallace_cla32_fa671_xor1 fa_xor1=s_wallace_cla32_fa818_xor1 fa_or0=s_wallace_cla32_fa818_or0
.subckt fa a=s_wallace_cla32_fa818_or0 b=s_wallace_cla32_fa612_xor1 cin=s_wallace_cla32_fa643_xor1 fa_xor1=s_wallace_cla32_fa819_xor1 fa_or0=s_wallace_cla32_fa819_or0
.subckt fa a=s_wallace_cla32_fa819_or0 b=s_wallace_cla32_fa580_xor1 cin=s_wallace_cla32_fa613_xor1 fa_xor1=s_wallace_cla32_fa820_xor1 fa_or0=s_wallace_cla32_fa820_or0
.subckt fa a=s_wallace_cla32_fa820_or0 b=s_wallace_cla32_fa581_xor1 cin=s_wallace_cla32_fa614_xor1 fa_xor1=s_wallace_cla32_fa821_xor1 fa_or0=s_wallace_cla32_fa821_or0
.subckt fa a=s_wallace_cla32_fa821_or0 b=s_wallace_cla32_fa646_xor1 cin=s_wallace_cla32_fa675_xor1 fa_xor1=s_wallace_cla32_fa822_xor1 fa_or0=s_wallace_cla32_fa822_or0
.subckt fa a=s_wallace_cla32_fa822_or0 b=s_wallace_cla32_fa676_xor1 cin=s_wallace_cla32_fa703_xor1 fa_xor1=s_wallace_cla32_fa823_xor1 fa_or0=s_wallace_cla32_fa823_or0
.subckt fa a=s_wallace_cla32_fa823_or0 b=s_wallace_cla32_fa704_xor1 cin=s_wallace_cla32_fa729_xor1 fa_xor1=s_wallace_cla32_fa824_xor1 fa_or0=s_wallace_cla32_fa824_or0
.subckt fa a=s_wallace_cla32_fa824_or0 b=s_wallace_cla32_fa730_xor1 cin=s_wallace_cla32_fa753_xor1 fa_xor1=s_wallace_cla32_fa825_xor1 fa_or0=s_wallace_cla32_fa825_or0
.subckt fa a=s_wallace_cla32_fa825_or0 b=s_wallace_cla32_fa754_xor1 cin=s_wallace_cla32_fa775_xor1 fa_xor1=s_wallace_cla32_fa826_xor1 fa_or0=s_wallace_cla32_fa826_or0
.subckt fa a=s_wallace_cla32_fa826_or0 b=s_wallace_cla32_fa776_xor1 cin=s_wallace_cla32_fa795_xor1 fa_xor1=s_wallace_cla32_fa827_xor1 fa_or0=s_wallace_cla32_fa827_or0
.subckt ha a=s_wallace_cla32_fa782_xor1 b=s_wallace_cla32_fa799_xor1 ha_xor0=s_wallace_cla32_ha23_xor0 ha_and0=s_wallace_cla32_ha23_and0
.subckt fa a=s_wallace_cla32_ha23_and0 b=s_wallace_cla32_fa764_xor1 cin=s_wallace_cla32_fa783_xor1 fa_xor1=s_wallace_cla32_fa828_xor1 fa_or0=s_wallace_cla32_fa828_or0
.subckt fa a=s_wallace_cla32_fa828_or0 b=s_wallace_cla32_fa744_xor1 cin=s_wallace_cla32_fa765_xor1 fa_xor1=s_wallace_cla32_fa829_xor1 fa_or0=s_wallace_cla32_fa829_or0
.subckt fa a=s_wallace_cla32_fa829_or0 b=s_wallace_cla32_fa722_xor1 cin=s_wallace_cla32_fa745_xor1 fa_xor1=s_wallace_cla32_fa830_xor1 fa_or0=s_wallace_cla32_fa830_or0
.subckt fa a=s_wallace_cla32_fa830_or0 b=s_wallace_cla32_fa698_xor1 cin=s_wallace_cla32_fa723_xor1 fa_xor1=s_wallace_cla32_fa831_xor1 fa_or0=s_wallace_cla32_fa831_or0
.subckt fa a=s_wallace_cla32_fa831_or0 b=s_wallace_cla32_fa672_xor1 cin=s_wallace_cla32_fa699_xor1 fa_xor1=s_wallace_cla32_fa832_xor1 fa_or0=s_wallace_cla32_fa832_or0
.subckt fa a=s_wallace_cla32_fa832_or0 b=s_wallace_cla32_fa644_xor1 cin=s_wallace_cla32_fa673_xor1 fa_xor1=s_wallace_cla32_fa833_xor1 fa_or0=s_wallace_cla32_fa833_or0
.subckt fa a=s_wallace_cla32_fa833_or0 b=s_wallace_cla32_fa645_xor1 cin=s_wallace_cla32_fa674_xor1 fa_xor1=s_wallace_cla32_fa834_xor1 fa_or0=s_wallace_cla32_fa834_or0
.subckt fa a=s_wallace_cla32_fa834_or0 b=s_wallace_cla32_fa702_xor1 cin=s_wallace_cla32_fa727_xor1 fa_xor1=s_wallace_cla32_fa835_xor1 fa_or0=s_wallace_cla32_fa835_or0
.subckt fa a=s_wallace_cla32_fa835_or0 b=s_wallace_cla32_fa728_xor1 cin=s_wallace_cla32_fa751_xor1 fa_xor1=s_wallace_cla32_fa836_xor1 fa_or0=s_wallace_cla32_fa836_or0
.subckt fa a=s_wallace_cla32_fa836_or0 b=s_wallace_cla32_fa752_xor1 cin=s_wallace_cla32_fa773_xor1 fa_xor1=s_wallace_cla32_fa837_xor1 fa_or0=s_wallace_cla32_fa837_or0
.subckt fa a=s_wallace_cla32_fa837_or0 b=s_wallace_cla32_fa774_xor1 cin=s_wallace_cla32_fa793_xor1 fa_xor1=s_wallace_cla32_fa838_xor1 fa_or0=s_wallace_cla32_fa838_or0
.subckt fa a=s_wallace_cla32_fa838_or0 b=s_wallace_cla32_fa794_xor1 cin=s_wallace_cla32_fa811_xor1 fa_xor1=s_wallace_cla32_fa839_xor1 fa_or0=s_wallace_cla32_fa839_or0
.subckt ha a=s_wallace_cla32_fa800_xor1 b=s_wallace_cla32_fa815_xor1 ha_xor0=s_wallace_cla32_ha24_xor0 ha_and0=s_wallace_cla32_ha24_and0
.subckt fa a=s_wallace_cla32_ha24_and0 b=s_wallace_cla32_fa784_xor1 cin=s_wallace_cla32_fa801_xor1 fa_xor1=s_wallace_cla32_fa840_xor1 fa_or0=s_wallace_cla32_fa840_or0
.subckt fa a=s_wallace_cla32_fa840_or0 b=s_wallace_cla32_fa766_xor1 cin=s_wallace_cla32_fa785_xor1 fa_xor1=s_wallace_cla32_fa841_xor1 fa_or0=s_wallace_cla32_fa841_or0
.subckt fa a=s_wallace_cla32_fa841_or0 b=s_wallace_cla32_fa746_xor1 cin=s_wallace_cla32_fa767_xor1 fa_xor1=s_wallace_cla32_fa842_xor1 fa_or0=s_wallace_cla32_fa842_or0
.subckt fa a=s_wallace_cla32_fa842_or0 b=s_wallace_cla32_fa724_xor1 cin=s_wallace_cla32_fa747_xor1 fa_xor1=s_wallace_cla32_fa843_xor1 fa_or0=s_wallace_cla32_fa843_or0
.subckt fa a=s_wallace_cla32_fa843_or0 b=s_wallace_cla32_fa700_xor1 cin=s_wallace_cla32_fa725_xor1 fa_xor1=s_wallace_cla32_fa844_xor1 fa_or0=s_wallace_cla32_fa844_or0
.subckt fa a=s_wallace_cla32_fa844_or0 b=s_wallace_cla32_fa701_xor1 cin=s_wallace_cla32_fa726_xor1 fa_xor1=s_wallace_cla32_fa845_xor1 fa_or0=s_wallace_cla32_fa845_or0
.subckt fa a=s_wallace_cla32_fa845_or0 b=s_wallace_cla32_fa750_xor1 cin=s_wallace_cla32_fa771_xor1 fa_xor1=s_wallace_cla32_fa846_xor1 fa_or0=s_wallace_cla32_fa846_or0
.subckt fa a=s_wallace_cla32_fa846_or0 b=s_wallace_cla32_fa772_xor1 cin=s_wallace_cla32_fa791_xor1 fa_xor1=s_wallace_cla32_fa847_xor1 fa_or0=s_wallace_cla32_fa847_or0
.subckt fa a=s_wallace_cla32_fa847_or0 b=s_wallace_cla32_fa792_xor1 cin=s_wallace_cla32_fa809_xor1 fa_xor1=s_wallace_cla32_fa848_xor1 fa_or0=s_wallace_cla32_fa848_or0
.subckt fa a=s_wallace_cla32_fa848_or0 b=s_wallace_cla32_fa810_xor1 cin=s_wallace_cla32_fa825_xor1 fa_xor1=s_wallace_cla32_fa849_xor1 fa_or0=s_wallace_cla32_fa849_or0
.subckt ha a=s_wallace_cla32_fa816_xor1 b=s_wallace_cla32_fa829_xor1 ha_xor0=s_wallace_cla32_ha25_xor0 ha_and0=s_wallace_cla32_ha25_and0
.subckt fa a=s_wallace_cla32_ha25_and0 b=s_wallace_cla32_fa802_xor1 cin=s_wallace_cla32_fa817_xor1 fa_xor1=s_wallace_cla32_fa850_xor1 fa_or0=s_wallace_cla32_fa850_or0
.subckt fa a=s_wallace_cla32_fa850_or0 b=s_wallace_cla32_fa786_xor1 cin=s_wallace_cla32_fa803_xor1 fa_xor1=s_wallace_cla32_fa851_xor1 fa_or0=s_wallace_cla32_fa851_or0
.subckt fa a=s_wallace_cla32_fa851_or0 b=s_wallace_cla32_fa768_xor1 cin=s_wallace_cla32_fa787_xor1 fa_xor1=s_wallace_cla32_fa852_xor1 fa_or0=s_wallace_cla32_fa852_or0
.subckt fa a=s_wallace_cla32_fa852_or0 b=s_wallace_cla32_fa748_xor1 cin=s_wallace_cla32_fa769_xor1 fa_xor1=s_wallace_cla32_fa853_xor1 fa_or0=s_wallace_cla32_fa853_or0
.subckt fa a=s_wallace_cla32_fa853_or0 b=s_wallace_cla32_fa749_xor1 cin=s_wallace_cla32_fa770_xor1 fa_xor1=s_wallace_cla32_fa854_xor1 fa_or0=s_wallace_cla32_fa854_or0
.subckt fa a=s_wallace_cla32_fa854_or0 b=s_wallace_cla32_fa790_xor1 cin=s_wallace_cla32_fa807_xor1 fa_xor1=s_wallace_cla32_fa855_xor1 fa_or0=s_wallace_cla32_fa855_or0
.subckt fa a=s_wallace_cla32_fa855_or0 b=s_wallace_cla32_fa808_xor1 cin=s_wallace_cla32_fa823_xor1 fa_xor1=s_wallace_cla32_fa856_xor1 fa_or0=s_wallace_cla32_fa856_or0
.subckt fa a=s_wallace_cla32_fa856_or0 b=s_wallace_cla32_fa824_xor1 cin=s_wallace_cla32_fa837_xor1 fa_xor1=s_wallace_cla32_fa857_xor1 fa_or0=s_wallace_cla32_fa857_or0
.subckt ha a=s_wallace_cla32_fa830_xor1 b=s_wallace_cla32_fa841_xor1 ha_xor0=s_wallace_cla32_ha26_xor0 ha_and0=s_wallace_cla32_ha26_and0
.subckt fa a=s_wallace_cla32_ha26_and0 b=s_wallace_cla32_fa818_xor1 cin=s_wallace_cla32_fa831_xor1 fa_xor1=s_wallace_cla32_fa858_xor1 fa_or0=s_wallace_cla32_fa858_or0
.subckt fa a=s_wallace_cla32_fa858_or0 b=s_wallace_cla32_fa804_xor1 cin=s_wallace_cla32_fa819_xor1 fa_xor1=s_wallace_cla32_fa859_xor1 fa_or0=s_wallace_cla32_fa859_or0
.subckt fa a=s_wallace_cla32_fa859_or0 b=s_wallace_cla32_fa788_xor1 cin=s_wallace_cla32_fa805_xor1 fa_xor1=s_wallace_cla32_fa860_xor1 fa_or0=s_wallace_cla32_fa860_or0
.subckt fa a=s_wallace_cla32_fa860_or0 b=s_wallace_cla32_fa789_xor1 cin=s_wallace_cla32_fa806_xor1 fa_xor1=s_wallace_cla32_fa861_xor1 fa_or0=s_wallace_cla32_fa861_or0
.subckt fa a=s_wallace_cla32_fa861_or0 b=s_wallace_cla32_fa822_xor1 cin=s_wallace_cla32_fa835_xor1 fa_xor1=s_wallace_cla32_fa862_xor1 fa_or0=s_wallace_cla32_fa862_or0
.subckt fa a=s_wallace_cla32_fa862_or0 b=s_wallace_cla32_fa836_xor1 cin=s_wallace_cla32_fa847_xor1 fa_xor1=s_wallace_cla32_fa863_xor1 fa_or0=s_wallace_cla32_fa863_or0
.subckt ha a=s_wallace_cla32_fa842_xor1 b=s_wallace_cla32_fa851_xor1 ha_xor0=s_wallace_cla32_ha27_xor0 ha_and0=s_wallace_cla32_ha27_and0
.subckt fa a=s_wallace_cla32_ha27_and0 b=s_wallace_cla32_fa832_xor1 cin=s_wallace_cla32_fa843_xor1 fa_xor1=s_wallace_cla32_fa864_xor1 fa_or0=s_wallace_cla32_fa864_or0
.subckt fa a=s_wallace_cla32_fa864_or0 b=s_wallace_cla32_fa820_xor1 cin=s_wallace_cla32_fa833_xor1 fa_xor1=s_wallace_cla32_fa865_xor1 fa_or0=s_wallace_cla32_fa865_or0
.subckt fa a=s_wallace_cla32_fa865_or0 b=s_wallace_cla32_fa821_xor1 cin=s_wallace_cla32_fa834_xor1 fa_xor1=s_wallace_cla32_fa866_xor1 fa_or0=s_wallace_cla32_fa866_or0
.subckt fa a=s_wallace_cla32_fa866_or0 b=s_wallace_cla32_fa846_xor1 cin=s_wallace_cla32_fa855_xor1 fa_xor1=s_wallace_cla32_fa867_xor1 fa_or0=s_wallace_cla32_fa867_or0
.subckt ha a=s_wallace_cla32_fa852_xor1 b=s_wallace_cla32_fa859_xor1 ha_xor0=s_wallace_cla32_ha28_xor0 ha_and0=s_wallace_cla32_ha28_and0
.subckt fa a=s_wallace_cla32_ha28_and0 b=s_wallace_cla32_fa844_xor1 cin=s_wallace_cla32_fa853_xor1 fa_xor1=s_wallace_cla32_fa868_xor1 fa_or0=s_wallace_cla32_fa868_or0
.subckt fa a=s_wallace_cla32_fa868_or0 b=s_wallace_cla32_fa845_xor1 cin=s_wallace_cla32_fa854_xor1 fa_xor1=s_wallace_cla32_fa869_xor1 fa_or0=s_wallace_cla32_fa869_or0
.subckt ha a=s_wallace_cla32_fa860_xor1 b=s_wallace_cla32_fa865_xor1 ha_xor0=s_wallace_cla32_ha29_xor0 ha_and0=s_wallace_cla32_ha29_and0
.subckt fa a=s_wallace_cla32_ha29_and0 b=s_wallace_cla32_fa861_xor1 cin=s_wallace_cla32_fa866_xor1 fa_xor1=s_wallace_cla32_fa870_xor1 fa_or0=s_wallace_cla32_fa870_or0
.subckt fa a=s_wallace_cla32_fa870_or0 b=s_wallace_cla32_fa869_or0 cin=s_wallace_cla32_fa862_xor1 fa_xor1=s_wallace_cla32_fa871_xor1 fa_or0=s_wallace_cla32_fa871_or0
.subckt fa a=s_wallace_cla32_fa871_or0 b=s_wallace_cla32_fa867_or0 cin=s_wallace_cla32_fa856_xor1 fa_xor1=s_wallace_cla32_fa872_xor1 fa_or0=s_wallace_cla32_fa872_or0
.subckt fa a=s_wallace_cla32_fa872_or0 b=s_wallace_cla32_fa863_or0 cin=s_wallace_cla32_fa848_xor1 fa_xor1=s_wallace_cla32_fa873_xor1 fa_or0=s_wallace_cla32_fa873_or0
.subckt fa a=s_wallace_cla32_fa873_or0 b=s_wallace_cla32_fa857_or0 cin=s_wallace_cla32_fa838_xor1 fa_xor1=s_wallace_cla32_fa874_xor1 fa_or0=s_wallace_cla32_fa874_or0
.subckt fa a=s_wallace_cla32_fa874_or0 b=s_wallace_cla32_fa849_or0 cin=s_wallace_cla32_fa826_xor1 fa_xor1=s_wallace_cla32_fa875_xor1 fa_or0=s_wallace_cla32_fa875_or0
.subckt fa a=s_wallace_cla32_fa875_or0 b=s_wallace_cla32_fa839_or0 cin=s_wallace_cla32_fa812_xor1 fa_xor1=s_wallace_cla32_fa876_xor1 fa_or0=s_wallace_cla32_fa876_or0
.subckt fa a=s_wallace_cla32_fa876_or0 b=s_wallace_cla32_fa827_or0 cin=s_wallace_cla32_fa796_xor1 fa_xor1=s_wallace_cla32_fa877_xor1 fa_or0=s_wallace_cla32_fa877_or0
.subckt fa a=s_wallace_cla32_fa877_or0 b=s_wallace_cla32_fa813_or0 cin=s_wallace_cla32_fa778_xor1 fa_xor1=s_wallace_cla32_fa878_xor1 fa_or0=s_wallace_cla32_fa878_or0
.subckt fa a=s_wallace_cla32_fa878_or0 b=s_wallace_cla32_fa797_or0 cin=s_wallace_cla32_fa758_xor1 fa_xor1=s_wallace_cla32_fa879_xor1 fa_or0=s_wallace_cla32_fa879_or0
.subckt fa a=s_wallace_cla32_fa879_or0 b=s_wallace_cla32_fa779_or0 cin=s_wallace_cla32_fa736_xor1 fa_xor1=s_wallace_cla32_fa880_xor1 fa_or0=s_wallace_cla32_fa880_or0
.subckt fa a=s_wallace_cla32_fa880_or0 b=s_wallace_cla32_fa759_or0 cin=s_wallace_cla32_fa712_xor1 fa_xor1=s_wallace_cla32_fa881_xor1 fa_or0=s_wallace_cla32_fa881_or0
.subckt fa a=s_wallace_cla32_fa881_or0 b=s_wallace_cla32_fa737_or0 cin=s_wallace_cla32_fa686_xor1 fa_xor1=s_wallace_cla32_fa882_xor1 fa_or0=s_wallace_cla32_fa882_or0
.subckt fa a=s_wallace_cla32_fa882_or0 b=s_wallace_cla32_fa713_or0 cin=s_wallace_cla32_fa658_xor1 fa_xor1=s_wallace_cla32_fa883_xor1 fa_or0=s_wallace_cla32_fa883_or0
.subckt fa a=s_wallace_cla32_fa883_or0 b=s_wallace_cla32_fa687_or0 cin=s_wallace_cla32_fa628_xor1 fa_xor1=s_wallace_cla32_fa884_xor1 fa_or0=s_wallace_cla32_fa884_or0
.subckt fa a=s_wallace_cla32_fa884_or0 b=s_wallace_cla32_fa659_or0 cin=s_wallace_cla32_fa596_xor1 fa_xor1=s_wallace_cla32_fa885_xor1 fa_or0=s_wallace_cla32_fa885_or0
.subckt fa a=s_wallace_cla32_fa885_or0 b=s_wallace_cla32_fa629_or0 cin=s_wallace_cla32_fa562_xor1 fa_xor1=s_wallace_cla32_fa886_xor1 fa_or0=s_wallace_cla32_fa886_or0
.subckt fa a=s_wallace_cla32_fa886_or0 b=s_wallace_cla32_fa597_or0 cin=s_wallace_cla32_fa526_xor1 fa_xor1=s_wallace_cla32_fa887_xor1 fa_or0=s_wallace_cla32_fa887_or0
.subckt fa a=s_wallace_cla32_fa887_or0 b=s_wallace_cla32_fa563_or0 cin=s_wallace_cla32_fa488_xor1 fa_xor1=s_wallace_cla32_fa888_xor1 fa_or0=s_wallace_cla32_fa888_or0
.subckt fa a=s_wallace_cla32_fa888_or0 b=s_wallace_cla32_fa527_or0 cin=s_wallace_cla32_fa448_xor1 fa_xor1=s_wallace_cla32_fa889_xor1 fa_or0=s_wallace_cla32_fa889_or0
.subckt fa a=s_wallace_cla32_fa889_or0 b=s_wallace_cla32_fa489_or0 cin=s_wallace_cla32_fa406_xor1 fa_xor1=s_wallace_cla32_fa890_xor1 fa_or0=s_wallace_cla32_fa890_or0
.subckt fa a=s_wallace_cla32_fa890_or0 b=s_wallace_cla32_fa449_or0 cin=s_wallace_cla32_fa362_xor1 fa_xor1=s_wallace_cla32_fa891_xor1 fa_or0=s_wallace_cla32_fa891_or0
.subckt fa a=s_wallace_cla32_fa891_or0 b=s_wallace_cla32_fa407_or0 cin=s_wallace_cla32_fa316_xor1 fa_xor1=s_wallace_cla32_fa892_xor1 fa_or0=s_wallace_cla32_fa892_or0
.subckt fa a=s_wallace_cla32_fa892_or0 b=s_wallace_cla32_fa363_or0 cin=s_wallace_cla32_fa268_xor1 fa_xor1=s_wallace_cla32_fa893_xor1 fa_or0=s_wallace_cla32_fa893_or0
.subckt fa a=s_wallace_cla32_fa893_or0 b=s_wallace_cla32_fa317_or0 cin=s_wallace_cla32_fa218_xor1 fa_xor1=s_wallace_cla32_fa894_xor1 fa_or0=s_wallace_cla32_fa894_or0
.subckt fa a=s_wallace_cla32_fa894_or0 b=s_wallace_cla32_fa269_or0 cin=s_wallace_cla32_fa166_xor1 fa_xor1=s_wallace_cla32_fa895_xor1 fa_or0=s_wallace_cla32_fa895_or0
.subckt fa a=s_wallace_cla32_fa895_or0 b=s_wallace_cla32_fa219_or0 cin=s_wallace_cla32_fa112_xor1 fa_xor1=s_wallace_cla32_fa896_xor1 fa_or0=s_wallace_cla32_fa896_or0
.subckt fa a=s_wallace_cla32_fa896_or0 b=s_wallace_cla32_fa167_or0 cin=s_wallace_cla32_fa56_xor1 fa_xor1=s_wallace_cla32_fa897_xor1 fa_or0=s_wallace_cla32_fa897_or0
.subckt nand_gate a=a[29] b=b[31] out=s_wallace_cla32_nand_29_31
.subckt fa a=s_wallace_cla32_fa897_or0 b=s_wallace_cla32_fa113_or0 cin=s_wallace_cla32_nand_29_31 fa_xor1=s_wallace_cla32_fa898_xor1 fa_or0=s_wallace_cla32_fa898_or0
.subckt nand_gate a=a[31] b=b[30] out=s_wallace_cla32_nand_31_30
.subckt fa a=s_wallace_cla32_fa898_or0 b=s_wallace_cla32_fa57_or0 cin=s_wallace_cla32_nand_31_30 fa_xor1=s_wallace_cla32_fa899_xor1 fa_or0=s_wallace_cla32_fa899_or0
.subckt and_gate a=a[0] b=b[0] out=s_wallace_cla32_and_0_0
.subckt and_gate a=a[1] b=b[0] out=s_wallace_cla32_and_1_0
.subckt and_gate a=a[0] b=b[2] out=s_wallace_cla32_and_0_2
.subckt nand_gate a=a[30] b=b[31] out=s_wallace_cla32_nand_30_31
.subckt and_gate a=a[0] b=b[1] out=s_wallace_cla32_and_0_1
.subckt and_gate a=a[31] b=b[31] out=s_wallace_cla32_and_31_31
.names s_wallace_cla32_and_1_0 s_wallace_cla32_u_cla62_a[0]
1 1
.names s_wallace_cla32_and_0_2 s_wallace_cla32_u_cla62_a[1]
1 1
.names s_wallace_cla32_fa0_xor1 s_wallace_cla32_u_cla62_a[2]
1 1
.names s_wallace_cla32_fa58_xor1 s_wallace_cla32_u_cla62_a[3]
1 1
.names s_wallace_cla32_fa114_xor1 s_wallace_cla32_u_cla62_a[4]
1 1
.names s_wallace_cla32_fa168_xor1 s_wallace_cla32_u_cla62_a[5]
1 1
.names s_wallace_cla32_fa220_xor1 s_wallace_cla32_u_cla62_a[6]
1 1
.names s_wallace_cla32_fa270_xor1 s_wallace_cla32_u_cla62_a[7]
1 1
.names s_wallace_cla32_fa318_xor1 s_wallace_cla32_u_cla62_a[8]
1 1
.names s_wallace_cla32_fa364_xor1 s_wallace_cla32_u_cla62_a[9]
1 1
.names s_wallace_cla32_fa408_xor1 s_wallace_cla32_u_cla62_a[10]
1 1
.names s_wallace_cla32_fa450_xor1 s_wallace_cla32_u_cla62_a[11]
1 1
.names s_wallace_cla32_fa490_xor1 s_wallace_cla32_u_cla62_a[12]
1 1
.names s_wallace_cla32_fa528_xor1 s_wallace_cla32_u_cla62_a[13]
1 1
.names s_wallace_cla32_fa564_xor1 s_wallace_cla32_u_cla62_a[14]
1 1
.names s_wallace_cla32_fa598_xor1 s_wallace_cla32_u_cla62_a[15]
1 1
.names s_wallace_cla32_fa630_xor1 s_wallace_cla32_u_cla62_a[16]
1 1
.names s_wallace_cla32_fa660_xor1 s_wallace_cla32_u_cla62_a[17]
1 1
.names s_wallace_cla32_fa688_xor1 s_wallace_cla32_u_cla62_a[18]
1 1
.names s_wallace_cla32_fa714_xor1 s_wallace_cla32_u_cla62_a[19]
1 1
.names s_wallace_cla32_fa738_xor1 s_wallace_cla32_u_cla62_a[20]
1 1
.names s_wallace_cla32_fa760_xor1 s_wallace_cla32_u_cla62_a[21]
1 1
.names s_wallace_cla32_fa780_xor1 s_wallace_cla32_u_cla62_a[22]
1 1
.names s_wallace_cla32_fa798_xor1 s_wallace_cla32_u_cla62_a[23]
1 1
.names s_wallace_cla32_fa814_xor1 s_wallace_cla32_u_cla62_a[24]
1 1
.names s_wallace_cla32_fa828_xor1 s_wallace_cla32_u_cla62_a[25]
1 1
.names s_wallace_cla32_fa840_xor1 s_wallace_cla32_u_cla62_a[26]
1 1
.names s_wallace_cla32_fa850_xor1 s_wallace_cla32_u_cla62_a[27]
1 1
.names s_wallace_cla32_fa858_xor1 s_wallace_cla32_u_cla62_a[28]
1 1
.names s_wallace_cla32_fa864_xor1 s_wallace_cla32_u_cla62_a[29]
1 1
.names s_wallace_cla32_fa868_xor1 s_wallace_cla32_u_cla62_a[30]
1 1
.names s_wallace_cla32_fa869_xor1 s_wallace_cla32_u_cla62_a[31]
1 1
.names s_wallace_cla32_fa867_xor1 s_wallace_cla32_u_cla62_a[32]
1 1
.names s_wallace_cla32_fa863_xor1 s_wallace_cla32_u_cla62_a[33]
1 1
.names s_wallace_cla32_fa857_xor1 s_wallace_cla32_u_cla62_a[34]
1 1
.names s_wallace_cla32_fa849_xor1 s_wallace_cla32_u_cla62_a[35]
1 1
.names s_wallace_cla32_fa839_xor1 s_wallace_cla32_u_cla62_a[36]
1 1
.names s_wallace_cla32_fa827_xor1 s_wallace_cla32_u_cla62_a[37]
1 1
.names s_wallace_cla32_fa813_xor1 s_wallace_cla32_u_cla62_a[38]
1 1
.names s_wallace_cla32_fa797_xor1 s_wallace_cla32_u_cla62_a[39]
1 1
.names s_wallace_cla32_fa779_xor1 s_wallace_cla32_u_cla62_a[40]
1 1
.names s_wallace_cla32_fa759_xor1 s_wallace_cla32_u_cla62_a[41]
1 1
.names s_wallace_cla32_fa737_xor1 s_wallace_cla32_u_cla62_a[42]
1 1
.names s_wallace_cla32_fa713_xor1 s_wallace_cla32_u_cla62_a[43]
1 1
.names s_wallace_cla32_fa687_xor1 s_wallace_cla32_u_cla62_a[44]
1 1
.names s_wallace_cla32_fa659_xor1 s_wallace_cla32_u_cla62_a[45]
1 1
.names s_wallace_cla32_fa629_xor1 s_wallace_cla32_u_cla62_a[46]
1 1
.names s_wallace_cla32_fa597_xor1 s_wallace_cla32_u_cla62_a[47]
1 1
.names s_wallace_cla32_fa563_xor1 s_wallace_cla32_u_cla62_a[48]
1 1
.names s_wallace_cla32_fa527_xor1 s_wallace_cla32_u_cla62_a[49]
1 1
.names s_wallace_cla32_fa489_xor1 s_wallace_cla32_u_cla62_a[50]
1 1
.names s_wallace_cla32_fa449_xor1 s_wallace_cla32_u_cla62_a[51]
1 1
.names s_wallace_cla32_fa407_xor1 s_wallace_cla32_u_cla62_a[52]
1 1
.names s_wallace_cla32_fa363_xor1 s_wallace_cla32_u_cla62_a[53]
1 1
.names s_wallace_cla32_fa317_xor1 s_wallace_cla32_u_cla62_a[54]
1 1
.names s_wallace_cla32_fa269_xor1 s_wallace_cla32_u_cla62_a[55]
1 1
.names s_wallace_cla32_fa219_xor1 s_wallace_cla32_u_cla62_a[56]
1 1
.names s_wallace_cla32_fa167_xor1 s_wallace_cla32_u_cla62_a[57]
1 1
.names s_wallace_cla32_fa113_xor1 s_wallace_cla32_u_cla62_a[58]
1 1
.names s_wallace_cla32_fa57_xor1 s_wallace_cla32_u_cla62_a[59]
1 1
.names s_wallace_cla32_nand_30_31 s_wallace_cla32_u_cla62_a[60]
1 1
.names s_wallace_cla32_fa899_or0 s_wallace_cla32_u_cla62_a[61]
1 1
.names s_wallace_cla32_and_0_1 s_wallace_cla32_u_cla62_b[0]
1 1
.names s_wallace_cla32_ha0_xor0 s_wallace_cla32_u_cla62_b[1]
1 1
.names s_wallace_cla32_ha1_xor0 s_wallace_cla32_u_cla62_b[2]
1 1
.names s_wallace_cla32_ha2_xor0 s_wallace_cla32_u_cla62_b[3]
1 1
.names s_wallace_cla32_ha3_xor0 s_wallace_cla32_u_cla62_b[4]
1 1
.names s_wallace_cla32_ha4_xor0 s_wallace_cla32_u_cla62_b[5]
1 1
.names s_wallace_cla32_ha5_xor0 s_wallace_cla32_u_cla62_b[6]
1 1
.names s_wallace_cla32_ha6_xor0 s_wallace_cla32_u_cla62_b[7]
1 1
.names s_wallace_cla32_ha7_xor0 s_wallace_cla32_u_cla62_b[8]
1 1
.names s_wallace_cla32_ha8_xor0 s_wallace_cla32_u_cla62_b[9]
1 1
.names s_wallace_cla32_ha9_xor0 s_wallace_cla32_u_cla62_b[10]
1 1
.names s_wallace_cla32_ha10_xor0 s_wallace_cla32_u_cla62_b[11]
1 1
.names s_wallace_cla32_ha11_xor0 s_wallace_cla32_u_cla62_b[12]
1 1
.names s_wallace_cla32_ha12_xor0 s_wallace_cla32_u_cla62_b[13]
1 1
.names s_wallace_cla32_ha13_xor0 s_wallace_cla32_u_cla62_b[14]
1 1
.names s_wallace_cla32_ha14_xor0 s_wallace_cla32_u_cla62_b[15]
1 1
.names s_wallace_cla32_ha15_xor0 s_wallace_cla32_u_cla62_b[16]
1 1
.names s_wallace_cla32_ha16_xor0 s_wallace_cla32_u_cla62_b[17]
1 1
.names s_wallace_cla32_ha17_xor0 s_wallace_cla32_u_cla62_b[18]
1 1
.names s_wallace_cla32_ha18_xor0 s_wallace_cla32_u_cla62_b[19]
1 1
.names s_wallace_cla32_ha19_xor0 s_wallace_cla32_u_cla62_b[20]
1 1
.names s_wallace_cla32_ha20_xor0 s_wallace_cla32_u_cla62_b[21]
1 1
.names s_wallace_cla32_ha21_xor0 s_wallace_cla32_u_cla62_b[22]
1 1
.names s_wallace_cla32_ha22_xor0 s_wallace_cla32_u_cla62_b[23]
1 1
.names s_wallace_cla32_ha23_xor0 s_wallace_cla32_u_cla62_b[24]
1 1
.names s_wallace_cla32_ha24_xor0 s_wallace_cla32_u_cla62_b[25]
1 1
.names s_wallace_cla32_ha25_xor0 s_wallace_cla32_u_cla62_b[26]
1 1
.names s_wallace_cla32_ha26_xor0 s_wallace_cla32_u_cla62_b[27]
1 1
.names s_wallace_cla32_ha27_xor0 s_wallace_cla32_u_cla62_b[28]
1 1
.names s_wallace_cla32_ha28_xor0 s_wallace_cla32_u_cla62_b[29]
1 1
.names s_wallace_cla32_ha29_xor0 s_wallace_cla32_u_cla62_b[30]
1 1
.names s_wallace_cla32_fa870_xor1 s_wallace_cla32_u_cla62_b[31]
1 1
.names s_wallace_cla32_fa871_xor1 s_wallace_cla32_u_cla62_b[32]
1 1
.names s_wallace_cla32_fa872_xor1 s_wallace_cla32_u_cla62_b[33]
1 1
.names s_wallace_cla32_fa873_xor1 s_wallace_cla32_u_cla62_b[34]
1 1
.names s_wallace_cla32_fa874_xor1 s_wallace_cla32_u_cla62_b[35]
1 1
.names s_wallace_cla32_fa875_xor1 s_wallace_cla32_u_cla62_b[36]
1 1
.names s_wallace_cla32_fa876_xor1 s_wallace_cla32_u_cla62_b[37]
1 1
.names s_wallace_cla32_fa877_xor1 s_wallace_cla32_u_cla62_b[38]
1 1
.names s_wallace_cla32_fa878_xor1 s_wallace_cla32_u_cla62_b[39]
1 1
.names s_wallace_cla32_fa879_xor1 s_wallace_cla32_u_cla62_b[40]
1 1
.names s_wallace_cla32_fa880_xor1 s_wallace_cla32_u_cla62_b[41]
1 1
.names s_wallace_cla32_fa881_xor1 s_wallace_cla32_u_cla62_b[42]
1 1
.names s_wallace_cla32_fa882_xor1 s_wallace_cla32_u_cla62_b[43]
1 1
.names s_wallace_cla32_fa883_xor1 s_wallace_cla32_u_cla62_b[44]
1 1
.names s_wallace_cla32_fa884_xor1 s_wallace_cla32_u_cla62_b[45]
1 1
.names s_wallace_cla32_fa885_xor1 s_wallace_cla32_u_cla62_b[46]
1 1
.names s_wallace_cla32_fa886_xor1 s_wallace_cla32_u_cla62_b[47]
1 1
.names s_wallace_cla32_fa887_xor1 s_wallace_cla32_u_cla62_b[48]
1 1
.names s_wallace_cla32_fa888_xor1 s_wallace_cla32_u_cla62_b[49]
1 1
.names s_wallace_cla32_fa889_xor1 s_wallace_cla32_u_cla62_b[50]
1 1
.names s_wallace_cla32_fa890_xor1 s_wallace_cla32_u_cla62_b[51]
1 1
.names s_wallace_cla32_fa891_xor1 s_wallace_cla32_u_cla62_b[52]
1 1
.names s_wallace_cla32_fa892_xor1 s_wallace_cla32_u_cla62_b[53]
1 1
.names s_wallace_cla32_fa893_xor1 s_wallace_cla32_u_cla62_b[54]
1 1
.names s_wallace_cla32_fa894_xor1 s_wallace_cla32_u_cla62_b[55]
1 1
.names s_wallace_cla32_fa895_xor1 s_wallace_cla32_u_cla62_b[56]
1 1
.names s_wallace_cla32_fa896_xor1 s_wallace_cla32_u_cla62_b[57]
1 1
.names s_wallace_cla32_fa897_xor1 s_wallace_cla32_u_cla62_b[58]
1 1
.names s_wallace_cla32_fa898_xor1 s_wallace_cla32_u_cla62_b[59]
1 1
.names s_wallace_cla32_fa899_xor1 s_wallace_cla32_u_cla62_b[60]
1 1
.names s_wallace_cla32_and_31_31 s_wallace_cla32_u_cla62_b[61]
1 1
.subckt u_cla62 a[0]=s_wallace_cla32_u_cla62_a[0] a[1]=s_wallace_cla32_u_cla62_a[1] a[2]=s_wallace_cla32_u_cla62_a[2] a[3]=s_wallace_cla32_u_cla62_a[3] a[4]=s_wallace_cla32_u_cla62_a[4] a[5]=s_wallace_cla32_u_cla62_a[5] a[6]=s_wallace_cla32_u_cla62_a[6] a[7]=s_wallace_cla32_u_cla62_a[7] a[8]=s_wallace_cla32_u_cla62_a[8] a[9]=s_wallace_cla32_u_cla62_a[9] a[10]=s_wallace_cla32_u_cla62_a[10] a[11]=s_wallace_cla32_u_cla62_a[11] a[12]=s_wallace_cla32_u_cla62_a[12] a[13]=s_wallace_cla32_u_cla62_a[13] a[14]=s_wallace_cla32_u_cla62_a[14] a[15]=s_wallace_cla32_u_cla62_a[15] a[16]=s_wallace_cla32_u_cla62_a[16] a[17]=s_wallace_cla32_u_cla62_a[17] a[18]=s_wallace_cla32_u_cla62_a[18] a[19]=s_wallace_cla32_u_cla62_a[19] a[20]=s_wallace_cla32_u_cla62_a[20] a[21]=s_wallace_cla32_u_cla62_a[21] a[22]=s_wallace_cla32_u_cla62_a[22] a[23]=s_wallace_cla32_u_cla62_a[23] a[24]=s_wallace_cla32_u_cla62_a[24] a[25]=s_wallace_cla32_u_cla62_a[25] a[26]=s_wallace_cla32_u_cla62_a[26] a[27]=s_wallace_cla32_u_cla62_a[27] a[28]=s_wallace_cla32_u_cla62_a[28] a[29]=s_wallace_cla32_u_cla62_a[29] a[30]=s_wallace_cla32_u_cla62_a[30] a[31]=s_wallace_cla32_u_cla62_a[31] a[32]=s_wallace_cla32_u_cla62_a[32] a[33]=s_wallace_cla32_u_cla62_a[33] a[34]=s_wallace_cla32_u_cla62_a[34] a[35]=s_wallace_cla32_u_cla62_a[35] a[36]=s_wallace_cla32_u_cla62_a[36] a[37]=s_wallace_cla32_u_cla62_a[37] a[38]=s_wallace_cla32_u_cla62_a[38] a[39]=s_wallace_cla32_u_cla62_a[39] a[40]=s_wallace_cla32_u_cla62_a[40] a[41]=s_wallace_cla32_u_cla62_a[41] a[42]=s_wallace_cla32_u_cla62_a[42] a[43]=s_wallace_cla32_u_cla62_a[43] a[44]=s_wallace_cla32_u_cla62_a[44] a[45]=s_wallace_cla32_u_cla62_a[45] a[46]=s_wallace_cla32_u_cla62_a[46] a[47]=s_wallace_cla32_u_cla62_a[47] a[48]=s_wallace_cla32_u_cla62_a[48] a[49]=s_wallace_cla32_u_cla62_a[49] a[50]=s_wallace_cla32_u_cla62_a[50] a[51]=s_wallace_cla32_u_cla62_a[51] a[52]=s_wallace_cla32_u_cla62_a[52] a[53]=s_wallace_cla32_u_cla62_a[53] a[54]=s_wallace_cla32_u_cla62_a[54] a[55]=s_wallace_cla32_u_cla62_a[55] a[56]=s_wallace_cla32_u_cla62_a[56] a[57]=s_wallace_cla32_u_cla62_a[57] a[58]=s_wallace_cla32_u_cla62_a[58] a[59]=s_wallace_cla32_u_cla62_a[59] a[60]=s_wallace_cla32_u_cla62_a[60] a[61]=s_wallace_cla32_u_cla62_a[61] b[0]=s_wallace_cla32_u_cla62_b[0] b[1]=s_wallace_cla32_u_cla62_b[1] b[2]=s_wallace_cla32_u_cla62_b[2] b[3]=s_wallace_cla32_u_cla62_b[3] b[4]=s_wallace_cla32_u_cla62_b[4] b[5]=s_wallace_cla32_u_cla62_b[5] b[6]=s_wallace_cla32_u_cla62_b[6] b[7]=s_wallace_cla32_u_cla62_b[7] b[8]=s_wallace_cla32_u_cla62_b[8] b[9]=s_wallace_cla32_u_cla62_b[9] b[10]=s_wallace_cla32_u_cla62_b[10] b[11]=s_wallace_cla32_u_cla62_b[11] b[12]=s_wallace_cla32_u_cla62_b[12] b[13]=s_wallace_cla32_u_cla62_b[13] b[14]=s_wallace_cla32_u_cla62_b[14] b[15]=s_wallace_cla32_u_cla62_b[15] b[16]=s_wallace_cla32_u_cla62_b[16] b[17]=s_wallace_cla32_u_cla62_b[17] b[18]=s_wallace_cla32_u_cla62_b[18] b[19]=s_wallace_cla32_u_cla62_b[19] b[20]=s_wallace_cla32_u_cla62_b[20] b[21]=s_wallace_cla32_u_cla62_b[21] b[22]=s_wallace_cla32_u_cla62_b[22] b[23]=s_wallace_cla32_u_cla62_b[23] b[24]=s_wallace_cla32_u_cla62_b[24] b[25]=s_wallace_cla32_u_cla62_b[25] b[26]=s_wallace_cla32_u_cla62_b[26] b[27]=s_wallace_cla32_u_cla62_b[27] b[28]=s_wallace_cla32_u_cla62_b[28] b[29]=s_wallace_cla32_u_cla62_b[29] b[30]=s_wallace_cla32_u_cla62_b[30] b[31]=s_wallace_cla32_u_cla62_b[31] b[32]=s_wallace_cla32_u_cla62_b[32] b[33]=s_wallace_cla32_u_cla62_b[33] b[34]=s_wallace_cla32_u_cla62_b[34] b[35]=s_wallace_cla32_u_cla62_b[35] b[36]=s_wallace_cla32_u_cla62_b[36] b[37]=s_wallace_cla32_u_cla62_b[37] b[38]=s_wallace_cla32_u_cla62_b[38] b[39]=s_wallace_cla32_u_cla62_b[39] b[40]=s_wallace_cla32_u_cla62_b[40] b[41]=s_wallace_cla32_u_cla62_b[41] b[42]=s_wallace_cla32_u_cla62_b[42] b[43]=s_wallace_cla32_u_cla62_b[43] b[44]=s_wallace_cla32_u_cla62_b[44] b[45]=s_wallace_cla32_u_cla62_b[45] b[46]=s_wallace_cla32_u_cla62_b[46] b[47]=s_wallace_cla32_u_cla62_b[47] b[48]=s_wallace_cla32_u_cla62_b[48] b[49]=s_wallace_cla32_u_cla62_b[49] b[50]=s_wallace_cla32_u_cla62_b[50] b[51]=s_wallace_cla32_u_cla62_b[51] b[52]=s_wallace_cla32_u_cla62_b[52] b[53]=s_wallace_cla32_u_cla62_b[53] b[54]=s_wallace_cla32_u_cla62_b[54] b[55]=s_wallace_cla32_u_cla62_b[55] b[56]=s_wallace_cla32_u_cla62_b[56] b[57]=s_wallace_cla32_u_cla62_b[57] b[58]=s_wallace_cla32_u_cla62_b[58] b[59]=s_wallace_cla32_u_cla62_b[59] b[60]=s_wallace_cla32_u_cla62_b[60] b[61]=s_wallace_cla32_u_cla62_b[61] u_cla62_out[0]=s_wallace_cla32_u_cla62_pg_logic0_xor0 u_cla62_out[1]=s_wallace_cla32_u_cla62_xor1 u_cla62_out[2]=s_wallace_cla32_u_cla62_xor2 u_cla62_out[3]=s_wallace_cla32_u_cla62_xor3 u_cla62_out[4]=s_wallace_cla32_u_cla62_xor4 u_cla62_out[5]=s_wallace_cla32_u_cla62_xor5 u_cla62_out[6]=s_wallace_cla32_u_cla62_xor6 u_cla62_out[7]=s_wallace_cla32_u_cla62_xor7 u_cla62_out[8]=s_wallace_cla32_u_cla62_xor8 u_cla62_out[9]=s_wallace_cla32_u_cla62_xor9 u_cla62_out[10]=s_wallace_cla32_u_cla62_xor10 u_cla62_out[11]=s_wallace_cla32_u_cla62_xor11 u_cla62_out[12]=s_wallace_cla32_u_cla62_xor12 u_cla62_out[13]=s_wallace_cla32_u_cla62_xor13 u_cla62_out[14]=s_wallace_cla32_u_cla62_xor14 u_cla62_out[15]=s_wallace_cla32_u_cla62_xor15 u_cla62_out[16]=s_wallace_cla32_u_cla62_xor16 u_cla62_out[17]=s_wallace_cla32_u_cla62_xor17 u_cla62_out[18]=s_wallace_cla32_u_cla62_xor18 u_cla62_out[19]=s_wallace_cla32_u_cla62_xor19 u_cla62_out[20]=s_wallace_cla32_u_cla62_xor20 u_cla62_out[21]=s_wallace_cla32_u_cla62_xor21 u_cla62_out[22]=s_wallace_cla32_u_cla62_xor22 u_cla62_out[23]=s_wallace_cla32_u_cla62_xor23 u_cla62_out[24]=s_wallace_cla32_u_cla62_xor24 u_cla62_out[25]=s_wallace_cla32_u_cla62_xor25 u_cla62_out[26]=s_wallace_cla32_u_cla62_xor26 u_cla62_out[27]=s_wallace_cla32_u_cla62_xor27 u_cla62_out[28]=s_wallace_cla32_u_cla62_xor28 u_cla62_out[29]=s_wallace_cla32_u_cla62_xor29 u_cla62_out[30]=s_wallace_cla32_u_cla62_xor30 u_cla62_out[31]=s_wallace_cla32_u_cla62_xor31 u_cla62_out[32]=s_wallace_cla32_u_cla62_xor32 u_cla62_out[33]=s_wallace_cla32_u_cla62_xor33 u_cla62_out[34]=s_wallace_cla32_u_cla62_xor34 u_cla62_out[35]=s_wallace_cla32_u_cla62_xor35 u_cla62_out[36]=s_wallace_cla32_u_cla62_xor36 u_cla62_out[37]=s_wallace_cla32_u_cla62_xor37 u_cla62_out[38]=s_wallace_cla32_u_cla62_xor38 u_cla62_out[39]=s_wallace_cla32_u_cla62_xor39 u_cla62_out[40]=s_wallace_cla32_u_cla62_xor40 u_cla62_out[41]=s_wallace_cla32_u_cla62_xor41 u_cla62_out[42]=s_wallace_cla32_u_cla62_xor42 u_cla62_out[43]=s_wallace_cla32_u_cla62_xor43 u_cla62_out[44]=s_wallace_cla32_u_cla62_xor44 u_cla62_out[45]=s_wallace_cla32_u_cla62_xor45 u_cla62_out[46]=s_wallace_cla32_u_cla62_xor46 u_cla62_out[47]=s_wallace_cla32_u_cla62_xor47 u_cla62_out[48]=s_wallace_cla32_u_cla62_xor48 u_cla62_out[49]=s_wallace_cla32_u_cla62_xor49 u_cla62_out[50]=s_wallace_cla32_u_cla62_xor50 u_cla62_out[51]=s_wallace_cla32_u_cla62_xor51 u_cla62_out[52]=s_wallace_cla32_u_cla62_xor52 u_cla62_out[53]=s_wallace_cla32_u_cla62_xor53 u_cla62_out[54]=s_wallace_cla32_u_cla62_xor54 u_cla62_out[55]=s_wallace_cla32_u_cla62_xor55 u_cla62_out[56]=s_wallace_cla32_u_cla62_xor56 u_cla62_out[57]=s_wallace_cla32_u_cla62_xor57 u_cla62_out[58]=s_wallace_cla32_u_cla62_xor58 u_cla62_out[59]=s_wallace_cla32_u_cla62_xor59 u_cla62_out[60]=s_wallace_cla32_u_cla62_xor60 u_cla62_out[61]=s_wallace_cla32_u_cla62_xor61 u_cla62_out[62]=s_wallace_cla32_u_cla62_or148
.subckt not_gate a=s_wallace_cla32_u_cla62_or148 out=s_wallace_cla32_xor0
.names s_wallace_cla32_and_0_0 s_wallace_cla32_out[0]
1 1
.names s_wallace_cla32_u_cla62_pg_logic0_xor0 s_wallace_cla32_out[1]
1 1
.names s_wallace_cla32_u_cla62_xor1 s_wallace_cla32_out[2]
1 1
.names s_wallace_cla32_u_cla62_xor2 s_wallace_cla32_out[3]
1 1
.names s_wallace_cla32_u_cla62_xor3 s_wallace_cla32_out[4]
1 1
.names s_wallace_cla32_u_cla62_xor4 s_wallace_cla32_out[5]
1 1
.names s_wallace_cla32_u_cla62_xor5 s_wallace_cla32_out[6]
1 1
.names s_wallace_cla32_u_cla62_xor6 s_wallace_cla32_out[7]
1 1
.names s_wallace_cla32_u_cla62_xor7 s_wallace_cla32_out[8]
1 1
.names s_wallace_cla32_u_cla62_xor8 s_wallace_cla32_out[9]
1 1
.names s_wallace_cla32_u_cla62_xor9 s_wallace_cla32_out[10]
1 1
.names s_wallace_cla32_u_cla62_xor10 s_wallace_cla32_out[11]
1 1
.names s_wallace_cla32_u_cla62_xor11 s_wallace_cla32_out[12]
1 1
.names s_wallace_cla32_u_cla62_xor12 s_wallace_cla32_out[13]
1 1
.names s_wallace_cla32_u_cla62_xor13 s_wallace_cla32_out[14]
1 1
.names s_wallace_cla32_u_cla62_xor14 s_wallace_cla32_out[15]
1 1
.names s_wallace_cla32_u_cla62_xor15 s_wallace_cla32_out[16]
1 1
.names s_wallace_cla32_u_cla62_xor16 s_wallace_cla32_out[17]
1 1
.names s_wallace_cla32_u_cla62_xor17 s_wallace_cla32_out[18]
1 1
.names s_wallace_cla32_u_cla62_xor18 s_wallace_cla32_out[19]
1 1
.names s_wallace_cla32_u_cla62_xor19 s_wallace_cla32_out[20]
1 1
.names s_wallace_cla32_u_cla62_xor20 s_wallace_cla32_out[21]
1 1
.names s_wallace_cla32_u_cla62_xor21 s_wallace_cla32_out[22]
1 1
.names s_wallace_cla32_u_cla62_xor22 s_wallace_cla32_out[23]
1 1
.names s_wallace_cla32_u_cla62_xor23 s_wallace_cla32_out[24]
1 1
.names s_wallace_cla32_u_cla62_xor24 s_wallace_cla32_out[25]
1 1
.names s_wallace_cla32_u_cla62_xor25 s_wallace_cla32_out[26]
1 1
.names s_wallace_cla32_u_cla62_xor26 s_wallace_cla32_out[27]
1 1
.names s_wallace_cla32_u_cla62_xor27 s_wallace_cla32_out[28]
1 1
.names s_wallace_cla32_u_cla62_xor28 s_wallace_cla32_out[29]
1 1
.names s_wallace_cla32_u_cla62_xor29 s_wallace_cla32_out[30]
1 1
.names s_wallace_cla32_u_cla62_xor30 s_wallace_cla32_out[31]
1 1
.names s_wallace_cla32_u_cla62_xor31 s_wallace_cla32_out[32]
1 1
.names s_wallace_cla32_u_cla62_xor32 s_wallace_cla32_out[33]
1 1
.names s_wallace_cla32_u_cla62_xor33 s_wallace_cla32_out[34]
1 1
.names s_wallace_cla32_u_cla62_xor34 s_wallace_cla32_out[35]
1 1
.names s_wallace_cla32_u_cla62_xor35 s_wallace_cla32_out[36]
1 1
.names s_wallace_cla32_u_cla62_xor36 s_wallace_cla32_out[37]
1 1
.names s_wallace_cla32_u_cla62_xor37 s_wallace_cla32_out[38]
1 1
.names s_wallace_cla32_u_cla62_xor38 s_wallace_cla32_out[39]
1 1
.names s_wallace_cla32_u_cla62_xor39 s_wallace_cla32_out[40]
1 1
.names s_wallace_cla32_u_cla62_xor40 s_wallace_cla32_out[41]
1 1
.names s_wallace_cla32_u_cla62_xor41 s_wallace_cla32_out[42]
1 1
.names s_wallace_cla32_u_cla62_xor42 s_wallace_cla32_out[43]
1 1
.names s_wallace_cla32_u_cla62_xor43 s_wallace_cla32_out[44]
1 1
.names s_wallace_cla32_u_cla62_xor44 s_wallace_cla32_out[45]
1 1
.names s_wallace_cla32_u_cla62_xor45 s_wallace_cla32_out[46]
1 1
.names s_wallace_cla32_u_cla62_xor46 s_wallace_cla32_out[47]
1 1
.names s_wallace_cla32_u_cla62_xor47 s_wallace_cla32_out[48]
1 1
.names s_wallace_cla32_u_cla62_xor48 s_wallace_cla32_out[49]
1 1
.names s_wallace_cla32_u_cla62_xor49 s_wallace_cla32_out[50]
1 1
.names s_wallace_cla32_u_cla62_xor50 s_wallace_cla32_out[51]
1 1
.names s_wallace_cla32_u_cla62_xor51 s_wallace_cla32_out[52]
1 1
.names s_wallace_cla32_u_cla62_xor52 s_wallace_cla32_out[53]
1 1
.names s_wallace_cla32_u_cla62_xor53 s_wallace_cla32_out[54]
1 1
.names s_wallace_cla32_u_cla62_xor54 s_wallace_cla32_out[55]
1 1
.names s_wallace_cla32_u_cla62_xor55 s_wallace_cla32_out[56]
1 1
.names s_wallace_cla32_u_cla62_xor56 s_wallace_cla32_out[57]
1 1
.names s_wallace_cla32_u_cla62_xor57 s_wallace_cla32_out[58]
1 1
.names s_wallace_cla32_u_cla62_xor58 s_wallace_cla32_out[59]
1 1
.names s_wallace_cla32_u_cla62_xor59 s_wallace_cla32_out[60]
1 1
.names s_wallace_cla32_u_cla62_xor60 s_wallace_cla32_out[61]
1 1
.names s_wallace_cla32_u_cla62_xor61 s_wallace_cla32_out[62]
1 1
.names s_wallace_cla32_xor0 s_wallace_cla32_out[63]
1 1
.end

.model u_cla62
.inputs a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] a[8] a[9] a[10] a[11] a[12] a[13] a[14] a[15] a[16] a[17] a[18] a[19] a[20] a[21] a[22] a[23] a[24] a[25] a[26] a[27] a[28] a[29] a[30] a[31] a[32] a[33] a[34] a[35] a[36] a[37] a[38] a[39] a[40] a[41] a[42] a[43] a[44] a[45] a[46] a[47] a[48] a[49] a[50] a[51] a[52] a[53] a[54] a[55] a[56] a[57] a[58] a[59] a[60] a[61] b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9] b[10] b[11] b[12] b[13] b[14] b[15] b[16] b[17] b[18] b[19] b[20] b[21] b[22] b[23] b[24] b[25] b[26] b[27] b[28] b[29] b[30] b[31] b[32] b[33] b[34] b[35] b[36] b[37] b[38] b[39] b[40] b[41] b[42] b[43] b[44] b[45] b[46] b[47] b[48] b[49] b[50] b[51] b[52] b[53] b[54] b[55] b[56] b[57] b[58] b[59] b[60] b[61]
.outputs u_cla62_out[0] u_cla62_out[1] u_cla62_out[2] u_cla62_out[3] u_cla62_out[4] u_cla62_out[5] u_cla62_out[6] u_cla62_out[7] u_cla62_out[8] u_cla62_out[9] u_cla62_out[10] u_cla62_out[11] u_cla62_out[12] u_cla62_out[13] u_cla62_out[14] u_cla62_out[15] u_cla62_out[16] u_cla62_out[17] u_cla62_out[18] u_cla62_out[19] u_cla62_out[20] u_cla62_out[21] u_cla62_out[22] u_cla62_out[23] u_cla62_out[24] u_cla62_out[25] u_cla62_out[26] u_cla62_out[27] u_cla62_out[28] u_cla62_out[29] u_cla62_out[30] u_cla62_out[31] u_cla62_out[32] u_cla62_out[33] u_cla62_out[34] u_cla62_out[35] u_cla62_out[36] u_cla62_out[37] u_cla62_out[38] u_cla62_out[39] u_cla62_out[40] u_cla62_out[41] u_cla62_out[42] u_cla62_out[43] u_cla62_out[44] u_cla62_out[45] u_cla62_out[46] u_cla62_out[47] u_cla62_out[48] u_cla62_out[49] u_cla62_out[50] u_cla62_out[51] u_cla62_out[52] u_cla62_out[53] u_cla62_out[54] u_cla62_out[55] u_cla62_out[56] u_cla62_out[57] u_cla62_out[58] u_cla62_out[59] u_cla62_out[60] u_cla62_out[61] u_cla62_out[62]
.names vdd
1
.names gnd
0
.subckt pg_logic a=a[0] b=b[0] pg_logic_or0=u_cla62_pg_logic0_or0 pg_logic_and0=u_cla62_pg_logic0_and0 pg_logic_xor0=u_cla62_pg_logic0_xor0
.subckt pg_logic a=a[1] b=b[1] pg_logic_or0=u_cla62_pg_logic1_or0 pg_logic_and0=u_cla62_pg_logic1_and0 pg_logic_xor0=u_cla62_pg_logic1_xor0
.subckt xor_gate a=u_cla62_pg_logic1_xor0 b=u_cla62_pg_logic0_and0 out=u_cla62_xor1
.subckt and_gate a=u_cla62_pg_logic0_and0 b=u_cla62_pg_logic1_or0 out=u_cla62_and0
.subckt or_gate a=u_cla62_pg_logic1_and0 b=u_cla62_and0 out=u_cla62_or0
.subckt pg_logic a=a[2] b=b[2] pg_logic_or0=u_cla62_pg_logic2_or0 pg_logic_and0=u_cla62_pg_logic2_and0 pg_logic_xor0=u_cla62_pg_logic2_xor0
.subckt xor_gate a=u_cla62_pg_logic2_xor0 b=u_cla62_or0 out=u_cla62_xor2
.subckt and_gate a=u_cla62_pg_logic2_or0 b=u_cla62_pg_logic0_or0 out=u_cla62_and1
.subckt and_gate a=u_cla62_pg_logic0_and0 b=u_cla62_pg_logic2_or0 out=u_cla62_and2
.subckt and_gate a=u_cla62_and2 b=u_cla62_pg_logic1_or0 out=u_cla62_and3
.subckt and_gate a=u_cla62_pg_logic1_and0 b=u_cla62_pg_logic2_or0 out=u_cla62_and4
.subckt or_gate a=u_cla62_and3 b=u_cla62_and4 out=u_cla62_or1
.subckt or_gate a=u_cla62_pg_logic2_and0 b=u_cla62_or1 out=u_cla62_or2
.subckt pg_logic a=a[3] b=b[3] pg_logic_or0=u_cla62_pg_logic3_or0 pg_logic_and0=u_cla62_pg_logic3_and0 pg_logic_xor0=u_cla62_pg_logic3_xor0
.subckt xor_gate a=u_cla62_pg_logic3_xor0 b=u_cla62_or2 out=u_cla62_xor3
.subckt and_gate a=u_cla62_pg_logic3_or0 b=u_cla62_pg_logic1_or0 out=u_cla62_and5
.subckt and_gate a=u_cla62_pg_logic0_and0 b=u_cla62_pg_logic2_or0 out=u_cla62_and6
.subckt and_gate a=u_cla62_pg_logic3_or0 b=u_cla62_pg_logic1_or0 out=u_cla62_and7
.subckt and_gate a=u_cla62_and6 b=u_cla62_and7 out=u_cla62_and8
.subckt and_gate a=u_cla62_pg_logic1_and0 b=u_cla62_pg_logic3_or0 out=u_cla62_and9
.subckt and_gate a=u_cla62_and9 b=u_cla62_pg_logic2_or0 out=u_cla62_and10
.subckt and_gate a=u_cla62_pg_logic2_and0 b=u_cla62_pg_logic3_or0 out=u_cla62_and11
.subckt or_gate a=u_cla62_and8 b=u_cla62_and11 out=u_cla62_or3
.subckt or_gate a=u_cla62_and10 b=u_cla62_or3 out=u_cla62_or4
.subckt or_gate a=u_cla62_pg_logic3_and0 b=u_cla62_or4 out=u_cla62_or5
.subckt pg_logic a=a[4] b=b[4] pg_logic_or0=u_cla62_pg_logic4_or0 pg_logic_and0=u_cla62_pg_logic4_and0 pg_logic_xor0=u_cla62_pg_logic4_xor0
.subckt xor_gate a=u_cla62_pg_logic4_xor0 b=u_cla62_or5 out=u_cla62_xor4
.subckt and_gate a=u_cla62_or5 b=u_cla62_pg_logic4_or0 out=u_cla62_and12
.subckt or_gate a=u_cla62_pg_logic4_and0 b=u_cla62_and12 out=u_cla62_or6
.subckt pg_logic a=a[5] b=b[5] pg_logic_or0=u_cla62_pg_logic5_or0 pg_logic_and0=u_cla62_pg_logic5_and0 pg_logic_xor0=u_cla62_pg_logic5_xor0
.subckt xor_gate a=u_cla62_pg_logic5_xor0 b=u_cla62_or6 out=u_cla62_xor5
.subckt and_gate a=u_cla62_or5 b=u_cla62_pg_logic5_or0 out=u_cla62_and13
.subckt and_gate a=u_cla62_and13 b=u_cla62_pg_logic4_or0 out=u_cla62_and14
.subckt and_gate a=u_cla62_pg_logic4_and0 b=u_cla62_pg_logic5_or0 out=u_cla62_and15
.subckt or_gate a=u_cla62_and14 b=u_cla62_and15 out=u_cla62_or7
.subckt or_gate a=u_cla62_pg_logic5_and0 b=u_cla62_or7 out=u_cla62_or8
.subckt pg_logic a=a[6] b=b[6] pg_logic_or0=u_cla62_pg_logic6_or0 pg_logic_and0=u_cla62_pg_logic6_and0 pg_logic_xor0=u_cla62_pg_logic6_xor0
.subckt xor_gate a=u_cla62_pg_logic6_xor0 b=u_cla62_or8 out=u_cla62_xor6
.subckt and_gate a=u_cla62_or5 b=u_cla62_pg_logic5_or0 out=u_cla62_and16
.subckt and_gate a=u_cla62_pg_logic6_or0 b=u_cla62_pg_logic4_or0 out=u_cla62_and17
.subckt and_gate a=u_cla62_and16 b=u_cla62_and17 out=u_cla62_and18
.subckt and_gate a=u_cla62_pg_logic4_and0 b=u_cla62_pg_logic6_or0 out=u_cla62_and19
.subckt and_gate a=u_cla62_and19 b=u_cla62_pg_logic5_or0 out=u_cla62_and20
.subckt and_gate a=u_cla62_pg_logic5_and0 b=u_cla62_pg_logic6_or0 out=u_cla62_and21
.subckt or_gate a=u_cla62_and18 b=u_cla62_and20 out=u_cla62_or9
.subckt or_gate a=u_cla62_or9 b=u_cla62_and21 out=u_cla62_or10
.subckt or_gate a=u_cla62_pg_logic6_and0 b=u_cla62_or10 out=u_cla62_or11
.subckt pg_logic a=a[7] b=b[7] pg_logic_or0=u_cla62_pg_logic7_or0 pg_logic_and0=u_cla62_pg_logic7_and0 pg_logic_xor0=u_cla62_pg_logic7_xor0
.subckt xor_gate a=u_cla62_pg_logic7_xor0 b=u_cla62_or11 out=u_cla62_xor7
.subckt and_gate a=u_cla62_or5 b=u_cla62_pg_logic6_or0 out=u_cla62_and22
.subckt and_gate a=u_cla62_pg_logic7_or0 b=u_cla62_pg_logic5_or0 out=u_cla62_and23
.subckt and_gate a=u_cla62_and22 b=u_cla62_and23 out=u_cla62_and24
.subckt and_gate a=u_cla62_and24 b=u_cla62_pg_logic4_or0 out=u_cla62_and25
.subckt and_gate a=u_cla62_pg_logic4_and0 b=u_cla62_pg_logic6_or0 out=u_cla62_and26
.subckt and_gate a=u_cla62_pg_logic7_or0 b=u_cla62_pg_logic5_or0 out=u_cla62_and27
.subckt and_gate a=u_cla62_and26 b=u_cla62_and27 out=u_cla62_and28
.subckt and_gate a=u_cla62_pg_logic5_and0 b=u_cla62_pg_logic7_or0 out=u_cla62_and29
.subckt and_gate a=u_cla62_and29 b=u_cla62_pg_logic6_or0 out=u_cla62_and30
.subckt and_gate a=u_cla62_pg_logic6_and0 b=u_cla62_pg_logic7_or0 out=u_cla62_and31
.subckt or_gate a=u_cla62_and25 b=u_cla62_and30 out=u_cla62_or12
.subckt or_gate a=u_cla62_and28 b=u_cla62_and31 out=u_cla62_or13
.subckt or_gate a=u_cla62_or12 b=u_cla62_or13 out=u_cla62_or14
.subckt or_gate a=u_cla62_pg_logic7_and0 b=u_cla62_or14 out=u_cla62_or15
.subckt pg_logic a=a[8] b=b[8] pg_logic_or0=u_cla62_pg_logic8_or0 pg_logic_and0=u_cla62_pg_logic8_and0 pg_logic_xor0=u_cla62_pg_logic8_xor0
.subckt xor_gate a=u_cla62_pg_logic8_xor0 b=u_cla62_or15 out=u_cla62_xor8
.subckt and_gate a=u_cla62_or15 b=u_cla62_pg_logic8_or0 out=u_cla62_and32
.subckt or_gate a=u_cla62_pg_logic8_and0 b=u_cla62_and32 out=u_cla62_or16
.subckt pg_logic a=a[9] b=b[9] pg_logic_or0=u_cla62_pg_logic9_or0 pg_logic_and0=u_cla62_pg_logic9_and0 pg_logic_xor0=u_cla62_pg_logic9_xor0
.subckt xor_gate a=u_cla62_pg_logic9_xor0 b=u_cla62_or16 out=u_cla62_xor9
.subckt and_gate a=u_cla62_or15 b=u_cla62_pg_logic9_or0 out=u_cla62_and33
.subckt and_gate a=u_cla62_and33 b=u_cla62_pg_logic8_or0 out=u_cla62_and34
.subckt and_gate a=u_cla62_pg_logic8_and0 b=u_cla62_pg_logic9_or0 out=u_cla62_and35
.subckt or_gate a=u_cla62_and34 b=u_cla62_and35 out=u_cla62_or17
.subckt or_gate a=u_cla62_pg_logic9_and0 b=u_cla62_or17 out=u_cla62_or18
.subckt pg_logic a=a[10] b=b[10] pg_logic_or0=u_cla62_pg_logic10_or0 pg_logic_and0=u_cla62_pg_logic10_and0 pg_logic_xor0=u_cla62_pg_logic10_xor0
.subckt xor_gate a=u_cla62_pg_logic10_xor0 b=u_cla62_or18 out=u_cla62_xor10
.subckt and_gate a=u_cla62_or15 b=u_cla62_pg_logic9_or0 out=u_cla62_and36
.subckt and_gate a=u_cla62_pg_logic10_or0 b=u_cla62_pg_logic8_or0 out=u_cla62_and37
.subckt and_gate a=u_cla62_and36 b=u_cla62_and37 out=u_cla62_and38
.subckt and_gate a=u_cla62_pg_logic8_and0 b=u_cla62_pg_logic10_or0 out=u_cla62_and39
.subckt and_gate a=u_cla62_and39 b=u_cla62_pg_logic9_or0 out=u_cla62_and40
.subckt and_gate a=u_cla62_pg_logic9_and0 b=u_cla62_pg_logic10_or0 out=u_cla62_and41
.subckt or_gate a=u_cla62_and38 b=u_cla62_and40 out=u_cla62_or19
.subckt or_gate a=u_cla62_or19 b=u_cla62_and41 out=u_cla62_or20
.subckt or_gate a=u_cla62_pg_logic10_and0 b=u_cla62_or20 out=u_cla62_or21
.subckt pg_logic a=a[11] b=b[11] pg_logic_or0=u_cla62_pg_logic11_or0 pg_logic_and0=u_cla62_pg_logic11_and0 pg_logic_xor0=u_cla62_pg_logic11_xor0
.subckt xor_gate a=u_cla62_pg_logic11_xor0 b=u_cla62_or21 out=u_cla62_xor11
.subckt and_gate a=u_cla62_or15 b=u_cla62_pg_logic10_or0 out=u_cla62_and42
.subckt and_gate a=u_cla62_pg_logic11_or0 b=u_cla62_pg_logic9_or0 out=u_cla62_and43
.subckt and_gate a=u_cla62_and42 b=u_cla62_and43 out=u_cla62_and44
.subckt and_gate a=u_cla62_and44 b=u_cla62_pg_logic8_or0 out=u_cla62_and45
.subckt and_gate a=u_cla62_pg_logic8_and0 b=u_cla62_pg_logic10_or0 out=u_cla62_and46
.subckt and_gate a=u_cla62_pg_logic11_or0 b=u_cla62_pg_logic9_or0 out=u_cla62_and47
.subckt and_gate a=u_cla62_and46 b=u_cla62_and47 out=u_cla62_and48
.subckt and_gate a=u_cla62_pg_logic9_and0 b=u_cla62_pg_logic11_or0 out=u_cla62_and49
.subckt and_gate a=u_cla62_and49 b=u_cla62_pg_logic10_or0 out=u_cla62_and50
.subckt and_gate a=u_cla62_pg_logic10_and0 b=u_cla62_pg_logic11_or0 out=u_cla62_and51
.subckt or_gate a=u_cla62_and45 b=u_cla62_and50 out=u_cla62_or22
.subckt or_gate a=u_cla62_and48 b=u_cla62_and51 out=u_cla62_or23
.subckt or_gate a=u_cla62_or22 b=u_cla62_or23 out=u_cla62_or24
.subckt or_gate a=u_cla62_pg_logic11_and0 b=u_cla62_or24 out=u_cla62_or25
.subckt pg_logic a=a[12] b=b[12] pg_logic_or0=u_cla62_pg_logic12_or0 pg_logic_and0=u_cla62_pg_logic12_and0 pg_logic_xor0=u_cla62_pg_logic12_xor0
.subckt xor_gate a=u_cla62_pg_logic12_xor0 b=u_cla62_or25 out=u_cla62_xor12
.subckt and_gate a=u_cla62_or25 b=u_cla62_pg_logic12_or0 out=u_cla62_and52
.subckt or_gate a=u_cla62_pg_logic12_and0 b=u_cla62_and52 out=u_cla62_or26
.subckt pg_logic a=a[13] b=b[13] pg_logic_or0=u_cla62_pg_logic13_or0 pg_logic_and0=u_cla62_pg_logic13_and0 pg_logic_xor0=u_cla62_pg_logic13_xor0
.subckt xor_gate a=u_cla62_pg_logic13_xor0 b=u_cla62_or26 out=u_cla62_xor13
.subckt and_gate a=u_cla62_or25 b=u_cla62_pg_logic13_or0 out=u_cla62_and53
.subckt and_gate a=u_cla62_and53 b=u_cla62_pg_logic12_or0 out=u_cla62_and54
.subckt and_gate a=u_cla62_pg_logic12_and0 b=u_cla62_pg_logic13_or0 out=u_cla62_and55
.subckt or_gate a=u_cla62_and54 b=u_cla62_and55 out=u_cla62_or27
.subckt or_gate a=u_cla62_pg_logic13_and0 b=u_cla62_or27 out=u_cla62_or28
.subckt pg_logic a=a[14] b=b[14] pg_logic_or0=u_cla62_pg_logic14_or0 pg_logic_and0=u_cla62_pg_logic14_and0 pg_logic_xor0=u_cla62_pg_logic14_xor0
.subckt xor_gate a=u_cla62_pg_logic14_xor0 b=u_cla62_or28 out=u_cla62_xor14
.subckt and_gate a=u_cla62_or25 b=u_cla62_pg_logic13_or0 out=u_cla62_and56
.subckt and_gate a=u_cla62_pg_logic14_or0 b=u_cla62_pg_logic12_or0 out=u_cla62_and57
.subckt and_gate a=u_cla62_and56 b=u_cla62_and57 out=u_cla62_and58
.subckt and_gate a=u_cla62_pg_logic12_and0 b=u_cla62_pg_logic14_or0 out=u_cla62_and59
.subckt and_gate a=u_cla62_and59 b=u_cla62_pg_logic13_or0 out=u_cla62_and60
.subckt and_gate a=u_cla62_pg_logic13_and0 b=u_cla62_pg_logic14_or0 out=u_cla62_and61
.subckt or_gate a=u_cla62_and58 b=u_cla62_and60 out=u_cla62_or29
.subckt or_gate a=u_cla62_or29 b=u_cla62_and61 out=u_cla62_or30
.subckt or_gate a=u_cla62_pg_logic14_and0 b=u_cla62_or30 out=u_cla62_or31
.subckt pg_logic a=a[15] b=b[15] pg_logic_or0=u_cla62_pg_logic15_or0 pg_logic_and0=u_cla62_pg_logic15_and0 pg_logic_xor0=u_cla62_pg_logic15_xor0
.subckt xor_gate a=u_cla62_pg_logic15_xor0 b=u_cla62_or31 out=u_cla62_xor15
.subckt and_gate a=u_cla62_or25 b=u_cla62_pg_logic14_or0 out=u_cla62_and62
.subckt and_gate a=u_cla62_pg_logic15_or0 b=u_cla62_pg_logic13_or0 out=u_cla62_and63
.subckt and_gate a=u_cla62_and62 b=u_cla62_and63 out=u_cla62_and64
.subckt and_gate a=u_cla62_and64 b=u_cla62_pg_logic12_or0 out=u_cla62_and65
.subckt and_gate a=u_cla62_pg_logic12_and0 b=u_cla62_pg_logic14_or0 out=u_cla62_and66
.subckt and_gate a=u_cla62_pg_logic15_or0 b=u_cla62_pg_logic13_or0 out=u_cla62_and67
.subckt and_gate a=u_cla62_and66 b=u_cla62_and67 out=u_cla62_and68
.subckt and_gate a=u_cla62_pg_logic13_and0 b=u_cla62_pg_logic15_or0 out=u_cla62_and69
.subckt and_gate a=u_cla62_and69 b=u_cla62_pg_logic14_or0 out=u_cla62_and70
.subckt and_gate a=u_cla62_pg_logic14_and0 b=u_cla62_pg_logic15_or0 out=u_cla62_and71
.subckt or_gate a=u_cla62_and65 b=u_cla62_and70 out=u_cla62_or32
.subckt or_gate a=u_cla62_and68 b=u_cla62_and71 out=u_cla62_or33
.subckt or_gate a=u_cla62_or32 b=u_cla62_or33 out=u_cla62_or34
.subckt or_gate a=u_cla62_pg_logic15_and0 b=u_cla62_or34 out=u_cla62_or35
.subckt pg_logic a=a[16] b=b[16] pg_logic_or0=u_cla62_pg_logic16_or0 pg_logic_and0=u_cla62_pg_logic16_and0 pg_logic_xor0=u_cla62_pg_logic16_xor0
.subckt xor_gate a=u_cla62_pg_logic16_xor0 b=u_cla62_or35 out=u_cla62_xor16
.subckt and_gate a=u_cla62_or35 b=u_cla62_pg_logic16_or0 out=u_cla62_and72
.subckt or_gate a=u_cla62_pg_logic16_and0 b=u_cla62_and72 out=u_cla62_or36
.subckt pg_logic a=a[17] b=b[17] pg_logic_or0=u_cla62_pg_logic17_or0 pg_logic_and0=u_cla62_pg_logic17_and0 pg_logic_xor0=u_cla62_pg_logic17_xor0
.subckt xor_gate a=u_cla62_pg_logic17_xor0 b=u_cla62_or36 out=u_cla62_xor17
.subckt and_gate a=u_cla62_or35 b=u_cla62_pg_logic17_or0 out=u_cla62_and73
.subckt and_gate a=u_cla62_and73 b=u_cla62_pg_logic16_or0 out=u_cla62_and74
.subckt and_gate a=u_cla62_pg_logic16_and0 b=u_cla62_pg_logic17_or0 out=u_cla62_and75
.subckt or_gate a=u_cla62_and74 b=u_cla62_and75 out=u_cla62_or37
.subckt or_gate a=u_cla62_pg_logic17_and0 b=u_cla62_or37 out=u_cla62_or38
.subckt pg_logic a=a[18] b=b[18] pg_logic_or0=u_cla62_pg_logic18_or0 pg_logic_and0=u_cla62_pg_logic18_and0 pg_logic_xor0=u_cla62_pg_logic18_xor0
.subckt xor_gate a=u_cla62_pg_logic18_xor0 b=u_cla62_or38 out=u_cla62_xor18
.subckt and_gate a=u_cla62_or35 b=u_cla62_pg_logic17_or0 out=u_cla62_and76
.subckt and_gate a=u_cla62_pg_logic18_or0 b=u_cla62_pg_logic16_or0 out=u_cla62_and77
.subckt and_gate a=u_cla62_and76 b=u_cla62_and77 out=u_cla62_and78
.subckt and_gate a=u_cla62_pg_logic16_and0 b=u_cla62_pg_logic18_or0 out=u_cla62_and79
.subckt and_gate a=u_cla62_and79 b=u_cla62_pg_logic17_or0 out=u_cla62_and80
.subckt and_gate a=u_cla62_pg_logic17_and0 b=u_cla62_pg_logic18_or0 out=u_cla62_and81
.subckt or_gate a=u_cla62_and78 b=u_cla62_and80 out=u_cla62_or39
.subckt or_gate a=u_cla62_or39 b=u_cla62_and81 out=u_cla62_or40
.subckt or_gate a=u_cla62_pg_logic18_and0 b=u_cla62_or40 out=u_cla62_or41
.subckt pg_logic a=a[19] b=b[19] pg_logic_or0=u_cla62_pg_logic19_or0 pg_logic_and0=u_cla62_pg_logic19_and0 pg_logic_xor0=u_cla62_pg_logic19_xor0
.subckt xor_gate a=u_cla62_pg_logic19_xor0 b=u_cla62_or41 out=u_cla62_xor19
.subckt and_gate a=u_cla62_or35 b=u_cla62_pg_logic18_or0 out=u_cla62_and82
.subckt and_gate a=u_cla62_pg_logic19_or0 b=u_cla62_pg_logic17_or0 out=u_cla62_and83
.subckt and_gate a=u_cla62_and82 b=u_cla62_and83 out=u_cla62_and84
.subckt and_gate a=u_cla62_and84 b=u_cla62_pg_logic16_or0 out=u_cla62_and85
.subckt and_gate a=u_cla62_pg_logic16_and0 b=u_cla62_pg_logic18_or0 out=u_cla62_and86
.subckt and_gate a=u_cla62_pg_logic19_or0 b=u_cla62_pg_logic17_or0 out=u_cla62_and87
.subckt and_gate a=u_cla62_and86 b=u_cla62_and87 out=u_cla62_and88
.subckt and_gate a=u_cla62_pg_logic17_and0 b=u_cla62_pg_logic19_or0 out=u_cla62_and89
.subckt and_gate a=u_cla62_and89 b=u_cla62_pg_logic18_or0 out=u_cla62_and90
.subckt and_gate a=u_cla62_pg_logic18_and0 b=u_cla62_pg_logic19_or0 out=u_cla62_and91
.subckt or_gate a=u_cla62_and85 b=u_cla62_and90 out=u_cla62_or42
.subckt or_gate a=u_cla62_and88 b=u_cla62_and91 out=u_cla62_or43
.subckt or_gate a=u_cla62_or42 b=u_cla62_or43 out=u_cla62_or44
.subckt or_gate a=u_cla62_pg_logic19_and0 b=u_cla62_or44 out=u_cla62_or45
.subckt pg_logic a=a[20] b=b[20] pg_logic_or0=u_cla62_pg_logic20_or0 pg_logic_and0=u_cla62_pg_logic20_and0 pg_logic_xor0=u_cla62_pg_logic20_xor0
.subckt xor_gate a=u_cla62_pg_logic20_xor0 b=u_cla62_or45 out=u_cla62_xor20
.subckt and_gate a=u_cla62_or45 b=u_cla62_pg_logic20_or0 out=u_cla62_and92
.subckt or_gate a=u_cla62_pg_logic20_and0 b=u_cla62_and92 out=u_cla62_or46
.subckt pg_logic a=a[21] b=b[21] pg_logic_or0=u_cla62_pg_logic21_or0 pg_logic_and0=u_cla62_pg_logic21_and0 pg_logic_xor0=u_cla62_pg_logic21_xor0
.subckt xor_gate a=u_cla62_pg_logic21_xor0 b=u_cla62_or46 out=u_cla62_xor21
.subckt and_gate a=u_cla62_or45 b=u_cla62_pg_logic21_or0 out=u_cla62_and93
.subckt and_gate a=u_cla62_and93 b=u_cla62_pg_logic20_or0 out=u_cla62_and94
.subckt and_gate a=u_cla62_pg_logic20_and0 b=u_cla62_pg_logic21_or0 out=u_cla62_and95
.subckt or_gate a=u_cla62_and94 b=u_cla62_and95 out=u_cla62_or47
.subckt or_gate a=u_cla62_pg_logic21_and0 b=u_cla62_or47 out=u_cla62_or48
.subckt pg_logic a=a[22] b=b[22] pg_logic_or0=u_cla62_pg_logic22_or0 pg_logic_and0=u_cla62_pg_logic22_and0 pg_logic_xor0=u_cla62_pg_logic22_xor0
.subckt xor_gate a=u_cla62_pg_logic22_xor0 b=u_cla62_or48 out=u_cla62_xor22
.subckt and_gate a=u_cla62_or45 b=u_cla62_pg_logic21_or0 out=u_cla62_and96
.subckt and_gate a=u_cla62_pg_logic22_or0 b=u_cla62_pg_logic20_or0 out=u_cla62_and97
.subckt and_gate a=u_cla62_and96 b=u_cla62_and97 out=u_cla62_and98
.subckt and_gate a=u_cla62_pg_logic20_and0 b=u_cla62_pg_logic22_or0 out=u_cla62_and99
.subckt and_gate a=u_cla62_and99 b=u_cla62_pg_logic21_or0 out=u_cla62_and100
.subckt and_gate a=u_cla62_pg_logic21_and0 b=u_cla62_pg_logic22_or0 out=u_cla62_and101
.subckt or_gate a=u_cla62_and98 b=u_cla62_and100 out=u_cla62_or49
.subckt or_gate a=u_cla62_or49 b=u_cla62_and101 out=u_cla62_or50
.subckt or_gate a=u_cla62_pg_logic22_and0 b=u_cla62_or50 out=u_cla62_or51
.subckt pg_logic a=a[23] b=b[23] pg_logic_or0=u_cla62_pg_logic23_or0 pg_logic_and0=u_cla62_pg_logic23_and0 pg_logic_xor0=u_cla62_pg_logic23_xor0
.subckt xor_gate a=u_cla62_pg_logic23_xor0 b=u_cla62_or51 out=u_cla62_xor23
.subckt and_gate a=u_cla62_or45 b=u_cla62_pg_logic22_or0 out=u_cla62_and102
.subckt and_gate a=u_cla62_pg_logic23_or0 b=u_cla62_pg_logic21_or0 out=u_cla62_and103
.subckt and_gate a=u_cla62_and102 b=u_cla62_and103 out=u_cla62_and104
.subckt and_gate a=u_cla62_and104 b=u_cla62_pg_logic20_or0 out=u_cla62_and105
.subckt and_gate a=u_cla62_pg_logic20_and0 b=u_cla62_pg_logic22_or0 out=u_cla62_and106
.subckt and_gate a=u_cla62_pg_logic23_or0 b=u_cla62_pg_logic21_or0 out=u_cla62_and107
.subckt and_gate a=u_cla62_and106 b=u_cla62_and107 out=u_cla62_and108
.subckt and_gate a=u_cla62_pg_logic21_and0 b=u_cla62_pg_logic23_or0 out=u_cla62_and109
.subckt and_gate a=u_cla62_and109 b=u_cla62_pg_logic22_or0 out=u_cla62_and110
.subckt and_gate a=u_cla62_pg_logic22_and0 b=u_cla62_pg_logic23_or0 out=u_cla62_and111
.subckt or_gate a=u_cla62_and105 b=u_cla62_and110 out=u_cla62_or52
.subckt or_gate a=u_cla62_and108 b=u_cla62_and111 out=u_cla62_or53
.subckt or_gate a=u_cla62_or52 b=u_cla62_or53 out=u_cla62_or54
.subckt or_gate a=u_cla62_pg_logic23_and0 b=u_cla62_or54 out=u_cla62_or55
.subckt pg_logic a=a[24] b=b[24] pg_logic_or0=u_cla62_pg_logic24_or0 pg_logic_and0=u_cla62_pg_logic24_and0 pg_logic_xor0=u_cla62_pg_logic24_xor0
.subckt xor_gate a=u_cla62_pg_logic24_xor0 b=u_cla62_or55 out=u_cla62_xor24
.subckt and_gate a=u_cla62_or55 b=u_cla62_pg_logic24_or0 out=u_cla62_and112
.subckt or_gate a=u_cla62_pg_logic24_and0 b=u_cla62_and112 out=u_cla62_or56
.subckt pg_logic a=a[25] b=b[25] pg_logic_or0=u_cla62_pg_logic25_or0 pg_logic_and0=u_cla62_pg_logic25_and0 pg_logic_xor0=u_cla62_pg_logic25_xor0
.subckt xor_gate a=u_cla62_pg_logic25_xor0 b=u_cla62_or56 out=u_cla62_xor25
.subckt and_gate a=u_cla62_or55 b=u_cla62_pg_logic25_or0 out=u_cla62_and113
.subckt and_gate a=u_cla62_and113 b=u_cla62_pg_logic24_or0 out=u_cla62_and114
.subckt and_gate a=u_cla62_pg_logic24_and0 b=u_cla62_pg_logic25_or0 out=u_cla62_and115
.subckt or_gate a=u_cla62_and114 b=u_cla62_and115 out=u_cla62_or57
.subckt or_gate a=u_cla62_pg_logic25_and0 b=u_cla62_or57 out=u_cla62_or58
.subckt pg_logic a=a[26] b=b[26] pg_logic_or0=u_cla62_pg_logic26_or0 pg_logic_and0=u_cla62_pg_logic26_and0 pg_logic_xor0=u_cla62_pg_logic26_xor0
.subckt xor_gate a=u_cla62_pg_logic26_xor0 b=u_cla62_or58 out=u_cla62_xor26
.subckt and_gate a=u_cla62_or55 b=u_cla62_pg_logic25_or0 out=u_cla62_and116
.subckt and_gate a=u_cla62_pg_logic26_or0 b=u_cla62_pg_logic24_or0 out=u_cla62_and117
.subckt and_gate a=u_cla62_and116 b=u_cla62_and117 out=u_cla62_and118
.subckt and_gate a=u_cla62_pg_logic24_and0 b=u_cla62_pg_logic26_or0 out=u_cla62_and119
.subckt and_gate a=u_cla62_and119 b=u_cla62_pg_logic25_or0 out=u_cla62_and120
.subckt and_gate a=u_cla62_pg_logic25_and0 b=u_cla62_pg_logic26_or0 out=u_cla62_and121
.subckt or_gate a=u_cla62_and118 b=u_cla62_and120 out=u_cla62_or59
.subckt or_gate a=u_cla62_or59 b=u_cla62_and121 out=u_cla62_or60
.subckt or_gate a=u_cla62_pg_logic26_and0 b=u_cla62_or60 out=u_cla62_or61
.subckt pg_logic a=a[27] b=b[27] pg_logic_or0=u_cla62_pg_logic27_or0 pg_logic_and0=u_cla62_pg_logic27_and0 pg_logic_xor0=u_cla62_pg_logic27_xor0
.subckt xor_gate a=u_cla62_pg_logic27_xor0 b=u_cla62_or61 out=u_cla62_xor27
.subckt and_gate a=u_cla62_or55 b=u_cla62_pg_logic26_or0 out=u_cla62_and122
.subckt and_gate a=u_cla62_pg_logic27_or0 b=u_cla62_pg_logic25_or0 out=u_cla62_and123
.subckt and_gate a=u_cla62_and122 b=u_cla62_and123 out=u_cla62_and124
.subckt and_gate a=u_cla62_and124 b=u_cla62_pg_logic24_or0 out=u_cla62_and125
.subckt and_gate a=u_cla62_pg_logic24_and0 b=u_cla62_pg_logic26_or0 out=u_cla62_and126
.subckt and_gate a=u_cla62_pg_logic27_or0 b=u_cla62_pg_logic25_or0 out=u_cla62_and127
.subckt and_gate a=u_cla62_and126 b=u_cla62_and127 out=u_cla62_and128
.subckt and_gate a=u_cla62_pg_logic25_and0 b=u_cla62_pg_logic27_or0 out=u_cla62_and129
.subckt and_gate a=u_cla62_and129 b=u_cla62_pg_logic26_or0 out=u_cla62_and130
.subckt and_gate a=u_cla62_pg_logic26_and0 b=u_cla62_pg_logic27_or0 out=u_cla62_and131
.subckt or_gate a=u_cla62_and125 b=u_cla62_and130 out=u_cla62_or62
.subckt or_gate a=u_cla62_and128 b=u_cla62_and131 out=u_cla62_or63
.subckt or_gate a=u_cla62_or62 b=u_cla62_or63 out=u_cla62_or64
.subckt or_gate a=u_cla62_pg_logic27_and0 b=u_cla62_or64 out=u_cla62_or65
.subckt pg_logic a=a[28] b=b[28] pg_logic_or0=u_cla62_pg_logic28_or0 pg_logic_and0=u_cla62_pg_logic28_and0 pg_logic_xor0=u_cla62_pg_logic28_xor0
.subckt xor_gate a=u_cla62_pg_logic28_xor0 b=u_cla62_or65 out=u_cla62_xor28
.subckt and_gate a=u_cla62_or65 b=u_cla62_pg_logic28_or0 out=u_cla62_and132
.subckt or_gate a=u_cla62_pg_logic28_and0 b=u_cla62_and132 out=u_cla62_or66
.subckt pg_logic a=a[29] b=b[29] pg_logic_or0=u_cla62_pg_logic29_or0 pg_logic_and0=u_cla62_pg_logic29_and0 pg_logic_xor0=u_cla62_pg_logic29_xor0
.subckt xor_gate a=u_cla62_pg_logic29_xor0 b=u_cla62_or66 out=u_cla62_xor29
.subckt and_gate a=u_cla62_or65 b=u_cla62_pg_logic29_or0 out=u_cla62_and133
.subckt and_gate a=u_cla62_and133 b=u_cla62_pg_logic28_or0 out=u_cla62_and134
.subckt and_gate a=u_cla62_pg_logic28_and0 b=u_cla62_pg_logic29_or0 out=u_cla62_and135
.subckt or_gate a=u_cla62_and134 b=u_cla62_and135 out=u_cla62_or67
.subckt or_gate a=u_cla62_pg_logic29_and0 b=u_cla62_or67 out=u_cla62_or68
.subckt pg_logic a=a[30] b=b[30] pg_logic_or0=u_cla62_pg_logic30_or0 pg_logic_and0=u_cla62_pg_logic30_and0 pg_logic_xor0=u_cla62_pg_logic30_xor0
.subckt xor_gate a=u_cla62_pg_logic30_xor0 b=u_cla62_or68 out=u_cla62_xor30
.subckt and_gate a=u_cla62_or65 b=u_cla62_pg_logic29_or0 out=u_cla62_and136
.subckt and_gate a=u_cla62_pg_logic30_or0 b=u_cla62_pg_logic28_or0 out=u_cla62_and137
.subckt and_gate a=u_cla62_and136 b=u_cla62_and137 out=u_cla62_and138
.subckt and_gate a=u_cla62_pg_logic28_and0 b=u_cla62_pg_logic30_or0 out=u_cla62_and139
.subckt and_gate a=u_cla62_and139 b=u_cla62_pg_logic29_or0 out=u_cla62_and140
.subckt and_gate a=u_cla62_pg_logic29_and0 b=u_cla62_pg_logic30_or0 out=u_cla62_and141
.subckt or_gate a=u_cla62_and138 b=u_cla62_and140 out=u_cla62_or69
.subckt or_gate a=u_cla62_or69 b=u_cla62_and141 out=u_cla62_or70
.subckt or_gate a=u_cla62_pg_logic30_and0 b=u_cla62_or70 out=u_cla62_or71
.subckt pg_logic a=a[31] b=b[31] pg_logic_or0=u_cla62_pg_logic31_or0 pg_logic_and0=u_cla62_pg_logic31_and0 pg_logic_xor0=u_cla62_pg_logic31_xor0
.subckt xor_gate a=u_cla62_pg_logic31_xor0 b=u_cla62_or71 out=u_cla62_xor31
.subckt and_gate a=u_cla62_or65 b=u_cla62_pg_logic30_or0 out=u_cla62_and142
.subckt and_gate a=u_cla62_pg_logic31_or0 b=u_cla62_pg_logic29_or0 out=u_cla62_and143
.subckt and_gate a=u_cla62_and142 b=u_cla62_and143 out=u_cla62_and144
.subckt and_gate a=u_cla62_and144 b=u_cla62_pg_logic28_or0 out=u_cla62_and145
.subckt and_gate a=u_cla62_pg_logic28_and0 b=u_cla62_pg_logic30_or0 out=u_cla62_and146
.subckt and_gate a=u_cla62_pg_logic31_or0 b=u_cla62_pg_logic29_or0 out=u_cla62_and147
.subckt and_gate a=u_cla62_and146 b=u_cla62_and147 out=u_cla62_and148
.subckt and_gate a=u_cla62_pg_logic29_and0 b=u_cla62_pg_logic31_or0 out=u_cla62_and149
.subckt and_gate a=u_cla62_and149 b=u_cla62_pg_logic30_or0 out=u_cla62_and150
.subckt and_gate a=u_cla62_pg_logic30_and0 b=u_cla62_pg_logic31_or0 out=u_cla62_and151
.subckt or_gate a=u_cla62_and145 b=u_cla62_and150 out=u_cla62_or72
.subckt or_gate a=u_cla62_and148 b=u_cla62_and151 out=u_cla62_or73
.subckt or_gate a=u_cla62_or72 b=u_cla62_or73 out=u_cla62_or74
.subckt or_gate a=u_cla62_pg_logic31_and0 b=u_cla62_or74 out=u_cla62_or75
.subckt pg_logic a=a[32] b=b[32] pg_logic_or0=u_cla62_pg_logic32_or0 pg_logic_and0=u_cla62_pg_logic32_and0 pg_logic_xor0=u_cla62_pg_logic32_xor0
.subckt xor_gate a=u_cla62_pg_logic32_xor0 b=u_cla62_or75 out=u_cla62_xor32
.subckt and_gate a=u_cla62_or75 b=u_cla62_pg_logic32_or0 out=u_cla62_and152
.subckt or_gate a=u_cla62_pg_logic32_and0 b=u_cla62_and152 out=u_cla62_or76
.subckt pg_logic a=a[33] b=b[33] pg_logic_or0=u_cla62_pg_logic33_or0 pg_logic_and0=u_cla62_pg_logic33_and0 pg_logic_xor0=u_cla62_pg_logic33_xor0
.subckt xor_gate a=u_cla62_pg_logic33_xor0 b=u_cla62_or76 out=u_cla62_xor33
.subckt and_gate a=u_cla62_or75 b=u_cla62_pg_logic33_or0 out=u_cla62_and153
.subckt and_gate a=u_cla62_and153 b=u_cla62_pg_logic32_or0 out=u_cla62_and154
.subckt and_gate a=u_cla62_pg_logic32_and0 b=u_cla62_pg_logic33_or0 out=u_cla62_and155
.subckt or_gate a=u_cla62_and154 b=u_cla62_and155 out=u_cla62_or77
.subckt or_gate a=u_cla62_pg_logic33_and0 b=u_cla62_or77 out=u_cla62_or78
.subckt pg_logic a=a[34] b=b[34] pg_logic_or0=u_cla62_pg_logic34_or0 pg_logic_and0=u_cla62_pg_logic34_and0 pg_logic_xor0=u_cla62_pg_logic34_xor0
.subckt xor_gate a=u_cla62_pg_logic34_xor0 b=u_cla62_or78 out=u_cla62_xor34
.subckt and_gate a=u_cla62_or75 b=u_cla62_pg_logic33_or0 out=u_cla62_and156
.subckt and_gate a=u_cla62_pg_logic34_or0 b=u_cla62_pg_logic32_or0 out=u_cla62_and157
.subckt and_gate a=u_cla62_and156 b=u_cla62_and157 out=u_cla62_and158
.subckt and_gate a=u_cla62_pg_logic32_and0 b=u_cla62_pg_logic34_or0 out=u_cla62_and159
.subckt and_gate a=u_cla62_and159 b=u_cla62_pg_logic33_or0 out=u_cla62_and160
.subckt and_gate a=u_cla62_pg_logic33_and0 b=u_cla62_pg_logic34_or0 out=u_cla62_and161
.subckt or_gate a=u_cla62_and158 b=u_cla62_and160 out=u_cla62_or79
.subckt or_gate a=u_cla62_or79 b=u_cla62_and161 out=u_cla62_or80
.subckt or_gate a=u_cla62_pg_logic34_and0 b=u_cla62_or80 out=u_cla62_or81
.subckt pg_logic a=a[35] b=b[35] pg_logic_or0=u_cla62_pg_logic35_or0 pg_logic_and0=u_cla62_pg_logic35_and0 pg_logic_xor0=u_cla62_pg_logic35_xor0
.subckt xor_gate a=u_cla62_pg_logic35_xor0 b=u_cla62_or81 out=u_cla62_xor35
.subckt and_gate a=u_cla62_or75 b=u_cla62_pg_logic34_or0 out=u_cla62_and162
.subckt and_gate a=u_cla62_pg_logic35_or0 b=u_cla62_pg_logic33_or0 out=u_cla62_and163
.subckt and_gate a=u_cla62_and162 b=u_cla62_and163 out=u_cla62_and164
.subckt and_gate a=u_cla62_and164 b=u_cla62_pg_logic32_or0 out=u_cla62_and165
.subckt and_gate a=u_cla62_pg_logic32_and0 b=u_cla62_pg_logic34_or0 out=u_cla62_and166
.subckt and_gate a=u_cla62_pg_logic35_or0 b=u_cla62_pg_logic33_or0 out=u_cla62_and167
.subckt and_gate a=u_cla62_and166 b=u_cla62_and167 out=u_cla62_and168
.subckt and_gate a=u_cla62_pg_logic33_and0 b=u_cla62_pg_logic35_or0 out=u_cla62_and169
.subckt and_gate a=u_cla62_and169 b=u_cla62_pg_logic34_or0 out=u_cla62_and170
.subckt and_gate a=u_cla62_pg_logic34_and0 b=u_cla62_pg_logic35_or0 out=u_cla62_and171
.subckt or_gate a=u_cla62_and165 b=u_cla62_and170 out=u_cla62_or82
.subckt or_gate a=u_cla62_and168 b=u_cla62_and171 out=u_cla62_or83
.subckt or_gate a=u_cla62_or82 b=u_cla62_or83 out=u_cla62_or84
.subckt or_gate a=u_cla62_pg_logic35_and0 b=u_cla62_or84 out=u_cla62_or85
.subckt pg_logic a=a[36] b=b[36] pg_logic_or0=u_cla62_pg_logic36_or0 pg_logic_and0=u_cla62_pg_logic36_and0 pg_logic_xor0=u_cla62_pg_logic36_xor0
.subckt xor_gate a=u_cla62_pg_logic36_xor0 b=u_cla62_or85 out=u_cla62_xor36
.subckt and_gate a=u_cla62_or85 b=u_cla62_pg_logic36_or0 out=u_cla62_and172
.subckt or_gate a=u_cla62_pg_logic36_and0 b=u_cla62_and172 out=u_cla62_or86
.subckt pg_logic a=a[37] b=b[37] pg_logic_or0=u_cla62_pg_logic37_or0 pg_logic_and0=u_cla62_pg_logic37_and0 pg_logic_xor0=u_cla62_pg_logic37_xor0
.subckt xor_gate a=u_cla62_pg_logic37_xor0 b=u_cla62_or86 out=u_cla62_xor37
.subckt and_gate a=u_cla62_or85 b=u_cla62_pg_logic37_or0 out=u_cla62_and173
.subckt and_gate a=u_cla62_and173 b=u_cla62_pg_logic36_or0 out=u_cla62_and174
.subckt and_gate a=u_cla62_pg_logic36_and0 b=u_cla62_pg_logic37_or0 out=u_cla62_and175
.subckt or_gate a=u_cla62_and174 b=u_cla62_and175 out=u_cla62_or87
.subckt or_gate a=u_cla62_pg_logic37_and0 b=u_cla62_or87 out=u_cla62_or88
.subckt pg_logic a=a[38] b=b[38] pg_logic_or0=u_cla62_pg_logic38_or0 pg_logic_and0=u_cla62_pg_logic38_and0 pg_logic_xor0=u_cla62_pg_logic38_xor0
.subckt xor_gate a=u_cla62_pg_logic38_xor0 b=u_cla62_or88 out=u_cla62_xor38
.subckt and_gate a=u_cla62_or85 b=u_cla62_pg_logic37_or0 out=u_cla62_and176
.subckt and_gate a=u_cla62_pg_logic38_or0 b=u_cla62_pg_logic36_or0 out=u_cla62_and177
.subckt and_gate a=u_cla62_and176 b=u_cla62_and177 out=u_cla62_and178
.subckt and_gate a=u_cla62_pg_logic36_and0 b=u_cla62_pg_logic38_or0 out=u_cla62_and179
.subckt and_gate a=u_cla62_and179 b=u_cla62_pg_logic37_or0 out=u_cla62_and180
.subckt and_gate a=u_cla62_pg_logic37_and0 b=u_cla62_pg_logic38_or0 out=u_cla62_and181
.subckt or_gate a=u_cla62_and178 b=u_cla62_and180 out=u_cla62_or89
.subckt or_gate a=u_cla62_or89 b=u_cla62_and181 out=u_cla62_or90
.subckt or_gate a=u_cla62_pg_logic38_and0 b=u_cla62_or90 out=u_cla62_or91
.subckt pg_logic a=a[39] b=b[39] pg_logic_or0=u_cla62_pg_logic39_or0 pg_logic_and0=u_cla62_pg_logic39_and0 pg_logic_xor0=u_cla62_pg_logic39_xor0
.subckt xor_gate a=u_cla62_pg_logic39_xor0 b=u_cla62_or91 out=u_cla62_xor39
.subckt and_gate a=u_cla62_or85 b=u_cla62_pg_logic38_or0 out=u_cla62_and182
.subckt and_gate a=u_cla62_pg_logic39_or0 b=u_cla62_pg_logic37_or0 out=u_cla62_and183
.subckt and_gate a=u_cla62_and182 b=u_cla62_and183 out=u_cla62_and184
.subckt and_gate a=u_cla62_and184 b=u_cla62_pg_logic36_or0 out=u_cla62_and185
.subckt and_gate a=u_cla62_pg_logic36_and0 b=u_cla62_pg_logic38_or0 out=u_cla62_and186
.subckt and_gate a=u_cla62_pg_logic39_or0 b=u_cla62_pg_logic37_or0 out=u_cla62_and187
.subckt and_gate a=u_cla62_and186 b=u_cla62_and187 out=u_cla62_and188
.subckt and_gate a=u_cla62_pg_logic37_and0 b=u_cla62_pg_logic39_or0 out=u_cla62_and189
.subckt and_gate a=u_cla62_and189 b=u_cla62_pg_logic38_or0 out=u_cla62_and190
.subckt and_gate a=u_cla62_pg_logic38_and0 b=u_cla62_pg_logic39_or0 out=u_cla62_and191
.subckt or_gate a=u_cla62_and185 b=u_cla62_and190 out=u_cla62_or92
.subckt or_gate a=u_cla62_and188 b=u_cla62_and191 out=u_cla62_or93
.subckt or_gate a=u_cla62_or92 b=u_cla62_or93 out=u_cla62_or94
.subckt or_gate a=u_cla62_pg_logic39_and0 b=u_cla62_or94 out=u_cla62_or95
.subckt pg_logic a=a[40] b=b[40] pg_logic_or0=u_cla62_pg_logic40_or0 pg_logic_and0=u_cla62_pg_logic40_and0 pg_logic_xor0=u_cla62_pg_logic40_xor0
.subckt xor_gate a=u_cla62_pg_logic40_xor0 b=u_cla62_or95 out=u_cla62_xor40
.subckt and_gate a=u_cla62_or95 b=u_cla62_pg_logic40_or0 out=u_cla62_and192
.subckt or_gate a=u_cla62_pg_logic40_and0 b=u_cla62_and192 out=u_cla62_or96
.subckt pg_logic a=a[41] b=b[41] pg_logic_or0=u_cla62_pg_logic41_or0 pg_logic_and0=u_cla62_pg_logic41_and0 pg_logic_xor0=u_cla62_pg_logic41_xor0
.subckt xor_gate a=u_cla62_pg_logic41_xor0 b=u_cla62_or96 out=u_cla62_xor41
.subckt and_gate a=u_cla62_or95 b=u_cla62_pg_logic41_or0 out=u_cla62_and193
.subckt and_gate a=u_cla62_and193 b=u_cla62_pg_logic40_or0 out=u_cla62_and194
.subckt and_gate a=u_cla62_pg_logic40_and0 b=u_cla62_pg_logic41_or0 out=u_cla62_and195
.subckt or_gate a=u_cla62_and194 b=u_cla62_and195 out=u_cla62_or97
.subckt or_gate a=u_cla62_pg_logic41_and0 b=u_cla62_or97 out=u_cla62_or98
.subckt pg_logic a=a[42] b=b[42] pg_logic_or0=u_cla62_pg_logic42_or0 pg_logic_and0=u_cla62_pg_logic42_and0 pg_logic_xor0=u_cla62_pg_logic42_xor0
.subckt xor_gate a=u_cla62_pg_logic42_xor0 b=u_cla62_or98 out=u_cla62_xor42
.subckt and_gate a=u_cla62_or95 b=u_cla62_pg_logic41_or0 out=u_cla62_and196
.subckt and_gate a=u_cla62_pg_logic42_or0 b=u_cla62_pg_logic40_or0 out=u_cla62_and197
.subckt and_gate a=u_cla62_and196 b=u_cla62_and197 out=u_cla62_and198
.subckt and_gate a=u_cla62_pg_logic40_and0 b=u_cla62_pg_logic42_or0 out=u_cla62_and199
.subckt and_gate a=u_cla62_and199 b=u_cla62_pg_logic41_or0 out=u_cla62_and200
.subckt and_gate a=u_cla62_pg_logic41_and0 b=u_cla62_pg_logic42_or0 out=u_cla62_and201
.subckt or_gate a=u_cla62_and198 b=u_cla62_and200 out=u_cla62_or99
.subckt or_gate a=u_cla62_or99 b=u_cla62_and201 out=u_cla62_or100
.subckt or_gate a=u_cla62_pg_logic42_and0 b=u_cla62_or100 out=u_cla62_or101
.subckt pg_logic a=a[43] b=b[43] pg_logic_or0=u_cla62_pg_logic43_or0 pg_logic_and0=u_cla62_pg_logic43_and0 pg_logic_xor0=u_cla62_pg_logic43_xor0
.subckt xor_gate a=u_cla62_pg_logic43_xor0 b=u_cla62_or101 out=u_cla62_xor43
.subckt and_gate a=u_cla62_or95 b=u_cla62_pg_logic42_or0 out=u_cla62_and202
.subckt and_gate a=u_cla62_pg_logic43_or0 b=u_cla62_pg_logic41_or0 out=u_cla62_and203
.subckt and_gate a=u_cla62_and202 b=u_cla62_and203 out=u_cla62_and204
.subckt and_gate a=u_cla62_and204 b=u_cla62_pg_logic40_or0 out=u_cla62_and205
.subckt and_gate a=u_cla62_pg_logic40_and0 b=u_cla62_pg_logic42_or0 out=u_cla62_and206
.subckt and_gate a=u_cla62_pg_logic43_or0 b=u_cla62_pg_logic41_or0 out=u_cla62_and207
.subckt and_gate a=u_cla62_and206 b=u_cla62_and207 out=u_cla62_and208
.subckt and_gate a=u_cla62_pg_logic41_and0 b=u_cla62_pg_logic43_or0 out=u_cla62_and209
.subckt and_gate a=u_cla62_and209 b=u_cla62_pg_logic42_or0 out=u_cla62_and210
.subckt and_gate a=u_cla62_pg_logic42_and0 b=u_cla62_pg_logic43_or0 out=u_cla62_and211
.subckt or_gate a=u_cla62_and205 b=u_cla62_and210 out=u_cla62_or102
.subckt or_gate a=u_cla62_and208 b=u_cla62_and211 out=u_cla62_or103
.subckt or_gate a=u_cla62_or102 b=u_cla62_or103 out=u_cla62_or104
.subckt or_gate a=u_cla62_pg_logic43_and0 b=u_cla62_or104 out=u_cla62_or105
.subckt pg_logic a=a[44] b=b[44] pg_logic_or0=u_cla62_pg_logic44_or0 pg_logic_and0=u_cla62_pg_logic44_and0 pg_logic_xor0=u_cla62_pg_logic44_xor0
.subckt xor_gate a=u_cla62_pg_logic44_xor0 b=u_cla62_or105 out=u_cla62_xor44
.subckt and_gate a=u_cla62_or105 b=u_cla62_pg_logic44_or0 out=u_cla62_and212
.subckt or_gate a=u_cla62_pg_logic44_and0 b=u_cla62_and212 out=u_cla62_or106
.subckt pg_logic a=a[45] b=b[45] pg_logic_or0=u_cla62_pg_logic45_or0 pg_logic_and0=u_cla62_pg_logic45_and0 pg_logic_xor0=u_cla62_pg_logic45_xor0
.subckt xor_gate a=u_cla62_pg_logic45_xor0 b=u_cla62_or106 out=u_cla62_xor45
.subckt and_gate a=u_cla62_or105 b=u_cla62_pg_logic45_or0 out=u_cla62_and213
.subckt and_gate a=u_cla62_and213 b=u_cla62_pg_logic44_or0 out=u_cla62_and214
.subckt and_gate a=u_cla62_pg_logic44_and0 b=u_cla62_pg_logic45_or0 out=u_cla62_and215
.subckt or_gate a=u_cla62_and214 b=u_cla62_and215 out=u_cla62_or107
.subckt or_gate a=u_cla62_pg_logic45_and0 b=u_cla62_or107 out=u_cla62_or108
.subckt pg_logic a=a[46] b=b[46] pg_logic_or0=u_cla62_pg_logic46_or0 pg_logic_and0=u_cla62_pg_logic46_and0 pg_logic_xor0=u_cla62_pg_logic46_xor0
.subckt xor_gate a=u_cla62_pg_logic46_xor0 b=u_cla62_or108 out=u_cla62_xor46
.subckt and_gate a=u_cla62_or105 b=u_cla62_pg_logic45_or0 out=u_cla62_and216
.subckt and_gate a=u_cla62_pg_logic46_or0 b=u_cla62_pg_logic44_or0 out=u_cla62_and217
.subckt and_gate a=u_cla62_and216 b=u_cla62_and217 out=u_cla62_and218
.subckt and_gate a=u_cla62_pg_logic44_and0 b=u_cla62_pg_logic46_or0 out=u_cla62_and219
.subckt and_gate a=u_cla62_and219 b=u_cla62_pg_logic45_or0 out=u_cla62_and220
.subckt and_gate a=u_cla62_pg_logic45_and0 b=u_cla62_pg_logic46_or0 out=u_cla62_and221
.subckt or_gate a=u_cla62_and218 b=u_cla62_and220 out=u_cla62_or109
.subckt or_gate a=u_cla62_or109 b=u_cla62_and221 out=u_cla62_or110
.subckt or_gate a=u_cla62_pg_logic46_and0 b=u_cla62_or110 out=u_cla62_or111
.subckt pg_logic a=a[47] b=b[47] pg_logic_or0=u_cla62_pg_logic47_or0 pg_logic_and0=u_cla62_pg_logic47_and0 pg_logic_xor0=u_cla62_pg_logic47_xor0
.subckt xor_gate a=u_cla62_pg_logic47_xor0 b=u_cla62_or111 out=u_cla62_xor47
.subckt and_gate a=u_cla62_or105 b=u_cla62_pg_logic46_or0 out=u_cla62_and222
.subckt and_gate a=u_cla62_pg_logic47_or0 b=u_cla62_pg_logic45_or0 out=u_cla62_and223
.subckt and_gate a=u_cla62_and222 b=u_cla62_and223 out=u_cla62_and224
.subckt and_gate a=u_cla62_and224 b=u_cla62_pg_logic44_or0 out=u_cla62_and225
.subckt and_gate a=u_cla62_pg_logic44_and0 b=u_cla62_pg_logic46_or0 out=u_cla62_and226
.subckt and_gate a=u_cla62_pg_logic47_or0 b=u_cla62_pg_logic45_or0 out=u_cla62_and227
.subckt and_gate a=u_cla62_and226 b=u_cla62_and227 out=u_cla62_and228
.subckt and_gate a=u_cla62_pg_logic45_and0 b=u_cla62_pg_logic47_or0 out=u_cla62_and229
.subckt and_gate a=u_cla62_and229 b=u_cla62_pg_logic46_or0 out=u_cla62_and230
.subckt and_gate a=u_cla62_pg_logic46_and0 b=u_cla62_pg_logic47_or0 out=u_cla62_and231
.subckt or_gate a=u_cla62_and225 b=u_cla62_and230 out=u_cla62_or112
.subckt or_gate a=u_cla62_and228 b=u_cla62_and231 out=u_cla62_or113
.subckt or_gate a=u_cla62_or112 b=u_cla62_or113 out=u_cla62_or114
.subckt or_gate a=u_cla62_pg_logic47_and0 b=u_cla62_or114 out=u_cla62_or115
.subckt pg_logic a=a[48] b=b[48] pg_logic_or0=u_cla62_pg_logic48_or0 pg_logic_and0=u_cla62_pg_logic48_and0 pg_logic_xor0=u_cla62_pg_logic48_xor0
.subckt xor_gate a=u_cla62_pg_logic48_xor0 b=u_cla62_or115 out=u_cla62_xor48
.subckt and_gate a=u_cla62_or115 b=u_cla62_pg_logic48_or0 out=u_cla62_and232
.subckt or_gate a=u_cla62_pg_logic48_and0 b=u_cla62_and232 out=u_cla62_or116
.subckt pg_logic a=a[49] b=b[49] pg_logic_or0=u_cla62_pg_logic49_or0 pg_logic_and0=u_cla62_pg_logic49_and0 pg_logic_xor0=u_cla62_pg_logic49_xor0
.subckt xor_gate a=u_cla62_pg_logic49_xor0 b=u_cla62_or116 out=u_cla62_xor49
.subckt and_gate a=u_cla62_or115 b=u_cla62_pg_logic49_or0 out=u_cla62_and233
.subckt and_gate a=u_cla62_and233 b=u_cla62_pg_logic48_or0 out=u_cla62_and234
.subckt and_gate a=u_cla62_pg_logic48_and0 b=u_cla62_pg_logic49_or0 out=u_cla62_and235
.subckt or_gate a=u_cla62_and234 b=u_cla62_and235 out=u_cla62_or117
.subckt or_gate a=u_cla62_pg_logic49_and0 b=u_cla62_or117 out=u_cla62_or118
.subckt pg_logic a=a[50] b=b[50] pg_logic_or0=u_cla62_pg_logic50_or0 pg_logic_and0=u_cla62_pg_logic50_and0 pg_logic_xor0=u_cla62_pg_logic50_xor0
.subckt xor_gate a=u_cla62_pg_logic50_xor0 b=u_cla62_or118 out=u_cla62_xor50
.subckt and_gate a=u_cla62_or115 b=u_cla62_pg_logic49_or0 out=u_cla62_and236
.subckt and_gate a=u_cla62_pg_logic50_or0 b=u_cla62_pg_logic48_or0 out=u_cla62_and237
.subckt and_gate a=u_cla62_and236 b=u_cla62_and237 out=u_cla62_and238
.subckt and_gate a=u_cla62_pg_logic48_and0 b=u_cla62_pg_logic50_or0 out=u_cla62_and239
.subckt and_gate a=u_cla62_and239 b=u_cla62_pg_logic49_or0 out=u_cla62_and240
.subckt and_gate a=u_cla62_pg_logic49_and0 b=u_cla62_pg_logic50_or0 out=u_cla62_and241
.subckt or_gate a=u_cla62_and238 b=u_cla62_and240 out=u_cla62_or119
.subckt or_gate a=u_cla62_or119 b=u_cla62_and241 out=u_cla62_or120
.subckt or_gate a=u_cla62_pg_logic50_and0 b=u_cla62_or120 out=u_cla62_or121
.subckt pg_logic a=a[51] b=b[51] pg_logic_or0=u_cla62_pg_logic51_or0 pg_logic_and0=u_cla62_pg_logic51_and0 pg_logic_xor0=u_cla62_pg_logic51_xor0
.subckt xor_gate a=u_cla62_pg_logic51_xor0 b=u_cla62_or121 out=u_cla62_xor51
.subckt and_gate a=u_cla62_or115 b=u_cla62_pg_logic50_or0 out=u_cla62_and242
.subckt and_gate a=u_cla62_pg_logic51_or0 b=u_cla62_pg_logic49_or0 out=u_cla62_and243
.subckt and_gate a=u_cla62_and242 b=u_cla62_and243 out=u_cla62_and244
.subckt and_gate a=u_cla62_and244 b=u_cla62_pg_logic48_or0 out=u_cla62_and245
.subckt and_gate a=u_cla62_pg_logic48_and0 b=u_cla62_pg_logic50_or0 out=u_cla62_and246
.subckt and_gate a=u_cla62_pg_logic51_or0 b=u_cla62_pg_logic49_or0 out=u_cla62_and247
.subckt and_gate a=u_cla62_and246 b=u_cla62_and247 out=u_cla62_and248
.subckt and_gate a=u_cla62_pg_logic49_and0 b=u_cla62_pg_logic51_or0 out=u_cla62_and249
.subckt and_gate a=u_cla62_and249 b=u_cla62_pg_logic50_or0 out=u_cla62_and250
.subckt and_gate a=u_cla62_pg_logic50_and0 b=u_cla62_pg_logic51_or0 out=u_cla62_and251
.subckt or_gate a=u_cla62_and245 b=u_cla62_and250 out=u_cla62_or122
.subckt or_gate a=u_cla62_and248 b=u_cla62_and251 out=u_cla62_or123
.subckt or_gate a=u_cla62_or122 b=u_cla62_or123 out=u_cla62_or124
.subckt or_gate a=u_cla62_pg_logic51_and0 b=u_cla62_or124 out=u_cla62_or125
.subckt pg_logic a=a[52] b=b[52] pg_logic_or0=u_cla62_pg_logic52_or0 pg_logic_and0=u_cla62_pg_logic52_and0 pg_logic_xor0=u_cla62_pg_logic52_xor0
.subckt xor_gate a=u_cla62_pg_logic52_xor0 b=u_cla62_or125 out=u_cla62_xor52
.subckt and_gate a=u_cla62_or125 b=u_cla62_pg_logic52_or0 out=u_cla62_and252
.subckt or_gate a=u_cla62_pg_logic52_and0 b=u_cla62_and252 out=u_cla62_or126
.subckt pg_logic a=a[53] b=b[53] pg_logic_or0=u_cla62_pg_logic53_or0 pg_logic_and0=u_cla62_pg_logic53_and0 pg_logic_xor0=u_cla62_pg_logic53_xor0
.subckt xor_gate a=u_cla62_pg_logic53_xor0 b=u_cla62_or126 out=u_cla62_xor53
.subckt and_gate a=u_cla62_or125 b=u_cla62_pg_logic53_or0 out=u_cla62_and253
.subckt and_gate a=u_cla62_and253 b=u_cla62_pg_logic52_or0 out=u_cla62_and254
.subckt and_gate a=u_cla62_pg_logic52_and0 b=u_cla62_pg_logic53_or0 out=u_cla62_and255
.subckt or_gate a=u_cla62_and254 b=u_cla62_and255 out=u_cla62_or127
.subckt or_gate a=u_cla62_pg_logic53_and0 b=u_cla62_or127 out=u_cla62_or128
.subckt pg_logic a=a[54] b=b[54] pg_logic_or0=u_cla62_pg_logic54_or0 pg_logic_and0=u_cla62_pg_logic54_and0 pg_logic_xor0=u_cla62_pg_logic54_xor0
.subckt xor_gate a=u_cla62_pg_logic54_xor0 b=u_cla62_or128 out=u_cla62_xor54
.subckt and_gate a=u_cla62_or125 b=u_cla62_pg_logic53_or0 out=u_cla62_and256
.subckt and_gate a=u_cla62_pg_logic54_or0 b=u_cla62_pg_logic52_or0 out=u_cla62_and257
.subckt and_gate a=u_cla62_and256 b=u_cla62_and257 out=u_cla62_and258
.subckt and_gate a=u_cla62_pg_logic52_and0 b=u_cla62_pg_logic54_or0 out=u_cla62_and259
.subckt and_gate a=u_cla62_and259 b=u_cla62_pg_logic53_or0 out=u_cla62_and260
.subckt and_gate a=u_cla62_pg_logic53_and0 b=u_cla62_pg_logic54_or0 out=u_cla62_and261
.subckt or_gate a=u_cla62_and258 b=u_cla62_and260 out=u_cla62_or129
.subckt or_gate a=u_cla62_or129 b=u_cla62_and261 out=u_cla62_or130
.subckt or_gate a=u_cla62_pg_logic54_and0 b=u_cla62_or130 out=u_cla62_or131
.subckt pg_logic a=a[55] b=b[55] pg_logic_or0=u_cla62_pg_logic55_or0 pg_logic_and0=u_cla62_pg_logic55_and0 pg_logic_xor0=u_cla62_pg_logic55_xor0
.subckt xor_gate a=u_cla62_pg_logic55_xor0 b=u_cla62_or131 out=u_cla62_xor55
.subckt and_gate a=u_cla62_or125 b=u_cla62_pg_logic54_or0 out=u_cla62_and262
.subckt and_gate a=u_cla62_pg_logic55_or0 b=u_cla62_pg_logic53_or0 out=u_cla62_and263
.subckt and_gate a=u_cla62_and262 b=u_cla62_and263 out=u_cla62_and264
.subckt and_gate a=u_cla62_and264 b=u_cla62_pg_logic52_or0 out=u_cla62_and265
.subckt and_gate a=u_cla62_pg_logic52_and0 b=u_cla62_pg_logic54_or0 out=u_cla62_and266
.subckt and_gate a=u_cla62_pg_logic55_or0 b=u_cla62_pg_logic53_or0 out=u_cla62_and267
.subckt and_gate a=u_cla62_and266 b=u_cla62_and267 out=u_cla62_and268
.subckt and_gate a=u_cla62_pg_logic53_and0 b=u_cla62_pg_logic55_or0 out=u_cla62_and269
.subckt and_gate a=u_cla62_and269 b=u_cla62_pg_logic54_or0 out=u_cla62_and270
.subckt and_gate a=u_cla62_pg_logic54_and0 b=u_cla62_pg_logic55_or0 out=u_cla62_and271
.subckt or_gate a=u_cla62_and265 b=u_cla62_and270 out=u_cla62_or132
.subckt or_gate a=u_cla62_and268 b=u_cla62_and271 out=u_cla62_or133
.subckt or_gate a=u_cla62_or132 b=u_cla62_or133 out=u_cla62_or134
.subckt or_gate a=u_cla62_pg_logic55_and0 b=u_cla62_or134 out=u_cla62_or135
.subckt pg_logic a=a[56] b=b[56] pg_logic_or0=u_cla62_pg_logic56_or0 pg_logic_and0=u_cla62_pg_logic56_and0 pg_logic_xor0=u_cla62_pg_logic56_xor0
.subckt xor_gate a=u_cla62_pg_logic56_xor0 b=u_cla62_or135 out=u_cla62_xor56
.subckt and_gate a=u_cla62_or135 b=u_cla62_pg_logic56_or0 out=u_cla62_and272
.subckt or_gate a=u_cla62_pg_logic56_and0 b=u_cla62_and272 out=u_cla62_or136
.subckt pg_logic a=a[57] b=b[57] pg_logic_or0=u_cla62_pg_logic57_or0 pg_logic_and0=u_cla62_pg_logic57_and0 pg_logic_xor0=u_cla62_pg_logic57_xor0
.subckt xor_gate a=u_cla62_pg_logic57_xor0 b=u_cla62_or136 out=u_cla62_xor57
.subckt and_gate a=u_cla62_or135 b=u_cla62_pg_logic57_or0 out=u_cla62_and273
.subckt and_gate a=u_cla62_and273 b=u_cla62_pg_logic56_or0 out=u_cla62_and274
.subckt and_gate a=u_cla62_pg_logic56_and0 b=u_cla62_pg_logic57_or0 out=u_cla62_and275
.subckt or_gate a=u_cla62_and274 b=u_cla62_and275 out=u_cla62_or137
.subckt or_gate a=u_cla62_pg_logic57_and0 b=u_cla62_or137 out=u_cla62_or138
.subckt pg_logic a=a[58] b=b[58] pg_logic_or0=u_cla62_pg_logic58_or0 pg_logic_and0=u_cla62_pg_logic58_and0 pg_logic_xor0=u_cla62_pg_logic58_xor0
.subckt xor_gate a=u_cla62_pg_logic58_xor0 b=u_cla62_or138 out=u_cla62_xor58
.subckt and_gate a=u_cla62_or135 b=u_cla62_pg_logic57_or0 out=u_cla62_and276
.subckt and_gate a=u_cla62_pg_logic58_or0 b=u_cla62_pg_logic56_or0 out=u_cla62_and277
.subckt and_gate a=u_cla62_and276 b=u_cla62_and277 out=u_cla62_and278
.subckt and_gate a=u_cla62_pg_logic56_and0 b=u_cla62_pg_logic58_or0 out=u_cla62_and279
.subckt and_gate a=u_cla62_and279 b=u_cla62_pg_logic57_or0 out=u_cla62_and280
.subckt and_gate a=u_cla62_pg_logic57_and0 b=u_cla62_pg_logic58_or0 out=u_cla62_and281
.subckt or_gate a=u_cla62_and278 b=u_cla62_and280 out=u_cla62_or139
.subckt or_gate a=u_cla62_or139 b=u_cla62_and281 out=u_cla62_or140
.subckt or_gate a=u_cla62_pg_logic58_and0 b=u_cla62_or140 out=u_cla62_or141
.subckt pg_logic a=a[59] b=b[59] pg_logic_or0=u_cla62_pg_logic59_or0 pg_logic_and0=u_cla62_pg_logic59_and0 pg_logic_xor0=u_cla62_pg_logic59_xor0
.subckt xor_gate a=u_cla62_pg_logic59_xor0 b=u_cla62_or141 out=u_cla62_xor59
.subckt and_gate a=u_cla62_or135 b=u_cla62_pg_logic58_or0 out=u_cla62_and282
.subckt and_gate a=u_cla62_pg_logic59_or0 b=u_cla62_pg_logic57_or0 out=u_cla62_and283
.subckt and_gate a=u_cla62_and282 b=u_cla62_and283 out=u_cla62_and284
.subckt and_gate a=u_cla62_and284 b=u_cla62_pg_logic56_or0 out=u_cla62_and285
.subckt and_gate a=u_cla62_pg_logic56_and0 b=u_cla62_pg_logic58_or0 out=u_cla62_and286
.subckt and_gate a=u_cla62_pg_logic59_or0 b=u_cla62_pg_logic57_or0 out=u_cla62_and287
.subckt and_gate a=u_cla62_and286 b=u_cla62_and287 out=u_cla62_and288
.subckt and_gate a=u_cla62_pg_logic57_and0 b=u_cla62_pg_logic59_or0 out=u_cla62_and289
.subckt and_gate a=u_cla62_and289 b=u_cla62_pg_logic58_or0 out=u_cla62_and290
.subckt and_gate a=u_cla62_pg_logic58_and0 b=u_cla62_pg_logic59_or0 out=u_cla62_and291
.subckt or_gate a=u_cla62_and285 b=u_cla62_and290 out=u_cla62_or142
.subckt or_gate a=u_cla62_and288 b=u_cla62_and291 out=u_cla62_or143
.subckt or_gate a=u_cla62_or142 b=u_cla62_or143 out=u_cla62_or144
.subckt or_gate a=u_cla62_pg_logic59_and0 b=u_cla62_or144 out=u_cla62_or145
.subckt pg_logic a=a[60] b=b[60] pg_logic_or0=u_cla62_pg_logic60_or0 pg_logic_and0=u_cla62_pg_logic60_and0 pg_logic_xor0=u_cla62_pg_logic60_xor0
.subckt xor_gate a=u_cla62_pg_logic60_xor0 b=u_cla62_or145 out=u_cla62_xor60
.subckt and_gate a=u_cla62_or145 b=u_cla62_pg_logic60_or0 out=u_cla62_and292
.subckt or_gate a=u_cla62_pg_logic60_and0 b=u_cla62_and292 out=u_cla62_or146
.subckt pg_logic a=a[61] b=b[61] pg_logic_or0=u_cla62_pg_logic61_or0 pg_logic_and0=u_cla62_pg_logic61_and0 pg_logic_xor0=u_cla62_pg_logic61_xor0
.subckt xor_gate a=u_cla62_pg_logic61_xor0 b=u_cla62_or146 out=u_cla62_xor61
.subckt and_gate a=u_cla62_or145 b=u_cla62_pg_logic61_or0 out=u_cla62_and293
.subckt and_gate a=u_cla62_and293 b=u_cla62_pg_logic60_or0 out=u_cla62_and294
.subckt and_gate a=u_cla62_pg_logic60_and0 b=u_cla62_pg_logic61_or0 out=u_cla62_and295
.subckt or_gate a=u_cla62_and294 b=u_cla62_and295 out=u_cla62_or147
.subckt or_gate a=u_cla62_pg_logic61_and0 b=u_cla62_or147 out=u_cla62_or148
.names u_cla62_pg_logic0_xor0 u_cla62_out[0]
1 1
.names u_cla62_xor1 u_cla62_out[1]
1 1
.names u_cla62_xor2 u_cla62_out[2]
1 1
.names u_cla62_xor3 u_cla62_out[3]
1 1
.names u_cla62_xor4 u_cla62_out[4]
1 1
.names u_cla62_xor5 u_cla62_out[5]
1 1
.names u_cla62_xor6 u_cla62_out[6]
1 1
.names u_cla62_xor7 u_cla62_out[7]
1 1
.names u_cla62_xor8 u_cla62_out[8]
1 1
.names u_cla62_xor9 u_cla62_out[9]
1 1
.names u_cla62_xor10 u_cla62_out[10]
1 1
.names u_cla62_xor11 u_cla62_out[11]
1 1
.names u_cla62_xor12 u_cla62_out[12]
1 1
.names u_cla62_xor13 u_cla62_out[13]
1 1
.names u_cla62_xor14 u_cla62_out[14]
1 1
.names u_cla62_xor15 u_cla62_out[15]
1 1
.names u_cla62_xor16 u_cla62_out[16]
1 1
.names u_cla62_xor17 u_cla62_out[17]
1 1
.names u_cla62_xor18 u_cla62_out[18]
1 1
.names u_cla62_xor19 u_cla62_out[19]
1 1
.names u_cla62_xor20 u_cla62_out[20]
1 1
.names u_cla62_xor21 u_cla62_out[21]
1 1
.names u_cla62_xor22 u_cla62_out[22]
1 1
.names u_cla62_xor23 u_cla62_out[23]
1 1
.names u_cla62_xor24 u_cla62_out[24]
1 1
.names u_cla62_xor25 u_cla62_out[25]
1 1
.names u_cla62_xor26 u_cla62_out[26]
1 1
.names u_cla62_xor27 u_cla62_out[27]
1 1
.names u_cla62_xor28 u_cla62_out[28]
1 1
.names u_cla62_xor29 u_cla62_out[29]
1 1
.names u_cla62_xor30 u_cla62_out[30]
1 1
.names u_cla62_xor31 u_cla62_out[31]
1 1
.names u_cla62_xor32 u_cla62_out[32]
1 1
.names u_cla62_xor33 u_cla62_out[33]
1 1
.names u_cla62_xor34 u_cla62_out[34]
1 1
.names u_cla62_xor35 u_cla62_out[35]
1 1
.names u_cla62_xor36 u_cla62_out[36]
1 1
.names u_cla62_xor37 u_cla62_out[37]
1 1
.names u_cla62_xor38 u_cla62_out[38]
1 1
.names u_cla62_xor39 u_cla62_out[39]
1 1
.names u_cla62_xor40 u_cla62_out[40]
1 1
.names u_cla62_xor41 u_cla62_out[41]
1 1
.names u_cla62_xor42 u_cla62_out[42]
1 1
.names u_cla62_xor43 u_cla62_out[43]
1 1
.names u_cla62_xor44 u_cla62_out[44]
1 1
.names u_cla62_xor45 u_cla62_out[45]
1 1
.names u_cla62_xor46 u_cla62_out[46]
1 1
.names u_cla62_xor47 u_cla62_out[47]
1 1
.names u_cla62_xor48 u_cla62_out[48]
1 1
.names u_cla62_xor49 u_cla62_out[49]
1 1
.names u_cla62_xor50 u_cla62_out[50]
1 1
.names u_cla62_xor51 u_cla62_out[51]
1 1
.names u_cla62_xor52 u_cla62_out[52]
1 1
.names u_cla62_xor53 u_cla62_out[53]
1 1
.names u_cla62_xor54 u_cla62_out[54]
1 1
.names u_cla62_xor55 u_cla62_out[55]
1 1
.names u_cla62_xor56 u_cla62_out[56]
1 1
.names u_cla62_xor57 u_cla62_out[57]
1 1
.names u_cla62_xor58 u_cla62_out[58]
1 1
.names u_cla62_xor59 u_cla62_out[59]
1 1
.names u_cla62_xor60 u_cla62_out[60]
1 1
.names u_cla62_xor61 u_cla62_out[61]
1 1
.names u_cla62_or148 u_cla62_out[62]
1 1
.end

.model pg_logic
.inputs a b
.outputs pg_logic_or0 pg_logic_and0 pg_logic_xor0
.names vdd
1
.names gnd
0
.subckt or_gate a=a b=b out=pg_logic_or0
.subckt and_gate a=a b=b out=pg_logic_and0
.subckt xor_gate a=a b=b out=pg_logic_xor0
.end

.model fa
.inputs a b cin
.outputs fa_xor1 fa_or0
.names vdd
1
.names gnd
0
.subckt xor_gate a=a b=b out=fa_xor0
.subckt and_gate a=a b=b out=fa_and0
.subckt xor_gate a=fa_xor0 b=cin out=fa_xor1
.subckt and_gate a=fa_xor0 b=cin out=fa_and1
.subckt or_gate a=fa_and0 b=fa_and1 out=fa_or0
.end

.model ha
.inputs a b
.outputs ha_xor0 ha_and0
.names vdd
1
.names gnd
0
.subckt xor_gate a=a b=b out=ha_xor0
.subckt and_gate a=a b=b out=ha_and0
.end

.model not_gate
.inputs a
.outputs out
.names vdd
1
.names gnd
0
.names a out
0 1
.end

.model nand_gate
.inputs a b
.outputs out
.names vdd
1
.names gnd
0
.names a b out
0- 1
-0 1
.end

.model or_gate
.inputs a b
.outputs out
.names vdd
1
.names gnd
0
.names a b out
1- 1
-1 1
.end

.model xor_gate
.inputs a b
.outputs out
.names vdd
1
.names gnd
0
.names a b out
01 1
10 1
.end

.model and_gate
.inputs a b
.outputs out
.names vdd
1
.names gnd
0
.names a b out
11 1
.end