.model u_wallace_cla24
.inputs a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] a[8] a[9] a[10] a[11] a[12] a[13] a[14] a[15] a[16] a[17] a[18] a[19] a[20] a[21] a[22] a[23] b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9] b[10] b[11] b[12] b[13] b[14] b[15] b[16] b[17] b[18] b[19] b[20] b[21] b[22] b[23]
.outputs u_wallace_cla24_out[0] u_wallace_cla24_out[1] u_wallace_cla24_out[2] u_wallace_cla24_out[3] u_wallace_cla24_out[4] u_wallace_cla24_out[5] u_wallace_cla24_out[6] u_wallace_cla24_out[7] u_wallace_cla24_out[8] u_wallace_cla24_out[9] u_wallace_cla24_out[10] u_wallace_cla24_out[11] u_wallace_cla24_out[12] u_wallace_cla24_out[13] u_wallace_cla24_out[14] u_wallace_cla24_out[15] u_wallace_cla24_out[16] u_wallace_cla24_out[17] u_wallace_cla24_out[18] u_wallace_cla24_out[19] u_wallace_cla24_out[20] u_wallace_cla24_out[21] u_wallace_cla24_out[22] u_wallace_cla24_out[23] u_wallace_cla24_out[24] u_wallace_cla24_out[25] u_wallace_cla24_out[26] u_wallace_cla24_out[27] u_wallace_cla24_out[28] u_wallace_cla24_out[29] u_wallace_cla24_out[30] u_wallace_cla24_out[31] u_wallace_cla24_out[32] u_wallace_cla24_out[33] u_wallace_cla24_out[34] u_wallace_cla24_out[35] u_wallace_cla24_out[36] u_wallace_cla24_out[37] u_wallace_cla24_out[38] u_wallace_cla24_out[39] u_wallace_cla24_out[40] u_wallace_cla24_out[41] u_wallace_cla24_out[42] u_wallace_cla24_out[43] u_wallace_cla24_out[44] u_wallace_cla24_out[45] u_wallace_cla24_out[46] u_wallace_cla24_out[47]
.names vdd
1
.names gnd
0
.subckt and_gate a=a[2] b=b[0] out=u_wallace_cla24_and_2_0
.subckt and_gate a=a[1] b=b[1] out=u_wallace_cla24_and_1_1
.subckt ha a=u_wallace_cla24_and_2_0 b=u_wallace_cla24_and_1_1 ha_xor0=u_wallace_cla24_ha0_xor0 ha_and0=u_wallace_cla24_ha0_and0
.subckt and_gate a=a[3] b=b[0] out=u_wallace_cla24_and_3_0
.subckt and_gate a=a[2] b=b[1] out=u_wallace_cla24_and_2_1
.subckt fa a=u_wallace_cla24_ha0_and0 b=u_wallace_cla24_and_3_0 cin=u_wallace_cla24_and_2_1 fa_xor1=u_wallace_cla24_fa0_xor1 fa_or0=u_wallace_cla24_fa0_or0
.subckt and_gate a=a[4] b=b[0] out=u_wallace_cla24_and_4_0
.subckt and_gate a=a[3] b=b[1] out=u_wallace_cla24_and_3_1
.subckt fa a=u_wallace_cla24_fa0_or0 b=u_wallace_cla24_and_4_0 cin=u_wallace_cla24_and_3_1 fa_xor1=u_wallace_cla24_fa1_xor1 fa_or0=u_wallace_cla24_fa1_or0
.subckt and_gate a=a[5] b=b[0] out=u_wallace_cla24_and_5_0
.subckt and_gate a=a[4] b=b[1] out=u_wallace_cla24_and_4_1
.subckt fa a=u_wallace_cla24_fa1_or0 b=u_wallace_cla24_and_5_0 cin=u_wallace_cla24_and_4_1 fa_xor1=u_wallace_cla24_fa2_xor1 fa_or0=u_wallace_cla24_fa2_or0
.subckt and_gate a=a[6] b=b[0] out=u_wallace_cla24_and_6_0
.subckt and_gate a=a[5] b=b[1] out=u_wallace_cla24_and_5_1
.subckt fa a=u_wallace_cla24_fa2_or0 b=u_wallace_cla24_and_6_0 cin=u_wallace_cla24_and_5_1 fa_xor1=u_wallace_cla24_fa3_xor1 fa_or0=u_wallace_cla24_fa3_or0
.subckt and_gate a=a[7] b=b[0] out=u_wallace_cla24_and_7_0
.subckt and_gate a=a[6] b=b[1] out=u_wallace_cla24_and_6_1
.subckt fa a=u_wallace_cla24_fa3_or0 b=u_wallace_cla24_and_7_0 cin=u_wallace_cla24_and_6_1 fa_xor1=u_wallace_cla24_fa4_xor1 fa_or0=u_wallace_cla24_fa4_or0
.subckt and_gate a=a[8] b=b[0] out=u_wallace_cla24_and_8_0
.subckt and_gate a=a[7] b=b[1] out=u_wallace_cla24_and_7_1
.subckt fa a=u_wallace_cla24_fa4_or0 b=u_wallace_cla24_and_8_0 cin=u_wallace_cla24_and_7_1 fa_xor1=u_wallace_cla24_fa5_xor1 fa_or0=u_wallace_cla24_fa5_or0
.subckt and_gate a=a[9] b=b[0] out=u_wallace_cla24_and_9_0
.subckt and_gate a=a[8] b=b[1] out=u_wallace_cla24_and_8_1
.subckt fa a=u_wallace_cla24_fa5_or0 b=u_wallace_cla24_and_9_0 cin=u_wallace_cla24_and_8_1 fa_xor1=u_wallace_cla24_fa6_xor1 fa_or0=u_wallace_cla24_fa6_or0
.subckt and_gate a=a[10] b=b[0] out=u_wallace_cla24_and_10_0
.subckt and_gate a=a[9] b=b[1] out=u_wallace_cla24_and_9_1
.subckt fa a=u_wallace_cla24_fa6_or0 b=u_wallace_cla24_and_10_0 cin=u_wallace_cla24_and_9_1 fa_xor1=u_wallace_cla24_fa7_xor1 fa_or0=u_wallace_cla24_fa7_or0
.subckt and_gate a=a[11] b=b[0] out=u_wallace_cla24_and_11_0
.subckt and_gate a=a[10] b=b[1] out=u_wallace_cla24_and_10_1
.subckt fa a=u_wallace_cla24_fa7_or0 b=u_wallace_cla24_and_11_0 cin=u_wallace_cla24_and_10_1 fa_xor1=u_wallace_cla24_fa8_xor1 fa_or0=u_wallace_cla24_fa8_or0
.subckt and_gate a=a[12] b=b[0] out=u_wallace_cla24_and_12_0
.subckt and_gate a=a[11] b=b[1] out=u_wallace_cla24_and_11_1
.subckt fa a=u_wallace_cla24_fa8_or0 b=u_wallace_cla24_and_12_0 cin=u_wallace_cla24_and_11_1 fa_xor1=u_wallace_cla24_fa9_xor1 fa_or0=u_wallace_cla24_fa9_or0
.subckt and_gate a=a[13] b=b[0] out=u_wallace_cla24_and_13_0
.subckt and_gate a=a[12] b=b[1] out=u_wallace_cla24_and_12_1
.subckt fa a=u_wallace_cla24_fa9_or0 b=u_wallace_cla24_and_13_0 cin=u_wallace_cla24_and_12_1 fa_xor1=u_wallace_cla24_fa10_xor1 fa_or0=u_wallace_cla24_fa10_or0
.subckt and_gate a=a[14] b=b[0] out=u_wallace_cla24_and_14_0
.subckt and_gate a=a[13] b=b[1] out=u_wallace_cla24_and_13_1
.subckt fa a=u_wallace_cla24_fa10_or0 b=u_wallace_cla24_and_14_0 cin=u_wallace_cla24_and_13_1 fa_xor1=u_wallace_cla24_fa11_xor1 fa_or0=u_wallace_cla24_fa11_or0
.subckt and_gate a=a[15] b=b[0] out=u_wallace_cla24_and_15_0
.subckt and_gate a=a[14] b=b[1] out=u_wallace_cla24_and_14_1
.subckt fa a=u_wallace_cla24_fa11_or0 b=u_wallace_cla24_and_15_0 cin=u_wallace_cla24_and_14_1 fa_xor1=u_wallace_cla24_fa12_xor1 fa_or0=u_wallace_cla24_fa12_or0
.subckt and_gate a=a[16] b=b[0] out=u_wallace_cla24_and_16_0
.subckt and_gate a=a[15] b=b[1] out=u_wallace_cla24_and_15_1
.subckt fa a=u_wallace_cla24_fa12_or0 b=u_wallace_cla24_and_16_0 cin=u_wallace_cla24_and_15_1 fa_xor1=u_wallace_cla24_fa13_xor1 fa_or0=u_wallace_cla24_fa13_or0
.subckt and_gate a=a[17] b=b[0] out=u_wallace_cla24_and_17_0
.subckt and_gate a=a[16] b=b[1] out=u_wallace_cla24_and_16_1
.subckt fa a=u_wallace_cla24_fa13_or0 b=u_wallace_cla24_and_17_0 cin=u_wallace_cla24_and_16_1 fa_xor1=u_wallace_cla24_fa14_xor1 fa_or0=u_wallace_cla24_fa14_or0
.subckt and_gate a=a[18] b=b[0] out=u_wallace_cla24_and_18_0
.subckt and_gate a=a[17] b=b[1] out=u_wallace_cla24_and_17_1
.subckt fa a=u_wallace_cla24_fa14_or0 b=u_wallace_cla24_and_18_0 cin=u_wallace_cla24_and_17_1 fa_xor1=u_wallace_cla24_fa15_xor1 fa_or0=u_wallace_cla24_fa15_or0
.subckt and_gate a=a[19] b=b[0] out=u_wallace_cla24_and_19_0
.subckt and_gate a=a[18] b=b[1] out=u_wallace_cla24_and_18_1
.subckt fa a=u_wallace_cla24_fa15_or0 b=u_wallace_cla24_and_19_0 cin=u_wallace_cla24_and_18_1 fa_xor1=u_wallace_cla24_fa16_xor1 fa_or0=u_wallace_cla24_fa16_or0
.subckt and_gate a=a[20] b=b[0] out=u_wallace_cla24_and_20_0
.subckt and_gate a=a[19] b=b[1] out=u_wallace_cla24_and_19_1
.subckt fa a=u_wallace_cla24_fa16_or0 b=u_wallace_cla24_and_20_0 cin=u_wallace_cla24_and_19_1 fa_xor1=u_wallace_cla24_fa17_xor1 fa_or0=u_wallace_cla24_fa17_or0
.subckt and_gate a=a[21] b=b[0] out=u_wallace_cla24_and_21_0
.subckt and_gate a=a[20] b=b[1] out=u_wallace_cla24_and_20_1
.subckt fa a=u_wallace_cla24_fa17_or0 b=u_wallace_cla24_and_21_0 cin=u_wallace_cla24_and_20_1 fa_xor1=u_wallace_cla24_fa18_xor1 fa_or0=u_wallace_cla24_fa18_or0
.subckt and_gate a=a[22] b=b[0] out=u_wallace_cla24_and_22_0
.subckt and_gate a=a[21] b=b[1] out=u_wallace_cla24_and_21_1
.subckt fa a=u_wallace_cla24_fa18_or0 b=u_wallace_cla24_and_22_0 cin=u_wallace_cla24_and_21_1 fa_xor1=u_wallace_cla24_fa19_xor1 fa_or0=u_wallace_cla24_fa19_or0
.subckt and_gate a=a[23] b=b[0] out=u_wallace_cla24_and_23_0
.subckt and_gate a=a[22] b=b[1] out=u_wallace_cla24_and_22_1
.subckt fa a=u_wallace_cla24_fa19_or0 b=u_wallace_cla24_and_23_0 cin=u_wallace_cla24_and_22_1 fa_xor1=u_wallace_cla24_fa20_xor1 fa_or0=u_wallace_cla24_fa20_or0
.subckt and_gate a=a[23] b=b[1] out=u_wallace_cla24_and_23_1
.subckt and_gate a=a[22] b=b[2] out=u_wallace_cla24_and_22_2
.subckt fa a=u_wallace_cla24_fa20_or0 b=u_wallace_cla24_and_23_1 cin=u_wallace_cla24_and_22_2 fa_xor1=u_wallace_cla24_fa21_xor1 fa_or0=u_wallace_cla24_fa21_or0
.subckt and_gate a=a[23] b=b[2] out=u_wallace_cla24_and_23_2
.subckt and_gate a=a[22] b=b[3] out=u_wallace_cla24_and_22_3
.subckt fa a=u_wallace_cla24_fa21_or0 b=u_wallace_cla24_and_23_2 cin=u_wallace_cla24_and_22_3 fa_xor1=u_wallace_cla24_fa22_xor1 fa_or0=u_wallace_cla24_fa22_or0
.subckt and_gate a=a[23] b=b[3] out=u_wallace_cla24_and_23_3
.subckt and_gate a=a[22] b=b[4] out=u_wallace_cla24_and_22_4
.subckt fa a=u_wallace_cla24_fa22_or0 b=u_wallace_cla24_and_23_3 cin=u_wallace_cla24_and_22_4 fa_xor1=u_wallace_cla24_fa23_xor1 fa_or0=u_wallace_cla24_fa23_or0
.subckt and_gate a=a[23] b=b[4] out=u_wallace_cla24_and_23_4
.subckt and_gate a=a[22] b=b[5] out=u_wallace_cla24_and_22_5
.subckt fa a=u_wallace_cla24_fa23_or0 b=u_wallace_cla24_and_23_4 cin=u_wallace_cla24_and_22_5 fa_xor1=u_wallace_cla24_fa24_xor1 fa_or0=u_wallace_cla24_fa24_or0
.subckt and_gate a=a[23] b=b[5] out=u_wallace_cla24_and_23_5
.subckt and_gate a=a[22] b=b[6] out=u_wallace_cla24_and_22_6
.subckt fa a=u_wallace_cla24_fa24_or0 b=u_wallace_cla24_and_23_5 cin=u_wallace_cla24_and_22_6 fa_xor1=u_wallace_cla24_fa25_xor1 fa_or0=u_wallace_cla24_fa25_or0
.subckt and_gate a=a[23] b=b[6] out=u_wallace_cla24_and_23_6
.subckt and_gate a=a[22] b=b[7] out=u_wallace_cla24_and_22_7
.subckt fa a=u_wallace_cla24_fa25_or0 b=u_wallace_cla24_and_23_6 cin=u_wallace_cla24_and_22_7 fa_xor1=u_wallace_cla24_fa26_xor1 fa_or0=u_wallace_cla24_fa26_or0
.subckt and_gate a=a[23] b=b[7] out=u_wallace_cla24_and_23_7
.subckt and_gate a=a[22] b=b[8] out=u_wallace_cla24_and_22_8
.subckt fa a=u_wallace_cla24_fa26_or0 b=u_wallace_cla24_and_23_7 cin=u_wallace_cla24_and_22_8 fa_xor1=u_wallace_cla24_fa27_xor1 fa_or0=u_wallace_cla24_fa27_or0
.subckt and_gate a=a[23] b=b[8] out=u_wallace_cla24_and_23_8
.subckt and_gate a=a[22] b=b[9] out=u_wallace_cla24_and_22_9
.subckt fa a=u_wallace_cla24_fa27_or0 b=u_wallace_cla24_and_23_8 cin=u_wallace_cla24_and_22_9 fa_xor1=u_wallace_cla24_fa28_xor1 fa_or0=u_wallace_cla24_fa28_or0
.subckt and_gate a=a[23] b=b[9] out=u_wallace_cla24_and_23_9
.subckt and_gate a=a[22] b=b[10] out=u_wallace_cla24_and_22_10
.subckt fa a=u_wallace_cla24_fa28_or0 b=u_wallace_cla24_and_23_9 cin=u_wallace_cla24_and_22_10 fa_xor1=u_wallace_cla24_fa29_xor1 fa_or0=u_wallace_cla24_fa29_or0
.subckt and_gate a=a[23] b=b[10] out=u_wallace_cla24_and_23_10
.subckt and_gate a=a[22] b=b[11] out=u_wallace_cla24_and_22_11
.subckt fa a=u_wallace_cla24_fa29_or0 b=u_wallace_cla24_and_23_10 cin=u_wallace_cla24_and_22_11 fa_xor1=u_wallace_cla24_fa30_xor1 fa_or0=u_wallace_cla24_fa30_or0
.subckt and_gate a=a[23] b=b[11] out=u_wallace_cla24_and_23_11
.subckt and_gate a=a[22] b=b[12] out=u_wallace_cla24_and_22_12
.subckt fa a=u_wallace_cla24_fa30_or0 b=u_wallace_cla24_and_23_11 cin=u_wallace_cla24_and_22_12 fa_xor1=u_wallace_cla24_fa31_xor1 fa_or0=u_wallace_cla24_fa31_or0
.subckt and_gate a=a[23] b=b[12] out=u_wallace_cla24_and_23_12
.subckt and_gate a=a[22] b=b[13] out=u_wallace_cla24_and_22_13
.subckt fa a=u_wallace_cla24_fa31_or0 b=u_wallace_cla24_and_23_12 cin=u_wallace_cla24_and_22_13 fa_xor1=u_wallace_cla24_fa32_xor1 fa_or0=u_wallace_cla24_fa32_or0
.subckt and_gate a=a[23] b=b[13] out=u_wallace_cla24_and_23_13
.subckt and_gate a=a[22] b=b[14] out=u_wallace_cla24_and_22_14
.subckt fa a=u_wallace_cla24_fa32_or0 b=u_wallace_cla24_and_23_13 cin=u_wallace_cla24_and_22_14 fa_xor1=u_wallace_cla24_fa33_xor1 fa_or0=u_wallace_cla24_fa33_or0
.subckt and_gate a=a[23] b=b[14] out=u_wallace_cla24_and_23_14
.subckt and_gate a=a[22] b=b[15] out=u_wallace_cla24_and_22_15
.subckt fa a=u_wallace_cla24_fa33_or0 b=u_wallace_cla24_and_23_14 cin=u_wallace_cla24_and_22_15 fa_xor1=u_wallace_cla24_fa34_xor1 fa_or0=u_wallace_cla24_fa34_or0
.subckt and_gate a=a[23] b=b[15] out=u_wallace_cla24_and_23_15
.subckt and_gate a=a[22] b=b[16] out=u_wallace_cla24_and_22_16
.subckt fa a=u_wallace_cla24_fa34_or0 b=u_wallace_cla24_and_23_15 cin=u_wallace_cla24_and_22_16 fa_xor1=u_wallace_cla24_fa35_xor1 fa_or0=u_wallace_cla24_fa35_or0
.subckt and_gate a=a[23] b=b[16] out=u_wallace_cla24_and_23_16
.subckt and_gate a=a[22] b=b[17] out=u_wallace_cla24_and_22_17
.subckt fa a=u_wallace_cla24_fa35_or0 b=u_wallace_cla24_and_23_16 cin=u_wallace_cla24_and_22_17 fa_xor1=u_wallace_cla24_fa36_xor1 fa_or0=u_wallace_cla24_fa36_or0
.subckt and_gate a=a[23] b=b[17] out=u_wallace_cla24_and_23_17
.subckt and_gate a=a[22] b=b[18] out=u_wallace_cla24_and_22_18
.subckt fa a=u_wallace_cla24_fa36_or0 b=u_wallace_cla24_and_23_17 cin=u_wallace_cla24_and_22_18 fa_xor1=u_wallace_cla24_fa37_xor1 fa_or0=u_wallace_cla24_fa37_or0
.subckt and_gate a=a[23] b=b[18] out=u_wallace_cla24_and_23_18
.subckt and_gate a=a[22] b=b[19] out=u_wallace_cla24_and_22_19
.subckt fa a=u_wallace_cla24_fa37_or0 b=u_wallace_cla24_and_23_18 cin=u_wallace_cla24_and_22_19 fa_xor1=u_wallace_cla24_fa38_xor1 fa_or0=u_wallace_cla24_fa38_or0
.subckt and_gate a=a[23] b=b[19] out=u_wallace_cla24_and_23_19
.subckt and_gate a=a[22] b=b[20] out=u_wallace_cla24_and_22_20
.subckt fa a=u_wallace_cla24_fa38_or0 b=u_wallace_cla24_and_23_19 cin=u_wallace_cla24_and_22_20 fa_xor1=u_wallace_cla24_fa39_xor1 fa_or0=u_wallace_cla24_fa39_or0
.subckt and_gate a=a[23] b=b[20] out=u_wallace_cla24_and_23_20
.subckt and_gate a=a[22] b=b[21] out=u_wallace_cla24_and_22_21
.subckt fa a=u_wallace_cla24_fa39_or0 b=u_wallace_cla24_and_23_20 cin=u_wallace_cla24_and_22_21 fa_xor1=u_wallace_cla24_fa40_xor1 fa_or0=u_wallace_cla24_fa40_or0
.subckt and_gate a=a[23] b=b[21] out=u_wallace_cla24_and_23_21
.subckt and_gate a=a[22] b=b[22] out=u_wallace_cla24_and_22_22
.subckt fa a=u_wallace_cla24_fa40_or0 b=u_wallace_cla24_and_23_21 cin=u_wallace_cla24_and_22_22 fa_xor1=u_wallace_cla24_fa41_xor1 fa_or0=u_wallace_cla24_fa41_or0
.subckt and_gate a=a[1] b=b[2] out=u_wallace_cla24_and_1_2
.subckt and_gate a=a[0] b=b[3] out=u_wallace_cla24_and_0_3
.subckt ha a=u_wallace_cla24_and_1_2 b=u_wallace_cla24_and_0_3 ha_xor0=u_wallace_cla24_ha1_xor0 ha_and0=u_wallace_cla24_ha1_and0
.subckt and_gate a=a[2] b=b[2] out=u_wallace_cla24_and_2_2
.subckt and_gate a=a[1] b=b[3] out=u_wallace_cla24_and_1_3
.subckt fa a=u_wallace_cla24_ha1_and0 b=u_wallace_cla24_and_2_2 cin=u_wallace_cla24_and_1_3 fa_xor1=u_wallace_cla24_fa42_xor1 fa_or0=u_wallace_cla24_fa42_or0
.subckt and_gate a=a[3] b=b[2] out=u_wallace_cla24_and_3_2
.subckt and_gate a=a[2] b=b[3] out=u_wallace_cla24_and_2_3
.subckt fa a=u_wallace_cla24_fa42_or0 b=u_wallace_cla24_and_3_2 cin=u_wallace_cla24_and_2_3 fa_xor1=u_wallace_cla24_fa43_xor1 fa_or0=u_wallace_cla24_fa43_or0
.subckt and_gate a=a[4] b=b[2] out=u_wallace_cla24_and_4_2
.subckt and_gate a=a[3] b=b[3] out=u_wallace_cla24_and_3_3
.subckt fa a=u_wallace_cla24_fa43_or0 b=u_wallace_cla24_and_4_2 cin=u_wallace_cla24_and_3_3 fa_xor1=u_wallace_cla24_fa44_xor1 fa_or0=u_wallace_cla24_fa44_or0
.subckt and_gate a=a[5] b=b[2] out=u_wallace_cla24_and_5_2
.subckt and_gate a=a[4] b=b[3] out=u_wallace_cla24_and_4_3
.subckt fa a=u_wallace_cla24_fa44_or0 b=u_wallace_cla24_and_5_2 cin=u_wallace_cla24_and_4_3 fa_xor1=u_wallace_cla24_fa45_xor1 fa_or0=u_wallace_cla24_fa45_or0
.subckt and_gate a=a[6] b=b[2] out=u_wallace_cla24_and_6_2
.subckt and_gate a=a[5] b=b[3] out=u_wallace_cla24_and_5_3
.subckt fa a=u_wallace_cla24_fa45_or0 b=u_wallace_cla24_and_6_2 cin=u_wallace_cla24_and_5_3 fa_xor1=u_wallace_cla24_fa46_xor1 fa_or0=u_wallace_cla24_fa46_or0
.subckt and_gate a=a[7] b=b[2] out=u_wallace_cla24_and_7_2
.subckt and_gate a=a[6] b=b[3] out=u_wallace_cla24_and_6_3
.subckt fa a=u_wallace_cla24_fa46_or0 b=u_wallace_cla24_and_7_2 cin=u_wallace_cla24_and_6_3 fa_xor1=u_wallace_cla24_fa47_xor1 fa_or0=u_wallace_cla24_fa47_or0
.subckt and_gate a=a[8] b=b[2] out=u_wallace_cla24_and_8_2
.subckt and_gate a=a[7] b=b[3] out=u_wallace_cla24_and_7_3
.subckt fa a=u_wallace_cla24_fa47_or0 b=u_wallace_cla24_and_8_2 cin=u_wallace_cla24_and_7_3 fa_xor1=u_wallace_cla24_fa48_xor1 fa_or0=u_wallace_cla24_fa48_or0
.subckt and_gate a=a[9] b=b[2] out=u_wallace_cla24_and_9_2
.subckt and_gate a=a[8] b=b[3] out=u_wallace_cla24_and_8_3
.subckt fa a=u_wallace_cla24_fa48_or0 b=u_wallace_cla24_and_9_2 cin=u_wallace_cla24_and_8_3 fa_xor1=u_wallace_cla24_fa49_xor1 fa_or0=u_wallace_cla24_fa49_or0
.subckt and_gate a=a[10] b=b[2] out=u_wallace_cla24_and_10_2
.subckt and_gate a=a[9] b=b[3] out=u_wallace_cla24_and_9_3
.subckt fa a=u_wallace_cla24_fa49_or0 b=u_wallace_cla24_and_10_2 cin=u_wallace_cla24_and_9_3 fa_xor1=u_wallace_cla24_fa50_xor1 fa_or0=u_wallace_cla24_fa50_or0
.subckt and_gate a=a[11] b=b[2] out=u_wallace_cla24_and_11_2
.subckt and_gate a=a[10] b=b[3] out=u_wallace_cla24_and_10_3
.subckt fa a=u_wallace_cla24_fa50_or0 b=u_wallace_cla24_and_11_2 cin=u_wallace_cla24_and_10_3 fa_xor1=u_wallace_cla24_fa51_xor1 fa_or0=u_wallace_cla24_fa51_or0
.subckt and_gate a=a[12] b=b[2] out=u_wallace_cla24_and_12_2
.subckt and_gate a=a[11] b=b[3] out=u_wallace_cla24_and_11_3
.subckt fa a=u_wallace_cla24_fa51_or0 b=u_wallace_cla24_and_12_2 cin=u_wallace_cla24_and_11_3 fa_xor1=u_wallace_cla24_fa52_xor1 fa_or0=u_wallace_cla24_fa52_or0
.subckt and_gate a=a[13] b=b[2] out=u_wallace_cla24_and_13_2
.subckt and_gate a=a[12] b=b[3] out=u_wallace_cla24_and_12_3
.subckt fa a=u_wallace_cla24_fa52_or0 b=u_wallace_cla24_and_13_2 cin=u_wallace_cla24_and_12_3 fa_xor1=u_wallace_cla24_fa53_xor1 fa_or0=u_wallace_cla24_fa53_or0
.subckt and_gate a=a[14] b=b[2] out=u_wallace_cla24_and_14_2
.subckt and_gate a=a[13] b=b[3] out=u_wallace_cla24_and_13_3
.subckt fa a=u_wallace_cla24_fa53_or0 b=u_wallace_cla24_and_14_2 cin=u_wallace_cla24_and_13_3 fa_xor1=u_wallace_cla24_fa54_xor1 fa_or0=u_wallace_cla24_fa54_or0
.subckt and_gate a=a[15] b=b[2] out=u_wallace_cla24_and_15_2
.subckt and_gate a=a[14] b=b[3] out=u_wallace_cla24_and_14_3
.subckt fa a=u_wallace_cla24_fa54_or0 b=u_wallace_cla24_and_15_2 cin=u_wallace_cla24_and_14_3 fa_xor1=u_wallace_cla24_fa55_xor1 fa_or0=u_wallace_cla24_fa55_or0
.subckt and_gate a=a[16] b=b[2] out=u_wallace_cla24_and_16_2
.subckt and_gate a=a[15] b=b[3] out=u_wallace_cla24_and_15_3
.subckt fa a=u_wallace_cla24_fa55_or0 b=u_wallace_cla24_and_16_2 cin=u_wallace_cla24_and_15_3 fa_xor1=u_wallace_cla24_fa56_xor1 fa_or0=u_wallace_cla24_fa56_or0
.subckt and_gate a=a[17] b=b[2] out=u_wallace_cla24_and_17_2
.subckt and_gate a=a[16] b=b[3] out=u_wallace_cla24_and_16_3
.subckt fa a=u_wallace_cla24_fa56_or0 b=u_wallace_cla24_and_17_2 cin=u_wallace_cla24_and_16_3 fa_xor1=u_wallace_cla24_fa57_xor1 fa_or0=u_wallace_cla24_fa57_or0
.subckt and_gate a=a[18] b=b[2] out=u_wallace_cla24_and_18_2
.subckt and_gate a=a[17] b=b[3] out=u_wallace_cla24_and_17_3
.subckt fa a=u_wallace_cla24_fa57_or0 b=u_wallace_cla24_and_18_2 cin=u_wallace_cla24_and_17_3 fa_xor1=u_wallace_cla24_fa58_xor1 fa_or0=u_wallace_cla24_fa58_or0
.subckt and_gate a=a[19] b=b[2] out=u_wallace_cla24_and_19_2
.subckt and_gate a=a[18] b=b[3] out=u_wallace_cla24_and_18_3
.subckt fa a=u_wallace_cla24_fa58_or0 b=u_wallace_cla24_and_19_2 cin=u_wallace_cla24_and_18_3 fa_xor1=u_wallace_cla24_fa59_xor1 fa_or0=u_wallace_cla24_fa59_or0
.subckt and_gate a=a[20] b=b[2] out=u_wallace_cla24_and_20_2
.subckt and_gate a=a[19] b=b[3] out=u_wallace_cla24_and_19_3
.subckt fa a=u_wallace_cla24_fa59_or0 b=u_wallace_cla24_and_20_2 cin=u_wallace_cla24_and_19_3 fa_xor1=u_wallace_cla24_fa60_xor1 fa_or0=u_wallace_cla24_fa60_or0
.subckt and_gate a=a[21] b=b[2] out=u_wallace_cla24_and_21_2
.subckt and_gate a=a[20] b=b[3] out=u_wallace_cla24_and_20_3
.subckt fa a=u_wallace_cla24_fa60_or0 b=u_wallace_cla24_and_21_2 cin=u_wallace_cla24_and_20_3 fa_xor1=u_wallace_cla24_fa61_xor1 fa_or0=u_wallace_cla24_fa61_or0
.subckt and_gate a=a[21] b=b[3] out=u_wallace_cla24_and_21_3
.subckt and_gate a=a[20] b=b[4] out=u_wallace_cla24_and_20_4
.subckt fa a=u_wallace_cla24_fa61_or0 b=u_wallace_cla24_and_21_3 cin=u_wallace_cla24_and_20_4 fa_xor1=u_wallace_cla24_fa62_xor1 fa_or0=u_wallace_cla24_fa62_or0
.subckt and_gate a=a[21] b=b[4] out=u_wallace_cla24_and_21_4
.subckt and_gate a=a[20] b=b[5] out=u_wallace_cla24_and_20_5
.subckt fa a=u_wallace_cla24_fa62_or0 b=u_wallace_cla24_and_21_4 cin=u_wallace_cla24_and_20_5 fa_xor1=u_wallace_cla24_fa63_xor1 fa_or0=u_wallace_cla24_fa63_or0
.subckt and_gate a=a[21] b=b[5] out=u_wallace_cla24_and_21_5
.subckt and_gate a=a[20] b=b[6] out=u_wallace_cla24_and_20_6
.subckt fa a=u_wallace_cla24_fa63_or0 b=u_wallace_cla24_and_21_5 cin=u_wallace_cla24_and_20_6 fa_xor1=u_wallace_cla24_fa64_xor1 fa_or0=u_wallace_cla24_fa64_or0
.subckt and_gate a=a[21] b=b[6] out=u_wallace_cla24_and_21_6
.subckt and_gate a=a[20] b=b[7] out=u_wallace_cla24_and_20_7
.subckt fa a=u_wallace_cla24_fa64_or0 b=u_wallace_cla24_and_21_6 cin=u_wallace_cla24_and_20_7 fa_xor1=u_wallace_cla24_fa65_xor1 fa_or0=u_wallace_cla24_fa65_or0
.subckt and_gate a=a[21] b=b[7] out=u_wallace_cla24_and_21_7
.subckt and_gate a=a[20] b=b[8] out=u_wallace_cla24_and_20_8
.subckt fa a=u_wallace_cla24_fa65_or0 b=u_wallace_cla24_and_21_7 cin=u_wallace_cla24_and_20_8 fa_xor1=u_wallace_cla24_fa66_xor1 fa_or0=u_wallace_cla24_fa66_or0
.subckt and_gate a=a[21] b=b[8] out=u_wallace_cla24_and_21_8
.subckt and_gate a=a[20] b=b[9] out=u_wallace_cla24_and_20_9
.subckt fa a=u_wallace_cla24_fa66_or0 b=u_wallace_cla24_and_21_8 cin=u_wallace_cla24_and_20_9 fa_xor1=u_wallace_cla24_fa67_xor1 fa_or0=u_wallace_cla24_fa67_or0
.subckt and_gate a=a[21] b=b[9] out=u_wallace_cla24_and_21_9
.subckt and_gate a=a[20] b=b[10] out=u_wallace_cla24_and_20_10
.subckt fa a=u_wallace_cla24_fa67_or0 b=u_wallace_cla24_and_21_9 cin=u_wallace_cla24_and_20_10 fa_xor1=u_wallace_cla24_fa68_xor1 fa_or0=u_wallace_cla24_fa68_or0
.subckt and_gate a=a[21] b=b[10] out=u_wallace_cla24_and_21_10
.subckt and_gate a=a[20] b=b[11] out=u_wallace_cla24_and_20_11
.subckt fa a=u_wallace_cla24_fa68_or0 b=u_wallace_cla24_and_21_10 cin=u_wallace_cla24_and_20_11 fa_xor1=u_wallace_cla24_fa69_xor1 fa_or0=u_wallace_cla24_fa69_or0
.subckt and_gate a=a[21] b=b[11] out=u_wallace_cla24_and_21_11
.subckt and_gate a=a[20] b=b[12] out=u_wallace_cla24_and_20_12
.subckt fa a=u_wallace_cla24_fa69_or0 b=u_wallace_cla24_and_21_11 cin=u_wallace_cla24_and_20_12 fa_xor1=u_wallace_cla24_fa70_xor1 fa_or0=u_wallace_cla24_fa70_or0
.subckt and_gate a=a[21] b=b[12] out=u_wallace_cla24_and_21_12
.subckt and_gate a=a[20] b=b[13] out=u_wallace_cla24_and_20_13
.subckt fa a=u_wallace_cla24_fa70_or0 b=u_wallace_cla24_and_21_12 cin=u_wallace_cla24_and_20_13 fa_xor1=u_wallace_cla24_fa71_xor1 fa_or0=u_wallace_cla24_fa71_or0
.subckt and_gate a=a[21] b=b[13] out=u_wallace_cla24_and_21_13
.subckt and_gate a=a[20] b=b[14] out=u_wallace_cla24_and_20_14
.subckt fa a=u_wallace_cla24_fa71_or0 b=u_wallace_cla24_and_21_13 cin=u_wallace_cla24_and_20_14 fa_xor1=u_wallace_cla24_fa72_xor1 fa_or0=u_wallace_cla24_fa72_or0
.subckt and_gate a=a[21] b=b[14] out=u_wallace_cla24_and_21_14
.subckt and_gate a=a[20] b=b[15] out=u_wallace_cla24_and_20_15
.subckt fa a=u_wallace_cla24_fa72_or0 b=u_wallace_cla24_and_21_14 cin=u_wallace_cla24_and_20_15 fa_xor1=u_wallace_cla24_fa73_xor1 fa_or0=u_wallace_cla24_fa73_or0
.subckt and_gate a=a[21] b=b[15] out=u_wallace_cla24_and_21_15
.subckt and_gate a=a[20] b=b[16] out=u_wallace_cla24_and_20_16
.subckt fa a=u_wallace_cla24_fa73_or0 b=u_wallace_cla24_and_21_15 cin=u_wallace_cla24_and_20_16 fa_xor1=u_wallace_cla24_fa74_xor1 fa_or0=u_wallace_cla24_fa74_or0
.subckt and_gate a=a[21] b=b[16] out=u_wallace_cla24_and_21_16
.subckt and_gate a=a[20] b=b[17] out=u_wallace_cla24_and_20_17
.subckt fa a=u_wallace_cla24_fa74_or0 b=u_wallace_cla24_and_21_16 cin=u_wallace_cla24_and_20_17 fa_xor1=u_wallace_cla24_fa75_xor1 fa_or0=u_wallace_cla24_fa75_or0
.subckt and_gate a=a[21] b=b[17] out=u_wallace_cla24_and_21_17
.subckt and_gate a=a[20] b=b[18] out=u_wallace_cla24_and_20_18
.subckt fa a=u_wallace_cla24_fa75_or0 b=u_wallace_cla24_and_21_17 cin=u_wallace_cla24_and_20_18 fa_xor1=u_wallace_cla24_fa76_xor1 fa_or0=u_wallace_cla24_fa76_or0
.subckt and_gate a=a[21] b=b[18] out=u_wallace_cla24_and_21_18
.subckt and_gate a=a[20] b=b[19] out=u_wallace_cla24_and_20_19
.subckt fa a=u_wallace_cla24_fa76_or0 b=u_wallace_cla24_and_21_18 cin=u_wallace_cla24_and_20_19 fa_xor1=u_wallace_cla24_fa77_xor1 fa_or0=u_wallace_cla24_fa77_or0
.subckt and_gate a=a[21] b=b[19] out=u_wallace_cla24_and_21_19
.subckt and_gate a=a[20] b=b[20] out=u_wallace_cla24_and_20_20
.subckt fa a=u_wallace_cla24_fa77_or0 b=u_wallace_cla24_and_21_19 cin=u_wallace_cla24_and_20_20 fa_xor1=u_wallace_cla24_fa78_xor1 fa_or0=u_wallace_cla24_fa78_or0
.subckt and_gate a=a[21] b=b[20] out=u_wallace_cla24_and_21_20
.subckt and_gate a=a[20] b=b[21] out=u_wallace_cla24_and_20_21
.subckt fa a=u_wallace_cla24_fa78_or0 b=u_wallace_cla24_and_21_20 cin=u_wallace_cla24_and_20_21 fa_xor1=u_wallace_cla24_fa79_xor1 fa_or0=u_wallace_cla24_fa79_or0
.subckt and_gate a=a[21] b=b[21] out=u_wallace_cla24_and_21_21
.subckt and_gate a=a[20] b=b[22] out=u_wallace_cla24_and_20_22
.subckt fa a=u_wallace_cla24_fa79_or0 b=u_wallace_cla24_and_21_21 cin=u_wallace_cla24_and_20_22 fa_xor1=u_wallace_cla24_fa80_xor1 fa_or0=u_wallace_cla24_fa80_or0
.subckt and_gate a=a[21] b=b[22] out=u_wallace_cla24_and_21_22
.subckt and_gate a=a[20] b=b[23] out=u_wallace_cla24_and_20_23
.subckt fa a=u_wallace_cla24_fa80_or0 b=u_wallace_cla24_and_21_22 cin=u_wallace_cla24_and_20_23 fa_xor1=u_wallace_cla24_fa81_xor1 fa_or0=u_wallace_cla24_fa81_or0
.subckt and_gate a=a[0] b=b[4] out=u_wallace_cla24_and_0_4
.subckt ha a=u_wallace_cla24_and_0_4 b=u_wallace_cla24_fa1_xor1 ha_xor0=u_wallace_cla24_ha2_xor0 ha_and0=u_wallace_cla24_ha2_and0
.subckt and_gate a=a[1] b=b[4] out=u_wallace_cla24_and_1_4
.subckt and_gate a=a[0] b=b[5] out=u_wallace_cla24_and_0_5
.subckt fa a=u_wallace_cla24_ha2_and0 b=u_wallace_cla24_and_1_4 cin=u_wallace_cla24_and_0_5 fa_xor1=u_wallace_cla24_fa82_xor1 fa_or0=u_wallace_cla24_fa82_or0
.subckt and_gate a=a[2] b=b[4] out=u_wallace_cla24_and_2_4
.subckt and_gate a=a[1] b=b[5] out=u_wallace_cla24_and_1_5
.subckt fa a=u_wallace_cla24_fa82_or0 b=u_wallace_cla24_and_2_4 cin=u_wallace_cla24_and_1_5 fa_xor1=u_wallace_cla24_fa83_xor1 fa_or0=u_wallace_cla24_fa83_or0
.subckt and_gate a=a[3] b=b[4] out=u_wallace_cla24_and_3_4
.subckt and_gate a=a[2] b=b[5] out=u_wallace_cla24_and_2_5
.subckt fa a=u_wallace_cla24_fa83_or0 b=u_wallace_cla24_and_3_4 cin=u_wallace_cla24_and_2_5 fa_xor1=u_wallace_cla24_fa84_xor1 fa_or0=u_wallace_cla24_fa84_or0
.subckt and_gate a=a[4] b=b[4] out=u_wallace_cla24_and_4_4
.subckt and_gate a=a[3] b=b[5] out=u_wallace_cla24_and_3_5
.subckt fa a=u_wallace_cla24_fa84_or0 b=u_wallace_cla24_and_4_4 cin=u_wallace_cla24_and_3_5 fa_xor1=u_wallace_cla24_fa85_xor1 fa_or0=u_wallace_cla24_fa85_or0
.subckt and_gate a=a[5] b=b[4] out=u_wallace_cla24_and_5_4
.subckt and_gate a=a[4] b=b[5] out=u_wallace_cla24_and_4_5
.subckt fa a=u_wallace_cla24_fa85_or0 b=u_wallace_cla24_and_5_4 cin=u_wallace_cla24_and_4_5 fa_xor1=u_wallace_cla24_fa86_xor1 fa_or0=u_wallace_cla24_fa86_or0
.subckt and_gate a=a[6] b=b[4] out=u_wallace_cla24_and_6_4
.subckt and_gate a=a[5] b=b[5] out=u_wallace_cla24_and_5_5
.subckt fa a=u_wallace_cla24_fa86_or0 b=u_wallace_cla24_and_6_4 cin=u_wallace_cla24_and_5_5 fa_xor1=u_wallace_cla24_fa87_xor1 fa_or0=u_wallace_cla24_fa87_or0
.subckt and_gate a=a[7] b=b[4] out=u_wallace_cla24_and_7_4
.subckt and_gate a=a[6] b=b[5] out=u_wallace_cla24_and_6_5
.subckt fa a=u_wallace_cla24_fa87_or0 b=u_wallace_cla24_and_7_4 cin=u_wallace_cla24_and_6_5 fa_xor1=u_wallace_cla24_fa88_xor1 fa_or0=u_wallace_cla24_fa88_or0
.subckt and_gate a=a[8] b=b[4] out=u_wallace_cla24_and_8_4
.subckt and_gate a=a[7] b=b[5] out=u_wallace_cla24_and_7_5
.subckt fa a=u_wallace_cla24_fa88_or0 b=u_wallace_cla24_and_8_4 cin=u_wallace_cla24_and_7_5 fa_xor1=u_wallace_cla24_fa89_xor1 fa_or0=u_wallace_cla24_fa89_or0
.subckt and_gate a=a[9] b=b[4] out=u_wallace_cla24_and_9_4
.subckt and_gate a=a[8] b=b[5] out=u_wallace_cla24_and_8_5
.subckt fa a=u_wallace_cla24_fa89_or0 b=u_wallace_cla24_and_9_4 cin=u_wallace_cla24_and_8_5 fa_xor1=u_wallace_cla24_fa90_xor1 fa_or0=u_wallace_cla24_fa90_or0
.subckt and_gate a=a[10] b=b[4] out=u_wallace_cla24_and_10_4
.subckt and_gate a=a[9] b=b[5] out=u_wallace_cla24_and_9_5
.subckt fa a=u_wallace_cla24_fa90_or0 b=u_wallace_cla24_and_10_4 cin=u_wallace_cla24_and_9_5 fa_xor1=u_wallace_cla24_fa91_xor1 fa_or0=u_wallace_cla24_fa91_or0
.subckt and_gate a=a[11] b=b[4] out=u_wallace_cla24_and_11_4
.subckt and_gate a=a[10] b=b[5] out=u_wallace_cla24_and_10_5
.subckt fa a=u_wallace_cla24_fa91_or0 b=u_wallace_cla24_and_11_4 cin=u_wallace_cla24_and_10_5 fa_xor1=u_wallace_cla24_fa92_xor1 fa_or0=u_wallace_cla24_fa92_or0
.subckt and_gate a=a[12] b=b[4] out=u_wallace_cla24_and_12_4
.subckt and_gate a=a[11] b=b[5] out=u_wallace_cla24_and_11_5
.subckt fa a=u_wallace_cla24_fa92_or0 b=u_wallace_cla24_and_12_4 cin=u_wallace_cla24_and_11_5 fa_xor1=u_wallace_cla24_fa93_xor1 fa_or0=u_wallace_cla24_fa93_or0
.subckt and_gate a=a[13] b=b[4] out=u_wallace_cla24_and_13_4
.subckt and_gate a=a[12] b=b[5] out=u_wallace_cla24_and_12_5
.subckt fa a=u_wallace_cla24_fa93_or0 b=u_wallace_cla24_and_13_4 cin=u_wallace_cla24_and_12_5 fa_xor1=u_wallace_cla24_fa94_xor1 fa_or0=u_wallace_cla24_fa94_or0
.subckt and_gate a=a[14] b=b[4] out=u_wallace_cla24_and_14_4
.subckt and_gate a=a[13] b=b[5] out=u_wallace_cla24_and_13_5
.subckt fa a=u_wallace_cla24_fa94_or0 b=u_wallace_cla24_and_14_4 cin=u_wallace_cla24_and_13_5 fa_xor1=u_wallace_cla24_fa95_xor1 fa_or0=u_wallace_cla24_fa95_or0
.subckt and_gate a=a[15] b=b[4] out=u_wallace_cla24_and_15_4
.subckt and_gate a=a[14] b=b[5] out=u_wallace_cla24_and_14_5
.subckt fa a=u_wallace_cla24_fa95_or0 b=u_wallace_cla24_and_15_4 cin=u_wallace_cla24_and_14_5 fa_xor1=u_wallace_cla24_fa96_xor1 fa_or0=u_wallace_cla24_fa96_or0
.subckt and_gate a=a[16] b=b[4] out=u_wallace_cla24_and_16_4
.subckt and_gate a=a[15] b=b[5] out=u_wallace_cla24_and_15_5
.subckt fa a=u_wallace_cla24_fa96_or0 b=u_wallace_cla24_and_16_4 cin=u_wallace_cla24_and_15_5 fa_xor1=u_wallace_cla24_fa97_xor1 fa_or0=u_wallace_cla24_fa97_or0
.subckt and_gate a=a[17] b=b[4] out=u_wallace_cla24_and_17_4
.subckt and_gate a=a[16] b=b[5] out=u_wallace_cla24_and_16_5
.subckt fa a=u_wallace_cla24_fa97_or0 b=u_wallace_cla24_and_17_4 cin=u_wallace_cla24_and_16_5 fa_xor1=u_wallace_cla24_fa98_xor1 fa_or0=u_wallace_cla24_fa98_or0
.subckt and_gate a=a[18] b=b[4] out=u_wallace_cla24_and_18_4
.subckt and_gate a=a[17] b=b[5] out=u_wallace_cla24_and_17_5
.subckt fa a=u_wallace_cla24_fa98_or0 b=u_wallace_cla24_and_18_4 cin=u_wallace_cla24_and_17_5 fa_xor1=u_wallace_cla24_fa99_xor1 fa_or0=u_wallace_cla24_fa99_or0
.subckt and_gate a=a[19] b=b[4] out=u_wallace_cla24_and_19_4
.subckt and_gate a=a[18] b=b[5] out=u_wallace_cla24_and_18_5
.subckt fa a=u_wallace_cla24_fa99_or0 b=u_wallace_cla24_and_19_4 cin=u_wallace_cla24_and_18_5 fa_xor1=u_wallace_cla24_fa100_xor1 fa_or0=u_wallace_cla24_fa100_or0
.subckt and_gate a=a[19] b=b[5] out=u_wallace_cla24_and_19_5
.subckt and_gate a=a[18] b=b[6] out=u_wallace_cla24_and_18_6
.subckt fa a=u_wallace_cla24_fa100_or0 b=u_wallace_cla24_and_19_5 cin=u_wallace_cla24_and_18_6 fa_xor1=u_wallace_cla24_fa101_xor1 fa_or0=u_wallace_cla24_fa101_or0
.subckt and_gate a=a[19] b=b[6] out=u_wallace_cla24_and_19_6
.subckt and_gate a=a[18] b=b[7] out=u_wallace_cla24_and_18_7
.subckt fa a=u_wallace_cla24_fa101_or0 b=u_wallace_cla24_and_19_6 cin=u_wallace_cla24_and_18_7 fa_xor1=u_wallace_cla24_fa102_xor1 fa_or0=u_wallace_cla24_fa102_or0
.subckt and_gate a=a[19] b=b[7] out=u_wallace_cla24_and_19_7
.subckt and_gate a=a[18] b=b[8] out=u_wallace_cla24_and_18_8
.subckt fa a=u_wallace_cla24_fa102_or0 b=u_wallace_cla24_and_19_7 cin=u_wallace_cla24_and_18_8 fa_xor1=u_wallace_cla24_fa103_xor1 fa_or0=u_wallace_cla24_fa103_or0
.subckt and_gate a=a[19] b=b[8] out=u_wallace_cla24_and_19_8
.subckt and_gate a=a[18] b=b[9] out=u_wallace_cla24_and_18_9
.subckt fa a=u_wallace_cla24_fa103_or0 b=u_wallace_cla24_and_19_8 cin=u_wallace_cla24_and_18_9 fa_xor1=u_wallace_cla24_fa104_xor1 fa_or0=u_wallace_cla24_fa104_or0
.subckt and_gate a=a[19] b=b[9] out=u_wallace_cla24_and_19_9
.subckt and_gate a=a[18] b=b[10] out=u_wallace_cla24_and_18_10
.subckt fa a=u_wallace_cla24_fa104_or0 b=u_wallace_cla24_and_19_9 cin=u_wallace_cla24_and_18_10 fa_xor1=u_wallace_cla24_fa105_xor1 fa_or0=u_wallace_cla24_fa105_or0
.subckt and_gate a=a[19] b=b[10] out=u_wallace_cla24_and_19_10
.subckt and_gate a=a[18] b=b[11] out=u_wallace_cla24_and_18_11
.subckt fa a=u_wallace_cla24_fa105_or0 b=u_wallace_cla24_and_19_10 cin=u_wallace_cla24_and_18_11 fa_xor1=u_wallace_cla24_fa106_xor1 fa_or0=u_wallace_cla24_fa106_or0
.subckt and_gate a=a[19] b=b[11] out=u_wallace_cla24_and_19_11
.subckt and_gate a=a[18] b=b[12] out=u_wallace_cla24_and_18_12
.subckt fa a=u_wallace_cla24_fa106_or0 b=u_wallace_cla24_and_19_11 cin=u_wallace_cla24_and_18_12 fa_xor1=u_wallace_cla24_fa107_xor1 fa_or0=u_wallace_cla24_fa107_or0
.subckt and_gate a=a[19] b=b[12] out=u_wallace_cla24_and_19_12
.subckt and_gate a=a[18] b=b[13] out=u_wallace_cla24_and_18_13
.subckt fa a=u_wallace_cla24_fa107_or0 b=u_wallace_cla24_and_19_12 cin=u_wallace_cla24_and_18_13 fa_xor1=u_wallace_cla24_fa108_xor1 fa_or0=u_wallace_cla24_fa108_or0
.subckt and_gate a=a[19] b=b[13] out=u_wallace_cla24_and_19_13
.subckt and_gate a=a[18] b=b[14] out=u_wallace_cla24_and_18_14
.subckt fa a=u_wallace_cla24_fa108_or0 b=u_wallace_cla24_and_19_13 cin=u_wallace_cla24_and_18_14 fa_xor1=u_wallace_cla24_fa109_xor1 fa_or0=u_wallace_cla24_fa109_or0
.subckt and_gate a=a[19] b=b[14] out=u_wallace_cla24_and_19_14
.subckt and_gate a=a[18] b=b[15] out=u_wallace_cla24_and_18_15
.subckt fa a=u_wallace_cla24_fa109_or0 b=u_wallace_cla24_and_19_14 cin=u_wallace_cla24_and_18_15 fa_xor1=u_wallace_cla24_fa110_xor1 fa_or0=u_wallace_cla24_fa110_or0
.subckt and_gate a=a[19] b=b[15] out=u_wallace_cla24_and_19_15
.subckt and_gate a=a[18] b=b[16] out=u_wallace_cla24_and_18_16
.subckt fa a=u_wallace_cla24_fa110_or0 b=u_wallace_cla24_and_19_15 cin=u_wallace_cla24_and_18_16 fa_xor1=u_wallace_cla24_fa111_xor1 fa_or0=u_wallace_cla24_fa111_or0
.subckt and_gate a=a[19] b=b[16] out=u_wallace_cla24_and_19_16
.subckt and_gate a=a[18] b=b[17] out=u_wallace_cla24_and_18_17
.subckt fa a=u_wallace_cla24_fa111_or0 b=u_wallace_cla24_and_19_16 cin=u_wallace_cla24_and_18_17 fa_xor1=u_wallace_cla24_fa112_xor1 fa_or0=u_wallace_cla24_fa112_or0
.subckt and_gate a=a[19] b=b[17] out=u_wallace_cla24_and_19_17
.subckt and_gate a=a[18] b=b[18] out=u_wallace_cla24_and_18_18
.subckt fa a=u_wallace_cla24_fa112_or0 b=u_wallace_cla24_and_19_17 cin=u_wallace_cla24_and_18_18 fa_xor1=u_wallace_cla24_fa113_xor1 fa_or0=u_wallace_cla24_fa113_or0
.subckt and_gate a=a[19] b=b[18] out=u_wallace_cla24_and_19_18
.subckt and_gate a=a[18] b=b[19] out=u_wallace_cla24_and_18_19
.subckt fa a=u_wallace_cla24_fa113_or0 b=u_wallace_cla24_and_19_18 cin=u_wallace_cla24_and_18_19 fa_xor1=u_wallace_cla24_fa114_xor1 fa_or0=u_wallace_cla24_fa114_or0
.subckt and_gate a=a[19] b=b[19] out=u_wallace_cla24_and_19_19
.subckt and_gate a=a[18] b=b[20] out=u_wallace_cla24_and_18_20
.subckt fa a=u_wallace_cla24_fa114_or0 b=u_wallace_cla24_and_19_19 cin=u_wallace_cla24_and_18_20 fa_xor1=u_wallace_cla24_fa115_xor1 fa_or0=u_wallace_cla24_fa115_or0
.subckt and_gate a=a[19] b=b[20] out=u_wallace_cla24_and_19_20
.subckt and_gate a=a[18] b=b[21] out=u_wallace_cla24_and_18_21
.subckt fa a=u_wallace_cla24_fa115_or0 b=u_wallace_cla24_and_19_20 cin=u_wallace_cla24_and_18_21 fa_xor1=u_wallace_cla24_fa116_xor1 fa_or0=u_wallace_cla24_fa116_or0
.subckt and_gate a=a[19] b=b[21] out=u_wallace_cla24_and_19_21
.subckt and_gate a=a[18] b=b[22] out=u_wallace_cla24_and_18_22
.subckt fa a=u_wallace_cla24_fa116_or0 b=u_wallace_cla24_and_19_21 cin=u_wallace_cla24_and_18_22 fa_xor1=u_wallace_cla24_fa117_xor1 fa_or0=u_wallace_cla24_fa117_or0
.subckt and_gate a=a[19] b=b[22] out=u_wallace_cla24_and_19_22
.subckt and_gate a=a[18] b=b[23] out=u_wallace_cla24_and_18_23
.subckt fa a=u_wallace_cla24_fa117_or0 b=u_wallace_cla24_and_19_22 cin=u_wallace_cla24_and_18_23 fa_xor1=u_wallace_cla24_fa118_xor1 fa_or0=u_wallace_cla24_fa118_or0
.subckt and_gate a=a[19] b=b[23] out=u_wallace_cla24_and_19_23
.subckt fa a=u_wallace_cla24_fa118_or0 b=u_wallace_cla24_and_19_23 cin=u_wallace_cla24_fa39_xor1 fa_xor1=u_wallace_cla24_fa119_xor1 fa_or0=u_wallace_cla24_fa119_or0
.subckt ha a=u_wallace_cla24_fa2_xor1 b=u_wallace_cla24_fa43_xor1 ha_xor0=u_wallace_cla24_ha3_xor0 ha_and0=u_wallace_cla24_ha3_and0
.subckt and_gate a=a[0] b=b[6] out=u_wallace_cla24_and_0_6
.subckt fa a=u_wallace_cla24_ha3_and0 b=u_wallace_cla24_and_0_6 cin=u_wallace_cla24_fa3_xor1 fa_xor1=u_wallace_cla24_fa120_xor1 fa_or0=u_wallace_cla24_fa120_or0
.subckt and_gate a=a[1] b=b[6] out=u_wallace_cla24_and_1_6
.subckt and_gate a=a[0] b=b[7] out=u_wallace_cla24_and_0_7
.subckt fa a=u_wallace_cla24_fa120_or0 b=u_wallace_cla24_and_1_6 cin=u_wallace_cla24_and_0_7 fa_xor1=u_wallace_cla24_fa121_xor1 fa_or0=u_wallace_cla24_fa121_or0
.subckt and_gate a=a[2] b=b[6] out=u_wallace_cla24_and_2_6
.subckt and_gate a=a[1] b=b[7] out=u_wallace_cla24_and_1_7
.subckt fa a=u_wallace_cla24_fa121_or0 b=u_wallace_cla24_and_2_6 cin=u_wallace_cla24_and_1_7 fa_xor1=u_wallace_cla24_fa122_xor1 fa_or0=u_wallace_cla24_fa122_or0
.subckt and_gate a=a[3] b=b[6] out=u_wallace_cla24_and_3_6
.subckt and_gate a=a[2] b=b[7] out=u_wallace_cla24_and_2_7
.subckt fa a=u_wallace_cla24_fa122_or0 b=u_wallace_cla24_and_3_6 cin=u_wallace_cla24_and_2_7 fa_xor1=u_wallace_cla24_fa123_xor1 fa_or0=u_wallace_cla24_fa123_or0
.subckt and_gate a=a[4] b=b[6] out=u_wallace_cla24_and_4_6
.subckt and_gate a=a[3] b=b[7] out=u_wallace_cla24_and_3_7
.subckt fa a=u_wallace_cla24_fa123_or0 b=u_wallace_cla24_and_4_6 cin=u_wallace_cla24_and_3_7 fa_xor1=u_wallace_cla24_fa124_xor1 fa_or0=u_wallace_cla24_fa124_or0
.subckt and_gate a=a[5] b=b[6] out=u_wallace_cla24_and_5_6
.subckt and_gate a=a[4] b=b[7] out=u_wallace_cla24_and_4_7
.subckt fa a=u_wallace_cla24_fa124_or0 b=u_wallace_cla24_and_5_6 cin=u_wallace_cla24_and_4_7 fa_xor1=u_wallace_cla24_fa125_xor1 fa_or0=u_wallace_cla24_fa125_or0
.subckt and_gate a=a[6] b=b[6] out=u_wallace_cla24_and_6_6
.subckt and_gate a=a[5] b=b[7] out=u_wallace_cla24_and_5_7
.subckt fa a=u_wallace_cla24_fa125_or0 b=u_wallace_cla24_and_6_6 cin=u_wallace_cla24_and_5_7 fa_xor1=u_wallace_cla24_fa126_xor1 fa_or0=u_wallace_cla24_fa126_or0
.subckt and_gate a=a[7] b=b[6] out=u_wallace_cla24_and_7_6
.subckt and_gate a=a[6] b=b[7] out=u_wallace_cla24_and_6_7
.subckt fa a=u_wallace_cla24_fa126_or0 b=u_wallace_cla24_and_7_6 cin=u_wallace_cla24_and_6_7 fa_xor1=u_wallace_cla24_fa127_xor1 fa_or0=u_wallace_cla24_fa127_or0
.subckt and_gate a=a[8] b=b[6] out=u_wallace_cla24_and_8_6
.subckt and_gate a=a[7] b=b[7] out=u_wallace_cla24_and_7_7
.subckt fa a=u_wallace_cla24_fa127_or0 b=u_wallace_cla24_and_8_6 cin=u_wallace_cla24_and_7_7 fa_xor1=u_wallace_cla24_fa128_xor1 fa_or0=u_wallace_cla24_fa128_or0
.subckt and_gate a=a[9] b=b[6] out=u_wallace_cla24_and_9_6
.subckt and_gate a=a[8] b=b[7] out=u_wallace_cla24_and_8_7
.subckt fa a=u_wallace_cla24_fa128_or0 b=u_wallace_cla24_and_9_6 cin=u_wallace_cla24_and_8_7 fa_xor1=u_wallace_cla24_fa129_xor1 fa_or0=u_wallace_cla24_fa129_or0
.subckt and_gate a=a[10] b=b[6] out=u_wallace_cla24_and_10_6
.subckt and_gate a=a[9] b=b[7] out=u_wallace_cla24_and_9_7
.subckt fa a=u_wallace_cla24_fa129_or0 b=u_wallace_cla24_and_10_6 cin=u_wallace_cla24_and_9_7 fa_xor1=u_wallace_cla24_fa130_xor1 fa_or0=u_wallace_cla24_fa130_or0
.subckt and_gate a=a[11] b=b[6] out=u_wallace_cla24_and_11_6
.subckt and_gate a=a[10] b=b[7] out=u_wallace_cla24_and_10_7
.subckt fa a=u_wallace_cla24_fa130_or0 b=u_wallace_cla24_and_11_6 cin=u_wallace_cla24_and_10_7 fa_xor1=u_wallace_cla24_fa131_xor1 fa_or0=u_wallace_cla24_fa131_or0
.subckt and_gate a=a[12] b=b[6] out=u_wallace_cla24_and_12_6
.subckt and_gate a=a[11] b=b[7] out=u_wallace_cla24_and_11_7
.subckt fa a=u_wallace_cla24_fa131_or0 b=u_wallace_cla24_and_12_6 cin=u_wallace_cla24_and_11_7 fa_xor1=u_wallace_cla24_fa132_xor1 fa_or0=u_wallace_cla24_fa132_or0
.subckt and_gate a=a[13] b=b[6] out=u_wallace_cla24_and_13_6
.subckt and_gate a=a[12] b=b[7] out=u_wallace_cla24_and_12_7
.subckt fa a=u_wallace_cla24_fa132_or0 b=u_wallace_cla24_and_13_6 cin=u_wallace_cla24_and_12_7 fa_xor1=u_wallace_cla24_fa133_xor1 fa_or0=u_wallace_cla24_fa133_or0
.subckt and_gate a=a[14] b=b[6] out=u_wallace_cla24_and_14_6
.subckt and_gate a=a[13] b=b[7] out=u_wallace_cla24_and_13_7
.subckt fa a=u_wallace_cla24_fa133_or0 b=u_wallace_cla24_and_14_6 cin=u_wallace_cla24_and_13_7 fa_xor1=u_wallace_cla24_fa134_xor1 fa_or0=u_wallace_cla24_fa134_or0
.subckt and_gate a=a[15] b=b[6] out=u_wallace_cla24_and_15_6
.subckt and_gate a=a[14] b=b[7] out=u_wallace_cla24_and_14_7
.subckt fa a=u_wallace_cla24_fa134_or0 b=u_wallace_cla24_and_15_6 cin=u_wallace_cla24_and_14_7 fa_xor1=u_wallace_cla24_fa135_xor1 fa_or0=u_wallace_cla24_fa135_or0
.subckt and_gate a=a[16] b=b[6] out=u_wallace_cla24_and_16_6
.subckt and_gate a=a[15] b=b[7] out=u_wallace_cla24_and_15_7
.subckt fa a=u_wallace_cla24_fa135_or0 b=u_wallace_cla24_and_16_6 cin=u_wallace_cla24_and_15_7 fa_xor1=u_wallace_cla24_fa136_xor1 fa_or0=u_wallace_cla24_fa136_or0
.subckt and_gate a=a[17] b=b[6] out=u_wallace_cla24_and_17_6
.subckt and_gate a=a[16] b=b[7] out=u_wallace_cla24_and_16_7
.subckt fa a=u_wallace_cla24_fa136_or0 b=u_wallace_cla24_and_17_6 cin=u_wallace_cla24_and_16_7 fa_xor1=u_wallace_cla24_fa137_xor1 fa_or0=u_wallace_cla24_fa137_or0
.subckt and_gate a=a[17] b=b[7] out=u_wallace_cla24_and_17_7
.subckt and_gate a=a[16] b=b[8] out=u_wallace_cla24_and_16_8
.subckt fa a=u_wallace_cla24_fa137_or0 b=u_wallace_cla24_and_17_7 cin=u_wallace_cla24_and_16_8 fa_xor1=u_wallace_cla24_fa138_xor1 fa_or0=u_wallace_cla24_fa138_or0
.subckt and_gate a=a[17] b=b[8] out=u_wallace_cla24_and_17_8
.subckt and_gate a=a[16] b=b[9] out=u_wallace_cla24_and_16_9
.subckt fa a=u_wallace_cla24_fa138_or0 b=u_wallace_cla24_and_17_8 cin=u_wallace_cla24_and_16_9 fa_xor1=u_wallace_cla24_fa139_xor1 fa_or0=u_wallace_cla24_fa139_or0
.subckt and_gate a=a[17] b=b[9] out=u_wallace_cla24_and_17_9
.subckt and_gate a=a[16] b=b[10] out=u_wallace_cla24_and_16_10
.subckt fa a=u_wallace_cla24_fa139_or0 b=u_wallace_cla24_and_17_9 cin=u_wallace_cla24_and_16_10 fa_xor1=u_wallace_cla24_fa140_xor1 fa_or0=u_wallace_cla24_fa140_or0
.subckt and_gate a=a[17] b=b[10] out=u_wallace_cla24_and_17_10
.subckt and_gate a=a[16] b=b[11] out=u_wallace_cla24_and_16_11
.subckt fa a=u_wallace_cla24_fa140_or0 b=u_wallace_cla24_and_17_10 cin=u_wallace_cla24_and_16_11 fa_xor1=u_wallace_cla24_fa141_xor1 fa_or0=u_wallace_cla24_fa141_or0
.subckt and_gate a=a[17] b=b[11] out=u_wallace_cla24_and_17_11
.subckt and_gate a=a[16] b=b[12] out=u_wallace_cla24_and_16_12
.subckt fa a=u_wallace_cla24_fa141_or0 b=u_wallace_cla24_and_17_11 cin=u_wallace_cla24_and_16_12 fa_xor1=u_wallace_cla24_fa142_xor1 fa_or0=u_wallace_cla24_fa142_or0
.subckt and_gate a=a[17] b=b[12] out=u_wallace_cla24_and_17_12
.subckt and_gate a=a[16] b=b[13] out=u_wallace_cla24_and_16_13
.subckt fa a=u_wallace_cla24_fa142_or0 b=u_wallace_cla24_and_17_12 cin=u_wallace_cla24_and_16_13 fa_xor1=u_wallace_cla24_fa143_xor1 fa_or0=u_wallace_cla24_fa143_or0
.subckt and_gate a=a[17] b=b[13] out=u_wallace_cla24_and_17_13
.subckt and_gate a=a[16] b=b[14] out=u_wallace_cla24_and_16_14
.subckt fa a=u_wallace_cla24_fa143_or0 b=u_wallace_cla24_and_17_13 cin=u_wallace_cla24_and_16_14 fa_xor1=u_wallace_cla24_fa144_xor1 fa_or0=u_wallace_cla24_fa144_or0
.subckt and_gate a=a[17] b=b[14] out=u_wallace_cla24_and_17_14
.subckt and_gate a=a[16] b=b[15] out=u_wallace_cla24_and_16_15
.subckt fa a=u_wallace_cla24_fa144_or0 b=u_wallace_cla24_and_17_14 cin=u_wallace_cla24_and_16_15 fa_xor1=u_wallace_cla24_fa145_xor1 fa_or0=u_wallace_cla24_fa145_or0
.subckt and_gate a=a[17] b=b[15] out=u_wallace_cla24_and_17_15
.subckt and_gate a=a[16] b=b[16] out=u_wallace_cla24_and_16_16
.subckt fa a=u_wallace_cla24_fa145_or0 b=u_wallace_cla24_and_17_15 cin=u_wallace_cla24_and_16_16 fa_xor1=u_wallace_cla24_fa146_xor1 fa_or0=u_wallace_cla24_fa146_or0
.subckt and_gate a=a[17] b=b[16] out=u_wallace_cla24_and_17_16
.subckt and_gate a=a[16] b=b[17] out=u_wallace_cla24_and_16_17
.subckt fa a=u_wallace_cla24_fa146_or0 b=u_wallace_cla24_and_17_16 cin=u_wallace_cla24_and_16_17 fa_xor1=u_wallace_cla24_fa147_xor1 fa_or0=u_wallace_cla24_fa147_or0
.subckt and_gate a=a[17] b=b[17] out=u_wallace_cla24_and_17_17
.subckt and_gate a=a[16] b=b[18] out=u_wallace_cla24_and_16_18
.subckt fa a=u_wallace_cla24_fa147_or0 b=u_wallace_cla24_and_17_17 cin=u_wallace_cla24_and_16_18 fa_xor1=u_wallace_cla24_fa148_xor1 fa_or0=u_wallace_cla24_fa148_or0
.subckt and_gate a=a[17] b=b[18] out=u_wallace_cla24_and_17_18
.subckt and_gate a=a[16] b=b[19] out=u_wallace_cla24_and_16_19
.subckt fa a=u_wallace_cla24_fa148_or0 b=u_wallace_cla24_and_17_18 cin=u_wallace_cla24_and_16_19 fa_xor1=u_wallace_cla24_fa149_xor1 fa_or0=u_wallace_cla24_fa149_or0
.subckt and_gate a=a[17] b=b[19] out=u_wallace_cla24_and_17_19
.subckt and_gate a=a[16] b=b[20] out=u_wallace_cla24_and_16_20
.subckt fa a=u_wallace_cla24_fa149_or0 b=u_wallace_cla24_and_17_19 cin=u_wallace_cla24_and_16_20 fa_xor1=u_wallace_cla24_fa150_xor1 fa_or0=u_wallace_cla24_fa150_or0
.subckt and_gate a=a[17] b=b[20] out=u_wallace_cla24_and_17_20
.subckt and_gate a=a[16] b=b[21] out=u_wallace_cla24_and_16_21
.subckt fa a=u_wallace_cla24_fa150_or0 b=u_wallace_cla24_and_17_20 cin=u_wallace_cla24_and_16_21 fa_xor1=u_wallace_cla24_fa151_xor1 fa_or0=u_wallace_cla24_fa151_or0
.subckt and_gate a=a[17] b=b[21] out=u_wallace_cla24_and_17_21
.subckt and_gate a=a[16] b=b[22] out=u_wallace_cla24_and_16_22
.subckt fa a=u_wallace_cla24_fa151_or0 b=u_wallace_cla24_and_17_21 cin=u_wallace_cla24_and_16_22 fa_xor1=u_wallace_cla24_fa152_xor1 fa_or0=u_wallace_cla24_fa152_or0
.subckt and_gate a=a[17] b=b[22] out=u_wallace_cla24_and_17_22
.subckt and_gate a=a[16] b=b[23] out=u_wallace_cla24_and_16_23
.subckt fa a=u_wallace_cla24_fa152_or0 b=u_wallace_cla24_and_17_22 cin=u_wallace_cla24_and_16_23 fa_xor1=u_wallace_cla24_fa153_xor1 fa_or0=u_wallace_cla24_fa153_or0
.subckt and_gate a=a[17] b=b[23] out=u_wallace_cla24_and_17_23
.subckt fa a=u_wallace_cla24_fa153_or0 b=u_wallace_cla24_and_17_23 cin=u_wallace_cla24_fa37_xor1 fa_xor1=u_wallace_cla24_fa154_xor1 fa_or0=u_wallace_cla24_fa154_or0
.subckt fa a=u_wallace_cla24_fa154_or0 b=u_wallace_cla24_fa38_xor1 cin=u_wallace_cla24_fa79_xor1 fa_xor1=u_wallace_cla24_fa155_xor1 fa_or0=u_wallace_cla24_fa155_or0
.subckt ha a=u_wallace_cla24_fa44_xor1 b=u_wallace_cla24_fa83_xor1 ha_xor0=u_wallace_cla24_ha4_xor0 ha_and0=u_wallace_cla24_ha4_and0
.subckt fa a=u_wallace_cla24_ha4_and0 b=u_wallace_cla24_fa4_xor1 cin=u_wallace_cla24_fa45_xor1 fa_xor1=u_wallace_cla24_fa156_xor1 fa_or0=u_wallace_cla24_fa156_or0
.subckt and_gate a=a[0] b=b[8] out=u_wallace_cla24_and_0_8
.subckt fa a=u_wallace_cla24_fa156_or0 b=u_wallace_cla24_and_0_8 cin=u_wallace_cla24_fa5_xor1 fa_xor1=u_wallace_cla24_fa157_xor1 fa_or0=u_wallace_cla24_fa157_or0
.subckt and_gate a=a[1] b=b[8] out=u_wallace_cla24_and_1_8
.subckt and_gate a=a[0] b=b[9] out=u_wallace_cla24_and_0_9
.subckt fa a=u_wallace_cla24_fa157_or0 b=u_wallace_cla24_and_1_8 cin=u_wallace_cla24_and_0_9 fa_xor1=u_wallace_cla24_fa158_xor1 fa_or0=u_wallace_cla24_fa158_or0
.subckt and_gate a=a[2] b=b[8] out=u_wallace_cla24_and_2_8
.subckt and_gate a=a[1] b=b[9] out=u_wallace_cla24_and_1_9
.subckt fa a=u_wallace_cla24_fa158_or0 b=u_wallace_cla24_and_2_8 cin=u_wallace_cla24_and_1_9 fa_xor1=u_wallace_cla24_fa159_xor1 fa_or0=u_wallace_cla24_fa159_or0
.subckt and_gate a=a[3] b=b[8] out=u_wallace_cla24_and_3_8
.subckt and_gate a=a[2] b=b[9] out=u_wallace_cla24_and_2_9
.subckt fa a=u_wallace_cla24_fa159_or0 b=u_wallace_cla24_and_3_8 cin=u_wallace_cla24_and_2_9 fa_xor1=u_wallace_cla24_fa160_xor1 fa_or0=u_wallace_cla24_fa160_or0
.subckt and_gate a=a[4] b=b[8] out=u_wallace_cla24_and_4_8
.subckt and_gate a=a[3] b=b[9] out=u_wallace_cla24_and_3_9
.subckt fa a=u_wallace_cla24_fa160_or0 b=u_wallace_cla24_and_4_8 cin=u_wallace_cla24_and_3_9 fa_xor1=u_wallace_cla24_fa161_xor1 fa_or0=u_wallace_cla24_fa161_or0
.subckt and_gate a=a[5] b=b[8] out=u_wallace_cla24_and_5_8
.subckt and_gate a=a[4] b=b[9] out=u_wallace_cla24_and_4_9
.subckt fa a=u_wallace_cla24_fa161_or0 b=u_wallace_cla24_and_5_8 cin=u_wallace_cla24_and_4_9 fa_xor1=u_wallace_cla24_fa162_xor1 fa_or0=u_wallace_cla24_fa162_or0
.subckt and_gate a=a[6] b=b[8] out=u_wallace_cla24_and_6_8
.subckt and_gate a=a[5] b=b[9] out=u_wallace_cla24_and_5_9
.subckt fa a=u_wallace_cla24_fa162_or0 b=u_wallace_cla24_and_6_8 cin=u_wallace_cla24_and_5_9 fa_xor1=u_wallace_cla24_fa163_xor1 fa_or0=u_wallace_cla24_fa163_or0
.subckt and_gate a=a[7] b=b[8] out=u_wallace_cla24_and_7_8
.subckt and_gate a=a[6] b=b[9] out=u_wallace_cla24_and_6_9
.subckt fa a=u_wallace_cla24_fa163_or0 b=u_wallace_cla24_and_7_8 cin=u_wallace_cla24_and_6_9 fa_xor1=u_wallace_cla24_fa164_xor1 fa_or0=u_wallace_cla24_fa164_or0
.subckt and_gate a=a[8] b=b[8] out=u_wallace_cla24_and_8_8
.subckt and_gate a=a[7] b=b[9] out=u_wallace_cla24_and_7_9
.subckt fa a=u_wallace_cla24_fa164_or0 b=u_wallace_cla24_and_8_8 cin=u_wallace_cla24_and_7_9 fa_xor1=u_wallace_cla24_fa165_xor1 fa_or0=u_wallace_cla24_fa165_or0
.subckt and_gate a=a[9] b=b[8] out=u_wallace_cla24_and_9_8
.subckt and_gate a=a[8] b=b[9] out=u_wallace_cla24_and_8_9
.subckt fa a=u_wallace_cla24_fa165_or0 b=u_wallace_cla24_and_9_8 cin=u_wallace_cla24_and_8_9 fa_xor1=u_wallace_cla24_fa166_xor1 fa_or0=u_wallace_cla24_fa166_or0
.subckt and_gate a=a[10] b=b[8] out=u_wallace_cla24_and_10_8
.subckt and_gate a=a[9] b=b[9] out=u_wallace_cla24_and_9_9
.subckt fa a=u_wallace_cla24_fa166_or0 b=u_wallace_cla24_and_10_8 cin=u_wallace_cla24_and_9_9 fa_xor1=u_wallace_cla24_fa167_xor1 fa_or0=u_wallace_cla24_fa167_or0
.subckt and_gate a=a[11] b=b[8] out=u_wallace_cla24_and_11_8
.subckt and_gate a=a[10] b=b[9] out=u_wallace_cla24_and_10_9
.subckt fa a=u_wallace_cla24_fa167_or0 b=u_wallace_cla24_and_11_8 cin=u_wallace_cla24_and_10_9 fa_xor1=u_wallace_cla24_fa168_xor1 fa_or0=u_wallace_cla24_fa168_or0
.subckt and_gate a=a[12] b=b[8] out=u_wallace_cla24_and_12_8
.subckt and_gate a=a[11] b=b[9] out=u_wallace_cla24_and_11_9
.subckt fa a=u_wallace_cla24_fa168_or0 b=u_wallace_cla24_and_12_8 cin=u_wallace_cla24_and_11_9 fa_xor1=u_wallace_cla24_fa169_xor1 fa_or0=u_wallace_cla24_fa169_or0
.subckt and_gate a=a[13] b=b[8] out=u_wallace_cla24_and_13_8
.subckt and_gate a=a[12] b=b[9] out=u_wallace_cla24_and_12_9
.subckt fa a=u_wallace_cla24_fa169_or0 b=u_wallace_cla24_and_13_8 cin=u_wallace_cla24_and_12_9 fa_xor1=u_wallace_cla24_fa170_xor1 fa_or0=u_wallace_cla24_fa170_or0
.subckt and_gate a=a[14] b=b[8] out=u_wallace_cla24_and_14_8
.subckt and_gate a=a[13] b=b[9] out=u_wallace_cla24_and_13_9
.subckt fa a=u_wallace_cla24_fa170_or0 b=u_wallace_cla24_and_14_8 cin=u_wallace_cla24_and_13_9 fa_xor1=u_wallace_cla24_fa171_xor1 fa_or0=u_wallace_cla24_fa171_or0
.subckt and_gate a=a[15] b=b[8] out=u_wallace_cla24_and_15_8
.subckt and_gate a=a[14] b=b[9] out=u_wallace_cla24_and_14_9
.subckt fa a=u_wallace_cla24_fa171_or0 b=u_wallace_cla24_and_15_8 cin=u_wallace_cla24_and_14_9 fa_xor1=u_wallace_cla24_fa172_xor1 fa_or0=u_wallace_cla24_fa172_or0
.subckt and_gate a=a[15] b=b[9] out=u_wallace_cla24_and_15_9
.subckt and_gate a=a[14] b=b[10] out=u_wallace_cla24_and_14_10
.subckt fa a=u_wallace_cla24_fa172_or0 b=u_wallace_cla24_and_15_9 cin=u_wallace_cla24_and_14_10 fa_xor1=u_wallace_cla24_fa173_xor1 fa_or0=u_wallace_cla24_fa173_or0
.subckt and_gate a=a[15] b=b[10] out=u_wallace_cla24_and_15_10
.subckt and_gate a=a[14] b=b[11] out=u_wallace_cla24_and_14_11
.subckt fa a=u_wallace_cla24_fa173_or0 b=u_wallace_cla24_and_15_10 cin=u_wallace_cla24_and_14_11 fa_xor1=u_wallace_cla24_fa174_xor1 fa_or0=u_wallace_cla24_fa174_or0
.subckt and_gate a=a[15] b=b[11] out=u_wallace_cla24_and_15_11
.subckt and_gate a=a[14] b=b[12] out=u_wallace_cla24_and_14_12
.subckt fa a=u_wallace_cla24_fa174_or0 b=u_wallace_cla24_and_15_11 cin=u_wallace_cla24_and_14_12 fa_xor1=u_wallace_cla24_fa175_xor1 fa_or0=u_wallace_cla24_fa175_or0
.subckt and_gate a=a[15] b=b[12] out=u_wallace_cla24_and_15_12
.subckt and_gate a=a[14] b=b[13] out=u_wallace_cla24_and_14_13
.subckt fa a=u_wallace_cla24_fa175_or0 b=u_wallace_cla24_and_15_12 cin=u_wallace_cla24_and_14_13 fa_xor1=u_wallace_cla24_fa176_xor1 fa_or0=u_wallace_cla24_fa176_or0
.subckt and_gate a=a[15] b=b[13] out=u_wallace_cla24_and_15_13
.subckt and_gate a=a[14] b=b[14] out=u_wallace_cla24_and_14_14
.subckt fa a=u_wallace_cla24_fa176_or0 b=u_wallace_cla24_and_15_13 cin=u_wallace_cla24_and_14_14 fa_xor1=u_wallace_cla24_fa177_xor1 fa_or0=u_wallace_cla24_fa177_or0
.subckt and_gate a=a[15] b=b[14] out=u_wallace_cla24_and_15_14
.subckt and_gate a=a[14] b=b[15] out=u_wallace_cla24_and_14_15
.subckt fa a=u_wallace_cla24_fa177_or0 b=u_wallace_cla24_and_15_14 cin=u_wallace_cla24_and_14_15 fa_xor1=u_wallace_cla24_fa178_xor1 fa_or0=u_wallace_cla24_fa178_or0
.subckt and_gate a=a[15] b=b[15] out=u_wallace_cla24_and_15_15
.subckt and_gate a=a[14] b=b[16] out=u_wallace_cla24_and_14_16
.subckt fa a=u_wallace_cla24_fa178_or0 b=u_wallace_cla24_and_15_15 cin=u_wallace_cla24_and_14_16 fa_xor1=u_wallace_cla24_fa179_xor1 fa_or0=u_wallace_cla24_fa179_or0
.subckt and_gate a=a[15] b=b[16] out=u_wallace_cla24_and_15_16
.subckt and_gate a=a[14] b=b[17] out=u_wallace_cla24_and_14_17
.subckt fa a=u_wallace_cla24_fa179_or0 b=u_wallace_cla24_and_15_16 cin=u_wallace_cla24_and_14_17 fa_xor1=u_wallace_cla24_fa180_xor1 fa_or0=u_wallace_cla24_fa180_or0
.subckt and_gate a=a[15] b=b[17] out=u_wallace_cla24_and_15_17
.subckt and_gate a=a[14] b=b[18] out=u_wallace_cla24_and_14_18
.subckt fa a=u_wallace_cla24_fa180_or0 b=u_wallace_cla24_and_15_17 cin=u_wallace_cla24_and_14_18 fa_xor1=u_wallace_cla24_fa181_xor1 fa_or0=u_wallace_cla24_fa181_or0
.subckt and_gate a=a[15] b=b[18] out=u_wallace_cla24_and_15_18
.subckt and_gate a=a[14] b=b[19] out=u_wallace_cla24_and_14_19
.subckt fa a=u_wallace_cla24_fa181_or0 b=u_wallace_cla24_and_15_18 cin=u_wallace_cla24_and_14_19 fa_xor1=u_wallace_cla24_fa182_xor1 fa_or0=u_wallace_cla24_fa182_or0
.subckt and_gate a=a[15] b=b[19] out=u_wallace_cla24_and_15_19
.subckt and_gate a=a[14] b=b[20] out=u_wallace_cla24_and_14_20
.subckt fa a=u_wallace_cla24_fa182_or0 b=u_wallace_cla24_and_15_19 cin=u_wallace_cla24_and_14_20 fa_xor1=u_wallace_cla24_fa183_xor1 fa_or0=u_wallace_cla24_fa183_or0
.subckt and_gate a=a[15] b=b[20] out=u_wallace_cla24_and_15_20
.subckt and_gate a=a[14] b=b[21] out=u_wallace_cla24_and_14_21
.subckt fa a=u_wallace_cla24_fa183_or0 b=u_wallace_cla24_and_15_20 cin=u_wallace_cla24_and_14_21 fa_xor1=u_wallace_cla24_fa184_xor1 fa_or0=u_wallace_cla24_fa184_or0
.subckt and_gate a=a[15] b=b[21] out=u_wallace_cla24_and_15_21
.subckt and_gate a=a[14] b=b[22] out=u_wallace_cla24_and_14_22
.subckt fa a=u_wallace_cla24_fa184_or0 b=u_wallace_cla24_and_15_21 cin=u_wallace_cla24_and_14_22 fa_xor1=u_wallace_cla24_fa185_xor1 fa_or0=u_wallace_cla24_fa185_or0
.subckt and_gate a=a[15] b=b[22] out=u_wallace_cla24_and_15_22
.subckt and_gate a=a[14] b=b[23] out=u_wallace_cla24_and_14_23
.subckt fa a=u_wallace_cla24_fa185_or0 b=u_wallace_cla24_and_15_22 cin=u_wallace_cla24_and_14_23 fa_xor1=u_wallace_cla24_fa186_xor1 fa_or0=u_wallace_cla24_fa186_or0
.subckt and_gate a=a[15] b=b[23] out=u_wallace_cla24_and_15_23
.subckt fa a=u_wallace_cla24_fa186_or0 b=u_wallace_cla24_and_15_23 cin=u_wallace_cla24_fa35_xor1 fa_xor1=u_wallace_cla24_fa187_xor1 fa_or0=u_wallace_cla24_fa187_or0
.subckt fa a=u_wallace_cla24_fa187_or0 b=u_wallace_cla24_fa36_xor1 cin=u_wallace_cla24_fa77_xor1 fa_xor1=u_wallace_cla24_fa188_xor1 fa_or0=u_wallace_cla24_fa188_or0
.subckt fa a=u_wallace_cla24_fa188_or0 b=u_wallace_cla24_fa78_xor1 cin=u_wallace_cla24_fa117_xor1 fa_xor1=u_wallace_cla24_fa189_xor1 fa_or0=u_wallace_cla24_fa189_or0
.subckt ha a=u_wallace_cla24_fa84_xor1 b=u_wallace_cla24_fa121_xor1 ha_xor0=u_wallace_cla24_ha5_xor0 ha_and0=u_wallace_cla24_ha5_and0
.subckt fa a=u_wallace_cla24_ha5_and0 b=u_wallace_cla24_fa46_xor1 cin=u_wallace_cla24_fa85_xor1 fa_xor1=u_wallace_cla24_fa190_xor1 fa_or0=u_wallace_cla24_fa190_or0
.subckt fa a=u_wallace_cla24_fa190_or0 b=u_wallace_cla24_fa6_xor1 cin=u_wallace_cla24_fa47_xor1 fa_xor1=u_wallace_cla24_fa191_xor1 fa_or0=u_wallace_cla24_fa191_or0
.subckt and_gate a=a[0] b=b[10] out=u_wallace_cla24_and_0_10
.subckt fa a=u_wallace_cla24_fa191_or0 b=u_wallace_cla24_and_0_10 cin=u_wallace_cla24_fa7_xor1 fa_xor1=u_wallace_cla24_fa192_xor1 fa_or0=u_wallace_cla24_fa192_or0
.subckt and_gate a=a[1] b=b[10] out=u_wallace_cla24_and_1_10
.subckt and_gate a=a[0] b=b[11] out=u_wallace_cla24_and_0_11
.subckt fa a=u_wallace_cla24_fa192_or0 b=u_wallace_cla24_and_1_10 cin=u_wallace_cla24_and_0_11 fa_xor1=u_wallace_cla24_fa193_xor1 fa_or0=u_wallace_cla24_fa193_or0
.subckt and_gate a=a[2] b=b[10] out=u_wallace_cla24_and_2_10
.subckt and_gate a=a[1] b=b[11] out=u_wallace_cla24_and_1_11
.subckt fa a=u_wallace_cla24_fa193_or0 b=u_wallace_cla24_and_2_10 cin=u_wallace_cla24_and_1_11 fa_xor1=u_wallace_cla24_fa194_xor1 fa_or0=u_wallace_cla24_fa194_or0
.subckt and_gate a=a[3] b=b[10] out=u_wallace_cla24_and_3_10
.subckt and_gate a=a[2] b=b[11] out=u_wallace_cla24_and_2_11
.subckt fa a=u_wallace_cla24_fa194_or0 b=u_wallace_cla24_and_3_10 cin=u_wallace_cla24_and_2_11 fa_xor1=u_wallace_cla24_fa195_xor1 fa_or0=u_wallace_cla24_fa195_or0
.subckt and_gate a=a[4] b=b[10] out=u_wallace_cla24_and_4_10
.subckt and_gate a=a[3] b=b[11] out=u_wallace_cla24_and_3_11
.subckt fa a=u_wallace_cla24_fa195_or0 b=u_wallace_cla24_and_4_10 cin=u_wallace_cla24_and_3_11 fa_xor1=u_wallace_cla24_fa196_xor1 fa_or0=u_wallace_cla24_fa196_or0
.subckt and_gate a=a[5] b=b[10] out=u_wallace_cla24_and_5_10
.subckt and_gate a=a[4] b=b[11] out=u_wallace_cla24_and_4_11
.subckt fa a=u_wallace_cla24_fa196_or0 b=u_wallace_cla24_and_5_10 cin=u_wallace_cla24_and_4_11 fa_xor1=u_wallace_cla24_fa197_xor1 fa_or0=u_wallace_cla24_fa197_or0
.subckt and_gate a=a[6] b=b[10] out=u_wallace_cla24_and_6_10
.subckt and_gate a=a[5] b=b[11] out=u_wallace_cla24_and_5_11
.subckt fa a=u_wallace_cla24_fa197_or0 b=u_wallace_cla24_and_6_10 cin=u_wallace_cla24_and_5_11 fa_xor1=u_wallace_cla24_fa198_xor1 fa_or0=u_wallace_cla24_fa198_or0
.subckt and_gate a=a[7] b=b[10] out=u_wallace_cla24_and_7_10
.subckt and_gate a=a[6] b=b[11] out=u_wallace_cla24_and_6_11
.subckt fa a=u_wallace_cla24_fa198_or0 b=u_wallace_cla24_and_7_10 cin=u_wallace_cla24_and_6_11 fa_xor1=u_wallace_cla24_fa199_xor1 fa_or0=u_wallace_cla24_fa199_or0
.subckt and_gate a=a[8] b=b[10] out=u_wallace_cla24_and_8_10
.subckt and_gate a=a[7] b=b[11] out=u_wallace_cla24_and_7_11
.subckt fa a=u_wallace_cla24_fa199_or0 b=u_wallace_cla24_and_8_10 cin=u_wallace_cla24_and_7_11 fa_xor1=u_wallace_cla24_fa200_xor1 fa_or0=u_wallace_cla24_fa200_or0
.subckt and_gate a=a[9] b=b[10] out=u_wallace_cla24_and_9_10
.subckt and_gate a=a[8] b=b[11] out=u_wallace_cla24_and_8_11
.subckt fa a=u_wallace_cla24_fa200_or0 b=u_wallace_cla24_and_9_10 cin=u_wallace_cla24_and_8_11 fa_xor1=u_wallace_cla24_fa201_xor1 fa_or0=u_wallace_cla24_fa201_or0
.subckt and_gate a=a[10] b=b[10] out=u_wallace_cla24_and_10_10
.subckt and_gate a=a[9] b=b[11] out=u_wallace_cla24_and_9_11
.subckt fa a=u_wallace_cla24_fa201_or0 b=u_wallace_cla24_and_10_10 cin=u_wallace_cla24_and_9_11 fa_xor1=u_wallace_cla24_fa202_xor1 fa_or0=u_wallace_cla24_fa202_or0
.subckt and_gate a=a[11] b=b[10] out=u_wallace_cla24_and_11_10
.subckt and_gate a=a[10] b=b[11] out=u_wallace_cla24_and_10_11
.subckt fa a=u_wallace_cla24_fa202_or0 b=u_wallace_cla24_and_11_10 cin=u_wallace_cla24_and_10_11 fa_xor1=u_wallace_cla24_fa203_xor1 fa_or0=u_wallace_cla24_fa203_or0
.subckt and_gate a=a[12] b=b[10] out=u_wallace_cla24_and_12_10
.subckt and_gate a=a[11] b=b[11] out=u_wallace_cla24_and_11_11
.subckt fa a=u_wallace_cla24_fa203_or0 b=u_wallace_cla24_and_12_10 cin=u_wallace_cla24_and_11_11 fa_xor1=u_wallace_cla24_fa204_xor1 fa_or0=u_wallace_cla24_fa204_or0
.subckt and_gate a=a[13] b=b[10] out=u_wallace_cla24_and_13_10
.subckt and_gate a=a[12] b=b[11] out=u_wallace_cla24_and_12_11
.subckt fa a=u_wallace_cla24_fa204_or0 b=u_wallace_cla24_and_13_10 cin=u_wallace_cla24_and_12_11 fa_xor1=u_wallace_cla24_fa205_xor1 fa_or0=u_wallace_cla24_fa205_or0
.subckt and_gate a=a[13] b=b[11] out=u_wallace_cla24_and_13_11
.subckt and_gate a=a[12] b=b[12] out=u_wallace_cla24_and_12_12
.subckt fa a=u_wallace_cla24_fa205_or0 b=u_wallace_cla24_and_13_11 cin=u_wallace_cla24_and_12_12 fa_xor1=u_wallace_cla24_fa206_xor1 fa_or0=u_wallace_cla24_fa206_or0
.subckt and_gate a=a[13] b=b[12] out=u_wallace_cla24_and_13_12
.subckt and_gate a=a[12] b=b[13] out=u_wallace_cla24_and_12_13
.subckt fa a=u_wallace_cla24_fa206_or0 b=u_wallace_cla24_and_13_12 cin=u_wallace_cla24_and_12_13 fa_xor1=u_wallace_cla24_fa207_xor1 fa_or0=u_wallace_cla24_fa207_or0
.subckt and_gate a=a[13] b=b[13] out=u_wallace_cla24_and_13_13
.subckt and_gate a=a[12] b=b[14] out=u_wallace_cla24_and_12_14
.subckt fa a=u_wallace_cla24_fa207_or0 b=u_wallace_cla24_and_13_13 cin=u_wallace_cla24_and_12_14 fa_xor1=u_wallace_cla24_fa208_xor1 fa_or0=u_wallace_cla24_fa208_or0
.subckt and_gate a=a[13] b=b[14] out=u_wallace_cla24_and_13_14
.subckt and_gate a=a[12] b=b[15] out=u_wallace_cla24_and_12_15
.subckt fa a=u_wallace_cla24_fa208_or0 b=u_wallace_cla24_and_13_14 cin=u_wallace_cla24_and_12_15 fa_xor1=u_wallace_cla24_fa209_xor1 fa_or0=u_wallace_cla24_fa209_or0
.subckt and_gate a=a[13] b=b[15] out=u_wallace_cla24_and_13_15
.subckt and_gate a=a[12] b=b[16] out=u_wallace_cla24_and_12_16
.subckt fa a=u_wallace_cla24_fa209_or0 b=u_wallace_cla24_and_13_15 cin=u_wallace_cla24_and_12_16 fa_xor1=u_wallace_cla24_fa210_xor1 fa_or0=u_wallace_cla24_fa210_or0
.subckt and_gate a=a[13] b=b[16] out=u_wallace_cla24_and_13_16
.subckt and_gate a=a[12] b=b[17] out=u_wallace_cla24_and_12_17
.subckt fa a=u_wallace_cla24_fa210_or0 b=u_wallace_cla24_and_13_16 cin=u_wallace_cla24_and_12_17 fa_xor1=u_wallace_cla24_fa211_xor1 fa_or0=u_wallace_cla24_fa211_or0
.subckt and_gate a=a[13] b=b[17] out=u_wallace_cla24_and_13_17
.subckt and_gate a=a[12] b=b[18] out=u_wallace_cla24_and_12_18
.subckt fa a=u_wallace_cla24_fa211_or0 b=u_wallace_cla24_and_13_17 cin=u_wallace_cla24_and_12_18 fa_xor1=u_wallace_cla24_fa212_xor1 fa_or0=u_wallace_cla24_fa212_or0
.subckt and_gate a=a[13] b=b[18] out=u_wallace_cla24_and_13_18
.subckt and_gate a=a[12] b=b[19] out=u_wallace_cla24_and_12_19
.subckt fa a=u_wallace_cla24_fa212_or0 b=u_wallace_cla24_and_13_18 cin=u_wallace_cla24_and_12_19 fa_xor1=u_wallace_cla24_fa213_xor1 fa_or0=u_wallace_cla24_fa213_or0
.subckt and_gate a=a[13] b=b[19] out=u_wallace_cla24_and_13_19
.subckt and_gate a=a[12] b=b[20] out=u_wallace_cla24_and_12_20
.subckt fa a=u_wallace_cla24_fa213_or0 b=u_wallace_cla24_and_13_19 cin=u_wallace_cla24_and_12_20 fa_xor1=u_wallace_cla24_fa214_xor1 fa_or0=u_wallace_cla24_fa214_or0
.subckt and_gate a=a[13] b=b[20] out=u_wallace_cla24_and_13_20
.subckt and_gate a=a[12] b=b[21] out=u_wallace_cla24_and_12_21
.subckt fa a=u_wallace_cla24_fa214_or0 b=u_wallace_cla24_and_13_20 cin=u_wallace_cla24_and_12_21 fa_xor1=u_wallace_cla24_fa215_xor1 fa_or0=u_wallace_cla24_fa215_or0
.subckt and_gate a=a[13] b=b[21] out=u_wallace_cla24_and_13_21
.subckt and_gate a=a[12] b=b[22] out=u_wallace_cla24_and_12_22
.subckt fa a=u_wallace_cla24_fa215_or0 b=u_wallace_cla24_and_13_21 cin=u_wallace_cla24_and_12_22 fa_xor1=u_wallace_cla24_fa216_xor1 fa_or0=u_wallace_cla24_fa216_or0
.subckt and_gate a=a[13] b=b[22] out=u_wallace_cla24_and_13_22
.subckt and_gate a=a[12] b=b[23] out=u_wallace_cla24_and_12_23
.subckt fa a=u_wallace_cla24_fa216_or0 b=u_wallace_cla24_and_13_22 cin=u_wallace_cla24_and_12_23 fa_xor1=u_wallace_cla24_fa217_xor1 fa_or0=u_wallace_cla24_fa217_or0
.subckt and_gate a=a[13] b=b[23] out=u_wallace_cla24_and_13_23
.subckt fa a=u_wallace_cla24_fa217_or0 b=u_wallace_cla24_and_13_23 cin=u_wallace_cla24_fa33_xor1 fa_xor1=u_wallace_cla24_fa218_xor1 fa_or0=u_wallace_cla24_fa218_or0
.subckt fa a=u_wallace_cla24_fa218_or0 b=u_wallace_cla24_fa34_xor1 cin=u_wallace_cla24_fa75_xor1 fa_xor1=u_wallace_cla24_fa219_xor1 fa_or0=u_wallace_cla24_fa219_or0
.subckt fa a=u_wallace_cla24_fa219_or0 b=u_wallace_cla24_fa76_xor1 cin=u_wallace_cla24_fa115_xor1 fa_xor1=u_wallace_cla24_fa220_xor1 fa_or0=u_wallace_cla24_fa220_or0
.subckt fa a=u_wallace_cla24_fa220_or0 b=u_wallace_cla24_fa116_xor1 cin=u_wallace_cla24_fa153_xor1 fa_xor1=u_wallace_cla24_fa221_xor1 fa_or0=u_wallace_cla24_fa221_or0
.subckt ha a=u_wallace_cla24_fa122_xor1 b=u_wallace_cla24_fa157_xor1 ha_xor0=u_wallace_cla24_ha6_xor0 ha_and0=u_wallace_cla24_ha6_and0
.subckt fa a=u_wallace_cla24_ha6_and0 b=u_wallace_cla24_fa86_xor1 cin=u_wallace_cla24_fa123_xor1 fa_xor1=u_wallace_cla24_fa222_xor1 fa_or0=u_wallace_cla24_fa222_or0
.subckt fa a=u_wallace_cla24_fa222_or0 b=u_wallace_cla24_fa48_xor1 cin=u_wallace_cla24_fa87_xor1 fa_xor1=u_wallace_cla24_fa223_xor1 fa_or0=u_wallace_cla24_fa223_or0
.subckt fa a=u_wallace_cla24_fa223_or0 b=u_wallace_cla24_fa8_xor1 cin=u_wallace_cla24_fa49_xor1 fa_xor1=u_wallace_cla24_fa224_xor1 fa_or0=u_wallace_cla24_fa224_or0
.subckt and_gate a=a[0] b=b[12] out=u_wallace_cla24_and_0_12
.subckt fa a=u_wallace_cla24_fa224_or0 b=u_wallace_cla24_and_0_12 cin=u_wallace_cla24_fa9_xor1 fa_xor1=u_wallace_cla24_fa225_xor1 fa_or0=u_wallace_cla24_fa225_or0
.subckt and_gate a=a[1] b=b[12] out=u_wallace_cla24_and_1_12
.subckt and_gate a=a[0] b=b[13] out=u_wallace_cla24_and_0_13
.subckt fa a=u_wallace_cla24_fa225_or0 b=u_wallace_cla24_and_1_12 cin=u_wallace_cla24_and_0_13 fa_xor1=u_wallace_cla24_fa226_xor1 fa_or0=u_wallace_cla24_fa226_or0
.subckt and_gate a=a[2] b=b[12] out=u_wallace_cla24_and_2_12
.subckt and_gate a=a[1] b=b[13] out=u_wallace_cla24_and_1_13
.subckt fa a=u_wallace_cla24_fa226_or0 b=u_wallace_cla24_and_2_12 cin=u_wallace_cla24_and_1_13 fa_xor1=u_wallace_cla24_fa227_xor1 fa_or0=u_wallace_cla24_fa227_or0
.subckt and_gate a=a[3] b=b[12] out=u_wallace_cla24_and_3_12
.subckt and_gate a=a[2] b=b[13] out=u_wallace_cla24_and_2_13
.subckt fa a=u_wallace_cla24_fa227_or0 b=u_wallace_cla24_and_3_12 cin=u_wallace_cla24_and_2_13 fa_xor1=u_wallace_cla24_fa228_xor1 fa_or0=u_wallace_cla24_fa228_or0
.subckt and_gate a=a[4] b=b[12] out=u_wallace_cla24_and_4_12
.subckt and_gate a=a[3] b=b[13] out=u_wallace_cla24_and_3_13
.subckt fa a=u_wallace_cla24_fa228_or0 b=u_wallace_cla24_and_4_12 cin=u_wallace_cla24_and_3_13 fa_xor1=u_wallace_cla24_fa229_xor1 fa_or0=u_wallace_cla24_fa229_or0
.subckt and_gate a=a[5] b=b[12] out=u_wallace_cla24_and_5_12
.subckt and_gate a=a[4] b=b[13] out=u_wallace_cla24_and_4_13
.subckt fa a=u_wallace_cla24_fa229_or0 b=u_wallace_cla24_and_5_12 cin=u_wallace_cla24_and_4_13 fa_xor1=u_wallace_cla24_fa230_xor1 fa_or0=u_wallace_cla24_fa230_or0
.subckt and_gate a=a[6] b=b[12] out=u_wallace_cla24_and_6_12
.subckt and_gate a=a[5] b=b[13] out=u_wallace_cla24_and_5_13
.subckt fa a=u_wallace_cla24_fa230_or0 b=u_wallace_cla24_and_6_12 cin=u_wallace_cla24_and_5_13 fa_xor1=u_wallace_cla24_fa231_xor1 fa_or0=u_wallace_cla24_fa231_or0
.subckt and_gate a=a[7] b=b[12] out=u_wallace_cla24_and_7_12
.subckt and_gate a=a[6] b=b[13] out=u_wallace_cla24_and_6_13
.subckt fa a=u_wallace_cla24_fa231_or0 b=u_wallace_cla24_and_7_12 cin=u_wallace_cla24_and_6_13 fa_xor1=u_wallace_cla24_fa232_xor1 fa_or0=u_wallace_cla24_fa232_or0
.subckt and_gate a=a[8] b=b[12] out=u_wallace_cla24_and_8_12
.subckt and_gate a=a[7] b=b[13] out=u_wallace_cla24_and_7_13
.subckt fa a=u_wallace_cla24_fa232_or0 b=u_wallace_cla24_and_8_12 cin=u_wallace_cla24_and_7_13 fa_xor1=u_wallace_cla24_fa233_xor1 fa_or0=u_wallace_cla24_fa233_or0
.subckt and_gate a=a[9] b=b[12] out=u_wallace_cla24_and_9_12
.subckt and_gate a=a[8] b=b[13] out=u_wallace_cla24_and_8_13
.subckt fa a=u_wallace_cla24_fa233_or0 b=u_wallace_cla24_and_9_12 cin=u_wallace_cla24_and_8_13 fa_xor1=u_wallace_cla24_fa234_xor1 fa_or0=u_wallace_cla24_fa234_or0
.subckt and_gate a=a[10] b=b[12] out=u_wallace_cla24_and_10_12
.subckt and_gate a=a[9] b=b[13] out=u_wallace_cla24_and_9_13
.subckt fa a=u_wallace_cla24_fa234_or0 b=u_wallace_cla24_and_10_12 cin=u_wallace_cla24_and_9_13 fa_xor1=u_wallace_cla24_fa235_xor1 fa_or0=u_wallace_cla24_fa235_or0
.subckt and_gate a=a[11] b=b[12] out=u_wallace_cla24_and_11_12
.subckt and_gate a=a[10] b=b[13] out=u_wallace_cla24_and_10_13
.subckt fa a=u_wallace_cla24_fa235_or0 b=u_wallace_cla24_and_11_12 cin=u_wallace_cla24_and_10_13 fa_xor1=u_wallace_cla24_fa236_xor1 fa_or0=u_wallace_cla24_fa236_or0
.subckt and_gate a=a[11] b=b[13] out=u_wallace_cla24_and_11_13
.subckt and_gate a=a[10] b=b[14] out=u_wallace_cla24_and_10_14
.subckt fa a=u_wallace_cla24_fa236_or0 b=u_wallace_cla24_and_11_13 cin=u_wallace_cla24_and_10_14 fa_xor1=u_wallace_cla24_fa237_xor1 fa_or0=u_wallace_cla24_fa237_or0
.subckt and_gate a=a[11] b=b[14] out=u_wallace_cla24_and_11_14
.subckt and_gate a=a[10] b=b[15] out=u_wallace_cla24_and_10_15
.subckt fa a=u_wallace_cla24_fa237_or0 b=u_wallace_cla24_and_11_14 cin=u_wallace_cla24_and_10_15 fa_xor1=u_wallace_cla24_fa238_xor1 fa_or0=u_wallace_cla24_fa238_or0
.subckt and_gate a=a[11] b=b[15] out=u_wallace_cla24_and_11_15
.subckt and_gate a=a[10] b=b[16] out=u_wallace_cla24_and_10_16
.subckt fa a=u_wallace_cla24_fa238_or0 b=u_wallace_cla24_and_11_15 cin=u_wallace_cla24_and_10_16 fa_xor1=u_wallace_cla24_fa239_xor1 fa_or0=u_wallace_cla24_fa239_or0
.subckt and_gate a=a[11] b=b[16] out=u_wallace_cla24_and_11_16
.subckt and_gate a=a[10] b=b[17] out=u_wallace_cla24_and_10_17
.subckt fa a=u_wallace_cla24_fa239_or0 b=u_wallace_cla24_and_11_16 cin=u_wallace_cla24_and_10_17 fa_xor1=u_wallace_cla24_fa240_xor1 fa_or0=u_wallace_cla24_fa240_or0
.subckt and_gate a=a[11] b=b[17] out=u_wallace_cla24_and_11_17
.subckt and_gate a=a[10] b=b[18] out=u_wallace_cla24_and_10_18
.subckt fa a=u_wallace_cla24_fa240_or0 b=u_wallace_cla24_and_11_17 cin=u_wallace_cla24_and_10_18 fa_xor1=u_wallace_cla24_fa241_xor1 fa_or0=u_wallace_cla24_fa241_or0
.subckt and_gate a=a[11] b=b[18] out=u_wallace_cla24_and_11_18
.subckt and_gate a=a[10] b=b[19] out=u_wallace_cla24_and_10_19
.subckt fa a=u_wallace_cla24_fa241_or0 b=u_wallace_cla24_and_11_18 cin=u_wallace_cla24_and_10_19 fa_xor1=u_wallace_cla24_fa242_xor1 fa_or0=u_wallace_cla24_fa242_or0
.subckt and_gate a=a[11] b=b[19] out=u_wallace_cla24_and_11_19
.subckt and_gate a=a[10] b=b[20] out=u_wallace_cla24_and_10_20
.subckt fa a=u_wallace_cla24_fa242_or0 b=u_wallace_cla24_and_11_19 cin=u_wallace_cla24_and_10_20 fa_xor1=u_wallace_cla24_fa243_xor1 fa_or0=u_wallace_cla24_fa243_or0
.subckt and_gate a=a[11] b=b[20] out=u_wallace_cla24_and_11_20
.subckt and_gate a=a[10] b=b[21] out=u_wallace_cla24_and_10_21
.subckt fa a=u_wallace_cla24_fa243_or0 b=u_wallace_cla24_and_11_20 cin=u_wallace_cla24_and_10_21 fa_xor1=u_wallace_cla24_fa244_xor1 fa_or0=u_wallace_cla24_fa244_or0
.subckt and_gate a=a[11] b=b[21] out=u_wallace_cla24_and_11_21
.subckt and_gate a=a[10] b=b[22] out=u_wallace_cla24_and_10_22
.subckt fa a=u_wallace_cla24_fa244_or0 b=u_wallace_cla24_and_11_21 cin=u_wallace_cla24_and_10_22 fa_xor1=u_wallace_cla24_fa245_xor1 fa_or0=u_wallace_cla24_fa245_or0
.subckt and_gate a=a[11] b=b[22] out=u_wallace_cla24_and_11_22
.subckt and_gate a=a[10] b=b[23] out=u_wallace_cla24_and_10_23
.subckt fa a=u_wallace_cla24_fa245_or0 b=u_wallace_cla24_and_11_22 cin=u_wallace_cla24_and_10_23 fa_xor1=u_wallace_cla24_fa246_xor1 fa_or0=u_wallace_cla24_fa246_or0
.subckt and_gate a=a[11] b=b[23] out=u_wallace_cla24_and_11_23
.subckt fa a=u_wallace_cla24_fa246_or0 b=u_wallace_cla24_and_11_23 cin=u_wallace_cla24_fa31_xor1 fa_xor1=u_wallace_cla24_fa247_xor1 fa_or0=u_wallace_cla24_fa247_or0
.subckt fa a=u_wallace_cla24_fa247_or0 b=u_wallace_cla24_fa32_xor1 cin=u_wallace_cla24_fa73_xor1 fa_xor1=u_wallace_cla24_fa248_xor1 fa_or0=u_wallace_cla24_fa248_or0
.subckt fa a=u_wallace_cla24_fa248_or0 b=u_wallace_cla24_fa74_xor1 cin=u_wallace_cla24_fa113_xor1 fa_xor1=u_wallace_cla24_fa249_xor1 fa_or0=u_wallace_cla24_fa249_or0
.subckt fa a=u_wallace_cla24_fa249_or0 b=u_wallace_cla24_fa114_xor1 cin=u_wallace_cla24_fa151_xor1 fa_xor1=u_wallace_cla24_fa250_xor1 fa_or0=u_wallace_cla24_fa250_or0
.subckt fa a=u_wallace_cla24_fa250_or0 b=u_wallace_cla24_fa152_xor1 cin=u_wallace_cla24_fa187_xor1 fa_xor1=u_wallace_cla24_fa251_xor1 fa_or0=u_wallace_cla24_fa251_or0
.subckt ha a=u_wallace_cla24_fa158_xor1 b=u_wallace_cla24_fa191_xor1 ha_xor0=u_wallace_cla24_ha7_xor0 ha_and0=u_wallace_cla24_ha7_and0
.subckt fa a=u_wallace_cla24_ha7_and0 b=u_wallace_cla24_fa124_xor1 cin=u_wallace_cla24_fa159_xor1 fa_xor1=u_wallace_cla24_fa252_xor1 fa_or0=u_wallace_cla24_fa252_or0
.subckt fa a=u_wallace_cla24_fa252_or0 b=u_wallace_cla24_fa88_xor1 cin=u_wallace_cla24_fa125_xor1 fa_xor1=u_wallace_cla24_fa253_xor1 fa_or0=u_wallace_cla24_fa253_or0
.subckt fa a=u_wallace_cla24_fa253_or0 b=u_wallace_cla24_fa50_xor1 cin=u_wallace_cla24_fa89_xor1 fa_xor1=u_wallace_cla24_fa254_xor1 fa_or0=u_wallace_cla24_fa254_or0
.subckt fa a=u_wallace_cla24_fa254_or0 b=u_wallace_cla24_fa10_xor1 cin=u_wallace_cla24_fa51_xor1 fa_xor1=u_wallace_cla24_fa255_xor1 fa_or0=u_wallace_cla24_fa255_or0
.subckt and_gate a=a[0] b=b[14] out=u_wallace_cla24_and_0_14
.subckt fa a=u_wallace_cla24_fa255_or0 b=u_wallace_cla24_and_0_14 cin=u_wallace_cla24_fa11_xor1 fa_xor1=u_wallace_cla24_fa256_xor1 fa_or0=u_wallace_cla24_fa256_or0
.subckt and_gate a=a[1] b=b[14] out=u_wallace_cla24_and_1_14
.subckt and_gate a=a[0] b=b[15] out=u_wallace_cla24_and_0_15
.subckt fa a=u_wallace_cla24_fa256_or0 b=u_wallace_cla24_and_1_14 cin=u_wallace_cla24_and_0_15 fa_xor1=u_wallace_cla24_fa257_xor1 fa_or0=u_wallace_cla24_fa257_or0
.subckt and_gate a=a[2] b=b[14] out=u_wallace_cla24_and_2_14
.subckt and_gate a=a[1] b=b[15] out=u_wallace_cla24_and_1_15
.subckt fa a=u_wallace_cla24_fa257_or0 b=u_wallace_cla24_and_2_14 cin=u_wallace_cla24_and_1_15 fa_xor1=u_wallace_cla24_fa258_xor1 fa_or0=u_wallace_cla24_fa258_or0
.subckt and_gate a=a[3] b=b[14] out=u_wallace_cla24_and_3_14
.subckt and_gate a=a[2] b=b[15] out=u_wallace_cla24_and_2_15
.subckt fa a=u_wallace_cla24_fa258_or0 b=u_wallace_cla24_and_3_14 cin=u_wallace_cla24_and_2_15 fa_xor1=u_wallace_cla24_fa259_xor1 fa_or0=u_wallace_cla24_fa259_or0
.subckt and_gate a=a[4] b=b[14] out=u_wallace_cla24_and_4_14
.subckt and_gate a=a[3] b=b[15] out=u_wallace_cla24_and_3_15
.subckt fa a=u_wallace_cla24_fa259_or0 b=u_wallace_cla24_and_4_14 cin=u_wallace_cla24_and_3_15 fa_xor1=u_wallace_cla24_fa260_xor1 fa_or0=u_wallace_cla24_fa260_or0
.subckt and_gate a=a[5] b=b[14] out=u_wallace_cla24_and_5_14
.subckt and_gate a=a[4] b=b[15] out=u_wallace_cla24_and_4_15
.subckt fa a=u_wallace_cla24_fa260_or0 b=u_wallace_cla24_and_5_14 cin=u_wallace_cla24_and_4_15 fa_xor1=u_wallace_cla24_fa261_xor1 fa_or0=u_wallace_cla24_fa261_or0
.subckt and_gate a=a[6] b=b[14] out=u_wallace_cla24_and_6_14
.subckt and_gate a=a[5] b=b[15] out=u_wallace_cla24_and_5_15
.subckt fa a=u_wallace_cla24_fa261_or0 b=u_wallace_cla24_and_6_14 cin=u_wallace_cla24_and_5_15 fa_xor1=u_wallace_cla24_fa262_xor1 fa_or0=u_wallace_cla24_fa262_or0
.subckt and_gate a=a[7] b=b[14] out=u_wallace_cla24_and_7_14
.subckt and_gate a=a[6] b=b[15] out=u_wallace_cla24_and_6_15
.subckt fa a=u_wallace_cla24_fa262_or0 b=u_wallace_cla24_and_7_14 cin=u_wallace_cla24_and_6_15 fa_xor1=u_wallace_cla24_fa263_xor1 fa_or0=u_wallace_cla24_fa263_or0
.subckt and_gate a=a[8] b=b[14] out=u_wallace_cla24_and_8_14
.subckt and_gate a=a[7] b=b[15] out=u_wallace_cla24_and_7_15
.subckt fa a=u_wallace_cla24_fa263_or0 b=u_wallace_cla24_and_8_14 cin=u_wallace_cla24_and_7_15 fa_xor1=u_wallace_cla24_fa264_xor1 fa_or0=u_wallace_cla24_fa264_or0
.subckt and_gate a=a[9] b=b[14] out=u_wallace_cla24_and_9_14
.subckt and_gate a=a[8] b=b[15] out=u_wallace_cla24_and_8_15
.subckt fa a=u_wallace_cla24_fa264_or0 b=u_wallace_cla24_and_9_14 cin=u_wallace_cla24_and_8_15 fa_xor1=u_wallace_cla24_fa265_xor1 fa_or0=u_wallace_cla24_fa265_or0
.subckt and_gate a=a[9] b=b[15] out=u_wallace_cla24_and_9_15
.subckt and_gate a=a[8] b=b[16] out=u_wallace_cla24_and_8_16
.subckt fa a=u_wallace_cla24_fa265_or0 b=u_wallace_cla24_and_9_15 cin=u_wallace_cla24_and_8_16 fa_xor1=u_wallace_cla24_fa266_xor1 fa_or0=u_wallace_cla24_fa266_or0
.subckt and_gate a=a[9] b=b[16] out=u_wallace_cla24_and_9_16
.subckt and_gate a=a[8] b=b[17] out=u_wallace_cla24_and_8_17
.subckt fa a=u_wallace_cla24_fa266_or0 b=u_wallace_cla24_and_9_16 cin=u_wallace_cla24_and_8_17 fa_xor1=u_wallace_cla24_fa267_xor1 fa_or0=u_wallace_cla24_fa267_or0
.subckt and_gate a=a[9] b=b[17] out=u_wallace_cla24_and_9_17
.subckt and_gate a=a[8] b=b[18] out=u_wallace_cla24_and_8_18
.subckt fa a=u_wallace_cla24_fa267_or0 b=u_wallace_cla24_and_9_17 cin=u_wallace_cla24_and_8_18 fa_xor1=u_wallace_cla24_fa268_xor1 fa_or0=u_wallace_cla24_fa268_or0
.subckt and_gate a=a[9] b=b[18] out=u_wallace_cla24_and_9_18
.subckt and_gate a=a[8] b=b[19] out=u_wallace_cla24_and_8_19
.subckt fa a=u_wallace_cla24_fa268_or0 b=u_wallace_cla24_and_9_18 cin=u_wallace_cla24_and_8_19 fa_xor1=u_wallace_cla24_fa269_xor1 fa_or0=u_wallace_cla24_fa269_or0
.subckt and_gate a=a[9] b=b[19] out=u_wallace_cla24_and_9_19
.subckt and_gate a=a[8] b=b[20] out=u_wallace_cla24_and_8_20
.subckt fa a=u_wallace_cla24_fa269_or0 b=u_wallace_cla24_and_9_19 cin=u_wallace_cla24_and_8_20 fa_xor1=u_wallace_cla24_fa270_xor1 fa_or0=u_wallace_cla24_fa270_or0
.subckt and_gate a=a[9] b=b[20] out=u_wallace_cla24_and_9_20
.subckt and_gate a=a[8] b=b[21] out=u_wallace_cla24_and_8_21
.subckt fa a=u_wallace_cla24_fa270_or0 b=u_wallace_cla24_and_9_20 cin=u_wallace_cla24_and_8_21 fa_xor1=u_wallace_cla24_fa271_xor1 fa_or0=u_wallace_cla24_fa271_or0
.subckt and_gate a=a[9] b=b[21] out=u_wallace_cla24_and_9_21
.subckt and_gate a=a[8] b=b[22] out=u_wallace_cla24_and_8_22
.subckt fa a=u_wallace_cla24_fa271_or0 b=u_wallace_cla24_and_9_21 cin=u_wallace_cla24_and_8_22 fa_xor1=u_wallace_cla24_fa272_xor1 fa_or0=u_wallace_cla24_fa272_or0
.subckt and_gate a=a[9] b=b[22] out=u_wallace_cla24_and_9_22
.subckt and_gate a=a[8] b=b[23] out=u_wallace_cla24_and_8_23
.subckt fa a=u_wallace_cla24_fa272_or0 b=u_wallace_cla24_and_9_22 cin=u_wallace_cla24_and_8_23 fa_xor1=u_wallace_cla24_fa273_xor1 fa_or0=u_wallace_cla24_fa273_or0
.subckt and_gate a=a[9] b=b[23] out=u_wallace_cla24_and_9_23
.subckt fa a=u_wallace_cla24_fa273_or0 b=u_wallace_cla24_and_9_23 cin=u_wallace_cla24_fa29_xor1 fa_xor1=u_wallace_cla24_fa274_xor1 fa_or0=u_wallace_cla24_fa274_or0
.subckt fa a=u_wallace_cla24_fa274_or0 b=u_wallace_cla24_fa30_xor1 cin=u_wallace_cla24_fa71_xor1 fa_xor1=u_wallace_cla24_fa275_xor1 fa_or0=u_wallace_cla24_fa275_or0
.subckt fa a=u_wallace_cla24_fa275_or0 b=u_wallace_cla24_fa72_xor1 cin=u_wallace_cla24_fa111_xor1 fa_xor1=u_wallace_cla24_fa276_xor1 fa_or0=u_wallace_cla24_fa276_or0
.subckt fa a=u_wallace_cla24_fa276_or0 b=u_wallace_cla24_fa112_xor1 cin=u_wallace_cla24_fa149_xor1 fa_xor1=u_wallace_cla24_fa277_xor1 fa_or0=u_wallace_cla24_fa277_or0
.subckt fa a=u_wallace_cla24_fa277_or0 b=u_wallace_cla24_fa150_xor1 cin=u_wallace_cla24_fa185_xor1 fa_xor1=u_wallace_cla24_fa278_xor1 fa_or0=u_wallace_cla24_fa278_or0
.subckt fa a=u_wallace_cla24_fa278_or0 b=u_wallace_cla24_fa186_xor1 cin=u_wallace_cla24_fa219_xor1 fa_xor1=u_wallace_cla24_fa279_xor1 fa_or0=u_wallace_cla24_fa279_or0
.subckt ha a=u_wallace_cla24_fa192_xor1 b=u_wallace_cla24_fa223_xor1 ha_xor0=u_wallace_cla24_ha8_xor0 ha_and0=u_wallace_cla24_ha8_and0
.subckt fa a=u_wallace_cla24_ha8_and0 b=u_wallace_cla24_fa160_xor1 cin=u_wallace_cla24_fa193_xor1 fa_xor1=u_wallace_cla24_fa280_xor1 fa_or0=u_wallace_cla24_fa280_or0
.subckt fa a=u_wallace_cla24_fa280_or0 b=u_wallace_cla24_fa126_xor1 cin=u_wallace_cla24_fa161_xor1 fa_xor1=u_wallace_cla24_fa281_xor1 fa_or0=u_wallace_cla24_fa281_or0
.subckt fa a=u_wallace_cla24_fa281_or0 b=u_wallace_cla24_fa90_xor1 cin=u_wallace_cla24_fa127_xor1 fa_xor1=u_wallace_cla24_fa282_xor1 fa_or0=u_wallace_cla24_fa282_or0
.subckt fa a=u_wallace_cla24_fa282_or0 b=u_wallace_cla24_fa52_xor1 cin=u_wallace_cla24_fa91_xor1 fa_xor1=u_wallace_cla24_fa283_xor1 fa_or0=u_wallace_cla24_fa283_or0
.subckt fa a=u_wallace_cla24_fa283_or0 b=u_wallace_cla24_fa12_xor1 cin=u_wallace_cla24_fa53_xor1 fa_xor1=u_wallace_cla24_fa284_xor1 fa_or0=u_wallace_cla24_fa284_or0
.subckt and_gate a=a[0] b=b[16] out=u_wallace_cla24_and_0_16
.subckt fa a=u_wallace_cla24_fa284_or0 b=u_wallace_cla24_and_0_16 cin=u_wallace_cla24_fa13_xor1 fa_xor1=u_wallace_cla24_fa285_xor1 fa_or0=u_wallace_cla24_fa285_or0
.subckt and_gate a=a[1] b=b[16] out=u_wallace_cla24_and_1_16
.subckt and_gate a=a[0] b=b[17] out=u_wallace_cla24_and_0_17
.subckt fa a=u_wallace_cla24_fa285_or0 b=u_wallace_cla24_and_1_16 cin=u_wallace_cla24_and_0_17 fa_xor1=u_wallace_cla24_fa286_xor1 fa_or0=u_wallace_cla24_fa286_or0
.subckt and_gate a=a[2] b=b[16] out=u_wallace_cla24_and_2_16
.subckt and_gate a=a[1] b=b[17] out=u_wallace_cla24_and_1_17
.subckt fa a=u_wallace_cla24_fa286_or0 b=u_wallace_cla24_and_2_16 cin=u_wallace_cla24_and_1_17 fa_xor1=u_wallace_cla24_fa287_xor1 fa_or0=u_wallace_cla24_fa287_or0
.subckt and_gate a=a[3] b=b[16] out=u_wallace_cla24_and_3_16
.subckt and_gate a=a[2] b=b[17] out=u_wallace_cla24_and_2_17
.subckt fa a=u_wallace_cla24_fa287_or0 b=u_wallace_cla24_and_3_16 cin=u_wallace_cla24_and_2_17 fa_xor1=u_wallace_cla24_fa288_xor1 fa_or0=u_wallace_cla24_fa288_or0
.subckt and_gate a=a[4] b=b[16] out=u_wallace_cla24_and_4_16
.subckt and_gate a=a[3] b=b[17] out=u_wallace_cla24_and_3_17
.subckt fa a=u_wallace_cla24_fa288_or0 b=u_wallace_cla24_and_4_16 cin=u_wallace_cla24_and_3_17 fa_xor1=u_wallace_cla24_fa289_xor1 fa_or0=u_wallace_cla24_fa289_or0
.subckt and_gate a=a[5] b=b[16] out=u_wallace_cla24_and_5_16
.subckt and_gate a=a[4] b=b[17] out=u_wallace_cla24_and_4_17
.subckt fa a=u_wallace_cla24_fa289_or0 b=u_wallace_cla24_and_5_16 cin=u_wallace_cla24_and_4_17 fa_xor1=u_wallace_cla24_fa290_xor1 fa_or0=u_wallace_cla24_fa290_or0
.subckt and_gate a=a[6] b=b[16] out=u_wallace_cla24_and_6_16
.subckt and_gate a=a[5] b=b[17] out=u_wallace_cla24_and_5_17
.subckt fa a=u_wallace_cla24_fa290_or0 b=u_wallace_cla24_and_6_16 cin=u_wallace_cla24_and_5_17 fa_xor1=u_wallace_cla24_fa291_xor1 fa_or0=u_wallace_cla24_fa291_or0
.subckt and_gate a=a[7] b=b[16] out=u_wallace_cla24_and_7_16
.subckt and_gate a=a[6] b=b[17] out=u_wallace_cla24_and_6_17
.subckt fa a=u_wallace_cla24_fa291_or0 b=u_wallace_cla24_and_7_16 cin=u_wallace_cla24_and_6_17 fa_xor1=u_wallace_cla24_fa292_xor1 fa_or0=u_wallace_cla24_fa292_or0
.subckt and_gate a=a[7] b=b[17] out=u_wallace_cla24_and_7_17
.subckt and_gate a=a[6] b=b[18] out=u_wallace_cla24_and_6_18
.subckt fa a=u_wallace_cla24_fa292_or0 b=u_wallace_cla24_and_7_17 cin=u_wallace_cla24_and_6_18 fa_xor1=u_wallace_cla24_fa293_xor1 fa_or0=u_wallace_cla24_fa293_or0
.subckt and_gate a=a[7] b=b[18] out=u_wallace_cla24_and_7_18
.subckt and_gate a=a[6] b=b[19] out=u_wallace_cla24_and_6_19
.subckt fa a=u_wallace_cla24_fa293_or0 b=u_wallace_cla24_and_7_18 cin=u_wallace_cla24_and_6_19 fa_xor1=u_wallace_cla24_fa294_xor1 fa_or0=u_wallace_cla24_fa294_or0
.subckt and_gate a=a[7] b=b[19] out=u_wallace_cla24_and_7_19
.subckt and_gate a=a[6] b=b[20] out=u_wallace_cla24_and_6_20
.subckt fa a=u_wallace_cla24_fa294_or0 b=u_wallace_cla24_and_7_19 cin=u_wallace_cla24_and_6_20 fa_xor1=u_wallace_cla24_fa295_xor1 fa_or0=u_wallace_cla24_fa295_or0
.subckt and_gate a=a[7] b=b[20] out=u_wallace_cla24_and_7_20
.subckt and_gate a=a[6] b=b[21] out=u_wallace_cla24_and_6_21
.subckt fa a=u_wallace_cla24_fa295_or0 b=u_wallace_cla24_and_7_20 cin=u_wallace_cla24_and_6_21 fa_xor1=u_wallace_cla24_fa296_xor1 fa_or0=u_wallace_cla24_fa296_or0
.subckt and_gate a=a[7] b=b[21] out=u_wallace_cla24_and_7_21
.subckt and_gate a=a[6] b=b[22] out=u_wallace_cla24_and_6_22
.subckt fa a=u_wallace_cla24_fa296_or0 b=u_wallace_cla24_and_7_21 cin=u_wallace_cla24_and_6_22 fa_xor1=u_wallace_cla24_fa297_xor1 fa_or0=u_wallace_cla24_fa297_or0
.subckt and_gate a=a[7] b=b[22] out=u_wallace_cla24_and_7_22
.subckt and_gate a=a[6] b=b[23] out=u_wallace_cla24_and_6_23
.subckt fa a=u_wallace_cla24_fa297_or0 b=u_wallace_cla24_and_7_22 cin=u_wallace_cla24_and_6_23 fa_xor1=u_wallace_cla24_fa298_xor1 fa_or0=u_wallace_cla24_fa298_or0
.subckt and_gate a=a[7] b=b[23] out=u_wallace_cla24_and_7_23
.subckt fa a=u_wallace_cla24_fa298_or0 b=u_wallace_cla24_and_7_23 cin=u_wallace_cla24_fa27_xor1 fa_xor1=u_wallace_cla24_fa299_xor1 fa_or0=u_wallace_cla24_fa299_or0
.subckt fa a=u_wallace_cla24_fa299_or0 b=u_wallace_cla24_fa28_xor1 cin=u_wallace_cla24_fa69_xor1 fa_xor1=u_wallace_cla24_fa300_xor1 fa_or0=u_wallace_cla24_fa300_or0
.subckt fa a=u_wallace_cla24_fa300_or0 b=u_wallace_cla24_fa70_xor1 cin=u_wallace_cla24_fa109_xor1 fa_xor1=u_wallace_cla24_fa301_xor1 fa_or0=u_wallace_cla24_fa301_or0
.subckt fa a=u_wallace_cla24_fa301_or0 b=u_wallace_cla24_fa110_xor1 cin=u_wallace_cla24_fa147_xor1 fa_xor1=u_wallace_cla24_fa302_xor1 fa_or0=u_wallace_cla24_fa302_or0
.subckt fa a=u_wallace_cla24_fa302_or0 b=u_wallace_cla24_fa148_xor1 cin=u_wallace_cla24_fa183_xor1 fa_xor1=u_wallace_cla24_fa303_xor1 fa_or0=u_wallace_cla24_fa303_or0
.subckt fa a=u_wallace_cla24_fa303_or0 b=u_wallace_cla24_fa184_xor1 cin=u_wallace_cla24_fa217_xor1 fa_xor1=u_wallace_cla24_fa304_xor1 fa_or0=u_wallace_cla24_fa304_or0
.subckt fa a=u_wallace_cla24_fa304_or0 b=u_wallace_cla24_fa218_xor1 cin=u_wallace_cla24_fa249_xor1 fa_xor1=u_wallace_cla24_fa305_xor1 fa_or0=u_wallace_cla24_fa305_or0
.subckt ha a=u_wallace_cla24_fa224_xor1 b=u_wallace_cla24_fa253_xor1 ha_xor0=u_wallace_cla24_ha9_xor0 ha_and0=u_wallace_cla24_ha9_and0
.subckt fa a=u_wallace_cla24_ha9_and0 b=u_wallace_cla24_fa194_xor1 cin=u_wallace_cla24_fa225_xor1 fa_xor1=u_wallace_cla24_fa306_xor1 fa_or0=u_wallace_cla24_fa306_or0
.subckt fa a=u_wallace_cla24_fa306_or0 b=u_wallace_cla24_fa162_xor1 cin=u_wallace_cla24_fa195_xor1 fa_xor1=u_wallace_cla24_fa307_xor1 fa_or0=u_wallace_cla24_fa307_or0
.subckt fa a=u_wallace_cla24_fa307_or0 b=u_wallace_cla24_fa128_xor1 cin=u_wallace_cla24_fa163_xor1 fa_xor1=u_wallace_cla24_fa308_xor1 fa_or0=u_wallace_cla24_fa308_or0
.subckt fa a=u_wallace_cla24_fa308_or0 b=u_wallace_cla24_fa92_xor1 cin=u_wallace_cla24_fa129_xor1 fa_xor1=u_wallace_cla24_fa309_xor1 fa_or0=u_wallace_cla24_fa309_or0
.subckt fa a=u_wallace_cla24_fa309_or0 b=u_wallace_cla24_fa54_xor1 cin=u_wallace_cla24_fa93_xor1 fa_xor1=u_wallace_cla24_fa310_xor1 fa_or0=u_wallace_cla24_fa310_or0
.subckt fa a=u_wallace_cla24_fa310_or0 b=u_wallace_cla24_fa14_xor1 cin=u_wallace_cla24_fa55_xor1 fa_xor1=u_wallace_cla24_fa311_xor1 fa_or0=u_wallace_cla24_fa311_or0
.subckt and_gate a=a[0] b=b[18] out=u_wallace_cla24_and_0_18
.subckt fa a=u_wallace_cla24_fa311_or0 b=u_wallace_cla24_and_0_18 cin=u_wallace_cla24_fa15_xor1 fa_xor1=u_wallace_cla24_fa312_xor1 fa_or0=u_wallace_cla24_fa312_or0
.subckt and_gate a=a[1] b=b[18] out=u_wallace_cla24_and_1_18
.subckt and_gate a=a[0] b=b[19] out=u_wallace_cla24_and_0_19
.subckt fa a=u_wallace_cla24_fa312_or0 b=u_wallace_cla24_and_1_18 cin=u_wallace_cla24_and_0_19 fa_xor1=u_wallace_cla24_fa313_xor1 fa_or0=u_wallace_cla24_fa313_or0
.subckt and_gate a=a[2] b=b[18] out=u_wallace_cla24_and_2_18
.subckt and_gate a=a[1] b=b[19] out=u_wallace_cla24_and_1_19
.subckt fa a=u_wallace_cla24_fa313_or0 b=u_wallace_cla24_and_2_18 cin=u_wallace_cla24_and_1_19 fa_xor1=u_wallace_cla24_fa314_xor1 fa_or0=u_wallace_cla24_fa314_or0
.subckt and_gate a=a[3] b=b[18] out=u_wallace_cla24_and_3_18
.subckt and_gate a=a[2] b=b[19] out=u_wallace_cla24_and_2_19
.subckt fa a=u_wallace_cla24_fa314_or0 b=u_wallace_cla24_and_3_18 cin=u_wallace_cla24_and_2_19 fa_xor1=u_wallace_cla24_fa315_xor1 fa_or0=u_wallace_cla24_fa315_or0
.subckt and_gate a=a[4] b=b[18] out=u_wallace_cla24_and_4_18
.subckt and_gate a=a[3] b=b[19] out=u_wallace_cla24_and_3_19
.subckt fa a=u_wallace_cla24_fa315_or0 b=u_wallace_cla24_and_4_18 cin=u_wallace_cla24_and_3_19 fa_xor1=u_wallace_cla24_fa316_xor1 fa_or0=u_wallace_cla24_fa316_or0
.subckt and_gate a=a[5] b=b[18] out=u_wallace_cla24_and_5_18
.subckt and_gate a=a[4] b=b[19] out=u_wallace_cla24_and_4_19
.subckt fa a=u_wallace_cla24_fa316_or0 b=u_wallace_cla24_and_5_18 cin=u_wallace_cla24_and_4_19 fa_xor1=u_wallace_cla24_fa317_xor1 fa_or0=u_wallace_cla24_fa317_or0
.subckt and_gate a=a[5] b=b[19] out=u_wallace_cla24_and_5_19
.subckt and_gate a=a[4] b=b[20] out=u_wallace_cla24_and_4_20
.subckt fa a=u_wallace_cla24_fa317_or0 b=u_wallace_cla24_and_5_19 cin=u_wallace_cla24_and_4_20 fa_xor1=u_wallace_cla24_fa318_xor1 fa_or0=u_wallace_cla24_fa318_or0
.subckt and_gate a=a[5] b=b[20] out=u_wallace_cla24_and_5_20
.subckt and_gate a=a[4] b=b[21] out=u_wallace_cla24_and_4_21
.subckt fa a=u_wallace_cla24_fa318_or0 b=u_wallace_cla24_and_5_20 cin=u_wallace_cla24_and_4_21 fa_xor1=u_wallace_cla24_fa319_xor1 fa_or0=u_wallace_cla24_fa319_or0
.subckt and_gate a=a[5] b=b[21] out=u_wallace_cla24_and_5_21
.subckt and_gate a=a[4] b=b[22] out=u_wallace_cla24_and_4_22
.subckt fa a=u_wallace_cla24_fa319_or0 b=u_wallace_cla24_and_5_21 cin=u_wallace_cla24_and_4_22 fa_xor1=u_wallace_cla24_fa320_xor1 fa_or0=u_wallace_cla24_fa320_or0
.subckt and_gate a=a[5] b=b[22] out=u_wallace_cla24_and_5_22
.subckt and_gate a=a[4] b=b[23] out=u_wallace_cla24_and_4_23
.subckt fa a=u_wallace_cla24_fa320_or0 b=u_wallace_cla24_and_5_22 cin=u_wallace_cla24_and_4_23 fa_xor1=u_wallace_cla24_fa321_xor1 fa_or0=u_wallace_cla24_fa321_or0
.subckt and_gate a=a[5] b=b[23] out=u_wallace_cla24_and_5_23
.subckt fa a=u_wallace_cla24_fa321_or0 b=u_wallace_cla24_and_5_23 cin=u_wallace_cla24_fa25_xor1 fa_xor1=u_wallace_cla24_fa322_xor1 fa_or0=u_wallace_cla24_fa322_or0
.subckt fa a=u_wallace_cla24_fa322_or0 b=u_wallace_cla24_fa26_xor1 cin=u_wallace_cla24_fa67_xor1 fa_xor1=u_wallace_cla24_fa323_xor1 fa_or0=u_wallace_cla24_fa323_or0
.subckt fa a=u_wallace_cla24_fa323_or0 b=u_wallace_cla24_fa68_xor1 cin=u_wallace_cla24_fa107_xor1 fa_xor1=u_wallace_cla24_fa324_xor1 fa_or0=u_wallace_cla24_fa324_or0
.subckt fa a=u_wallace_cla24_fa324_or0 b=u_wallace_cla24_fa108_xor1 cin=u_wallace_cla24_fa145_xor1 fa_xor1=u_wallace_cla24_fa325_xor1 fa_or0=u_wallace_cla24_fa325_or0
.subckt fa a=u_wallace_cla24_fa325_or0 b=u_wallace_cla24_fa146_xor1 cin=u_wallace_cla24_fa181_xor1 fa_xor1=u_wallace_cla24_fa326_xor1 fa_or0=u_wallace_cla24_fa326_or0
.subckt fa a=u_wallace_cla24_fa326_or0 b=u_wallace_cla24_fa182_xor1 cin=u_wallace_cla24_fa215_xor1 fa_xor1=u_wallace_cla24_fa327_xor1 fa_or0=u_wallace_cla24_fa327_or0
.subckt fa a=u_wallace_cla24_fa327_or0 b=u_wallace_cla24_fa216_xor1 cin=u_wallace_cla24_fa247_xor1 fa_xor1=u_wallace_cla24_fa328_xor1 fa_or0=u_wallace_cla24_fa328_or0
.subckt fa a=u_wallace_cla24_fa328_or0 b=u_wallace_cla24_fa248_xor1 cin=u_wallace_cla24_fa277_xor1 fa_xor1=u_wallace_cla24_fa329_xor1 fa_or0=u_wallace_cla24_fa329_or0
.subckt ha a=u_wallace_cla24_fa254_xor1 b=u_wallace_cla24_fa281_xor1 ha_xor0=u_wallace_cla24_ha10_xor0 ha_and0=u_wallace_cla24_ha10_and0
.subckt fa a=u_wallace_cla24_ha10_and0 b=u_wallace_cla24_fa226_xor1 cin=u_wallace_cla24_fa255_xor1 fa_xor1=u_wallace_cla24_fa330_xor1 fa_or0=u_wallace_cla24_fa330_or0
.subckt fa a=u_wallace_cla24_fa330_or0 b=u_wallace_cla24_fa196_xor1 cin=u_wallace_cla24_fa227_xor1 fa_xor1=u_wallace_cla24_fa331_xor1 fa_or0=u_wallace_cla24_fa331_or0
.subckt fa a=u_wallace_cla24_fa331_or0 b=u_wallace_cla24_fa164_xor1 cin=u_wallace_cla24_fa197_xor1 fa_xor1=u_wallace_cla24_fa332_xor1 fa_or0=u_wallace_cla24_fa332_or0
.subckt fa a=u_wallace_cla24_fa332_or0 b=u_wallace_cla24_fa130_xor1 cin=u_wallace_cla24_fa165_xor1 fa_xor1=u_wallace_cla24_fa333_xor1 fa_or0=u_wallace_cla24_fa333_or0
.subckt fa a=u_wallace_cla24_fa333_or0 b=u_wallace_cla24_fa94_xor1 cin=u_wallace_cla24_fa131_xor1 fa_xor1=u_wallace_cla24_fa334_xor1 fa_or0=u_wallace_cla24_fa334_or0
.subckt fa a=u_wallace_cla24_fa334_or0 b=u_wallace_cla24_fa56_xor1 cin=u_wallace_cla24_fa95_xor1 fa_xor1=u_wallace_cla24_fa335_xor1 fa_or0=u_wallace_cla24_fa335_or0
.subckt fa a=u_wallace_cla24_fa335_or0 b=u_wallace_cla24_fa16_xor1 cin=u_wallace_cla24_fa57_xor1 fa_xor1=u_wallace_cla24_fa336_xor1 fa_or0=u_wallace_cla24_fa336_or0
.subckt and_gate a=a[0] b=b[20] out=u_wallace_cla24_and_0_20
.subckt fa a=u_wallace_cla24_fa336_or0 b=u_wallace_cla24_and_0_20 cin=u_wallace_cla24_fa17_xor1 fa_xor1=u_wallace_cla24_fa337_xor1 fa_or0=u_wallace_cla24_fa337_or0
.subckt and_gate a=a[1] b=b[20] out=u_wallace_cla24_and_1_20
.subckt and_gate a=a[0] b=b[21] out=u_wallace_cla24_and_0_21
.subckt fa a=u_wallace_cla24_fa337_or0 b=u_wallace_cla24_and_1_20 cin=u_wallace_cla24_and_0_21 fa_xor1=u_wallace_cla24_fa338_xor1 fa_or0=u_wallace_cla24_fa338_or0
.subckt and_gate a=a[2] b=b[20] out=u_wallace_cla24_and_2_20
.subckt and_gate a=a[1] b=b[21] out=u_wallace_cla24_and_1_21
.subckt fa a=u_wallace_cla24_fa338_or0 b=u_wallace_cla24_and_2_20 cin=u_wallace_cla24_and_1_21 fa_xor1=u_wallace_cla24_fa339_xor1 fa_or0=u_wallace_cla24_fa339_or0
.subckt and_gate a=a[3] b=b[20] out=u_wallace_cla24_and_3_20
.subckt and_gate a=a[2] b=b[21] out=u_wallace_cla24_and_2_21
.subckt fa a=u_wallace_cla24_fa339_or0 b=u_wallace_cla24_and_3_20 cin=u_wallace_cla24_and_2_21 fa_xor1=u_wallace_cla24_fa340_xor1 fa_or0=u_wallace_cla24_fa340_or0
.subckt and_gate a=a[3] b=b[21] out=u_wallace_cla24_and_3_21
.subckt and_gate a=a[2] b=b[22] out=u_wallace_cla24_and_2_22
.subckt fa a=u_wallace_cla24_fa340_or0 b=u_wallace_cla24_and_3_21 cin=u_wallace_cla24_and_2_22 fa_xor1=u_wallace_cla24_fa341_xor1 fa_or0=u_wallace_cla24_fa341_or0
.subckt and_gate a=a[3] b=b[22] out=u_wallace_cla24_and_3_22
.subckt and_gate a=a[2] b=b[23] out=u_wallace_cla24_and_2_23
.subckt fa a=u_wallace_cla24_fa341_or0 b=u_wallace_cla24_and_3_22 cin=u_wallace_cla24_and_2_23 fa_xor1=u_wallace_cla24_fa342_xor1 fa_or0=u_wallace_cla24_fa342_or0
.subckt and_gate a=a[3] b=b[23] out=u_wallace_cla24_and_3_23
.subckt fa a=u_wallace_cla24_fa342_or0 b=u_wallace_cla24_and_3_23 cin=u_wallace_cla24_fa23_xor1 fa_xor1=u_wallace_cla24_fa343_xor1 fa_or0=u_wallace_cla24_fa343_or0
.subckt fa a=u_wallace_cla24_fa343_or0 b=u_wallace_cla24_fa24_xor1 cin=u_wallace_cla24_fa65_xor1 fa_xor1=u_wallace_cla24_fa344_xor1 fa_or0=u_wallace_cla24_fa344_or0
.subckt fa a=u_wallace_cla24_fa344_or0 b=u_wallace_cla24_fa66_xor1 cin=u_wallace_cla24_fa105_xor1 fa_xor1=u_wallace_cla24_fa345_xor1 fa_or0=u_wallace_cla24_fa345_or0
.subckt fa a=u_wallace_cla24_fa345_or0 b=u_wallace_cla24_fa106_xor1 cin=u_wallace_cla24_fa143_xor1 fa_xor1=u_wallace_cla24_fa346_xor1 fa_or0=u_wallace_cla24_fa346_or0
.subckt fa a=u_wallace_cla24_fa346_or0 b=u_wallace_cla24_fa144_xor1 cin=u_wallace_cla24_fa179_xor1 fa_xor1=u_wallace_cla24_fa347_xor1 fa_or0=u_wallace_cla24_fa347_or0
.subckt fa a=u_wallace_cla24_fa347_or0 b=u_wallace_cla24_fa180_xor1 cin=u_wallace_cla24_fa213_xor1 fa_xor1=u_wallace_cla24_fa348_xor1 fa_or0=u_wallace_cla24_fa348_or0
.subckt fa a=u_wallace_cla24_fa348_or0 b=u_wallace_cla24_fa214_xor1 cin=u_wallace_cla24_fa245_xor1 fa_xor1=u_wallace_cla24_fa349_xor1 fa_or0=u_wallace_cla24_fa349_or0
.subckt fa a=u_wallace_cla24_fa349_or0 b=u_wallace_cla24_fa246_xor1 cin=u_wallace_cla24_fa275_xor1 fa_xor1=u_wallace_cla24_fa350_xor1 fa_or0=u_wallace_cla24_fa350_or0
.subckt fa a=u_wallace_cla24_fa350_or0 b=u_wallace_cla24_fa276_xor1 cin=u_wallace_cla24_fa303_xor1 fa_xor1=u_wallace_cla24_fa351_xor1 fa_or0=u_wallace_cla24_fa351_or0
.subckt ha a=u_wallace_cla24_fa282_xor1 b=u_wallace_cla24_fa307_xor1 ha_xor0=u_wallace_cla24_ha11_xor0 ha_and0=u_wallace_cla24_ha11_and0
.subckt fa a=u_wallace_cla24_ha11_and0 b=u_wallace_cla24_fa256_xor1 cin=u_wallace_cla24_fa283_xor1 fa_xor1=u_wallace_cla24_fa352_xor1 fa_or0=u_wallace_cla24_fa352_or0
.subckt fa a=u_wallace_cla24_fa352_or0 b=u_wallace_cla24_fa228_xor1 cin=u_wallace_cla24_fa257_xor1 fa_xor1=u_wallace_cla24_fa353_xor1 fa_or0=u_wallace_cla24_fa353_or0
.subckt fa a=u_wallace_cla24_fa353_or0 b=u_wallace_cla24_fa198_xor1 cin=u_wallace_cla24_fa229_xor1 fa_xor1=u_wallace_cla24_fa354_xor1 fa_or0=u_wallace_cla24_fa354_or0
.subckt fa a=u_wallace_cla24_fa354_or0 b=u_wallace_cla24_fa166_xor1 cin=u_wallace_cla24_fa199_xor1 fa_xor1=u_wallace_cla24_fa355_xor1 fa_or0=u_wallace_cla24_fa355_or0
.subckt fa a=u_wallace_cla24_fa355_or0 b=u_wallace_cla24_fa132_xor1 cin=u_wallace_cla24_fa167_xor1 fa_xor1=u_wallace_cla24_fa356_xor1 fa_or0=u_wallace_cla24_fa356_or0
.subckt fa a=u_wallace_cla24_fa356_or0 b=u_wallace_cla24_fa96_xor1 cin=u_wallace_cla24_fa133_xor1 fa_xor1=u_wallace_cla24_fa357_xor1 fa_or0=u_wallace_cla24_fa357_or0
.subckt fa a=u_wallace_cla24_fa357_or0 b=u_wallace_cla24_fa58_xor1 cin=u_wallace_cla24_fa97_xor1 fa_xor1=u_wallace_cla24_fa358_xor1 fa_or0=u_wallace_cla24_fa358_or0
.subckt fa a=u_wallace_cla24_fa358_or0 b=u_wallace_cla24_fa18_xor1 cin=u_wallace_cla24_fa59_xor1 fa_xor1=u_wallace_cla24_fa359_xor1 fa_or0=u_wallace_cla24_fa359_or0
.subckt and_gate a=a[0] b=b[22] out=u_wallace_cla24_and_0_22
.subckt fa a=u_wallace_cla24_fa359_or0 b=u_wallace_cla24_and_0_22 cin=u_wallace_cla24_fa19_xor1 fa_xor1=u_wallace_cla24_fa360_xor1 fa_or0=u_wallace_cla24_fa360_or0
.subckt and_gate a=a[1] b=b[22] out=u_wallace_cla24_and_1_22
.subckt and_gate a=a[0] b=b[23] out=u_wallace_cla24_and_0_23
.subckt fa a=u_wallace_cla24_fa360_or0 b=u_wallace_cla24_and_1_22 cin=u_wallace_cla24_and_0_23 fa_xor1=u_wallace_cla24_fa361_xor1 fa_or0=u_wallace_cla24_fa361_or0
.subckt and_gate a=a[1] b=b[23] out=u_wallace_cla24_and_1_23
.subckt fa a=u_wallace_cla24_fa361_or0 b=u_wallace_cla24_and_1_23 cin=u_wallace_cla24_fa21_xor1 fa_xor1=u_wallace_cla24_fa362_xor1 fa_or0=u_wallace_cla24_fa362_or0
.subckt fa a=u_wallace_cla24_fa362_or0 b=u_wallace_cla24_fa22_xor1 cin=u_wallace_cla24_fa63_xor1 fa_xor1=u_wallace_cla24_fa363_xor1 fa_or0=u_wallace_cla24_fa363_or0
.subckt fa a=u_wallace_cla24_fa363_or0 b=u_wallace_cla24_fa64_xor1 cin=u_wallace_cla24_fa103_xor1 fa_xor1=u_wallace_cla24_fa364_xor1 fa_or0=u_wallace_cla24_fa364_or0
.subckt fa a=u_wallace_cla24_fa364_or0 b=u_wallace_cla24_fa104_xor1 cin=u_wallace_cla24_fa141_xor1 fa_xor1=u_wallace_cla24_fa365_xor1 fa_or0=u_wallace_cla24_fa365_or0
.subckt fa a=u_wallace_cla24_fa365_or0 b=u_wallace_cla24_fa142_xor1 cin=u_wallace_cla24_fa177_xor1 fa_xor1=u_wallace_cla24_fa366_xor1 fa_or0=u_wallace_cla24_fa366_or0
.subckt fa a=u_wallace_cla24_fa366_or0 b=u_wallace_cla24_fa178_xor1 cin=u_wallace_cla24_fa211_xor1 fa_xor1=u_wallace_cla24_fa367_xor1 fa_or0=u_wallace_cla24_fa367_or0
.subckt fa a=u_wallace_cla24_fa367_or0 b=u_wallace_cla24_fa212_xor1 cin=u_wallace_cla24_fa243_xor1 fa_xor1=u_wallace_cla24_fa368_xor1 fa_or0=u_wallace_cla24_fa368_or0
.subckt fa a=u_wallace_cla24_fa368_or0 b=u_wallace_cla24_fa244_xor1 cin=u_wallace_cla24_fa273_xor1 fa_xor1=u_wallace_cla24_fa369_xor1 fa_or0=u_wallace_cla24_fa369_or0
.subckt fa a=u_wallace_cla24_fa369_or0 b=u_wallace_cla24_fa274_xor1 cin=u_wallace_cla24_fa301_xor1 fa_xor1=u_wallace_cla24_fa370_xor1 fa_or0=u_wallace_cla24_fa370_or0
.subckt fa a=u_wallace_cla24_fa370_or0 b=u_wallace_cla24_fa302_xor1 cin=u_wallace_cla24_fa327_xor1 fa_xor1=u_wallace_cla24_fa371_xor1 fa_or0=u_wallace_cla24_fa371_or0
.subckt ha a=u_wallace_cla24_fa308_xor1 b=u_wallace_cla24_fa331_xor1 ha_xor0=u_wallace_cla24_ha12_xor0 ha_and0=u_wallace_cla24_ha12_and0
.subckt fa a=u_wallace_cla24_ha12_and0 b=u_wallace_cla24_fa284_xor1 cin=u_wallace_cla24_fa309_xor1 fa_xor1=u_wallace_cla24_fa372_xor1 fa_or0=u_wallace_cla24_fa372_or0
.subckt fa a=u_wallace_cla24_fa372_or0 b=u_wallace_cla24_fa258_xor1 cin=u_wallace_cla24_fa285_xor1 fa_xor1=u_wallace_cla24_fa373_xor1 fa_or0=u_wallace_cla24_fa373_or0
.subckt fa a=u_wallace_cla24_fa373_or0 b=u_wallace_cla24_fa230_xor1 cin=u_wallace_cla24_fa259_xor1 fa_xor1=u_wallace_cla24_fa374_xor1 fa_or0=u_wallace_cla24_fa374_or0
.subckt fa a=u_wallace_cla24_fa374_or0 b=u_wallace_cla24_fa200_xor1 cin=u_wallace_cla24_fa231_xor1 fa_xor1=u_wallace_cla24_fa375_xor1 fa_or0=u_wallace_cla24_fa375_or0
.subckt fa a=u_wallace_cla24_fa375_or0 b=u_wallace_cla24_fa168_xor1 cin=u_wallace_cla24_fa201_xor1 fa_xor1=u_wallace_cla24_fa376_xor1 fa_or0=u_wallace_cla24_fa376_or0
.subckt fa a=u_wallace_cla24_fa376_or0 b=u_wallace_cla24_fa134_xor1 cin=u_wallace_cla24_fa169_xor1 fa_xor1=u_wallace_cla24_fa377_xor1 fa_or0=u_wallace_cla24_fa377_or0
.subckt fa a=u_wallace_cla24_fa377_or0 b=u_wallace_cla24_fa98_xor1 cin=u_wallace_cla24_fa135_xor1 fa_xor1=u_wallace_cla24_fa378_xor1 fa_or0=u_wallace_cla24_fa378_or0
.subckt fa a=u_wallace_cla24_fa378_or0 b=u_wallace_cla24_fa60_xor1 cin=u_wallace_cla24_fa99_xor1 fa_xor1=u_wallace_cla24_fa379_xor1 fa_or0=u_wallace_cla24_fa379_or0
.subckt fa a=u_wallace_cla24_fa379_or0 b=u_wallace_cla24_fa20_xor1 cin=u_wallace_cla24_fa61_xor1 fa_xor1=u_wallace_cla24_fa380_xor1 fa_or0=u_wallace_cla24_fa380_or0
.subckt fa a=u_wallace_cla24_fa380_or0 b=u_wallace_cla24_fa62_xor1 cin=u_wallace_cla24_fa101_xor1 fa_xor1=u_wallace_cla24_fa381_xor1 fa_or0=u_wallace_cla24_fa381_or0
.subckt fa a=u_wallace_cla24_fa381_or0 b=u_wallace_cla24_fa102_xor1 cin=u_wallace_cla24_fa139_xor1 fa_xor1=u_wallace_cla24_fa382_xor1 fa_or0=u_wallace_cla24_fa382_or0
.subckt fa a=u_wallace_cla24_fa382_or0 b=u_wallace_cla24_fa140_xor1 cin=u_wallace_cla24_fa175_xor1 fa_xor1=u_wallace_cla24_fa383_xor1 fa_or0=u_wallace_cla24_fa383_or0
.subckt fa a=u_wallace_cla24_fa383_or0 b=u_wallace_cla24_fa176_xor1 cin=u_wallace_cla24_fa209_xor1 fa_xor1=u_wallace_cla24_fa384_xor1 fa_or0=u_wallace_cla24_fa384_or0
.subckt fa a=u_wallace_cla24_fa384_or0 b=u_wallace_cla24_fa210_xor1 cin=u_wallace_cla24_fa241_xor1 fa_xor1=u_wallace_cla24_fa385_xor1 fa_or0=u_wallace_cla24_fa385_or0
.subckt fa a=u_wallace_cla24_fa385_or0 b=u_wallace_cla24_fa242_xor1 cin=u_wallace_cla24_fa271_xor1 fa_xor1=u_wallace_cla24_fa386_xor1 fa_or0=u_wallace_cla24_fa386_or0
.subckt fa a=u_wallace_cla24_fa386_or0 b=u_wallace_cla24_fa272_xor1 cin=u_wallace_cla24_fa299_xor1 fa_xor1=u_wallace_cla24_fa387_xor1 fa_or0=u_wallace_cla24_fa387_or0
.subckt fa a=u_wallace_cla24_fa387_or0 b=u_wallace_cla24_fa300_xor1 cin=u_wallace_cla24_fa325_xor1 fa_xor1=u_wallace_cla24_fa388_xor1 fa_or0=u_wallace_cla24_fa388_or0
.subckt fa a=u_wallace_cla24_fa388_or0 b=u_wallace_cla24_fa326_xor1 cin=u_wallace_cla24_fa349_xor1 fa_xor1=u_wallace_cla24_fa389_xor1 fa_or0=u_wallace_cla24_fa389_or0
.subckt ha a=u_wallace_cla24_fa332_xor1 b=u_wallace_cla24_fa353_xor1 ha_xor0=u_wallace_cla24_ha13_xor0 ha_and0=u_wallace_cla24_ha13_and0
.subckt fa a=u_wallace_cla24_ha13_and0 b=u_wallace_cla24_fa310_xor1 cin=u_wallace_cla24_fa333_xor1 fa_xor1=u_wallace_cla24_fa390_xor1 fa_or0=u_wallace_cla24_fa390_or0
.subckt fa a=u_wallace_cla24_fa390_or0 b=u_wallace_cla24_fa286_xor1 cin=u_wallace_cla24_fa311_xor1 fa_xor1=u_wallace_cla24_fa391_xor1 fa_or0=u_wallace_cla24_fa391_or0
.subckt fa a=u_wallace_cla24_fa391_or0 b=u_wallace_cla24_fa260_xor1 cin=u_wallace_cla24_fa287_xor1 fa_xor1=u_wallace_cla24_fa392_xor1 fa_or0=u_wallace_cla24_fa392_or0
.subckt fa a=u_wallace_cla24_fa392_or0 b=u_wallace_cla24_fa232_xor1 cin=u_wallace_cla24_fa261_xor1 fa_xor1=u_wallace_cla24_fa393_xor1 fa_or0=u_wallace_cla24_fa393_or0
.subckt fa a=u_wallace_cla24_fa393_or0 b=u_wallace_cla24_fa202_xor1 cin=u_wallace_cla24_fa233_xor1 fa_xor1=u_wallace_cla24_fa394_xor1 fa_or0=u_wallace_cla24_fa394_or0
.subckt fa a=u_wallace_cla24_fa394_or0 b=u_wallace_cla24_fa170_xor1 cin=u_wallace_cla24_fa203_xor1 fa_xor1=u_wallace_cla24_fa395_xor1 fa_or0=u_wallace_cla24_fa395_or0
.subckt fa a=u_wallace_cla24_fa395_or0 b=u_wallace_cla24_fa136_xor1 cin=u_wallace_cla24_fa171_xor1 fa_xor1=u_wallace_cla24_fa396_xor1 fa_or0=u_wallace_cla24_fa396_or0
.subckt fa a=u_wallace_cla24_fa396_or0 b=u_wallace_cla24_fa100_xor1 cin=u_wallace_cla24_fa137_xor1 fa_xor1=u_wallace_cla24_fa397_xor1 fa_or0=u_wallace_cla24_fa397_or0
.subckt fa a=u_wallace_cla24_fa397_or0 b=u_wallace_cla24_fa138_xor1 cin=u_wallace_cla24_fa173_xor1 fa_xor1=u_wallace_cla24_fa398_xor1 fa_or0=u_wallace_cla24_fa398_or0
.subckt fa a=u_wallace_cla24_fa398_or0 b=u_wallace_cla24_fa174_xor1 cin=u_wallace_cla24_fa207_xor1 fa_xor1=u_wallace_cla24_fa399_xor1 fa_or0=u_wallace_cla24_fa399_or0
.subckt fa a=u_wallace_cla24_fa399_or0 b=u_wallace_cla24_fa208_xor1 cin=u_wallace_cla24_fa239_xor1 fa_xor1=u_wallace_cla24_fa400_xor1 fa_or0=u_wallace_cla24_fa400_or0
.subckt fa a=u_wallace_cla24_fa400_or0 b=u_wallace_cla24_fa240_xor1 cin=u_wallace_cla24_fa269_xor1 fa_xor1=u_wallace_cla24_fa401_xor1 fa_or0=u_wallace_cla24_fa401_or0
.subckt fa a=u_wallace_cla24_fa401_or0 b=u_wallace_cla24_fa270_xor1 cin=u_wallace_cla24_fa297_xor1 fa_xor1=u_wallace_cla24_fa402_xor1 fa_or0=u_wallace_cla24_fa402_or0
.subckt fa a=u_wallace_cla24_fa402_or0 b=u_wallace_cla24_fa298_xor1 cin=u_wallace_cla24_fa323_xor1 fa_xor1=u_wallace_cla24_fa403_xor1 fa_or0=u_wallace_cla24_fa403_or0
.subckt fa a=u_wallace_cla24_fa403_or0 b=u_wallace_cla24_fa324_xor1 cin=u_wallace_cla24_fa347_xor1 fa_xor1=u_wallace_cla24_fa404_xor1 fa_or0=u_wallace_cla24_fa404_or0
.subckt fa a=u_wallace_cla24_fa404_or0 b=u_wallace_cla24_fa348_xor1 cin=u_wallace_cla24_fa369_xor1 fa_xor1=u_wallace_cla24_fa405_xor1 fa_or0=u_wallace_cla24_fa405_or0
.subckt ha a=u_wallace_cla24_fa354_xor1 b=u_wallace_cla24_fa373_xor1 ha_xor0=u_wallace_cla24_ha14_xor0 ha_and0=u_wallace_cla24_ha14_and0
.subckt fa a=u_wallace_cla24_ha14_and0 b=u_wallace_cla24_fa334_xor1 cin=u_wallace_cla24_fa355_xor1 fa_xor1=u_wallace_cla24_fa406_xor1 fa_or0=u_wallace_cla24_fa406_or0
.subckt fa a=u_wallace_cla24_fa406_or0 b=u_wallace_cla24_fa312_xor1 cin=u_wallace_cla24_fa335_xor1 fa_xor1=u_wallace_cla24_fa407_xor1 fa_or0=u_wallace_cla24_fa407_or0
.subckt fa a=u_wallace_cla24_fa407_or0 b=u_wallace_cla24_fa288_xor1 cin=u_wallace_cla24_fa313_xor1 fa_xor1=u_wallace_cla24_fa408_xor1 fa_or0=u_wallace_cla24_fa408_or0
.subckt fa a=u_wallace_cla24_fa408_or0 b=u_wallace_cla24_fa262_xor1 cin=u_wallace_cla24_fa289_xor1 fa_xor1=u_wallace_cla24_fa409_xor1 fa_or0=u_wallace_cla24_fa409_or0
.subckt fa a=u_wallace_cla24_fa409_or0 b=u_wallace_cla24_fa234_xor1 cin=u_wallace_cla24_fa263_xor1 fa_xor1=u_wallace_cla24_fa410_xor1 fa_or0=u_wallace_cla24_fa410_or0
.subckt fa a=u_wallace_cla24_fa410_or0 b=u_wallace_cla24_fa204_xor1 cin=u_wallace_cla24_fa235_xor1 fa_xor1=u_wallace_cla24_fa411_xor1 fa_or0=u_wallace_cla24_fa411_or0
.subckt fa a=u_wallace_cla24_fa411_or0 b=u_wallace_cla24_fa172_xor1 cin=u_wallace_cla24_fa205_xor1 fa_xor1=u_wallace_cla24_fa412_xor1 fa_or0=u_wallace_cla24_fa412_or0
.subckt fa a=u_wallace_cla24_fa412_or0 b=u_wallace_cla24_fa206_xor1 cin=u_wallace_cla24_fa237_xor1 fa_xor1=u_wallace_cla24_fa413_xor1 fa_or0=u_wallace_cla24_fa413_or0
.subckt fa a=u_wallace_cla24_fa413_or0 b=u_wallace_cla24_fa238_xor1 cin=u_wallace_cla24_fa267_xor1 fa_xor1=u_wallace_cla24_fa414_xor1 fa_or0=u_wallace_cla24_fa414_or0
.subckt fa a=u_wallace_cla24_fa414_or0 b=u_wallace_cla24_fa268_xor1 cin=u_wallace_cla24_fa295_xor1 fa_xor1=u_wallace_cla24_fa415_xor1 fa_or0=u_wallace_cla24_fa415_or0
.subckt fa a=u_wallace_cla24_fa415_or0 b=u_wallace_cla24_fa296_xor1 cin=u_wallace_cla24_fa321_xor1 fa_xor1=u_wallace_cla24_fa416_xor1 fa_or0=u_wallace_cla24_fa416_or0
.subckt fa a=u_wallace_cla24_fa416_or0 b=u_wallace_cla24_fa322_xor1 cin=u_wallace_cla24_fa345_xor1 fa_xor1=u_wallace_cla24_fa417_xor1 fa_or0=u_wallace_cla24_fa417_or0
.subckt fa a=u_wallace_cla24_fa417_or0 b=u_wallace_cla24_fa346_xor1 cin=u_wallace_cla24_fa367_xor1 fa_xor1=u_wallace_cla24_fa418_xor1 fa_or0=u_wallace_cla24_fa418_or0
.subckt fa a=u_wallace_cla24_fa418_or0 b=u_wallace_cla24_fa368_xor1 cin=u_wallace_cla24_fa387_xor1 fa_xor1=u_wallace_cla24_fa419_xor1 fa_or0=u_wallace_cla24_fa419_or0
.subckt ha a=u_wallace_cla24_fa374_xor1 b=u_wallace_cla24_fa391_xor1 ha_xor0=u_wallace_cla24_ha15_xor0 ha_and0=u_wallace_cla24_ha15_and0
.subckt fa a=u_wallace_cla24_ha15_and0 b=u_wallace_cla24_fa356_xor1 cin=u_wallace_cla24_fa375_xor1 fa_xor1=u_wallace_cla24_fa420_xor1 fa_or0=u_wallace_cla24_fa420_or0
.subckt fa a=u_wallace_cla24_fa420_or0 b=u_wallace_cla24_fa336_xor1 cin=u_wallace_cla24_fa357_xor1 fa_xor1=u_wallace_cla24_fa421_xor1 fa_or0=u_wallace_cla24_fa421_or0
.subckt fa a=u_wallace_cla24_fa421_or0 b=u_wallace_cla24_fa314_xor1 cin=u_wallace_cla24_fa337_xor1 fa_xor1=u_wallace_cla24_fa422_xor1 fa_or0=u_wallace_cla24_fa422_or0
.subckt fa a=u_wallace_cla24_fa422_or0 b=u_wallace_cla24_fa290_xor1 cin=u_wallace_cla24_fa315_xor1 fa_xor1=u_wallace_cla24_fa423_xor1 fa_or0=u_wallace_cla24_fa423_or0
.subckt fa a=u_wallace_cla24_fa423_or0 b=u_wallace_cla24_fa264_xor1 cin=u_wallace_cla24_fa291_xor1 fa_xor1=u_wallace_cla24_fa424_xor1 fa_or0=u_wallace_cla24_fa424_or0
.subckt fa a=u_wallace_cla24_fa424_or0 b=u_wallace_cla24_fa236_xor1 cin=u_wallace_cla24_fa265_xor1 fa_xor1=u_wallace_cla24_fa425_xor1 fa_or0=u_wallace_cla24_fa425_or0
.subckt fa a=u_wallace_cla24_fa425_or0 b=u_wallace_cla24_fa266_xor1 cin=u_wallace_cla24_fa293_xor1 fa_xor1=u_wallace_cla24_fa426_xor1 fa_or0=u_wallace_cla24_fa426_or0
.subckt fa a=u_wallace_cla24_fa426_or0 b=u_wallace_cla24_fa294_xor1 cin=u_wallace_cla24_fa319_xor1 fa_xor1=u_wallace_cla24_fa427_xor1 fa_or0=u_wallace_cla24_fa427_or0
.subckt fa a=u_wallace_cla24_fa427_or0 b=u_wallace_cla24_fa320_xor1 cin=u_wallace_cla24_fa343_xor1 fa_xor1=u_wallace_cla24_fa428_xor1 fa_or0=u_wallace_cla24_fa428_or0
.subckt fa a=u_wallace_cla24_fa428_or0 b=u_wallace_cla24_fa344_xor1 cin=u_wallace_cla24_fa365_xor1 fa_xor1=u_wallace_cla24_fa429_xor1 fa_or0=u_wallace_cla24_fa429_or0
.subckt fa a=u_wallace_cla24_fa429_or0 b=u_wallace_cla24_fa366_xor1 cin=u_wallace_cla24_fa385_xor1 fa_xor1=u_wallace_cla24_fa430_xor1 fa_or0=u_wallace_cla24_fa430_or0
.subckt fa a=u_wallace_cla24_fa430_or0 b=u_wallace_cla24_fa386_xor1 cin=u_wallace_cla24_fa403_xor1 fa_xor1=u_wallace_cla24_fa431_xor1 fa_or0=u_wallace_cla24_fa431_or0
.subckt ha a=u_wallace_cla24_fa392_xor1 b=u_wallace_cla24_fa407_xor1 ha_xor0=u_wallace_cla24_ha16_xor0 ha_and0=u_wallace_cla24_ha16_and0
.subckt fa a=u_wallace_cla24_ha16_and0 b=u_wallace_cla24_fa376_xor1 cin=u_wallace_cla24_fa393_xor1 fa_xor1=u_wallace_cla24_fa432_xor1 fa_or0=u_wallace_cla24_fa432_or0
.subckt fa a=u_wallace_cla24_fa432_or0 b=u_wallace_cla24_fa358_xor1 cin=u_wallace_cla24_fa377_xor1 fa_xor1=u_wallace_cla24_fa433_xor1 fa_or0=u_wallace_cla24_fa433_or0
.subckt fa a=u_wallace_cla24_fa433_or0 b=u_wallace_cla24_fa338_xor1 cin=u_wallace_cla24_fa359_xor1 fa_xor1=u_wallace_cla24_fa434_xor1 fa_or0=u_wallace_cla24_fa434_or0
.subckt fa a=u_wallace_cla24_fa434_or0 b=u_wallace_cla24_fa316_xor1 cin=u_wallace_cla24_fa339_xor1 fa_xor1=u_wallace_cla24_fa435_xor1 fa_or0=u_wallace_cla24_fa435_or0
.subckt fa a=u_wallace_cla24_fa435_or0 b=u_wallace_cla24_fa292_xor1 cin=u_wallace_cla24_fa317_xor1 fa_xor1=u_wallace_cla24_fa436_xor1 fa_or0=u_wallace_cla24_fa436_or0
.subckt fa a=u_wallace_cla24_fa436_or0 b=u_wallace_cla24_fa318_xor1 cin=u_wallace_cla24_fa341_xor1 fa_xor1=u_wallace_cla24_fa437_xor1 fa_or0=u_wallace_cla24_fa437_or0
.subckt fa a=u_wallace_cla24_fa437_or0 b=u_wallace_cla24_fa342_xor1 cin=u_wallace_cla24_fa363_xor1 fa_xor1=u_wallace_cla24_fa438_xor1 fa_or0=u_wallace_cla24_fa438_or0
.subckt fa a=u_wallace_cla24_fa438_or0 b=u_wallace_cla24_fa364_xor1 cin=u_wallace_cla24_fa383_xor1 fa_xor1=u_wallace_cla24_fa439_xor1 fa_or0=u_wallace_cla24_fa439_or0
.subckt fa a=u_wallace_cla24_fa439_or0 b=u_wallace_cla24_fa384_xor1 cin=u_wallace_cla24_fa401_xor1 fa_xor1=u_wallace_cla24_fa440_xor1 fa_or0=u_wallace_cla24_fa440_or0
.subckt fa a=u_wallace_cla24_fa440_or0 b=u_wallace_cla24_fa402_xor1 cin=u_wallace_cla24_fa417_xor1 fa_xor1=u_wallace_cla24_fa441_xor1 fa_or0=u_wallace_cla24_fa441_or0
.subckt ha a=u_wallace_cla24_fa408_xor1 b=u_wallace_cla24_fa421_xor1 ha_xor0=u_wallace_cla24_ha17_xor0 ha_and0=u_wallace_cla24_ha17_and0
.subckt fa a=u_wallace_cla24_ha17_and0 b=u_wallace_cla24_fa394_xor1 cin=u_wallace_cla24_fa409_xor1 fa_xor1=u_wallace_cla24_fa442_xor1 fa_or0=u_wallace_cla24_fa442_or0
.subckt fa a=u_wallace_cla24_fa442_or0 b=u_wallace_cla24_fa378_xor1 cin=u_wallace_cla24_fa395_xor1 fa_xor1=u_wallace_cla24_fa443_xor1 fa_or0=u_wallace_cla24_fa443_or0
.subckt fa a=u_wallace_cla24_fa443_or0 b=u_wallace_cla24_fa360_xor1 cin=u_wallace_cla24_fa379_xor1 fa_xor1=u_wallace_cla24_fa444_xor1 fa_or0=u_wallace_cla24_fa444_or0
.subckt fa a=u_wallace_cla24_fa444_or0 b=u_wallace_cla24_fa340_xor1 cin=u_wallace_cla24_fa361_xor1 fa_xor1=u_wallace_cla24_fa445_xor1 fa_or0=u_wallace_cla24_fa445_or0
.subckt fa a=u_wallace_cla24_fa445_or0 b=u_wallace_cla24_fa362_xor1 cin=u_wallace_cla24_fa381_xor1 fa_xor1=u_wallace_cla24_fa446_xor1 fa_or0=u_wallace_cla24_fa446_or0
.subckt fa a=u_wallace_cla24_fa446_or0 b=u_wallace_cla24_fa382_xor1 cin=u_wallace_cla24_fa399_xor1 fa_xor1=u_wallace_cla24_fa447_xor1 fa_or0=u_wallace_cla24_fa447_or0
.subckt fa a=u_wallace_cla24_fa447_or0 b=u_wallace_cla24_fa400_xor1 cin=u_wallace_cla24_fa415_xor1 fa_xor1=u_wallace_cla24_fa448_xor1 fa_or0=u_wallace_cla24_fa448_or0
.subckt fa a=u_wallace_cla24_fa448_or0 b=u_wallace_cla24_fa416_xor1 cin=u_wallace_cla24_fa429_xor1 fa_xor1=u_wallace_cla24_fa449_xor1 fa_or0=u_wallace_cla24_fa449_or0
.subckt ha a=u_wallace_cla24_fa422_xor1 b=u_wallace_cla24_fa433_xor1 ha_xor0=u_wallace_cla24_ha18_xor0 ha_and0=u_wallace_cla24_ha18_and0
.subckt fa a=u_wallace_cla24_ha18_and0 b=u_wallace_cla24_fa410_xor1 cin=u_wallace_cla24_fa423_xor1 fa_xor1=u_wallace_cla24_fa450_xor1 fa_or0=u_wallace_cla24_fa450_or0
.subckt fa a=u_wallace_cla24_fa450_or0 b=u_wallace_cla24_fa396_xor1 cin=u_wallace_cla24_fa411_xor1 fa_xor1=u_wallace_cla24_fa451_xor1 fa_or0=u_wallace_cla24_fa451_or0
.subckt fa a=u_wallace_cla24_fa451_or0 b=u_wallace_cla24_fa380_xor1 cin=u_wallace_cla24_fa397_xor1 fa_xor1=u_wallace_cla24_fa452_xor1 fa_or0=u_wallace_cla24_fa452_or0
.subckt fa a=u_wallace_cla24_fa452_or0 b=u_wallace_cla24_fa398_xor1 cin=u_wallace_cla24_fa413_xor1 fa_xor1=u_wallace_cla24_fa453_xor1 fa_or0=u_wallace_cla24_fa453_or0
.subckt fa a=u_wallace_cla24_fa453_or0 b=u_wallace_cla24_fa414_xor1 cin=u_wallace_cla24_fa427_xor1 fa_xor1=u_wallace_cla24_fa454_xor1 fa_or0=u_wallace_cla24_fa454_or0
.subckt fa a=u_wallace_cla24_fa454_or0 b=u_wallace_cla24_fa428_xor1 cin=u_wallace_cla24_fa439_xor1 fa_xor1=u_wallace_cla24_fa455_xor1 fa_or0=u_wallace_cla24_fa455_or0
.subckt ha a=u_wallace_cla24_fa434_xor1 b=u_wallace_cla24_fa443_xor1 ha_xor0=u_wallace_cla24_ha19_xor0 ha_and0=u_wallace_cla24_ha19_and0
.subckt fa a=u_wallace_cla24_ha19_and0 b=u_wallace_cla24_fa424_xor1 cin=u_wallace_cla24_fa435_xor1 fa_xor1=u_wallace_cla24_fa456_xor1 fa_or0=u_wallace_cla24_fa456_or0
.subckt fa a=u_wallace_cla24_fa456_or0 b=u_wallace_cla24_fa412_xor1 cin=u_wallace_cla24_fa425_xor1 fa_xor1=u_wallace_cla24_fa457_xor1 fa_or0=u_wallace_cla24_fa457_or0
.subckt fa a=u_wallace_cla24_fa457_or0 b=u_wallace_cla24_fa426_xor1 cin=u_wallace_cla24_fa437_xor1 fa_xor1=u_wallace_cla24_fa458_xor1 fa_or0=u_wallace_cla24_fa458_or0
.subckt fa a=u_wallace_cla24_fa458_or0 b=u_wallace_cla24_fa438_xor1 cin=u_wallace_cla24_fa447_xor1 fa_xor1=u_wallace_cla24_fa459_xor1 fa_or0=u_wallace_cla24_fa459_or0
.subckt ha a=u_wallace_cla24_fa444_xor1 b=u_wallace_cla24_fa451_xor1 ha_xor0=u_wallace_cla24_ha20_xor0 ha_and0=u_wallace_cla24_ha20_and0
.subckt fa a=u_wallace_cla24_ha20_and0 b=u_wallace_cla24_fa436_xor1 cin=u_wallace_cla24_fa445_xor1 fa_xor1=u_wallace_cla24_fa460_xor1 fa_or0=u_wallace_cla24_fa460_or0
.subckt fa a=u_wallace_cla24_fa460_or0 b=u_wallace_cla24_fa446_xor1 cin=u_wallace_cla24_fa453_xor1 fa_xor1=u_wallace_cla24_fa461_xor1 fa_or0=u_wallace_cla24_fa461_or0
.subckt ha a=u_wallace_cla24_fa452_xor1 b=u_wallace_cla24_fa457_xor1 ha_xor0=u_wallace_cla24_ha21_xor0 ha_and0=u_wallace_cla24_ha21_and0
.subckt ha a=u_wallace_cla24_ha21_and0 b=u_wallace_cla24_fa458_xor1 ha_xor0=u_wallace_cla24_ha22_xor0 ha_and0=u_wallace_cla24_ha22_and0
.subckt fa a=u_wallace_cla24_ha22_and0 b=u_wallace_cla24_fa461_or0 cin=u_wallace_cla24_fa454_xor1 fa_xor1=u_wallace_cla24_fa462_xor1 fa_or0=u_wallace_cla24_fa462_or0
.subckt fa a=u_wallace_cla24_fa462_or0 b=u_wallace_cla24_fa459_or0 cin=u_wallace_cla24_fa448_xor1 fa_xor1=u_wallace_cla24_fa463_xor1 fa_or0=u_wallace_cla24_fa463_or0
.subckt fa a=u_wallace_cla24_fa463_or0 b=u_wallace_cla24_fa455_or0 cin=u_wallace_cla24_fa440_xor1 fa_xor1=u_wallace_cla24_fa464_xor1 fa_or0=u_wallace_cla24_fa464_or0
.subckt fa a=u_wallace_cla24_fa464_or0 b=u_wallace_cla24_fa449_or0 cin=u_wallace_cla24_fa430_xor1 fa_xor1=u_wallace_cla24_fa465_xor1 fa_or0=u_wallace_cla24_fa465_or0
.subckt fa a=u_wallace_cla24_fa465_or0 b=u_wallace_cla24_fa441_or0 cin=u_wallace_cla24_fa418_xor1 fa_xor1=u_wallace_cla24_fa466_xor1 fa_or0=u_wallace_cla24_fa466_or0
.subckt fa a=u_wallace_cla24_fa466_or0 b=u_wallace_cla24_fa431_or0 cin=u_wallace_cla24_fa404_xor1 fa_xor1=u_wallace_cla24_fa467_xor1 fa_or0=u_wallace_cla24_fa467_or0
.subckt fa a=u_wallace_cla24_fa467_or0 b=u_wallace_cla24_fa419_or0 cin=u_wallace_cla24_fa388_xor1 fa_xor1=u_wallace_cla24_fa468_xor1 fa_or0=u_wallace_cla24_fa468_or0
.subckt fa a=u_wallace_cla24_fa468_or0 b=u_wallace_cla24_fa405_or0 cin=u_wallace_cla24_fa370_xor1 fa_xor1=u_wallace_cla24_fa469_xor1 fa_or0=u_wallace_cla24_fa469_or0
.subckt fa a=u_wallace_cla24_fa469_or0 b=u_wallace_cla24_fa389_or0 cin=u_wallace_cla24_fa350_xor1 fa_xor1=u_wallace_cla24_fa470_xor1 fa_or0=u_wallace_cla24_fa470_or0
.subckt fa a=u_wallace_cla24_fa470_or0 b=u_wallace_cla24_fa371_or0 cin=u_wallace_cla24_fa328_xor1 fa_xor1=u_wallace_cla24_fa471_xor1 fa_or0=u_wallace_cla24_fa471_or0
.subckt fa a=u_wallace_cla24_fa471_or0 b=u_wallace_cla24_fa351_or0 cin=u_wallace_cla24_fa304_xor1 fa_xor1=u_wallace_cla24_fa472_xor1 fa_or0=u_wallace_cla24_fa472_or0
.subckt fa a=u_wallace_cla24_fa472_or0 b=u_wallace_cla24_fa329_or0 cin=u_wallace_cla24_fa278_xor1 fa_xor1=u_wallace_cla24_fa473_xor1 fa_or0=u_wallace_cla24_fa473_or0
.subckt fa a=u_wallace_cla24_fa473_or0 b=u_wallace_cla24_fa305_or0 cin=u_wallace_cla24_fa250_xor1 fa_xor1=u_wallace_cla24_fa474_xor1 fa_or0=u_wallace_cla24_fa474_or0
.subckt fa a=u_wallace_cla24_fa474_or0 b=u_wallace_cla24_fa279_or0 cin=u_wallace_cla24_fa220_xor1 fa_xor1=u_wallace_cla24_fa475_xor1 fa_or0=u_wallace_cla24_fa475_or0
.subckt fa a=u_wallace_cla24_fa475_or0 b=u_wallace_cla24_fa251_or0 cin=u_wallace_cla24_fa188_xor1 fa_xor1=u_wallace_cla24_fa476_xor1 fa_or0=u_wallace_cla24_fa476_or0
.subckt fa a=u_wallace_cla24_fa476_or0 b=u_wallace_cla24_fa221_or0 cin=u_wallace_cla24_fa154_xor1 fa_xor1=u_wallace_cla24_fa477_xor1 fa_or0=u_wallace_cla24_fa477_or0
.subckt fa a=u_wallace_cla24_fa477_or0 b=u_wallace_cla24_fa189_or0 cin=u_wallace_cla24_fa118_xor1 fa_xor1=u_wallace_cla24_fa478_xor1 fa_or0=u_wallace_cla24_fa478_or0
.subckt fa a=u_wallace_cla24_fa478_or0 b=u_wallace_cla24_fa155_or0 cin=u_wallace_cla24_fa80_xor1 fa_xor1=u_wallace_cla24_fa479_xor1 fa_or0=u_wallace_cla24_fa479_or0
.subckt fa a=u_wallace_cla24_fa479_or0 b=u_wallace_cla24_fa119_or0 cin=u_wallace_cla24_fa40_xor1 fa_xor1=u_wallace_cla24_fa480_xor1 fa_or0=u_wallace_cla24_fa480_or0
.subckt and_gate a=a[21] b=b[23] out=u_wallace_cla24_and_21_23
.subckt fa a=u_wallace_cla24_fa480_or0 b=u_wallace_cla24_fa81_or0 cin=u_wallace_cla24_and_21_23 fa_xor1=u_wallace_cla24_fa481_xor1 fa_or0=u_wallace_cla24_fa481_or0
.subckt and_gate a=a[23] b=b[22] out=u_wallace_cla24_and_23_22
.subckt fa a=u_wallace_cla24_fa481_or0 b=u_wallace_cla24_fa41_or0 cin=u_wallace_cla24_and_23_22 fa_xor1=u_wallace_cla24_fa482_xor1 fa_or0=u_wallace_cla24_fa482_or0
.subckt and_gate a=a[0] b=b[0] out=u_wallace_cla24_and_0_0
.subckt and_gate a=a[1] b=b[0] out=u_wallace_cla24_and_1_0
.subckt and_gate a=a[0] b=b[2] out=u_wallace_cla24_and_0_2
.subckt and_gate a=a[22] b=b[23] out=u_wallace_cla24_and_22_23
.subckt and_gate a=a[0] b=b[1] out=u_wallace_cla24_and_0_1
.subckt and_gate a=a[23] b=b[23] out=u_wallace_cla24_and_23_23
.names u_wallace_cla24_and_1_0 u_wallace_cla24_u_cla46_a[0]
1 1
.names u_wallace_cla24_and_0_2 u_wallace_cla24_u_cla46_a[1]
1 1
.names u_wallace_cla24_fa0_xor1 u_wallace_cla24_u_cla46_a[2]
1 1
.names u_wallace_cla24_fa42_xor1 u_wallace_cla24_u_cla46_a[3]
1 1
.names u_wallace_cla24_fa82_xor1 u_wallace_cla24_u_cla46_a[4]
1 1
.names u_wallace_cla24_fa120_xor1 u_wallace_cla24_u_cla46_a[5]
1 1
.names u_wallace_cla24_fa156_xor1 u_wallace_cla24_u_cla46_a[6]
1 1
.names u_wallace_cla24_fa190_xor1 u_wallace_cla24_u_cla46_a[7]
1 1
.names u_wallace_cla24_fa222_xor1 u_wallace_cla24_u_cla46_a[8]
1 1
.names u_wallace_cla24_fa252_xor1 u_wallace_cla24_u_cla46_a[9]
1 1
.names u_wallace_cla24_fa280_xor1 u_wallace_cla24_u_cla46_a[10]
1 1
.names u_wallace_cla24_fa306_xor1 u_wallace_cla24_u_cla46_a[11]
1 1
.names u_wallace_cla24_fa330_xor1 u_wallace_cla24_u_cla46_a[12]
1 1
.names u_wallace_cla24_fa352_xor1 u_wallace_cla24_u_cla46_a[13]
1 1
.names u_wallace_cla24_fa372_xor1 u_wallace_cla24_u_cla46_a[14]
1 1
.names u_wallace_cla24_fa390_xor1 u_wallace_cla24_u_cla46_a[15]
1 1
.names u_wallace_cla24_fa406_xor1 u_wallace_cla24_u_cla46_a[16]
1 1
.names u_wallace_cla24_fa420_xor1 u_wallace_cla24_u_cla46_a[17]
1 1
.names u_wallace_cla24_fa432_xor1 u_wallace_cla24_u_cla46_a[18]
1 1
.names u_wallace_cla24_fa442_xor1 u_wallace_cla24_u_cla46_a[19]
1 1
.names u_wallace_cla24_fa450_xor1 u_wallace_cla24_u_cla46_a[20]
1 1
.names u_wallace_cla24_fa456_xor1 u_wallace_cla24_u_cla46_a[21]
1 1
.names u_wallace_cla24_fa460_xor1 u_wallace_cla24_u_cla46_a[22]
1 1
.names u_wallace_cla24_fa461_xor1 u_wallace_cla24_u_cla46_a[23]
1 1
.names u_wallace_cla24_fa459_xor1 u_wallace_cla24_u_cla46_a[24]
1 1
.names u_wallace_cla24_fa455_xor1 u_wallace_cla24_u_cla46_a[25]
1 1
.names u_wallace_cla24_fa449_xor1 u_wallace_cla24_u_cla46_a[26]
1 1
.names u_wallace_cla24_fa441_xor1 u_wallace_cla24_u_cla46_a[27]
1 1
.names u_wallace_cla24_fa431_xor1 u_wallace_cla24_u_cla46_a[28]
1 1
.names u_wallace_cla24_fa419_xor1 u_wallace_cla24_u_cla46_a[29]
1 1
.names u_wallace_cla24_fa405_xor1 u_wallace_cla24_u_cla46_a[30]
1 1
.names u_wallace_cla24_fa389_xor1 u_wallace_cla24_u_cla46_a[31]
1 1
.names u_wallace_cla24_fa371_xor1 u_wallace_cla24_u_cla46_a[32]
1 1
.names u_wallace_cla24_fa351_xor1 u_wallace_cla24_u_cla46_a[33]
1 1
.names u_wallace_cla24_fa329_xor1 u_wallace_cla24_u_cla46_a[34]
1 1
.names u_wallace_cla24_fa305_xor1 u_wallace_cla24_u_cla46_a[35]
1 1
.names u_wallace_cla24_fa279_xor1 u_wallace_cla24_u_cla46_a[36]
1 1
.names u_wallace_cla24_fa251_xor1 u_wallace_cla24_u_cla46_a[37]
1 1
.names u_wallace_cla24_fa221_xor1 u_wallace_cla24_u_cla46_a[38]
1 1
.names u_wallace_cla24_fa189_xor1 u_wallace_cla24_u_cla46_a[39]
1 1
.names u_wallace_cla24_fa155_xor1 u_wallace_cla24_u_cla46_a[40]
1 1
.names u_wallace_cla24_fa119_xor1 u_wallace_cla24_u_cla46_a[41]
1 1
.names u_wallace_cla24_fa81_xor1 u_wallace_cla24_u_cla46_a[42]
1 1
.names u_wallace_cla24_fa41_xor1 u_wallace_cla24_u_cla46_a[43]
1 1
.names u_wallace_cla24_and_22_23 u_wallace_cla24_u_cla46_a[44]
1 1
.names u_wallace_cla24_fa482_or0 u_wallace_cla24_u_cla46_a[45]
1 1
.names u_wallace_cla24_and_0_1 u_wallace_cla24_u_cla46_b[0]
1 1
.names u_wallace_cla24_ha0_xor0 u_wallace_cla24_u_cla46_b[1]
1 1
.names u_wallace_cla24_ha1_xor0 u_wallace_cla24_u_cla46_b[2]
1 1
.names u_wallace_cla24_ha2_xor0 u_wallace_cla24_u_cla46_b[3]
1 1
.names u_wallace_cla24_ha3_xor0 u_wallace_cla24_u_cla46_b[4]
1 1
.names u_wallace_cla24_ha4_xor0 u_wallace_cla24_u_cla46_b[5]
1 1
.names u_wallace_cla24_ha5_xor0 u_wallace_cla24_u_cla46_b[6]
1 1
.names u_wallace_cla24_ha6_xor0 u_wallace_cla24_u_cla46_b[7]
1 1
.names u_wallace_cla24_ha7_xor0 u_wallace_cla24_u_cla46_b[8]
1 1
.names u_wallace_cla24_ha8_xor0 u_wallace_cla24_u_cla46_b[9]
1 1
.names u_wallace_cla24_ha9_xor0 u_wallace_cla24_u_cla46_b[10]
1 1
.names u_wallace_cla24_ha10_xor0 u_wallace_cla24_u_cla46_b[11]
1 1
.names u_wallace_cla24_ha11_xor0 u_wallace_cla24_u_cla46_b[12]
1 1
.names u_wallace_cla24_ha12_xor0 u_wallace_cla24_u_cla46_b[13]
1 1
.names u_wallace_cla24_ha13_xor0 u_wallace_cla24_u_cla46_b[14]
1 1
.names u_wallace_cla24_ha14_xor0 u_wallace_cla24_u_cla46_b[15]
1 1
.names u_wallace_cla24_ha15_xor0 u_wallace_cla24_u_cla46_b[16]
1 1
.names u_wallace_cla24_ha16_xor0 u_wallace_cla24_u_cla46_b[17]
1 1
.names u_wallace_cla24_ha17_xor0 u_wallace_cla24_u_cla46_b[18]
1 1
.names u_wallace_cla24_ha18_xor0 u_wallace_cla24_u_cla46_b[19]
1 1
.names u_wallace_cla24_ha19_xor0 u_wallace_cla24_u_cla46_b[20]
1 1
.names u_wallace_cla24_ha20_xor0 u_wallace_cla24_u_cla46_b[21]
1 1
.names u_wallace_cla24_ha21_xor0 u_wallace_cla24_u_cla46_b[22]
1 1
.names u_wallace_cla24_ha22_xor0 u_wallace_cla24_u_cla46_b[23]
1 1
.names u_wallace_cla24_fa462_xor1 u_wallace_cla24_u_cla46_b[24]
1 1
.names u_wallace_cla24_fa463_xor1 u_wallace_cla24_u_cla46_b[25]
1 1
.names u_wallace_cla24_fa464_xor1 u_wallace_cla24_u_cla46_b[26]
1 1
.names u_wallace_cla24_fa465_xor1 u_wallace_cla24_u_cla46_b[27]
1 1
.names u_wallace_cla24_fa466_xor1 u_wallace_cla24_u_cla46_b[28]
1 1
.names u_wallace_cla24_fa467_xor1 u_wallace_cla24_u_cla46_b[29]
1 1
.names u_wallace_cla24_fa468_xor1 u_wallace_cla24_u_cla46_b[30]
1 1
.names u_wallace_cla24_fa469_xor1 u_wallace_cla24_u_cla46_b[31]
1 1
.names u_wallace_cla24_fa470_xor1 u_wallace_cla24_u_cla46_b[32]
1 1
.names u_wallace_cla24_fa471_xor1 u_wallace_cla24_u_cla46_b[33]
1 1
.names u_wallace_cla24_fa472_xor1 u_wallace_cla24_u_cla46_b[34]
1 1
.names u_wallace_cla24_fa473_xor1 u_wallace_cla24_u_cla46_b[35]
1 1
.names u_wallace_cla24_fa474_xor1 u_wallace_cla24_u_cla46_b[36]
1 1
.names u_wallace_cla24_fa475_xor1 u_wallace_cla24_u_cla46_b[37]
1 1
.names u_wallace_cla24_fa476_xor1 u_wallace_cla24_u_cla46_b[38]
1 1
.names u_wallace_cla24_fa477_xor1 u_wallace_cla24_u_cla46_b[39]
1 1
.names u_wallace_cla24_fa478_xor1 u_wallace_cla24_u_cla46_b[40]
1 1
.names u_wallace_cla24_fa479_xor1 u_wallace_cla24_u_cla46_b[41]
1 1
.names u_wallace_cla24_fa480_xor1 u_wallace_cla24_u_cla46_b[42]
1 1
.names u_wallace_cla24_fa481_xor1 u_wallace_cla24_u_cla46_b[43]
1 1
.names u_wallace_cla24_fa482_xor1 u_wallace_cla24_u_cla46_b[44]
1 1
.names u_wallace_cla24_and_23_23 u_wallace_cla24_u_cla46_b[45]
1 1
.subckt u_cla46 a[0]=u_wallace_cla24_u_cla46_a[0] a[1]=u_wallace_cla24_u_cla46_a[1] a[2]=u_wallace_cla24_u_cla46_a[2] a[3]=u_wallace_cla24_u_cla46_a[3] a[4]=u_wallace_cla24_u_cla46_a[4] a[5]=u_wallace_cla24_u_cla46_a[5] a[6]=u_wallace_cla24_u_cla46_a[6] a[7]=u_wallace_cla24_u_cla46_a[7] a[8]=u_wallace_cla24_u_cla46_a[8] a[9]=u_wallace_cla24_u_cla46_a[9] a[10]=u_wallace_cla24_u_cla46_a[10] a[11]=u_wallace_cla24_u_cla46_a[11] a[12]=u_wallace_cla24_u_cla46_a[12] a[13]=u_wallace_cla24_u_cla46_a[13] a[14]=u_wallace_cla24_u_cla46_a[14] a[15]=u_wallace_cla24_u_cla46_a[15] a[16]=u_wallace_cla24_u_cla46_a[16] a[17]=u_wallace_cla24_u_cla46_a[17] a[18]=u_wallace_cla24_u_cla46_a[18] a[19]=u_wallace_cla24_u_cla46_a[19] a[20]=u_wallace_cla24_u_cla46_a[20] a[21]=u_wallace_cla24_u_cla46_a[21] a[22]=u_wallace_cla24_u_cla46_a[22] a[23]=u_wallace_cla24_u_cla46_a[23] a[24]=u_wallace_cla24_u_cla46_a[24] a[25]=u_wallace_cla24_u_cla46_a[25] a[26]=u_wallace_cla24_u_cla46_a[26] a[27]=u_wallace_cla24_u_cla46_a[27] a[28]=u_wallace_cla24_u_cla46_a[28] a[29]=u_wallace_cla24_u_cla46_a[29] a[30]=u_wallace_cla24_u_cla46_a[30] a[31]=u_wallace_cla24_u_cla46_a[31] a[32]=u_wallace_cla24_u_cla46_a[32] a[33]=u_wallace_cla24_u_cla46_a[33] a[34]=u_wallace_cla24_u_cla46_a[34] a[35]=u_wallace_cla24_u_cla46_a[35] a[36]=u_wallace_cla24_u_cla46_a[36] a[37]=u_wallace_cla24_u_cla46_a[37] a[38]=u_wallace_cla24_u_cla46_a[38] a[39]=u_wallace_cla24_u_cla46_a[39] a[40]=u_wallace_cla24_u_cla46_a[40] a[41]=u_wallace_cla24_u_cla46_a[41] a[42]=u_wallace_cla24_u_cla46_a[42] a[43]=u_wallace_cla24_u_cla46_a[43] a[44]=u_wallace_cla24_u_cla46_a[44] a[45]=u_wallace_cla24_u_cla46_a[45] b[0]=u_wallace_cla24_u_cla46_b[0] b[1]=u_wallace_cla24_u_cla46_b[1] b[2]=u_wallace_cla24_u_cla46_b[2] b[3]=u_wallace_cla24_u_cla46_b[3] b[4]=u_wallace_cla24_u_cla46_b[4] b[5]=u_wallace_cla24_u_cla46_b[5] b[6]=u_wallace_cla24_u_cla46_b[6] b[7]=u_wallace_cla24_u_cla46_b[7] b[8]=u_wallace_cla24_u_cla46_b[8] b[9]=u_wallace_cla24_u_cla46_b[9] b[10]=u_wallace_cla24_u_cla46_b[10] b[11]=u_wallace_cla24_u_cla46_b[11] b[12]=u_wallace_cla24_u_cla46_b[12] b[13]=u_wallace_cla24_u_cla46_b[13] b[14]=u_wallace_cla24_u_cla46_b[14] b[15]=u_wallace_cla24_u_cla46_b[15] b[16]=u_wallace_cla24_u_cla46_b[16] b[17]=u_wallace_cla24_u_cla46_b[17] b[18]=u_wallace_cla24_u_cla46_b[18] b[19]=u_wallace_cla24_u_cla46_b[19] b[20]=u_wallace_cla24_u_cla46_b[20] b[21]=u_wallace_cla24_u_cla46_b[21] b[22]=u_wallace_cla24_u_cla46_b[22] b[23]=u_wallace_cla24_u_cla46_b[23] b[24]=u_wallace_cla24_u_cla46_b[24] b[25]=u_wallace_cla24_u_cla46_b[25] b[26]=u_wallace_cla24_u_cla46_b[26] b[27]=u_wallace_cla24_u_cla46_b[27] b[28]=u_wallace_cla24_u_cla46_b[28] b[29]=u_wallace_cla24_u_cla46_b[29] b[30]=u_wallace_cla24_u_cla46_b[30] b[31]=u_wallace_cla24_u_cla46_b[31] b[32]=u_wallace_cla24_u_cla46_b[32] b[33]=u_wallace_cla24_u_cla46_b[33] b[34]=u_wallace_cla24_u_cla46_b[34] b[35]=u_wallace_cla24_u_cla46_b[35] b[36]=u_wallace_cla24_u_cla46_b[36] b[37]=u_wallace_cla24_u_cla46_b[37] b[38]=u_wallace_cla24_u_cla46_b[38] b[39]=u_wallace_cla24_u_cla46_b[39] b[40]=u_wallace_cla24_u_cla46_b[40] b[41]=u_wallace_cla24_u_cla46_b[41] b[42]=u_wallace_cla24_u_cla46_b[42] b[43]=u_wallace_cla24_u_cla46_b[43] b[44]=u_wallace_cla24_u_cla46_b[44] b[45]=u_wallace_cla24_u_cla46_b[45] u_cla46_out[0]=u_wallace_cla24_u_cla46_pg_logic0_xor0 u_cla46_out[1]=u_wallace_cla24_u_cla46_xor1 u_cla46_out[2]=u_wallace_cla24_u_cla46_xor2 u_cla46_out[3]=u_wallace_cla24_u_cla46_xor3 u_cla46_out[4]=u_wallace_cla24_u_cla46_xor4 u_cla46_out[5]=u_wallace_cla24_u_cla46_xor5 u_cla46_out[6]=u_wallace_cla24_u_cla46_xor6 u_cla46_out[7]=u_wallace_cla24_u_cla46_xor7 u_cla46_out[8]=u_wallace_cla24_u_cla46_xor8 u_cla46_out[9]=u_wallace_cla24_u_cla46_xor9 u_cla46_out[10]=u_wallace_cla24_u_cla46_xor10 u_cla46_out[11]=u_wallace_cla24_u_cla46_xor11 u_cla46_out[12]=u_wallace_cla24_u_cla46_xor12 u_cla46_out[13]=u_wallace_cla24_u_cla46_xor13 u_cla46_out[14]=u_wallace_cla24_u_cla46_xor14 u_cla46_out[15]=u_wallace_cla24_u_cla46_xor15 u_cla46_out[16]=u_wallace_cla24_u_cla46_xor16 u_cla46_out[17]=u_wallace_cla24_u_cla46_xor17 u_cla46_out[18]=u_wallace_cla24_u_cla46_xor18 u_cla46_out[19]=u_wallace_cla24_u_cla46_xor19 u_cla46_out[20]=u_wallace_cla24_u_cla46_xor20 u_cla46_out[21]=u_wallace_cla24_u_cla46_xor21 u_cla46_out[22]=u_wallace_cla24_u_cla46_xor22 u_cla46_out[23]=u_wallace_cla24_u_cla46_xor23 u_cla46_out[24]=u_wallace_cla24_u_cla46_xor24 u_cla46_out[25]=u_wallace_cla24_u_cla46_xor25 u_cla46_out[26]=u_wallace_cla24_u_cla46_xor26 u_cla46_out[27]=u_wallace_cla24_u_cla46_xor27 u_cla46_out[28]=u_wallace_cla24_u_cla46_xor28 u_cla46_out[29]=u_wallace_cla24_u_cla46_xor29 u_cla46_out[30]=u_wallace_cla24_u_cla46_xor30 u_cla46_out[31]=u_wallace_cla24_u_cla46_xor31 u_cla46_out[32]=u_wallace_cla24_u_cla46_xor32 u_cla46_out[33]=u_wallace_cla24_u_cla46_xor33 u_cla46_out[34]=u_wallace_cla24_u_cla46_xor34 u_cla46_out[35]=u_wallace_cla24_u_cla46_xor35 u_cla46_out[36]=u_wallace_cla24_u_cla46_xor36 u_cla46_out[37]=u_wallace_cla24_u_cla46_xor37 u_cla46_out[38]=u_wallace_cla24_u_cla46_xor38 u_cla46_out[39]=u_wallace_cla24_u_cla46_xor39 u_cla46_out[40]=u_wallace_cla24_u_cla46_xor40 u_cla46_out[41]=u_wallace_cla24_u_cla46_xor41 u_cla46_out[42]=u_wallace_cla24_u_cla46_xor42 u_cla46_out[43]=u_wallace_cla24_u_cla46_xor43 u_cla46_out[44]=u_wallace_cla24_u_cla46_xor44 u_cla46_out[45]=u_wallace_cla24_u_cla46_xor45 u_cla46_out[46]=u_wallace_cla24_u_cla46_or108
.names u_wallace_cla24_and_0_0 u_wallace_cla24_out[0]
1 1
.names u_wallace_cla24_u_cla46_pg_logic0_xor0 u_wallace_cla24_out[1]
1 1
.names u_wallace_cla24_u_cla46_xor1 u_wallace_cla24_out[2]
1 1
.names u_wallace_cla24_u_cla46_xor2 u_wallace_cla24_out[3]
1 1
.names u_wallace_cla24_u_cla46_xor3 u_wallace_cla24_out[4]
1 1
.names u_wallace_cla24_u_cla46_xor4 u_wallace_cla24_out[5]
1 1
.names u_wallace_cla24_u_cla46_xor5 u_wallace_cla24_out[6]
1 1
.names u_wallace_cla24_u_cla46_xor6 u_wallace_cla24_out[7]
1 1
.names u_wallace_cla24_u_cla46_xor7 u_wallace_cla24_out[8]
1 1
.names u_wallace_cla24_u_cla46_xor8 u_wallace_cla24_out[9]
1 1
.names u_wallace_cla24_u_cla46_xor9 u_wallace_cla24_out[10]
1 1
.names u_wallace_cla24_u_cla46_xor10 u_wallace_cla24_out[11]
1 1
.names u_wallace_cla24_u_cla46_xor11 u_wallace_cla24_out[12]
1 1
.names u_wallace_cla24_u_cla46_xor12 u_wallace_cla24_out[13]
1 1
.names u_wallace_cla24_u_cla46_xor13 u_wallace_cla24_out[14]
1 1
.names u_wallace_cla24_u_cla46_xor14 u_wallace_cla24_out[15]
1 1
.names u_wallace_cla24_u_cla46_xor15 u_wallace_cla24_out[16]
1 1
.names u_wallace_cla24_u_cla46_xor16 u_wallace_cla24_out[17]
1 1
.names u_wallace_cla24_u_cla46_xor17 u_wallace_cla24_out[18]
1 1
.names u_wallace_cla24_u_cla46_xor18 u_wallace_cla24_out[19]
1 1
.names u_wallace_cla24_u_cla46_xor19 u_wallace_cla24_out[20]
1 1
.names u_wallace_cla24_u_cla46_xor20 u_wallace_cla24_out[21]
1 1
.names u_wallace_cla24_u_cla46_xor21 u_wallace_cla24_out[22]
1 1
.names u_wallace_cla24_u_cla46_xor22 u_wallace_cla24_out[23]
1 1
.names u_wallace_cla24_u_cla46_xor23 u_wallace_cla24_out[24]
1 1
.names u_wallace_cla24_u_cla46_xor24 u_wallace_cla24_out[25]
1 1
.names u_wallace_cla24_u_cla46_xor25 u_wallace_cla24_out[26]
1 1
.names u_wallace_cla24_u_cla46_xor26 u_wallace_cla24_out[27]
1 1
.names u_wallace_cla24_u_cla46_xor27 u_wallace_cla24_out[28]
1 1
.names u_wallace_cla24_u_cla46_xor28 u_wallace_cla24_out[29]
1 1
.names u_wallace_cla24_u_cla46_xor29 u_wallace_cla24_out[30]
1 1
.names u_wallace_cla24_u_cla46_xor30 u_wallace_cla24_out[31]
1 1
.names u_wallace_cla24_u_cla46_xor31 u_wallace_cla24_out[32]
1 1
.names u_wallace_cla24_u_cla46_xor32 u_wallace_cla24_out[33]
1 1
.names u_wallace_cla24_u_cla46_xor33 u_wallace_cla24_out[34]
1 1
.names u_wallace_cla24_u_cla46_xor34 u_wallace_cla24_out[35]
1 1
.names u_wallace_cla24_u_cla46_xor35 u_wallace_cla24_out[36]
1 1
.names u_wallace_cla24_u_cla46_xor36 u_wallace_cla24_out[37]
1 1
.names u_wallace_cla24_u_cla46_xor37 u_wallace_cla24_out[38]
1 1
.names u_wallace_cla24_u_cla46_xor38 u_wallace_cla24_out[39]
1 1
.names u_wallace_cla24_u_cla46_xor39 u_wallace_cla24_out[40]
1 1
.names u_wallace_cla24_u_cla46_xor40 u_wallace_cla24_out[41]
1 1
.names u_wallace_cla24_u_cla46_xor41 u_wallace_cla24_out[42]
1 1
.names u_wallace_cla24_u_cla46_xor42 u_wallace_cla24_out[43]
1 1
.names u_wallace_cla24_u_cla46_xor43 u_wallace_cla24_out[44]
1 1
.names u_wallace_cla24_u_cla46_xor44 u_wallace_cla24_out[45]
1 1
.names u_wallace_cla24_u_cla46_xor45 u_wallace_cla24_out[46]
1 1
.names u_wallace_cla24_u_cla46_or108 u_wallace_cla24_out[47]
1 1
.end

.model u_cla46
.inputs a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] a[8] a[9] a[10] a[11] a[12] a[13] a[14] a[15] a[16] a[17] a[18] a[19] a[20] a[21] a[22] a[23] a[24] a[25] a[26] a[27] a[28] a[29] a[30] a[31] a[32] a[33] a[34] a[35] a[36] a[37] a[38] a[39] a[40] a[41] a[42] a[43] a[44] a[45] b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9] b[10] b[11] b[12] b[13] b[14] b[15] b[16] b[17] b[18] b[19] b[20] b[21] b[22] b[23] b[24] b[25] b[26] b[27] b[28] b[29] b[30] b[31] b[32] b[33] b[34] b[35] b[36] b[37] b[38] b[39] b[40] b[41] b[42] b[43] b[44] b[45]
.outputs u_cla46_out[0] u_cla46_out[1] u_cla46_out[2] u_cla46_out[3] u_cla46_out[4] u_cla46_out[5] u_cla46_out[6] u_cla46_out[7] u_cla46_out[8] u_cla46_out[9] u_cla46_out[10] u_cla46_out[11] u_cla46_out[12] u_cla46_out[13] u_cla46_out[14] u_cla46_out[15] u_cla46_out[16] u_cla46_out[17] u_cla46_out[18] u_cla46_out[19] u_cla46_out[20] u_cla46_out[21] u_cla46_out[22] u_cla46_out[23] u_cla46_out[24] u_cla46_out[25] u_cla46_out[26] u_cla46_out[27] u_cla46_out[28] u_cla46_out[29] u_cla46_out[30] u_cla46_out[31] u_cla46_out[32] u_cla46_out[33] u_cla46_out[34] u_cla46_out[35] u_cla46_out[36] u_cla46_out[37] u_cla46_out[38] u_cla46_out[39] u_cla46_out[40] u_cla46_out[41] u_cla46_out[42] u_cla46_out[43] u_cla46_out[44] u_cla46_out[45] u_cla46_out[46]
.names vdd
1
.names gnd
0
.subckt pg_logic a=a[0] b=b[0] pg_logic_or0=u_cla46_pg_logic0_or0 pg_logic_and0=u_cla46_pg_logic0_and0 pg_logic_xor0=u_cla46_pg_logic0_xor0
.subckt pg_logic a=a[1] b=b[1] pg_logic_or0=u_cla46_pg_logic1_or0 pg_logic_and0=u_cla46_pg_logic1_and0 pg_logic_xor0=u_cla46_pg_logic1_xor0
.subckt xor_gate a=u_cla46_pg_logic1_xor0 b=u_cla46_pg_logic0_and0 out=u_cla46_xor1
.subckt and_gate a=u_cla46_pg_logic0_and0 b=u_cla46_pg_logic1_or0 out=u_cla46_and0
.subckt or_gate a=u_cla46_pg_logic1_and0 b=u_cla46_and0 out=u_cla46_or0
.subckt pg_logic a=a[2] b=b[2] pg_logic_or0=u_cla46_pg_logic2_or0 pg_logic_and0=u_cla46_pg_logic2_and0 pg_logic_xor0=u_cla46_pg_logic2_xor0
.subckt xor_gate a=u_cla46_pg_logic2_xor0 b=u_cla46_or0 out=u_cla46_xor2
.subckt and_gate a=u_cla46_pg_logic2_or0 b=u_cla46_pg_logic0_or0 out=u_cla46_and1
.subckt and_gate a=u_cla46_pg_logic0_and0 b=u_cla46_pg_logic2_or0 out=u_cla46_and2
.subckt and_gate a=u_cla46_and2 b=u_cla46_pg_logic1_or0 out=u_cla46_and3
.subckt and_gate a=u_cla46_pg_logic1_and0 b=u_cla46_pg_logic2_or0 out=u_cla46_and4
.subckt or_gate a=u_cla46_and3 b=u_cla46_and4 out=u_cla46_or1
.subckt or_gate a=u_cla46_pg_logic2_and0 b=u_cla46_or1 out=u_cla46_or2
.subckt pg_logic a=a[3] b=b[3] pg_logic_or0=u_cla46_pg_logic3_or0 pg_logic_and0=u_cla46_pg_logic3_and0 pg_logic_xor0=u_cla46_pg_logic3_xor0
.subckt xor_gate a=u_cla46_pg_logic3_xor0 b=u_cla46_or2 out=u_cla46_xor3
.subckt and_gate a=u_cla46_pg_logic3_or0 b=u_cla46_pg_logic1_or0 out=u_cla46_and5
.subckt and_gate a=u_cla46_pg_logic0_and0 b=u_cla46_pg_logic2_or0 out=u_cla46_and6
.subckt and_gate a=u_cla46_pg_logic3_or0 b=u_cla46_pg_logic1_or0 out=u_cla46_and7
.subckt and_gate a=u_cla46_and6 b=u_cla46_and7 out=u_cla46_and8
.subckt and_gate a=u_cla46_pg_logic1_and0 b=u_cla46_pg_logic3_or0 out=u_cla46_and9
.subckt and_gate a=u_cla46_and9 b=u_cla46_pg_logic2_or0 out=u_cla46_and10
.subckt and_gate a=u_cla46_pg_logic2_and0 b=u_cla46_pg_logic3_or0 out=u_cla46_and11
.subckt or_gate a=u_cla46_and8 b=u_cla46_and11 out=u_cla46_or3
.subckt or_gate a=u_cla46_and10 b=u_cla46_or3 out=u_cla46_or4
.subckt or_gate a=u_cla46_pg_logic3_and0 b=u_cla46_or4 out=u_cla46_or5
.subckt pg_logic a=a[4] b=b[4] pg_logic_or0=u_cla46_pg_logic4_or0 pg_logic_and0=u_cla46_pg_logic4_and0 pg_logic_xor0=u_cla46_pg_logic4_xor0
.subckt xor_gate a=u_cla46_pg_logic4_xor0 b=u_cla46_or5 out=u_cla46_xor4
.subckt and_gate a=u_cla46_or5 b=u_cla46_pg_logic4_or0 out=u_cla46_and12
.subckt or_gate a=u_cla46_pg_logic4_and0 b=u_cla46_and12 out=u_cla46_or6
.subckt pg_logic a=a[5] b=b[5] pg_logic_or0=u_cla46_pg_logic5_or0 pg_logic_and0=u_cla46_pg_logic5_and0 pg_logic_xor0=u_cla46_pg_logic5_xor0
.subckt xor_gate a=u_cla46_pg_logic5_xor0 b=u_cla46_or6 out=u_cla46_xor5
.subckt and_gate a=u_cla46_or5 b=u_cla46_pg_logic5_or0 out=u_cla46_and13
.subckt and_gate a=u_cla46_and13 b=u_cla46_pg_logic4_or0 out=u_cla46_and14
.subckt and_gate a=u_cla46_pg_logic4_and0 b=u_cla46_pg_logic5_or0 out=u_cla46_and15
.subckt or_gate a=u_cla46_and14 b=u_cla46_and15 out=u_cla46_or7
.subckt or_gate a=u_cla46_pg_logic5_and0 b=u_cla46_or7 out=u_cla46_or8
.subckt pg_logic a=a[6] b=b[6] pg_logic_or0=u_cla46_pg_logic6_or0 pg_logic_and0=u_cla46_pg_logic6_and0 pg_logic_xor0=u_cla46_pg_logic6_xor0
.subckt xor_gate a=u_cla46_pg_logic6_xor0 b=u_cla46_or8 out=u_cla46_xor6
.subckt and_gate a=u_cla46_or5 b=u_cla46_pg_logic5_or0 out=u_cla46_and16
.subckt and_gate a=u_cla46_pg_logic6_or0 b=u_cla46_pg_logic4_or0 out=u_cla46_and17
.subckt and_gate a=u_cla46_and16 b=u_cla46_and17 out=u_cla46_and18
.subckt and_gate a=u_cla46_pg_logic4_and0 b=u_cla46_pg_logic6_or0 out=u_cla46_and19
.subckt and_gate a=u_cla46_and19 b=u_cla46_pg_logic5_or0 out=u_cla46_and20
.subckt and_gate a=u_cla46_pg_logic5_and0 b=u_cla46_pg_logic6_or0 out=u_cla46_and21
.subckt or_gate a=u_cla46_and18 b=u_cla46_and20 out=u_cla46_or9
.subckt or_gate a=u_cla46_or9 b=u_cla46_and21 out=u_cla46_or10
.subckt or_gate a=u_cla46_pg_logic6_and0 b=u_cla46_or10 out=u_cla46_or11
.subckt pg_logic a=a[7] b=b[7] pg_logic_or0=u_cla46_pg_logic7_or0 pg_logic_and0=u_cla46_pg_logic7_and0 pg_logic_xor0=u_cla46_pg_logic7_xor0
.subckt xor_gate a=u_cla46_pg_logic7_xor0 b=u_cla46_or11 out=u_cla46_xor7
.subckt and_gate a=u_cla46_or5 b=u_cla46_pg_logic6_or0 out=u_cla46_and22
.subckt and_gate a=u_cla46_pg_logic7_or0 b=u_cla46_pg_logic5_or0 out=u_cla46_and23
.subckt and_gate a=u_cla46_and22 b=u_cla46_and23 out=u_cla46_and24
.subckt and_gate a=u_cla46_and24 b=u_cla46_pg_logic4_or0 out=u_cla46_and25
.subckt and_gate a=u_cla46_pg_logic4_and0 b=u_cla46_pg_logic6_or0 out=u_cla46_and26
.subckt and_gate a=u_cla46_pg_logic7_or0 b=u_cla46_pg_logic5_or0 out=u_cla46_and27
.subckt and_gate a=u_cla46_and26 b=u_cla46_and27 out=u_cla46_and28
.subckt and_gate a=u_cla46_pg_logic5_and0 b=u_cla46_pg_logic7_or0 out=u_cla46_and29
.subckt and_gate a=u_cla46_and29 b=u_cla46_pg_logic6_or0 out=u_cla46_and30
.subckt and_gate a=u_cla46_pg_logic6_and0 b=u_cla46_pg_logic7_or0 out=u_cla46_and31
.subckt or_gate a=u_cla46_and25 b=u_cla46_and30 out=u_cla46_or12
.subckt or_gate a=u_cla46_and28 b=u_cla46_and31 out=u_cla46_or13
.subckt or_gate a=u_cla46_or12 b=u_cla46_or13 out=u_cla46_or14
.subckt or_gate a=u_cla46_pg_logic7_and0 b=u_cla46_or14 out=u_cla46_or15
.subckt pg_logic a=a[8] b=b[8] pg_logic_or0=u_cla46_pg_logic8_or0 pg_logic_and0=u_cla46_pg_logic8_and0 pg_logic_xor0=u_cla46_pg_logic8_xor0
.subckt xor_gate a=u_cla46_pg_logic8_xor0 b=u_cla46_or15 out=u_cla46_xor8
.subckt and_gate a=u_cla46_or15 b=u_cla46_pg_logic8_or0 out=u_cla46_and32
.subckt or_gate a=u_cla46_pg_logic8_and0 b=u_cla46_and32 out=u_cla46_or16
.subckt pg_logic a=a[9] b=b[9] pg_logic_or0=u_cla46_pg_logic9_or0 pg_logic_and0=u_cla46_pg_logic9_and0 pg_logic_xor0=u_cla46_pg_logic9_xor0
.subckt xor_gate a=u_cla46_pg_logic9_xor0 b=u_cla46_or16 out=u_cla46_xor9
.subckt and_gate a=u_cla46_or15 b=u_cla46_pg_logic9_or0 out=u_cla46_and33
.subckt and_gate a=u_cla46_and33 b=u_cla46_pg_logic8_or0 out=u_cla46_and34
.subckt and_gate a=u_cla46_pg_logic8_and0 b=u_cla46_pg_logic9_or0 out=u_cla46_and35
.subckt or_gate a=u_cla46_and34 b=u_cla46_and35 out=u_cla46_or17
.subckt or_gate a=u_cla46_pg_logic9_and0 b=u_cla46_or17 out=u_cla46_or18
.subckt pg_logic a=a[10] b=b[10] pg_logic_or0=u_cla46_pg_logic10_or0 pg_logic_and0=u_cla46_pg_logic10_and0 pg_logic_xor0=u_cla46_pg_logic10_xor0
.subckt xor_gate a=u_cla46_pg_logic10_xor0 b=u_cla46_or18 out=u_cla46_xor10
.subckt and_gate a=u_cla46_or15 b=u_cla46_pg_logic9_or0 out=u_cla46_and36
.subckt and_gate a=u_cla46_pg_logic10_or0 b=u_cla46_pg_logic8_or0 out=u_cla46_and37
.subckt and_gate a=u_cla46_and36 b=u_cla46_and37 out=u_cla46_and38
.subckt and_gate a=u_cla46_pg_logic8_and0 b=u_cla46_pg_logic10_or0 out=u_cla46_and39
.subckt and_gate a=u_cla46_and39 b=u_cla46_pg_logic9_or0 out=u_cla46_and40
.subckt and_gate a=u_cla46_pg_logic9_and0 b=u_cla46_pg_logic10_or0 out=u_cla46_and41
.subckt or_gate a=u_cla46_and38 b=u_cla46_and40 out=u_cla46_or19
.subckt or_gate a=u_cla46_or19 b=u_cla46_and41 out=u_cla46_or20
.subckt or_gate a=u_cla46_pg_logic10_and0 b=u_cla46_or20 out=u_cla46_or21
.subckt pg_logic a=a[11] b=b[11] pg_logic_or0=u_cla46_pg_logic11_or0 pg_logic_and0=u_cla46_pg_logic11_and0 pg_logic_xor0=u_cla46_pg_logic11_xor0
.subckt xor_gate a=u_cla46_pg_logic11_xor0 b=u_cla46_or21 out=u_cla46_xor11
.subckt and_gate a=u_cla46_or15 b=u_cla46_pg_logic10_or0 out=u_cla46_and42
.subckt and_gate a=u_cla46_pg_logic11_or0 b=u_cla46_pg_logic9_or0 out=u_cla46_and43
.subckt and_gate a=u_cla46_and42 b=u_cla46_and43 out=u_cla46_and44
.subckt and_gate a=u_cla46_and44 b=u_cla46_pg_logic8_or0 out=u_cla46_and45
.subckt and_gate a=u_cla46_pg_logic8_and0 b=u_cla46_pg_logic10_or0 out=u_cla46_and46
.subckt and_gate a=u_cla46_pg_logic11_or0 b=u_cla46_pg_logic9_or0 out=u_cla46_and47
.subckt and_gate a=u_cla46_and46 b=u_cla46_and47 out=u_cla46_and48
.subckt and_gate a=u_cla46_pg_logic9_and0 b=u_cla46_pg_logic11_or0 out=u_cla46_and49
.subckt and_gate a=u_cla46_and49 b=u_cla46_pg_logic10_or0 out=u_cla46_and50
.subckt and_gate a=u_cla46_pg_logic10_and0 b=u_cla46_pg_logic11_or0 out=u_cla46_and51
.subckt or_gate a=u_cla46_and45 b=u_cla46_and50 out=u_cla46_or22
.subckt or_gate a=u_cla46_and48 b=u_cla46_and51 out=u_cla46_or23
.subckt or_gate a=u_cla46_or22 b=u_cla46_or23 out=u_cla46_or24
.subckt or_gate a=u_cla46_pg_logic11_and0 b=u_cla46_or24 out=u_cla46_or25
.subckt pg_logic a=a[12] b=b[12] pg_logic_or0=u_cla46_pg_logic12_or0 pg_logic_and0=u_cla46_pg_logic12_and0 pg_logic_xor0=u_cla46_pg_logic12_xor0
.subckt xor_gate a=u_cla46_pg_logic12_xor0 b=u_cla46_or25 out=u_cla46_xor12
.subckt and_gate a=u_cla46_or25 b=u_cla46_pg_logic12_or0 out=u_cla46_and52
.subckt or_gate a=u_cla46_pg_logic12_and0 b=u_cla46_and52 out=u_cla46_or26
.subckt pg_logic a=a[13] b=b[13] pg_logic_or0=u_cla46_pg_logic13_or0 pg_logic_and0=u_cla46_pg_logic13_and0 pg_logic_xor0=u_cla46_pg_logic13_xor0
.subckt xor_gate a=u_cla46_pg_logic13_xor0 b=u_cla46_or26 out=u_cla46_xor13
.subckt and_gate a=u_cla46_or25 b=u_cla46_pg_logic13_or0 out=u_cla46_and53
.subckt and_gate a=u_cla46_and53 b=u_cla46_pg_logic12_or0 out=u_cla46_and54
.subckt and_gate a=u_cla46_pg_logic12_and0 b=u_cla46_pg_logic13_or0 out=u_cla46_and55
.subckt or_gate a=u_cla46_and54 b=u_cla46_and55 out=u_cla46_or27
.subckt or_gate a=u_cla46_pg_logic13_and0 b=u_cla46_or27 out=u_cla46_or28
.subckt pg_logic a=a[14] b=b[14] pg_logic_or0=u_cla46_pg_logic14_or0 pg_logic_and0=u_cla46_pg_logic14_and0 pg_logic_xor0=u_cla46_pg_logic14_xor0
.subckt xor_gate a=u_cla46_pg_logic14_xor0 b=u_cla46_or28 out=u_cla46_xor14
.subckt and_gate a=u_cla46_or25 b=u_cla46_pg_logic13_or0 out=u_cla46_and56
.subckt and_gate a=u_cla46_pg_logic14_or0 b=u_cla46_pg_logic12_or0 out=u_cla46_and57
.subckt and_gate a=u_cla46_and56 b=u_cla46_and57 out=u_cla46_and58
.subckt and_gate a=u_cla46_pg_logic12_and0 b=u_cla46_pg_logic14_or0 out=u_cla46_and59
.subckt and_gate a=u_cla46_and59 b=u_cla46_pg_logic13_or0 out=u_cla46_and60
.subckt and_gate a=u_cla46_pg_logic13_and0 b=u_cla46_pg_logic14_or0 out=u_cla46_and61
.subckt or_gate a=u_cla46_and58 b=u_cla46_and60 out=u_cla46_or29
.subckt or_gate a=u_cla46_or29 b=u_cla46_and61 out=u_cla46_or30
.subckt or_gate a=u_cla46_pg_logic14_and0 b=u_cla46_or30 out=u_cla46_or31
.subckt pg_logic a=a[15] b=b[15] pg_logic_or0=u_cla46_pg_logic15_or0 pg_logic_and0=u_cla46_pg_logic15_and0 pg_logic_xor0=u_cla46_pg_logic15_xor0
.subckt xor_gate a=u_cla46_pg_logic15_xor0 b=u_cla46_or31 out=u_cla46_xor15
.subckt and_gate a=u_cla46_or25 b=u_cla46_pg_logic14_or0 out=u_cla46_and62
.subckt and_gate a=u_cla46_pg_logic15_or0 b=u_cla46_pg_logic13_or0 out=u_cla46_and63
.subckt and_gate a=u_cla46_and62 b=u_cla46_and63 out=u_cla46_and64
.subckt and_gate a=u_cla46_and64 b=u_cla46_pg_logic12_or0 out=u_cla46_and65
.subckt and_gate a=u_cla46_pg_logic12_and0 b=u_cla46_pg_logic14_or0 out=u_cla46_and66
.subckt and_gate a=u_cla46_pg_logic15_or0 b=u_cla46_pg_logic13_or0 out=u_cla46_and67
.subckt and_gate a=u_cla46_and66 b=u_cla46_and67 out=u_cla46_and68
.subckt and_gate a=u_cla46_pg_logic13_and0 b=u_cla46_pg_logic15_or0 out=u_cla46_and69
.subckt and_gate a=u_cla46_and69 b=u_cla46_pg_logic14_or0 out=u_cla46_and70
.subckt and_gate a=u_cla46_pg_logic14_and0 b=u_cla46_pg_logic15_or0 out=u_cla46_and71
.subckt or_gate a=u_cla46_and65 b=u_cla46_and70 out=u_cla46_or32
.subckt or_gate a=u_cla46_and68 b=u_cla46_and71 out=u_cla46_or33
.subckt or_gate a=u_cla46_or32 b=u_cla46_or33 out=u_cla46_or34
.subckt or_gate a=u_cla46_pg_logic15_and0 b=u_cla46_or34 out=u_cla46_or35
.subckt pg_logic a=a[16] b=b[16] pg_logic_or0=u_cla46_pg_logic16_or0 pg_logic_and0=u_cla46_pg_logic16_and0 pg_logic_xor0=u_cla46_pg_logic16_xor0
.subckt xor_gate a=u_cla46_pg_logic16_xor0 b=u_cla46_or35 out=u_cla46_xor16
.subckt and_gate a=u_cla46_or35 b=u_cla46_pg_logic16_or0 out=u_cla46_and72
.subckt or_gate a=u_cla46_pg_logic16_and0 b=u_cla46_and72 out=u_cla46_or36
.subckt pg_logic a=a[17] b=b[17] pg_logic_or0=u_cla46_pg_logic17_or0 pg_logic_and0=u_cla46_pg_logic17_and0 pg_logic_xor0=u_cla46_pg_logic17_xor0
.subckt xor_gate a=u_cla46_pg_logic17_xor0 b=u_cla46_or36 out=u_cla46_xor17
.subckt and_gate a=u_cla46_or35 b=u_cla46_pg_logic17_or0 out=u_cla46_and73
.subckt and_gate a=u_cla46_and73 b=u_cla46_pg_logic16_or0 out=u_cla46_and74
.subckt and_gate a=u_cla46_pg_logic16_and0 b=u_cla46_pg_logic17_or0 out=u_cla46_and75
.subckt or_gate a=u_cla46_and74 b=u_cla46_and75 out=u_cla46_or37
.subckt or_gate a=u_cla46_pg_logic17_and0 b=u_cla46_or37 out=u_cla46_or38
.subckt pg_logic a=a[18] b=b[18] pg_logic_or0=u_cla46_pg_logic18_or0 pg_logic_and0=u_cla46_pg_logic18_and0 pg_logic_xor0=u_cla46_pg_logic18_xor0
.subckt xor_gate a=u_cla46_pg_logic18_xor0 b=u_cla46_or38 out=u_cla46_xor18
.subckt and_gate a=u_cla46_or35 b=u_cla46_pg_logic17_or0 out=u_cla46_and76
.subckt and_gate a=u_cla46_pg_logic18_or0 b=u_cla46_pg_logic16_or0 out=u_cla46_and77
.subckt and_gate a=u_cla46_and76 b=u_cla46_and77 out=u_cla46_and78
.subckt and_gate a=u_cla46_pg_logic16_and0 b=u_cla46_pg_logic18_or0 out=u_cla46_and79
.subckt and_gate a=u_cla46_and79 b=u_cla46_pg_logic17_or0 out=u_cla46_and80
.subckt and_gate a=u_cla46_pg_logic17_and0 b=u_cla46_pg_logic18_or0 out=u_cla46_and81
.subckt or_gate a=u_cla46_and78 b=u_cla46_and80 out=u_cla46_or39
.subckt or_gate a=u_cla46_or39 b=u_cla46_and81 out=u_cla46_or40
.subckt or_gate a=u_cla46_pg_logic18_and0 b=u_cla46_or40 out=u_cla46_or41
.subckt pg_logic a=a[19] b=b[19] pg_logic_or0=u_cla46_pg_logic19_or0 pg_logic_and0=u_cla46_pg_logic19_and0 pg_logic_xor0=u_cla46_pg_logic19_xor0
.subckt xor_gate a=u_cla46_pg_logic19_xor0 b=u_cla46_or41 out=u_cla46_xor19
.subckt and_gate a=u_cla46_or35 b=u_cla46_pg_logic18_or0 out=u_cla46_and82
.subckt and_gate a=u_cla46_pg_logic19_or0 b=u_cla46_pg_logic17_or0 out=u_cla46_and83
.subckt and_gate a=u_cla46_and82 b=u_cla46_and83 out=u_cla46_and84
.subckt and_gate a=u_cla46_and84 b=u_cla46_pg_logic16_or0 out=u_cla46_and85
.subckt and_gate a=u_cla46_pg_logic16_and0 b=u_cla46_pg_logic18_or0 out=u_cla46_and86
.subckt and_gate a=u_cla46_pg_logic19_or0 b=u_cla46_pg_logic17_or0 out=u_cla46_and87
.subckt and_gate a=u_cla46_and86 b=u_cla46_and87 out=u_cla46_and88
.subckt and_gate a=u_cla46_pg_logic17_and0 b=u_cla46_pg_logic19_or0 out=u_cla46_and89
.subckt and_gate a=u_cla46_and89 b=u_cla46_pg_logic18_or0 out=u_cla46_and90
.subckt and_gate a=u_cla46_pg_logic18_and0 b=u_cla46_pg_logic19_or0 out=u_cla46_and91
.subckt or_gate a=u_cla46_and85 b=u_cla46_and90 out=u_cla46_or42
.subckt or_gate a=u_cla46_and88 b=u_cla46_and91 out=u_cla46_or43
.subckt or_gate a=u_cla46_or42 b=u_cla46_or43 out=u_cla46_or44
.subckt or_gate a=u_cla46_pg_logic19_and0 b=u_cla46_or44 out=u_cla46_or45
.subckt pg_logic a=a[20] b=b[20] pg_logic_or0=u_cla46_pg_logic20_or0 pg_logic_and0=u_cla46_pg_logic20_and0 pg_logic_xor0=u_cla46_pg_logic20_xor0
.subckt xor_gate a=u_cla46_pg_logic20_xor0 b=u_cla46_or45 out=u_cla46_xor20
.subckt and_gate a=u_cla46_or45 b=u_cla46_pg_logic20_or0 out=u_cla46_and92
.subckt or_gate a=u_cla46_pg_logic20_and0 b=u_cla46_and92 out=u_cla46_or46
.subckt pg_logic a=a[21] b=b[21] pg_logic_or0=u_cla46_pg_logic21_or0 pg_logic_and0=u_cla46_pg_logic21_and0 pg_logic_xor0=u_cla46_pg_logic21_xor0
.subckt xor_gate a=u_cla46_pg_logic21_xor0 b=u_cla46_or46 out=u_cla46_xor21
.subckt and_gate a=u_cla46_or45 b=u_cla46_pg_logic21_or0 out=u_cla46_and93
.subckt and_gate a=u_cla46_and93 b=u_cla46_pg_logic20_or0 out=u_cla46_and94
.subckt and_gate a=u_cla46_pg_logic20_and0 b=u_cla46_pg_logic21_or0 out=u_cla46_and95
.subckt or_gate a=u_cla46_and94 b=u_cla46_and95 out=u_cla46_or47
.subckt or_gate a=u_cla46_pg_logic21_and0 b=u_cla46_or47 out=u_cla46_or48
.subckt pg_logic a=a[22] b=b[22] pg_logic_or0=u_cla46_pg_logic22_or0 pg_logic_and0=u_cla46_pg_logic22_and0 pg_logic_xor0=u_cla46_pg_logic22_xor0
.subckt xor_gate a=u_cla46_pg_logic22_xor0 b=u_cla46_or48 out=u_cla46_xor22
.subckt and_gate a=u_cla46_or45 b=u_cla46_pg_logic21_or0 out=u_cla46_and96
.subckt and_gate a=u_cla46_pg_logic22_or0 b=u_cla46_pg_logic20_or0 out=u_cla46_and97
.subckt and_gate a=u_cla46_and96 b=u_cla46_and97 out=u_cla46_and98
.subckt and_gate a=u_cla46_pg_logic20_and0 b=u_cla46_pg_logic22_or0 out=u_cla46_and99
.subckt and_gate a=u_cla46_and99 b=u_cla46_pg_logic21_or0 out=u_cla46_and100
.subckt and_gate a=u_cla46_pg_logic21_and0 b=u_cla46_pg_logic22_or0 out=u_cla46_and101
.subckt or_gate a=u_cla46_and98 b=u_cla46_and100 out=u_cla46_or49
.subckt or_gate a=u_cla46_or49 b=u_cla46_and101 out=u_cla46_or50
.subckt or_gate a=u_cla46_pg_logic22_and0 b=u_cla46_or50 out=u_cla46_or51
.subckt pg_logic a=a[23] b=b[23] pg_logic_or0=u_cla46_pg_logic23_or0 pg_logic_and0=u_cla46_pg_logic23_and0 pg_logic_xor0=u_cla46_pg_logic23_xor0
.subckt xor_gate a=u_cla46_pg_logic23_xor0 b=u_cla46_or51 out=u_cla46_xor23
.subckt and_gate a=u_cla46_or45 b=u_cla46_pg_logic22_or0 out=u_cla46_and102
.subckt and_gate a=u_cla46_pg_logic23_or0 b=u_cla46_pg_logic21_or0 out=u_cla46_and103
.subckt and_gate a=u_cla46_and102 b=u_cla46_and103 out=u_cla46_and104
.subckt and_gate a=u_cla46_and104 b=u_cla46_pg_logic20_or0 out=u_cla46_and105
.subckt and_gate a=u_cla46_pg_logic20_and0 b=u_cla46_pg_logic22_or0 out=u_cla46_and106
.subckt and_gate a=u_cla46_pg_logic23_or0 b=u_cla46_pg_logic21_or0 out=u_cla46_and107
.subckt and_gate a=u_cla46_and106 b=u_cla46_and107 out=u_cla46_and108
.subckt and_gate a=u_cla46_pg_logic21_and0 b=u_cla46_pg_logic23_or0 out=u_cla46_and109
.subckt and_gate a=u_cla46_and109 b=u_cla46_pg_logic22_or0 out=u_cla46_and110
.subckt and_gate a=u_cla46_pg_logic22_and0 b=u_cla46_pg_logic23_or0 out=u_cla46_and111
.subckt or_gate a=u_cla46_and105 b=u_cla46_and110 out=u_cla46_or52
.subckt or_gate a=u_cla46_and108 b=u_cla46_and111 out=u_cla46_or53
.subckt or_gate a=u_cla46_or52 b=u_cla46_or53 out=u_cla46_or54
.subckt or_gate a=u_cla46_pg_logic23_and0 b=u_cla46_or54 out=u_cla46_or55
.subckt pg_logic a=a[24] b=b[24] pg_logic_or0=u_cla46_pg_logic24_or0 pg_logic_and0=u_cla46_pg_logic24_and0 pg_logic_xor0=u_cla46_pg_logic24_xor0
.subckt xor_gate a=u_cla46_pg_logic24_xor0 b=u_cla46_or55 out=u_cla46_xor24
.subckt and_gate a=u_cla46_or55 b=u_cla46_pg_logic24_or0 out=u_cla46_and112
.subckt or_gate a=u_cla46_pg_logic24_and0 b=u_cla46_and112 out=u_cla46_or56
.subckt pg_logic a=a[25] b=b[25] pg_logic_or0=u_cla46_pg_logic25_or0 pg_logic_and0=u_cla46_pg_logic25_and0 pg_logic_xor0=u_cla46_pg_logic25_xor0
.subckt xor_gate a=u_cla46_pg_logic25_xor0 b=u_cla46_or56 out=u_cla46_xor25
.subckt and_gate a=u_cla46_or55 b=u_cla46_pg_logic25_or0 out=u_cla46_and113
.subckt and_gate a=u_cla46_and113 b=u_cla46_pg_logic24_or0 out=u_cla46_and114
.subckt and_gate a=u_cla46_pg_logic24_and0 b=u_cla46_pg_logic25_or0 out=u_cla46_and115
.subckt or_gate a=u_cla46_and114 b=u_cla46_and115 out=u_cla46_or57
.subckt or_gate a=u_cla46_pg_logic25_and0 b=u_cla46_or57 out=u_cla46_or58
.subckt pg_logic a=a[26] b=b[26] pg_logic_or0=u_cla46_pg_logic26_or0 pg_logic_and0=u_cla46_pg_logic26_and0 pg_logic_xor0=u_cla46_pg_logic26_xor0
.subckt xor_gate a=u_cla46_pg_logic26_xor0 b=u_cla46_or58 out=u_cla46_xor26
.subckt and_gate a=u_cla46_or55 b=u_cla46_pg_logic25_or0 out=u_cla46_and116
.subckt and_gate a=u_cla46_pg_logic26_or0 b=u_cla46_pg_logic24_or0 out=u_cla46_and117
.subckt and_gate a=u_cla46_and116 b=u_cla46_and117 out=u_cla46_and118
.subckt and_gate a=u_cla46_pg_logic24_and0 b=u_cla46_pg_logic26_or0 out=u_cla46_and119
.subckt and_gate a=u_cla46_and119 b=u_cla46_pg_logic25_or0 out=u_cla46_and120
.subckt and_gate a=u_cla46_pg_logic25_and0 b=u_cla46_pg_logic26_or0 out=u_cla46_and121
.subckt or_gate a=u_cla46_and118 b=u_cla46_and120 out=u_cla46_or59
.subckt or_gate a=u_cla46_or59 b=u_cla46_and121 out=u_cla46_or60
.subckt or_gate a=u_cla46_pg_logic26_and0 b=u_cla46_or60 out=u_cla46_or61
.subckt pg_logic a=a[27] b=b[27] pg_logic_or0=u_cla46_pg_logic27_or0 pg_logic_and0=u_cla46_pg_logic27_and0 pg_logic_xor0=u_cla46_pg_logic27_xor0
.subckt xor_gate a=u_cla46_pg_logic27_xor0 b=u_cla46_or61 out=u_cla46_xor27
.subckt and_gate a=u_cla46_or55 b=u_cla46_pg_logic26_or0 out=u_cla46_and122
.subckt and_gate a=u_cla46_pg_logic27_or0 b=u_cla46_pg_logic25_or0 out=u_cla46_and123
.subckt and_gate a=u_cla46_and122 b=u_cla46_and123 out=u_cla46_and124
.subckt and_gate a=u_cla46_and124 b=u_cla46_pg_logic24_or0 out=u_cla46_and125
.subckt and_gate a=u_cla46_pg_logic24_and0 b=u_cla46_pg_logic26_or0 out=u_cla46_and126
.subckt and_gate a=u_cla46_pg_logic27_or0 b=u_cla46_pg_logic25_or0 out=u_cla46_and127
.subckt and_gate a=u_cla46_and126 b=u_cla46_and127 out=u_cla46_and128
.subckt and_gate a=u_cla46_pg_logic25_and0 b=u_cla46_pg_logic27_or0 out=u_cla46_and129
.subckt and_gate a=u_cla46_and129 b=u_cla46_pg_logic26_or0 out=u_cla46_and130
.subckt and_gate a=u_cla46_pg_logic26_and0 b=u_cla46_pg_logic27_or0 out=u_cla46_and131
.subckt or_gate a=u_cla46_and125 b=u_cla46_and130 out=u_cla46_or62
.subckt or_gate a=u_cla46_and128 b=u_cla46_and131 out=u_cla46_or63
.subckt or_gate a=u_cla46_or62 b=u_cla46_or63 out=u_cla46_or64
.subckt or_gate a=u_cla46_pg_logic27_and0 b=u_cla46_or64 out=u_cla46_or65
.subckt pg_logic a=a[28] b=b[28] pg_logic_or0=u_cla46_pg_logic28_or0 pg_logic_and0=u_cla46_pg_logic28_and0 pg_logic_xor0=u_cla46_pg_logic28_xor0
.subckt xor_gate a=u_cla46_pg_logic28_xor0 b=u_cla46_or65 out=u_cla46_xor28
.subckt and_gate a=u_cla46_or65 b=u_cla46_pg_logic28_or0 out=u_cla46_and132
.subckt or_gate a=u_cla46_pg_logic28_and0 b=u_cla46_and132 out=u_cla46_or66
.subckt pg_logic a=a[29] b=b[29] pg_logic_or0=u_cla46_pg_logic29_or0 pg_logic_and0=u_cla46_pg_logic29_and0 pg_logic_xor0=u_cla46_pg_logic29_xor0
.subckt xor_gate a=u_cla46_pg_logic29_xor0 b=u_cla46_or66 out=u_cla46_xor29
.subckt and_gate a=u_cla46_or65 b=u_cla46_pg_logic29_or0 out=u_cla46_and133
.subckt and_gate a=u_cla46_and133 b=u_cla46_pg_logic28_or0 out=u_cla46_and134
.subckt and_gate a=u_cla46_pg_logic28_and0 b=u_cla46_pg_logic29_or0 out=u_cla46_and135
.subckt or_gate a=u_cla46_and134 b=u_cla46_and135 out=u_cla46_or67
.subckt or_gate a=u_cla46_pg_logic29_and0 b=u_cla46_or67 out=u_cla46_or68
.subckt pg_logic a=a[30] b=b[30] pg_logic_or0=u_cla46_pg_logic30_or0 pg_logic_and0=u_cla46_pg_logic30_and0 pg_logic_xor0=u_cla46_pg_logic30_xor0
.subckt xor_gate a=u_cla46_pg_logic30_xor0 b=u_cla46_or68 out=u_cla46_xor30
.subckt and_gate a=u_cla46_or65 b=u_cla46_pg_logic29_or0 out=u_cla46_and136
.subckt and_gate a=u_cla46_pg_logic30_or0 b=u_cla46_pg_logic28_or0 out=u_cla46_and137
.subckt and_gate a=u_cla46_and136 b=u_cla46_and137 out=u_cla46_and138
.subckt and_gate a=u_cla46_pg_logic28_and0 b=u_cla46_pg_logic30_or0 out=u_cla46_and139
.subckt and_gate a=u_cla46_and139 b=u_cla46_pg_logic29_or0 out=u_cla46_and140
.subckt and_gate a=u_cla46_pg_logic29_and0 b=u_cla46_pg_logic30_or0 out=u_cla46_and141
.subckt or_gate a=u_cla46_and138 b=u_cla46_and140 out=u_cla46_or69
.subckt or_gate a=u_cla46_or69 b=u_cla46_and141 out=u_cla46_or70
.subckt or_gate a=u_cla46_pg_logic30_and0 b=u_cla46_or70 out=u_cla46_or71
.subckt pg_logic a=a[31] b=b[31] pg_logic_or0=u_cla46_pg_logic31_or0 pg_logic_and0=u_cla46_pg_logic31_and0 pg_logic_xor0=u_cla46_pg_logic31_xor0
.subckt xor_gate a=u_cla46_pg_logic31_xor0 b=u_cla46_or71 out=u_cla46_xor31
.subckt and_gate a=u_cla46_or65 b=u_cla46_pg_logic30_or0 out=u_cla46_and142
.subckt and_gate a=u_cla46_pg_logic31_or0 b=u_cla46_pg_logic29_or0 out=u_cla46_and143
.subckt and_gate a=u_cla46_and142 b=u_cla46_and143 out=u_cla46_and144
.subckt and_gate a=u_cla46_and144 b=u_cla46_pg_logic28_or0 out=u_cla46_and145
.subckt and_gate a=u_cla46_pg_logic28_and0 b=u_cla46_pg_logic30_or0 out=u_cla46_and146
.subckt and_gate a=u_cla46_pg_logic31_or0 b=u_cla46_pg_logic29_or0 out=u_cla46_and147
.subckt and_gate a=u_cla46_and146 b=u_cla46_and147 out=u_cla46_and148
.subckt and_gate a=u_cla46_pg_logic29_and0 b=u_cla46_pg_logic31_or0 out=u_cla46_and149
.subckt and_gate a=u_cla46_and149 b=u_cla46_pg_logic30_or0 out=u_cla46_and150
.subckt and_gate a=u_cla46_pg_logic30_and0 b=u_cla46_pg_logic31_or0 out=u_cla46_and151
.subckt or_gate a=u_cla46_and145 b=u_cla46_and150 out=u_cla46_or72
.subckt or_gate a=u_cla46_and148 b=u_cla46_and151 out=u_cla46_or73
.subckt or_gate a=u_cla46_or72 b=u_cla46_or73 out=u_cla46_or74
.subckt or_gate a=u_cla46_pg_logic31_and0 b=u_cla46_or74 out=u_cla46_or75
.subckt pg_logic a=a[32] b=b[32] pg_logic_or0=u_cla46_pg_logic32_or0 pg_logic_and0=u_cla46_pg_logic32_and0 pg_logic_xor0=u_cla46_pg_logic32_xor0
.subckt xor_gate a=u_cla46_pg_logic32_xor0 b=u_cla46_or75 out=u_cla46_xor32
.subckt and_gate a=u_cla46_or75 b=u_cla46_pg_logic32_or0 out=u_cla46_and152
.subckt or_gate a=u_cla46_pg_logic32_and0 b=u_cla46_and152 out=u_cla46_or76
.subckt pg_logic a=a[33] b=b[33] pg_logic_or0=u_cla46_pg_logic33_or0 pg_logic_and0=u_cla46_pg_logic33_and0 pg_logic_xor0=u_cla46_pg_logic33_xor0
.subckt xor_gate a=u_cla46_pg_logic33_xor0 b=u_cla46_or76 out=u_cla46_xor33
.subckt and_gate a=u_cla46_or75 b=u_cla46_pg_logic33_or0 out=u_cla46_and153
.subckt and_gate a=u_cla46_and153 b=u_cla46_pg_logic32_or0 out=u_cla46_and154
.subckt and_gate a=u_cla46_pg_logic32_and0 b=u_cla46_pg_logic33_or0 out=u_cla46_and155
.subckt or_gate a=u_cla46_and154 b=u_cla46_and155 out=u_cla46_or77
.subckt or_gate a=u_cla46_pg_logic33_and0 b=u_cla46_or77 out=u_cla46_or78
.subckt pg_logic a=a[34] b=b[34] pg_logic_or0=u_cla46_pg_logic34_or0 pg_logic_and0=u_cla46_pg_logic34_and0 pg_logic_xor0=u_cla46_pg_logic34_xor0
.subckt xor_gate a=u_cla46_pg_logic34_xor0 b=u_cla46_or78 out=u_cla46_xor34
.subckt and_gate a=u_cla46_or75 b=u_cla46_pg_logic33_or0 out=u_cla46_and156
.subckt and_gate a=u_cla46_pg_logic34_or0 b=u_cla46_pg_logic32_or0 out=u_cla46_and157
.subckt and_gate a=u_cla46_and156 b=u_cla46_and157 out=u_cla46_and158
.subckt and_gate a=u_cla46_pg_logic32_and0 b=u_cla46_pg_logic34_or0 out=u_cla46_and159
.subckt and_gate a=u_cla46_and159 b=u_cla46_pg_logic33_or0 out=u_cla46_and160
.subckt and_gate a=u_cla46_pg_logic33_and0 b=u_cla46_pg_logic34_or0 out=u_cla46_and161
.subckt or_gate a=u_cla46_and158 b=u_cla46_and160 out=u_cla46_or79
.subckt or_gate a=u_cla46_or79 b=u_cla46_and161 out=u_cla46_or80
.subckt or_gate a=u_cla46_pg_logic34_and0 b=u_cla46_or80 out=u_cla46_or81
.subckt pg_logic a=a[35] b=b[35] pg_logic_or0=u_cla46_pg_logic35_or0 pg_logic_and0=u_cla46_pg_logic35_and0 pg_logic_xor0=u_cla46_pg_logic35_xor0
.subckt xor_gate a=u_cla46_pg_logic35_xor0 b=u_cla46_or81 out=u_cla46_xor35
.subckt and_gate a=u_cla46_or75 b=u_cla46_pg_logic34_or0 out=u_cla46_and162
.subckt and_gate a=u_cla46_pg_logic35_or0 b=u_cla46_pg_logic33_or0 out=u_cla46_and163
.subckt and_gate a=u_cla46_and162 b=u_cla46_and163 out=u_cla46_and164
.subckt and_gate a=u_cla46_and164 b=u_cla46_pg_logic32_or0 out=u_cla46_and165
.subckt and_gate a=u_cla46_pg_logic32_and0 b=u_cla46_pg_logic34_or0 out=u_cla46_and166
.subckt and_gate a=u_cla46_pg_logic35_or0 b=u_cla46_pg_logic33_or0 out=u_cla46_and167
.subckt and_gate a=u_cla46_and166 b=u_cla46_and167 out=u_cla46_and168
.subckt and_gate a=u_cla46_pg_logic33_and0 b=u_cla46_pg_logic35_or0 out=u_cla46_and169
.subckt and_gate a=u_cla46_and169 b=u_cla46_pg_logic34_or0 out=u_cla46_and170
.subckt and_gate a=u_cla46_pg_logic34_and0 b=u_cla46_pg_logic35_or0 out=u_cla46_and171
.subckt or_gate a=u_cla46_and165 b=u_cla46_and170 out=u_cla46_or82
.subckt or_gate a=u_cla46_and168 b=u_cla46_and171 out=u_cla46_or83
.subckt or_gate a=u_cla46_or82 b=u_cla46_or83 out=u_cla46_or84
.subckt or_gate a=u_cla46_pg_logic35_and0 b=u_cla46_or84 out=u_cla46_or85
.subckt pg_logic a=a[36] b=b[36] pg_logic_or0=u_cla46_pg_logic36_or0 pg_logic_and0=u_cla46_pg_logic36_and0 pg_logic_xor0=u_cla46_pg_logic36_xor0
.subckt xor_gate a=u_cla46_pg_logic36_xor0 b=u_cla46_or85 out=u_cla46_xor36
.subckt and_gate a=u_cla46_or85 b=u_cla46_pg_logic36_or0 out=u_cla46_and172
.subckt or_gate a=u_cla46_pg_logic36_and0 b=u_cla46_and172 out=u_cla46_or86
.subckt pg_logic a=a[37] b=b[37] pg_logic_or0=u_cla46_pg_logic37_or0 pg_logic_and0=u_cla46_pg_logic37_and0 pg_logic_xor0=u_cla46_pg_logic37_xor0
.subckt xor_gate a=u_cla46_pg_logic37_xor0 b=u_cla46_or86 out=u_cla46_xor37
.subckt and_gate a=u_cla46_or85 b=u_cla46_pg_logic37_or0 out=u_cla46_and173
.subckt and_gate a=u_cla46_and173 b=u_cla46_pg_logic36_or0 out=u_cla46_and174
.subckt and_gate a=u_cla46_pg_logic36_and0 b=u_cla46_pg_logic37_or0 out=u_cla46_and175
.subckt or_gate a=u_cla46_and174 b=u_cla46_and175 out=u_cla46_or87
.subckt or_gate a=u_cla46_pg_logic37_and0 b=u_cla46_or87 out=u_cla46_or88
.subckt pg_logic a=a[38] b=b[38] pg_logic_or0=u_cla46_pg_logic38_or0 pg_logic_and0=u_cla46_pg_logic38_and0 pg_logic_xor0=u_cla46_pg_logic38_xor0
.subckt xor_gate a=u_cla46_pg_logic38_xor0 b=u_cla46_or88 out=u_cla46_xor38
.subckt and_gate a=u_cla46_or85 b=u_cla46_pg_logic37_or0 out=u_cla46_and176
.subckt and_gate a=u_cla46_pg_logic38_or0 b=u_cla46_pg_logic36_or0 out=u_cla46_and177
.subckt and_gate a=u_cla46_and176 b=u_cla46_and177 out=u_cla46_and178
.subckt and_gate a=u_cla46_pg_logic36_and0 b=u_cla46_pg_logic38_or0 out=u_cla46_and179
.subckt and_gate a=u_cla46_and179 b=u_cla46_pg_logic37_or0 out=u_cla46_and180
.subckt and_gate a=u_cla46_pg_logic37_and0 b=u_cla46_pg_logic38_or0 out=u_cla46_and181
.subckt or_gate a=u_cla46_and178 b=u_cla46_and180 out=u_cla46_or89
.subckt or_gate a=u_cla46_or89 b=u_cla46_and181 out=u_cla46_or90
.subckt or_gate a=u_cla46_pg_logic38_and0 b=u_cla46_or90 out=u_cla46_or91
.subckt pg_logic a=a[39] b=b[39] pg_logic_or0=u_cla46_pg_logic39_or0 pg_logic_and0=u_cla46_pg_logic39_and0 pg_logic_xor0=u_cla46_pg_logic39_xor0
.subckt xor_gate a=u_cla46_pg_logic39_xor0 b=u_cla46_or91 out=u_cla46_xor39
.subckt and_gate a=u_cla46_or85 b=u_cla46_pg_logic38_or0 out=u_cla46_and182
.subckt and_gate a=u_cla46_pg_logic39_or0 b=u_cla46_pg_logic37_or0 out=u_cla46_and183
.subckt and_gate a=u_cla46_and182 b=u_cla46_and183 out=u_cla46_and184
.subckt and_gate a=u_cla46_and184 b=u_cla46_pg_logic36_or0 out=u_cla46_and185
.subckt and_gate a=u_cla46_pg_logic36_and0 b=u_cla46_pg_logic38_or0 out=u_cla46_and186
.subckt and_gate a=u_cla46_pg_logic39_or0 b=u_cla46_pg_logic37_or0 out=u_cla46_and187
.subckt and_gate a=u_cla46_and186 b=u_cla46_and187 out=u_cla46_and188
.subckt and_gate a=u_cla46_pg_logic37_and0 b=u_cla46_pg_logic39_or0 out=u_cla46_and189
.subckt and_gate a=u_cla46_and189 b=u_cla46_pg_logic38_or0 out=u_cla46_and190
.subckt and_gate a=u_cla46_pg_logic38_and0 b=u_cla46_pg_logic39_or0 out=u_cla46_and191
.subckt or_gate a=u_cla46_and185 b=u_cla46_and190 out=u_cla46_or92
.subckt or_gate a=u_cla46_and188 b=u_cla46_and191 out=u_cla46_or93
.subckt or_gate a=u_cla46_or92 b=u_cla46_or93 out=u_cla46_or94
.subckt or_gate a=u_cla46_pg_logic39_and0 b=u_cla46_or94 out=u_cla46_or95
.subckt pg_logic a=a[40] b=b[40] pg_logic_or0=u_cla46_pg_logic40_or0 pg_logic_and0=u_cla46_pg_logic40_and0 pg_logic_xor0=u_cla46_pg_logic40_xor0
.subckt xor_gate a=u_cla46_pg_logic40_xor0 b=u_cla46_or95 out=u_cla46_xor40
.subckt and_gate a=u_cla46_or95 b=u_cla46_pg_logic40_or0 out=u_cla46_and192
.subckt or_gate a=u_cla46_pg_logic40_and0 b=u_cla46_and192 out=u_cla46_or96
.subckt pg_logic a=a[41] b=b[41] pg_logic_or0=u_cla46_pg_logic41_or0 pg_logic_and0=u_cla46_pg_logic41_and0 pg_logic_xor0=u_cla46_pg_logic41_xor0
.subckt xor_gate a=u_cla46_pg_logic41_xor0 b=u_cla46_or96 out=u_cla46_xor41
.subckt and_gate a=u_cla46_or95 b=u_cla46_pg_logic41_or0 out=u_cla46_and193
.subckt and_gate a=u_cla46_and193 b=u_cla46_pg_logic40_or0 out=u_cla46_and194
.subckt and_gate a=u_cla46_pg_logic40_and0 b=u_cla46_pg_logic41_or0 out=u_cla46_and195
.subckt or_gate a=u_cla46_and194 b=u_cla46_and195 out=u_cla46_or97
.subckt or_gate a=u_cla46_pg_logic41_and0 b=u_cla46_or97 out=u_cla46_or98
.subckt pg_logic a=a[42] b=b[42] pg_logic_or0=u_cla46_pg_logic42_or0 pg_logic_and0=u_cla46_pg_logic42_and0 pg_logic_xor0=u_cla46_pg_logic42_xor0
.subckt xor_gate a=u_cla46_pg_logic42_xor0 b=u_cla46_or98 out=u_cla46_xor42
.subckt and_gate a=u_cla46_or95 b=u_cla46_pg_logic41_or0 out=u_cla46_and196
.subckt and_gate a=u_cla46_pg_logic42_or0 b=u_cla46_pg_logic40_or0 out=u_cla46_and197
.subckt and_gate a=u_cla46_and196 b=u_cla46_and197 out=u_cla46_and198
.subckt and_gate a=u_cla46_pg_logic40_and0 b=u_cla46_pg_logic42_or0 out=u_cla46_and199
.subckt and_gate a=u_cla46_and199 b=u_cla46_pg_logic41_or0 out=u_cla46_and200
.subckt and_gate a=u_cla46_pg_logic41_and0 b=u_cla46_pg_logic42_or0 out=u_cla46_and201
.subckt or_gate a=u_cla46_and198 b=u_cla46_and200 out=u_cla46_or99
.subckt or_gate a=u_cla46_or99 b=u_cla46_and201 out=u_cla46_or100
.subckt or_gate a=u_cla46_pg_logic42_and0 b=u_cla46_or100 out=u_cla46_or101
.subckt pg_logic a=a[43] b=b[43] pg_logic_or0=u_cla46_pg_logic43_or0 pg_logic_and0=u_cla46_pg_logic43_and0 pg_logic_xor0=u_cla46_pg_logic43_xor0
.subckt xor_gate a=u_cla46_pg_logic43_xor0 b=u_cla46_or101 out=u_cla46_xor43
.subckt and_gate a=u_cla46_or95 b=u_cla46_pg_logic42_or0 out=u_cla46_and202
.subckt and_gate a=u_cla46_pg_logic43_or0 b=u_cla46_pg_logic41_or0 out=u_cla46_and203
.subckt and_gate a=u_cla46_and202 b=u_cla46_and203 out=u_cla46_and204
.subckt and_gate a=u_cla46_and204 b=u_cla46_pg_logic40_or0 out=u_cla46_and205
.subckt and_gate a=u_cla46_pg_logic40_and0 b=u_cla46_pg_logic42_or0 out=u_cla46_and206
.subckt and_gate a=u_cla46_pg_logic43_or0 b=u_cla46_pg_logic41_or0 out=u_cla46_and207
.subckt and_gate a=u_cla46_and206 b=u_cla46_and207 out=u_cla46_and208
.subckt and_gate a=u_cla46_pg_logic41_and0 b=u_cla46_pg_logic43_or0 out=u_cla46_and209
.subckt and_gate a=u_cla46_and209 b=u_cla46_pg_logic42_or0 out=u_cla46_and210
.subckt and_gate a=u_cla46_pg_logic42_and0 b=u_cla46_pg_logic43_or0 out=u_cla46_and211
.subckt or_gate a=u_cla46_and205 b=u_cla46_and210 out=u_cla46_or102
.subckt or_gate a=u_cla46_and208 b=u_cla46_and211 out=u_cla46_or103
.subckt or_gate a=u_cla46_or102 b=u_cla46_or103 out=u_cla46_or104
.subckt or_gate a=u_cla46_pg_logic43_and0 b=u_cla46_or104 out=u_cla46_or105
.subckt pg_logic a=a[44] b=b[44] pg_logic_or0=u_cla46_pg_logic44_or0 pg_logic_and0=u_cla46_pg_logic44_and0 pg_logic_xor0=u_cla46_pg_logic44_xor0
.subckt xor_gate a=u_cla46_pg_logic44_xor0 b=u_cla46_or105 out=u_cla46_xor44
.subckt and_gate a=u_cla46_or105 b=u_cla46_pg_logic44_or0 out=u_cla46_and212
.subckt or_gate a=u_cla46_pg_logic44_and0 b=u_cla46_and212 out=u_cla46_or106
.subckt pg_logic a=a[45] b=b[45] pg_logic_or0=u_cla46_pg_logic45_or0 pg_logic_and0=u_cla46_pg_logic45_and0 pg_logic_xor0=u_cla46_pg_logic45_xor0
.subckt xor_gate a=u_cla46_pg_logic45_xor0 b=u_cla46_or106 out=u_cla46_xor45
.subckt and_gate a=u_cla46_or105 b=u_cla46_pg_logic45_or0 out=u_cla46_and213
.subckt and_gate a=u_cla46_and213 b=u_cla46_pg_logic44_or0 out=u_cla46_and214
.subckt and_gate a=u_cla46_pg_logic44_and0 b=u_cla46_pg_logic45_or0 out=u_cla46_and215
.subckt or_gate a=u_cla46_and214 b=u_cla46_and215 out=u_cla46_or107
.subckt or_gate a=u_cla46_pg_logic45_and0 b=u_cla46_or107 out=u_cla46_or108
.names u_cla46_pg_logic0_xor0 u_cla46_out[0]
1 1
.names u_cla46_xor1 u_cla46_out[1]
1 1
.names u_cla46_xor2 u_cla46_out[2]
1 1
.names u_cla46_xor3 u_cla46_out[3]
1 1
.names u_cla46_xor4 u_cla46_out[4]
1 1
.names u_cla46_xor5 u_cla46_out[5]
1 1
.names u_cla46_xor6 u_cla46_out[6]
1 1
.names u_cla46_xor7 u_cla46_out[7]
1 1
.names u_cla46_xor8 u_cla46_out[8]
1 1
.names u_cla46_xor9 u_cla46_out[9]
1 1
.names u_cla46_xor10 u_cla46_out[10]
1 1
.names u_cla46_xor11 u_cla46_out[11]
1 1
.names u_cla46_xor12 u_cla46_out[12]
1 1
.names u_cla46_xor13 u_cla46_out[13]
1 1
.names u_cla46_xor14 u_cla46_out[14]
1 1
.names u_cla46_xor15 u_cla46_out[15]
1 1
.names u_cla46_xor16 u_cla46_out[16]
1 1
.names u_cla46_xor17 u_cla46_out[17]
1 1
.names u_cla46_xor18 u_cla46_out[18]
1 1
.names u_cla46_xor19 u_cla46_out[19]
1 1
.names u_cla46_xor20 u_cla46_out[20]
1 1
.names u_cla46_xor21 u_cla46_out[21]
1 1
.names u_cla46_xor22 u_cla46_out[22]
1 1
.names u_cla46_xor23 u_cla46_out[23]
1 1
.names u_cla46_xor24 u_cla46_out[24]
1 1
.names u_cla46_xor25 u_cla46_out[25]
1 1
.names u_cla46_xor26 u_cla46_out[26]
1 1
.names u_cla46_xor27 u_cla46_out[27]
1 1
.names u_cla46_xor28 u_cla46_out[28]
1 1
.names u_cla46_xor29 u_cla46_out[29]
1 1
.names u_cla46_xor30 u_cla46_out[30]
1 1
.names u_cla46_xor31 u_cla46_out[31]
1 1
.names u_cla46_xor32 u_cla46_out[32]
1 1
.names u_cla46_xor33 u_cla46_out[33]
1 1
.names u_cla46_xor34 u_cla46_out[34]
1 1
.names u_cla46_xor35 u_cla46_out[35]
1 1
.names u_cla46_xor36 u_cla46_out[36]
1 1
.names u_cla46_xor37 u_cla46_out[37]
1 1
.names u_cla46_xor38 u_cla46_out[38]
1 1
.names u_cla46_xor39 u_cla46_out[39]
1 1
.names u_cla46_xor40 u_cla46_out[40]
1 1
.names u_cla46_xor41 u_cla46_out[41]
1 1
.names u_cla46_xor42 u_cla46_out[42]
1 1
.names u_cla46_xor43 u_cla46_out[43]
1 1
.names u_cla46_xor44 u_cla46_out[44]
1 1
.names u_cla46_xor45 u_cla46_out[45]
1 1
.names u_cla46_or108 u_cla46_out[46]
1 1
.end

.model pg_logic
.inputs a b
.outputs pg_logic_or0 pg_logic_and0 pg_logic_xor0
.names vdd
1
.names gnd
0
.subckt or_gate a=a b=b out=pg_logic_or0
.subckt and_gate a=a b=b out=pg_logic_and0
.subckt xor_gate a=a b=b out=pg_logic_xor0
.end

.model fa
.inputs a b cin
.outputs fa_xor1 fa_or0
.names vdd
1
.names gnd
0
.subckt xor_gate a=a b=b out=fa_xor0
.subckt and_gate a=a b=b out=fa_and0
.subckt xor_gate a=fa_xor0 b=cin out=fa_xor1
.subckt and_gate a=fa_xor0 b=cin out=fa_and1
.subckt or_gate a=fa_and0 b=fa_and1 out=fa_or0
.end

.model ha
.inputs a b
.outputs ha_xor0 ha_and0
.names vdd
1
.names gnd
0
.subckt xor_gate a=a b=b out=ha_xor0
.subckt and_gate a=a b=b out=ha_and0
.end

.model or_gate
.inputs a b
.outputs out
.names vdd
1
.names gnd
0
.names a b out
1- 1
-1 1
.end

.model xor_gate
.inputs a b
.outputs out
.names vdd
1
.names gnd
0
.names a b out
01 1
10 1
.end

.model and_gate
.inputs a b
.outputs out
.names vdd
1
.names gnd
0
.names a b out
11 1
.end