.model h_s_cska24
.inputs a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] a[8] a[9] a[10] a[11] a[12] a[13] a[14] a[15] a[16] a[17] a[18] a[19] a[20] a[21] a[22] a[23] b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9] b[10] b[11] b[12] b[13] b[14] b[15] b[16] b[17] b[18] b[19] b[20] b[21] b[22] b[23]
.outputs h_s_cska24_out[0] h_s_cska24_out[1] h_s_cska24_out[2] h_s_cska24_out[3] h_s_cska24_out[4] h_s_cska24_out[5] h_s_cska24_out[6] h_s_cska24_out[7] h_s_cska24_out[8] h_s_cska24_out[9] h_s_cska24_out[10] h_s_cska24_out[11] h_s_cska24_out[12] h_s_cska24_out[13] h_s_cska24_out[14] h_s_cska24_out[15] h_s_cska24_out[16] h_s_cska24_out[17] h_s_cska24_out[18] h_s_cska24_out[19] h_s_cska24_out[20] h_s_cska24_out[21] h_s_cska24_out[22] h_s_cska24_out[23] h_s_cska24_out[24]
.names vdd
1
.names gnd
0
.subckt xor_gate a=a[0] b=b[0] out=h_s_cska24_xor0
.subckt ha a=a[0] b=b[0] ha_xor0=h_s_cska24_ha0_xor0 ha_and0=h_s_cska24_ha0_and0
.subckt xor_gate a=a[1] b=b[1] out=h_s_cska24_xor1
.subckt fa a=a[1] b=b[1] cin=h_s_cska24_ha0_and0 fa_xor1=h_s_cska24_fa0_xor1 fa_or0=h_s_cska24_fa0_or0
.subckt xor_gate a=a[2] b=b[2] out=h_s_cska24_xor2
.subckt fa a=a[2] b=b[2] cin=h_s_cska24_fa0_or0 fa_xor1=h_s_cska24_fa1_xor1 fa_or0=h_s_cska24_fa1_or0
.subckt xor_gate a=a[3] b=b[3] out=h_s_cska24_xor3
.subckt fa a=a[3] b=b[3] cin=h_s_cska24_fa1_or0 fa_xor1=h_s_cska24_fa2_xor1 fa_or0=h_s_cska24_fa2_or0
.subckt and_gate a=h_s_cska24_xor0 b=h_s_cska24_xor2 out=h_s_cska24_and_propagate00
.subckt and_gate a=h_s_cska24_xor1 b=h_s_cska24_xor3 out=h_s_cska24_and_propagate01
.subckt and_gate a=h_s_cska24_and_propagate00 b=h_s_cska24_and_propagate01 out=h_s_cska24_and_propagate02
.subckt mux2to1 d0=h_s_cska24_fa2_or0 d1=gnd sel=h_s_cska24_and_propagate02 mux2to1_xor0=h_s_cska24_mux2to10_and1
.subckt xor_gate a=a[4] b=b[4] out=h_s_cska24_xor4
.subckt fa a=a[4] b=b[4] cin=h_s_cska24_mux2to10_and1 fa_xor1=h_s_cska24_fa3_xor1 fa_or0=h_s_cska24_fa3_or0
.subckt xor_gate a=a[5] b=b[5] out=h_s_cska24_xor5
.subckt fa a=a[5] b=b[5] cin=h_s_cska24_fa3_or0 fa_xor1=h_s_cska24_fa4_xor1 fa_or0=h_s_cska24_fa4_or0
.subckt xor_gate a=a[6] b=b[6] out=h_s_cska24_xor6
.subckt fa a=a[6] b=b[6] cin=h_s_cska24_fa4_or0 fa_xor1=h_s_cska24_fa5_xor1 fa_or0=h_s_cska24_fa5_or0
.subckt xor_gate a=a[7] b=b[7] out=h_s_cska24_xor7
.subckt fa a=a[7] b=b[7] cin=h_s_cska24_fa5_or0 fa_xor1=h_s_cska24_fa6_xor1 fa_or0=h_s_cska24_fa6_or0
.subckt and_gate a=h_s_cska24_xor4 b=h_s_cska24_xor6 out=h_s_cska24_and_propagate13
.subckt and_gate a=h_s_cska24_xor5 b=h_s_cska24_xor7 out=h_s_cska24_and_propagate14
.subckt and_gate a=h_s_cska24_and_propagate13 b=h_s_cska24_and_propagate14 out=h_s_cska24_and_propagate15
.subckt mux2to1 d0=h_s_cska24_fa6_or0 d1=h_s_cska24_mux2to10_and1 sel=h_s_cska24_and_propagate15 mux2to1_xor0=h_s_cska24_mux2to11_xor0
.subckt xor_gate a=a[8] b=b[8] out=h_s_cska24_xor8
.subckt fa a=a[8] b=b[8] cin=h_s_cska24_mux2to11_xor0 fa_xor1=h_s_cska24_fa7_xor1 fa_or0=h_s_cska24_fa7_or0
.subckt xor_gate a=a[9] b=b[9] out=h_s_cska24_xor9
.subckt fa a=a[9] b=b[9] cin=h_s_cska24_fa7_or0 fa_xor1=h_s_cska24_fa8_xor1 fa_or0=h_s_cska24_fa8_or0
.subckt xor_gate a=a[10] b=b[10] out=h_s_cska24_xor10
.subckt fa a=a[10] b=b[10] cin=h_s_cska24_fa8_or0 fa_xor1=h_s_cska24_fa9_xor1 fa_or0=h_s_cska24_fa9_or0
.subckt xor_gate a=a[11] b=b[11] out=h_s_cska24_xor11
.subckt fa a=a[11] b=b[11] cin=h_s_cska24_fa9_or0 fa_xor1=h_s_cska24_fa10_xor1 fa_or0=h_s_cska24_fa10_or0
.subckt and_gate a=h_s_cska24_xor8 b=h_s_cska24_xor10 out=h_s_cska24_and_propagate26
.subckt and_gate a=h_s_cska24_xor9 b=h_s_cska24_xor11 out=h_s_cska24_and_propagate27
.subckt and_gate a=h_s_cska24_and_propagate26 b=h_s_cska24_and_propagate27 out=h_s_cska24_and_propagate28
.subckt mux2to1 d0=h_s_cska24_fa10_or0 d1=h_s_cska24_mux2to11_xor0 sel=h_s_cska24_and_propagate28 mux2to1_xor0=h_s_cska24_mux2to12_xor0
.subckt xor_gate a=a[12] b=b[12] out=h_s_cska24_xor12
.subckt fa a=a[12] b=b[12] cin=h_s_cska24_mux2to12_xor0 fa_xor1=h_s_cska24_fa11_xor1 fa_or0=h_s_cska24_fa11_or0
.subckt xor_gate a=a[13] b=b[13] out=h_s_cska24_xor13
.subckt fa a=a[13] b=b[13] cin=h_s_cska24_fa11_or0 fa_xor1=h_s_cska24_fa12_xor1 fa_or0=h_s_cska24_fa12_or0
.subckt xor_gate a=a[14] b=b[14] out=h_s_cska24_xor14
.subckt fa a=a[14] b=b[14] cin=h_s_cska24_fa12_or0 fa_xor1=h_s_cska24_fa13_xor1 fa_or0=h_s_cska24_fa13_or0
.subckt xor_gate a=a[15] b=b[15] out=h_s_cska24_xor15
.subckt fa a=a[15] b=b[15] cin=h_s_cska24_fa13_or0 fa_xor1=h_s_cska24_fa14_xor1 fa_or0=h_s_cska24_fa14_or0
.subckt and_gate a=h_s_cska24_xor12 b=h_s_cska24_xor14 out=h_s_cska24_and_propagate39
.subckt and_gate a=h_s_cska24_xor13 b=h_s_cska24_xor15 out=h_s_cska24_and_propagate310
.subckt and_gate a=h_s_cska24_and_propagate39 b=h_s_cska24_and_propagate310 out=h_s_cska24_and_propagate311
.subckt mux2to1 d0=h_s_cska24_fa14_or0 d1=h_s_cska24_mux2to12_xor0 sel=h_s_cska24_and_propagate311 mux2to1_xor0=h_s_cska24_mux2to13_xor0
.subckt xor_gate a=a[16] b=b[16] out=h_s_cska24_xor16
.subckt fa a=a[16] b=b[16] cin=h_s_cska24_mux2to13_xor0 fa_xor1=h_s_cska24_fa15_xor1 fa_or0=h_s_cska24_fa15_or0
.subckt xor_gate a=a[17] b=b[17] out=h_s_cska24_xor17
.subckt fa a=a[17] b=b[17] cin=h_s_cska24_fa15_or0 fa_xor1=h_s_cska24_fa16_xor1 fa_or0=h_s_cska24_fa16_or0
.subckt xor_gate a=a[18] b=b[18] out=h_s_cska24_xor18
.subckt fa a=a[18] b=b[18] cin=h_s_cska24_fa16_or0 fa_xor1=h_s_cska24_fa17_xor1 fa_or0=h_s_cska24_fa17_or0
.subckt xor_gate a=a[19] b=b[19] out=h_s_cska24_xor19
.subckt fa a=a[19] b=b[19] cin=h_s_cska24_fa17_or0 fa_xor1=h_s_cska24_fa18_xor1 fa_or0=h_s_cska24_fa18_or0
.subckt and_gate a=h_s_cska24_xor16 b=h_s_cska24_xor18 out=h_s_cska24_and_propagate412
.subckt and_gate a=h_s_cska24_xor17 b=h_s_cska24_xor19 out=h_s_cska24_and_propagate413
.subckt and_gate a=h_s_cska24_and_propagate412 b=h_s_cska24_and_propagate413 out=h_s_cska24_and_propagate414
.subckt mux2to1 d0=h_s_cska24_fa18_or0 d1=h_s_cska24_mux2to13_xor0 sel=h_s_cska24_and_propagate414 mux2to1_xor0=h_s_cska24_mux2to14_xor0
.subckt xor_gate a=a[20] b=b[20] out=h_s_cska24_xor20
.subckt fa a=a[20] b=b[20] cin=h_s_cska24_mux2to14_xor0 fa_xor1=h_s_cska24_fa19_xor1 fa_or0=h_s_cska24_fa19_or0
.subckt xor_gate a=a[21] b=b[21] out=h_s_cska24_xor21
.subckt fa a=a[21] b=b[21] cin=h_s_cska24_fa19_or0 fa_xor1=h_s_cska24_fa20_xor1 fa_or0=h_s_cska24_fa20_or0
.subckt xor_gate a=a[22] b=b[22] out=h_s_cska24_xor22
.subckt fa a=a[22] b=b[22] cin=h_s_cska24_fa20_or0 fa_xor1=h_s_cska24_fa21_xor1 fa_or0=h_s_cska24_fa21_or0
.subckt xor_gate a=a[23] b=b[23] out=h_s_cska24_xor23
.subckt fa a=a[23] b=b[23] cin=h_s_cska24_fa21_or0 fa_xor1=h_s_cska24_fa22_xor1 fa_or0=h_s_cska24_fa22_or0
.subckt and_gate a=h_s_cska24_xor20 b=h_s_cska24_xor22 out=h_s_cska24_and_propagate515
.subckt and_gate a=h_s_cska24_xor21 b=h_s_cska24_xor23 out=h_s_cska24_and_propagate516
.subckt and_gate a=h_s_cska24_and_propagate515 b=h_s_cska24_and_propagate516 out=h_s_cska24_and_propagate517
.subckt mux2to1 d0=h_s_cska24_fa22_or0 d1=h_s_cska24_mux2to14_xor0 sel=h_s_cska24_and_propagate517 mux2to1_xor0=h_s_cska24_mux2to15_xor0
.subckt xor_gate a=a[23] b=b[23] out=h_s_cska24_xor24
.subckt xor_gate a=h_s_cska24_xor24 b=h_s_cska24_mux2to15_xor0 out=h_s_cska24_xor25
.names h_s_cska24_ha0_xor0 h_s_cska24_out[0]
1 1
.names h_s_cska24_fa0_xor1 h_s_cska24_out[1]
1 1
.names h_s_cska24_fa1_xor1 h_s_cska24_out[2]
1 1
.names h_s_cska24_fa2_xor1 h_s_cska24_out[3]
1 1
.names h_s_cska24_fa3_xor1 h_s_cska24_out[4]
1 1
.names h_s_cska24_fa4_xor1 h_s_cska24_out[5]
1 1
.names h_s_cska24_fa5_xor1 h_s_cska24_out[6]
1 1
.names h_s_cska24_fa6_xor1 h_s_cska24_out[7]
1 1
.names h_s_cska24_fa7_xor1 h_s_cska24_out[8]
1 1
.names h_s_cska24_fa8_xor1 h_s_cska24_out[9]
1 1
.names h_s_cska24_fa9_xor1 h_s_cska24_out[10]
1 1
.names h_s_cska24_fa10_xor1 h_s_cska24_out[11]
1 1
.names h_s_cska24_fa11_xor1 h_s_cska24_out[12]
1 1
.names h_s_cska24_fa12_xor1 h_s_cska24_out[13]
1 1
.names h_s_cska24_fa13_xor1 h_s_cska24_out[14]
1 1
.names h_s_cska24_fa14_xor1 h_s_cska24_out[15]
1 1
.names h_s_cska24_fa15_xor1 h_s_cska24_out[16]
1 1
.names h_s_cska24_fa16_xor1 h_s_cska24_out[17]
1 1
.names h_s_cska24_fa17_xor1 h_s_cska24_out[18]
1 1
.names h_s_cska24_fa18_xor1 h_s_cska24_out[19]
1 1
.names h_s_cska24_fa19_xor1 h_s_cska24_out[20]
1 1
.names h_s_cska24_fa20_xor1 h_s_cska24_out[21]
1 1
.names h_s_cska24_fa21_xor1 h_s_cska24_out[22]
1 1
.names h_s_cska24_fa22_xor1 h_s_cska24_out[23]
1 1
.names h_s_cska24_xor25 h_s_cska24_out[24]
1 1
.end

.model mux2to1
.inputs d0 d1 sel
.outputs mux2to1_xor0
.names vdd
1
.names gnd
0
.subckt and_gate a=d1 b=sel out=mux2to1_and0
.subckt not_gate a=sel out=mux2to1_not0
.subckt and_gate a=d0 b=mux2to1_not0 out=mux2to1_and1
.subckt xor_gate a=mux2to1_and0 b=mux2to1_and1 out=mux2to1_xor0
.end

.model fa
.inputs a b cin
.outputs fa_xor1 fa_or0
.names vdd
1
.names gnd
0
.subckt xor_gate a=a b=b out=fa_xor0
.subckt and_gate a=a b=b out=fa_and0
.subckt xor_gate a=fa_xor0 b=cin out=fa_xor1
.subckt and_gate a=fa_xor0 b=cin out=fa_and1
.subckt or_gate a=fa_and0 b=fa_and1 out=fa_or0
.end

.model ha
.inputs a b
.outputs ha_xor0 ha_and0
.names vdd
1
.names gnd
0
.subckt xor_gate a=a b=b out=ha_xor0
.subckt and_gate a=a b=b out=ha_and0
.end

.model not_gate
.inputs a
.outputs out
.names vdd
1
.names gnd
0
.names a out
0 1
.end

.model or_gate
.inputs a b
.outputs out
.names vdd
1
.names gnd
0
.names a b out
1- 1
-1 1
.end

.model and_gate
.inputs a b
.outputs out
.names vdd
1
.names gnd
0
.names a b out
11 1
.end

.model xor_gate
.inputs a b
.outputs out
.names vdd
1
.names gnd
0
.names a b out
01 1
10 1
.end