.model s_CSAwallace_cla4
.inputs a[0] a[1] a[2] a[3] b[0] b[1] b[2] b[3]
.outputs s_CSAwallace_cla4_out[0] s_CSAwallace_cla4_out[1] s_CSAwallace_cla4_out[2] s_CSAwallace_cla4_out[3] s_CSAwallace_cla4_out[4] s_CSAwallace_cla4_out[5] s_CSAwallace_cla4_out[6] s_CSAwallace_cla4_out[7]
.names vdd
1
.names gnd
0
.names a[0] b[0] s_CSAwallace_cla4_and_0_0
11 1
.names a[1] b[0] s_CSAwallace_cla4_and_1_0
11 1
.names a[2] b[0] s_CSAwallace_cla4_and_2_0
11 1
.names a[3] b[0] s_CSAwallace_cla4_nand_3_0
0- 1
-0 1
.names a[0] b[1] s_CSAwallace_cla4_and_0_1
11 1
.names a[1] b[1] s_CSAwallace_cla4_and_1_1
11 1
.names a[2] b[1] s_CSAwallace_cla4_and_2_1
11 1
.names a[3] b[1] s_CSAwallace_cla4_nand_3_1
0- 1
-0 1
.names a[0] b[2] s_CSAwallace_cla4_and_0_2
11 1
.names a[1] b[2] s_CSAwallace_cla4_and_1_2
11 1
.names a[2] b[2] s_CSAwallace_cla4_and_2_2
11 1
.names a[3] b[2] s_CSAwallace_cla4_nand_3_2
0- 1
-0 1
.names a[0] b[3] s_CSAwallace_cla4_nand_0_3
0- 1
-0 1
.names a[1] b[3] s_CSAwallace_cla4_nand_1_3
0- 1
-0 1
.names a[2] b[3] s_CSAwallace_cla4_nand_2_3
0- 1
-0 1
.names a[3] b[3] s_CSAwallace_cla4_and_3_3
11 1
.names s_CSAwallace_cla4_and_1_0 s_CSAwallace_cla4_and_0_1 s_CSAwallace_cla4_csa0_csa_component_fa1_xor0
01 1
10 1
.names s_CSAwallace_cla4_and_1_0 s_CSAwallace_cla4_and_0_1 s_CSAwallace_cla4_csa0_csa_component_fa1_and0
11 1
.names s_CSAwallace_cla4_and_2_0 s_CSAwallace_cla4_and_1_1 s_CSAwallace_cla4_csa0_csa_component_fa2_xor0
01 1
10 1
.names s_CSAwallace_cla4_and_2_0 s_CSAwallace_cla4_and_1_1 s_CSAwallace_cla4_csa0_csa_component_fa2_and0
11 1
.names s_CSAwallace_cla4_csa0_csa_component_fa2_xor0 s_CSAwallace_cla4_and_0_2 s_CSAwallace_cla4_csa0_csa_component_fa2_xor1
01 1
10 1
.names s_CSAwallace_cla4_csa0_csa_component_fa2_xor0 s_CSAwallace_cla4_and_0_2 s_CSAwallace_cla4_csa0_csa_component_fa2_and1
11 1
.names s_CSAwallace_cla4_csa0_csa_component_fa2_and0 s_CSAwallace_cla4_csa0_csa_component_fa2_and1 s_CSAwallace_cla4_csa0_csa_component_fa2_or0
1- 1
-1 1
.names s_CSAwallace_cla4_nand_3_0 s_CSAwallace_cla4_and_2_1 s_CSAwallace_cla4_csa0_csa_component_fa3_xor0
01 1
10 1
.names s_CSAwallace_cla4_nand_3_0 s_CSAwallace_cla4_and_2_1 s_CSAwallace_cla4_csa0_csa_component_fa3_and0
11 1
.names s_CSAwallace_cla4_csa0_csa_component_fa3_xor0 s_CSAwallace_cla4_and_1_2 s_CSAwallace_cla4_csa0_csa_component_fa3_xor1
01 1
10 1
.names s_CSAwallace_cla4_csa0_csa_component_fa3_xor0 s_CSAwallace_cla4_and_1_2 s_CSAwallace_cla4_csa0_csa_component_fa3_and1
11 1
.names s_CSAwallace_cla4_csa0_csa_component_fa3_and0 s_CSAwallace_cla4_csa0_csa_component_fa3_and1 s_CSAwallace_cla4_csa0_csa_component_fa3_or0
1- 1
-1 1
.names s_CSAwallace_cla4_nand_3_1 s_CSAwallace_cla4_csa0_csa_component_fa4_xor0
0 1
.names s_CSAwallace_cla4_csa0_csa_component_fa4_xor0 s_CSAwallace_cla4_and_2_2 s_CSAwallace_cla4_csa0_csa_component_fa4_xor1
01 1
10 1
.names s_CSAwallace_cla4_csa0_csa_component_fa4_xor0 s_CSAwallace_cla4_and_2_2 s_CSAwallace_cla4_csa0_csa_component_fa4_and1
11 1
.names s_CSAwallace_cla4_nand_3_1 s_CSAwallace_cla4_csa0_csa_component_fa4_and1 s_CSAwallace_cla4_csa0_csa_component_fa4_or0
1- 1
-1 1
.names s_CSAwallace_cla4_csa0_csa_component_fa2_xor1 s_CSAwallace_cla4_csa0_csa_component_fa1_and0 s_CSAwallace_cla4_csa1_csa_component_fa2_xor0
01 1
10 1
.names s_CSAwallace_cla4_csa0_csa_component_fa2_xor1 s_CSAwallace_cla4_csa0_csa_component_fa1_and0 s_CSAwallace_cla4_csa1_csa_component_fa2_and0
11 1
.names s_CSAwallace_cla4_csa0_csa_component_fa3_xor1 s_CSAwallace_cla4_csa0_csa_component_fa2_or0 s_CSAwallace_cla4_csa1_csa_component_fa3_xor0
01 1
10 1
.names s_CSAwallace_cla4_csa0_csa_component_fa3_xor1 s_CSAwallace_cla4_csa0_csa_component_fa2_or0 s_CSAwallace_cla4_csa1_csa_component_fa3_and0
11 1
.names s_CSAwallace_cla4_csa1_csa_component_fa3_xor0 s_CSAwallace_cla4_nand_0_3 s_CSAwallace_cla4_csa1_csa_component_fa3_xor1
01 1
10 1
.names s_CSAwallace_cla4_csa1_csa_component_fa3_xor0 s_CSAwallace_cla4_nand_0_3 s_CSAwallace_cla4_csa1_csa_component_fa3_and1
11 1
.names s_CSAwallace_cla4_csa1_csa_component_fa3_and0 s_CSAwallace_cla4_csa1_csa_component_fa3_and1 s_CSAwallace_cla4_csa1_csa_component_fa3_or0
1- 1
-1 1
.names s_CSAwallace_cla4_csa0_csa_component_fa4_xor1 s_CSAwallace_cla4_csa0_csa_component_fa3_or0 s_CSAwallace_cla4_csa1_csa_component_fa4_xor0
01 1
10 1
.names s_CSAwallace_cla4_csa0_csa_component_fa4_xor1 s_CSAwallace_cla4_csa0_csa_component_fa3_or0 s_CSAwallace_cla4_csa1_csa_component_fa4_and0
11 1
.names s_CSAwallace_cla4_csa1_csa_component_fa4_xor0 s_CSAwallace_cla4_nand_1_3 s_CSAwallace_cla4_csa1_csa_component_fa4_xor1
01 1
10 1
.names s_CSAwallace_cla4_csa1_csa_component_fa4_xor0 s_CSAwallace_cla4_nand_1_3 s_CSAwallace_cla4_csa1_csa_component_fa4_and1
11 1
.names s_CSAwallace_cla4_csa1_csa_component_fa4_and0 s_CSAwallace_cla4_csa1_csa_component_fa4_and1 s_CSAwallace_cla4_csa1_csa_component_fa4_or0
1- 1
-1 1
.names s_CSAwallace_cla4_nand_3_2 s_CSAwallace_cla4_csa0_csa_component_fa4_or0 s_CSAwallace_cla4_csa1_csa_component_fa5_xor0
01 1
10 1
.names s_CSAwallace_cla4_nand_3_2 s_CSAwallace_cla4_csa0_csa_component_fa4_or0 s_CSAwallace_cla4_csa1_csa_component_fa5_and0
11 1
.names s_CSAwallace_cla4_csa1_csa_component_fa5_xor0 s_CSAwallace_cla4_nand_2_3 s_CSAwallace_cla4_csa1_csa_component_fa5_xor1
01 1
10 1
.names s_CSAwallace_cla4_csa1_csa_component_fa5_xor0 s_CSAwallace_cla4_nand_2_3 s_CSAwallace_cla4_csa1_csa_component_fa5_and1
11 1
.names s_CSAwallace_cla4_csa1_csa_component_fa5_and0 s_CSAwallace_cla4_csa1_csa_component_fa5_and1 s_CSAwallace_cla4_csa1_csa_component_fa5_or0
1- 1
-1 1
.names s_CSAwallace_cla4_csa1_csa_component_fa2_xor0 s_CSAwallace_cla4_and_0_0 s_CSAwallace_cla4_u_cla8_and0
11 1
.names s_CSAwallace_cla4_csa1_csa_component_fa3_xor1 s_CSAwallace_cla4_csa1_csa_component_fa2_and0 s_CSAwallace_cla4_u_cla8_pg_logic3_or0
1- 1
-1 1
.names s_CSAwallace_cla4_csa1_csa_component_fa3_xor1 s_CSAwallace_cla4_csa1_csa_component_fa2_and0 s_CSAwallace_cla4_u_cla8_pg_logic3_and0
11 1
.names s_CSAwallace_cla4_csa1_csa_component_fa3_xor1 s_CSAwallace_cla4_csa1_csa_component_fa2_and0 s_CSAwallace_cla4_u_cla8_pg_logic3_xor0
01 1
10 1
.names s_CSAwallace_cla4_u_cla8_pg_logic3_or0 s_CSAwallace_cla4_csa0_csa_component_fa1_xor0 s_CSAwallace_cla4_u_cla8_and1
11 1
.names s_CSAwallace_cla4_u_cla8_pg_logic3_or0 s_CSAwallace_cla4_csa0_csa_component_fa1_xor0 s_CSAwallace_cla4_u_cla8_and2
11 1
.names s_CSAwallace_cla4_csa1_csa_component_fa4_xor1 s_CSAwallace_cla4_csa1_csa_component_fa3_or0 s_CSAwallace_cla4_u_cla8_pg_logic4_or0
1- 1
-1 1
.names s_CSAwallace_cla4_csa1_csa_component_fa4_xor1 s_CSAwallace_cla4_csa1_csa_component_fa3_or0 s_CSAwallace_cla4_u_cla8_pg_logic4_and0
11 1
.names s_CSAwallace_cla4_csa1_csa_component_fa4_xor1 s_CSAwallace_cla4_csa1_csa_component_fa3_or0 s_CSAwallace_cla4_u_cla8_pg_logic4_xor0
01 1
10 1
.names s_CSAwallace_cla4_u_cla8_pg_logic4_xor0 s_CSAwallace_cla4_u_cla8_pg_logic3_and0 s_CSAwallace_cla4_u_cla8_xor4
01 1
10 1
.names s_CSAwallace_cla4_u_cla8_pg_logic3_and0 s_CSAwallace_cla4_u_cla8_pg_logic4_or0 s_CSAwallace_cla4_u_cla8_and3
11 1
.names s_CSAwallace_cla4_u_cla8_pg_logic4_and0 s_CSAwallace_cla4_u_cla8_and3 s_CSAwallace_cla4_u_cla8_or0
1- 1
-1 1
.names s_CSAwallace_cla4_csa1_csa_component_fa5_xor1 s_CSAwallace_cla4_csa1_csa_component_fa4_or0 s_CSAwallace_cla4_u_cla8_pg_logic5_or0
1- 1
-1 1
.names s_CSAwallace_cla4_csa1_csa_component_fa5_xor1 s_CSAwallace_cla4_csa1_csa_component_fa4_or0 s_CSAwallace_cla4_u_cla8_pg_logic5_and0
11 1
.names s_CSAwallace_cla4_csa1_csa_component_fa5_xor1 s_CSAwallace_cla4_csa1_csa_component_fa4_or0 s_CSAwallace_cla4_u_cla8_pg_logic5_xor0
01 1
10 1
.names s_CSAwallace_cla4_u_cla8_pg_logic5_xor0 s_CSAwallace_cla4_u_cla8_or0 s_CSAwallace_cla4_u_cla8_xor5
01 1
10 1
.names s_CSAwallace_cla4_u_cla8_pg_logic3_and0 s_CSAwallace_cla4_u_cla8_pg_logic5_or0 s_CSAwallace_cla4_u_cla8_and4
11 1
.names s_CSAwallace_cla4_u_cla8_and4 s_CSAwallace_cla4_u_cla8_pg_logic4_or0 s_CSAwallace_cla4_u_cla8_and5
11 1
.names s_CSAwallace_cla4_u_cla8_pg_logic4_and0 s_CSAwallace_cla4_u_cla8_pg_logic5_or0 s_CSAwallace_cla4_u_cla8_and6
11 1
.names s_CSAwallace_cla4_u_cla8_and5 s_CSAwallace_cla4_u_cla8_and6 s_CSAwallace_cla4_u_cla8_or1
1- 1
-1 1
.names s_CSAwallace_cla4_u_cla8_pg_logic5_and0 s_CSAwallace_cla4_u_cla8_or1 s_CSAwallace_cla4_u_cla8_or2
1- 1
-1 1
.names s_CSAwallace_cla4_and_3_3 s_CSAwallace_cla4_csa1_csa_component_fa5_or0 s_CSAwallace_cla4_u_cla8_pg_logic6_or0
1- 1
-1 1
.names s_CSAwallace_cla4_and_3_3 s_CSAwallace_cla4_csa1_csa_component_fa5_or0 s_CSAwallace_cla4_u_cla8_pg_logic6_and0
11 1
.names s_CSAwallace_cla4_and_3_3 s_CSAwallace_cla4_csa1_csa_component_fa5_or0 s_CSAwallace_cla4_u_cla8_pg_logic6_xor0
01 1
10 1
.names s_CSAwallace_cla4_u_cla8_pg_logic6_xor0 s_CSAwallace_cla4_u_cla8_or2 s_CSAwallace_cla4_u_cla8_xor6
01 1
10 1
.names s_CSAwallace_cla4_u_cla8_pg_logic3_and0 s_CSAwallace_cla4_u_cla8_pg_logic5_or0 s_CSAwallace_cla4_u_cla8_and7
11 1
.names s_CSAwallace_cla4_u_cla8_pg_logic6_or0 s_CSAwallace_cla4_u_cla8_pg_logic4_or0 s_CSAwallace_cla4_u_cla8_and8
11 1
.names s_CSAwallace_cla4_u_cla8_and7 s_CSAwallace_cla4_u_cla8_and8 s_CSAwallace_cla4_u_cla8_and9
11 1
.names s_CSAwallace_cla4_u_cla8_pg_logic4_and0 s_CSAwallace_cla4_u_cla8_pg_logic6_or0 s_CSAwallace_cla4_u_cla8_and10
11 1
.names s_CSAwallace_cla4_u_cla8_and10 s_CSAwallace_cla4_u_cla8_pg_logic5_or0 s_CSAwallace_cla4_u_cla8_and11
11 1
.names s_CSAwallace_cla4_u_cla8_pg_logic5_and0 s_CSAwallace_cla4_u_cla8_pg_logic6_or0 s_CSAwallace_cla4_u_cla8_and12
11 1
.names s_CSAwallace_cla4_u_cla8_and9 s_CSAwallace_cla4_u_cla8_and11 s_CSAwallace_cla4_u_cla8_or3
1- 1
-1 1
.names s_CSAwallace_cla4_u_cla8_or3 s_CSAwallace_cla4_u_cla8_and12 s_CSAwallace_cla4_u_cla8_or4
1- 1
-1 1
.names s_CSAwallace_cla4_u_cla8_pg_logic6_and0 s_CSAwallace_cla4_u_cla8_or4 s_CSAwallace_cla4_u_cla8_or5
1- 1
-1 1
.names s_CSAwallace_cla4_u_cla8_pg_logic3_and0 s_CSAwallace_cla4_u_cla8_pg_logic6_or0 s_CSAwallace_cla4_u_cla8_and13
11 1
.names s_CSAwallace_cla4_u_cla8_and13 s_CSAwallace_cla4_u_cla8_pg_logic5_or0 s_CSAwallace_cla4_u_cla8_and14
11 1
.names s_CSAwallace_cla4_u_cla8_and14 s_CSAwallace_cla4_u_cla8_pg_logic4_or0 s_CSAwallace_cla4_u_cla8_and15
11 1
.names s_CSAwallace_cla4_u_cla8_pg_logic4_and0 s_CSAwallace_cla4_u_cla8_pg_logic6_or0 s_CSAwallace_cla4_u_cla8_and16
11 1
.names s_CSAwallace_cla4_u_cla8_and16 s_CSAwallace_cla4_u_cla8_pg_logic5_or0 s_CSAwallace_cla4_u_cla8_and17
11 1
.names s_CSAwallace_cla4_u_cla8_pg_logic5_and0 s_CSAwallace_cla4_u_cla8_pg_logic6_or0 s_CSAwallace_cla4_u_cla8_and18
11 1
.names s_CSAwallace_cla4_u_cla8_and15 s_CSAwallace_cla4_u_cla8_and18 s_CSAwallace_cla4_u_cla8_or6
1- 1
-1 1
.names s_CSAwallace_cla4_u_cla8_and17 s_CSAwallace_cla4_u_cla8_pg_logic6_and0 s_CSAwallace_cla4_u_cla8_or7
1- 1
-1 1
.names s_CSAwallace_cla4_u_cla8_or6 s_CSAwallace_cla4_u_cla8_or7 s_CSAwallace_cla4_u_cla8_or8
1- 1
-1 1
.names s_CSAwallace_cla4_u_cla8_or5 s_CSAwallace_cla4_xor0
0 1
.names s_CSAwallace_cla4_and_0_0 s_CSAwallace_cla4_out[0]
1 1
.names s_CSAwallace_cla4_csa0_csa_component_fa1_xor0 s_CSAwallace_cla4_out[1]
1 1
.names s_CSAwallace_cla4_csa1_csa_component_fa2_xor0 s_CSAwallace_cla4_out[2]
1 1
.names s_CSAwallace_cla4_u_cla8_pg_logic3_xor0 s_CSAwallace_cla4_out[3]
1 1
.names s_CSAwallace_cla4_u_cla8_xor4 s_CSAwallace_cla4_out[4]
1 1
.names s_CSAwallace_cla4_u_cla8_xor5 s_CSAwallace_cla4_out[5]
1 1
.names s_CSAwallace_cla4_u_cla8_xor6 s_CSAwallace_cla4_out[6]
1 1
.names s_CSAwallace_cla4_xor0 s_CSAwallace_cla4_out[7]
1 1
.end