.model u_wallace_cska16
.inputs a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] a[8] a[9] a[10] a[11] a[12] a[13] a[14] a[15] b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9] b[10] b[11] b[12] b[13] b[14] b[15]
.outputs u_wallace_cska16_out[0] u_wallace_cska16_out[1] u_wallace_cska16_out[2] u_wallace_cska16_out[3] u_wallace_cska16_out[4] u_wallace_cska16_out[5] u_wallace_cska16_out[6] u_wallace_cska16_out[7] u_wallace_cska16_out[8] u_wallace_cska16_out[9] u_wallace_cska16_out[10] u_wallace_cska16_out[11] u_wallace_cska16_out[12] u_wallace_cska16_out[13] u_wallace_cska16_out[14] u_wallace_cska16_out[15] u_wallace_cska16_out[16] u_wallace_cska16_out[17] u_wallace_cska16_out[18] u_wallace_cska16_out[19] u_wallace_cska16_out[20] u_wallace_cska16_out[21] u_wallace_cska16_out[22] u_wallace_cska16_out[23] u_wallace_cska16_out[24] u_wallace_cska16_out[25] u_wallace_cska16_out[26] u_wallace_cska16_out[27] u_wallace_cska16_out[28] u_wallace_cska16_out[29] u_wallace_cska16_out[30] u_wallace_cska16_out[31]
.names vdd
1
.names gnd
0
.subckt and_gate a=a[2] b=b[0] out=u_wallace_cska16_and_2_0
.subckt and_gate a=a[1] b=b[1] out=u_wallace_cska16_and_1_1
.subckt ha a=u_wallace_cska16_and_2_0 b=u_wallace_cska16_and_1_1 ha_xor0=u_wallace_cska16_ha0_xor0 ha_and0=u_wallace_cska16_ha0_and0
.subckt and_gate a=a[3] b=b[0] out=u_wallace_cska16_and_3_0
.subckt and_gate a=a[2] b=b[1] out=u_wallace_cska16_and_2_1
.subckt fa a=u_wallace_cska16_ha0_and0 b=u_wallace_cska16_and_3_0 cin=u_wallace_cska16_and_2_1 fa_xor1=u_wallace_cska16_fa0_xor1 fa_or0=u_wallace_cska16_fa0_or0
.subckt and_gate a=a[4] b=b[0] out=u_wallace_cska16_and_4_0
.subckt and_gate a=a[3] b=b[1] out=u_wallace_cska16_and_3_1
.subckt fa a=u_wallace_cska16_fa0_or0 b=u_wallace_cska16_and_4_0 cin=u_wallace_cska16_and_3_1 fa_xor1=u_wallace_cska16_fa1_xor1 fa_or0=u_wallace_cska16_fa1_or0
.subckt and_gate a=a[5] b=b[0] out=u_wallace_cska16_and_5_0
.subckt and_gate a=a[4] b=b[1] out=u_wallace_cska16_and_4_1
.subckt fa a=u_wallace_cska16_fa1_or0 b=u_wallace_cska16_and_5_0 cin=u_wallace_cska16_and_4_1 fa_xor1=u_wallace_cska16_fa2_xor1 fa_or0=u_wallace_cska16_fa2_or0
.subckt and_gate a=a[6] b=b[0] out=u_wallace_cska16_and_6_0
.subckt and_gate a=a[5] b=b[1] out=u_wallace_cska16_and_5_1
.subckt fa a=u_wallace_cska16_fa2_or0 b=u_wallace_cska16_and_6_0 cin=u_wallace_cska16_and_5_1 fa_xor1=u_wallace_cska16_fa3_xor1 fa_or0=u_wallace_cska16_fa3_or0
.subckt and_gate a=a[7] b=b[0] out=u_wallace_cska16_and_7_0
.subckt and_gate a=a[6] b=b[1] out=u_wallace_cska16_and_6_1
.subckt fa a=u_wallace_cska16_fa3_or0 b=u_wallace_cska16_and_7_0 cin=u_wallace_cska16_and_6_1 fa_xor1=u_wallace_cska16_fa4_xor1 fa_or0=u_wallace_cska16_fa4_or0
.subckt and_gate a=a[8] b=b[0] out=u_wallace_cska16_and_8_0
.subckt and_gate a=a[7] b=b[1] out=u_wallace_cska16_and_7_1
.subckt fa a=u_wallace_cska16_fa4_or0 b=u_wallace_cska16_and_8_0 cin=u_wallace_cska16_and_7_1 fa_xor1=u_wallace_cska16_fa5_xor1 fa_or0=u_wallace_cska16_fa5_or0
.subckt and_gate a=a[9] b=b[0] out=u_wallace_cska16_and_9_0
.subckt and_gate a=a[8] b=b[1] out=u_wallace_cska16_and_8_1
.subckt fa a=u_wallace_cska16_fa5_or0 b=u_wallace_cska16_and_9_0 cin=u_wallace_cska16_and_8_1 fa_xor1=u_wallace_cska16_fa6_xor1 fa_or0=u_wallace_cska16_fa6_or0
.subckt and_gate a=a[10] b=b[0] out=u_wallace_cska16_and_10_0
.subckt and_gate a=a[9] b=b[1] out=u_wallace_cska16_and_9_1
.subckt fa a=u_wallace_cska16_fa6_or0 b=u_wallace_cska16_and_10_0 cin=u_wallace_cska16_and_9_1 fa_xor1=u_wallace_cska16_fa7_xor1 fa_or0=u_wallace_cska16_fa7_or0
.subckt and_gate a=a[11] b=b[0] out=u_wallace_cska16_and_11_0
.subckt and_gate a=a[10] b=b[1] out=u_wallace_cska16_and_10_1
.subckt fa a=u_wallace_cska16_fa7_or0 b=u_wallace_cska16_and_11_0 cin=u_wallace_cska16_and_10_1 fa_xor1=u_wallace_cska16_fa8_xor1 fa_or0=u_wallace_cska16_fa8_or0
.subckt and_gate a=a[12] b=b[0] out=u_wallace_cska16_and_12_0
.subckt and_gate a=a[11] b=b[1] out=u_wallace_cska16_and_11_1
.subckt fa a=u_wallace_cska16_fa8_or0 b=u_wallace_cska16_and_12_0 cin=u_wallace_cska16_and_11_1 fa_xor1=u_wallace_cska16_fa9_xor1 fa_or0=u_wallace_cska16_fa9_or0
.subckt and_gate a=a[13] b=b[0] out=u_wallace_cska16_and_13_0
.subckt and_gate a=a[12] b=b[1] out=u_wallace_cska16_and_12_1
.subckt fa a=u_wallace_cska16_fa9_or0 b=u_wallace_cska16_and_13_0 cin=u_wallace_cska16_and_12_1 fa_xor1=u_wallace_cska16_fa10_xor1 fa_or0=u_wallace_cska16_fa10_or0
.subckt and_gate a=a[14] b=b[0] out=u_wallace_cska16_and_14_0
.subckt and_gate a=a[13] b=b[1] out=u_wallace_cska16_and_13_1
.subckt fa a=u_wallace_cska16_fa10_or0 b=u_wallace_cska16_and_14_0 cin=u_wallace_cska16_and_13_1 fa_xor1=u_wallace_cska16_fa11_xor1 fa_or0=u_wallace_cska16_fa11_or0
.subckt and_gate a=a[15] b=b[0] out=u_wallace_cska16_and_15_0
.subckt and_gate a=a[14] b=b[1] out=u_wallace_cska16_and_14_1
.subckt fa a=u_wallace_cska16_fa11_or0 b=u_wallace_cska16_and_15_0 cin=u_wallace_cska16_and_14_1 fa_xor1=u_wallace_cska16_fa12_xor1 fa_or0=u_wallace_cska16_fa12_or0
.subckt and_gate a=a[15] b=b[1] out=u_wallace_cska16_and_15_1
.subckt and_gate a=a[14] b=b[2] out=u_wallace_cska16_and_14_2
.subckt fa a=u_wallace_cska16_fa12_or0 b=u_wallace_cska16_and_15_1 cin=u_wallace_cska16_and_14_2 fa_xor1=u_wallace_cska16_fa13_xor1 fa_or0=u_wallace_cska16_fa13_or0
.subckt and_gate a=a[15] b=b[2] out=u_wallace_cska16_and_15_2
.subckt and_gate a=a[14] b=b[3] out=u_wallace_cska16_and_14_3
.subckt fa a=u_wallace_cska16_fa13_or0 b=u_wallace_cska16_and_15_2 cin=u_wallace_cska16_and_14_3 fa_xor1=u_wallace_cska16_fa14_xor1 fa_or0=u_wallace_cska16_fa14_or0
.subckt and_gate a=a[15] b=b[3] out=u_wallace_cska16_and_15_3
.subckt and_gate a=a[14] b=b[4] out=u_wallace_cska16_and_14_4
.subckt fa a=u_wallace_cska16_fa14_or0 b=u_wallace_cska16_and_15_3 cin=u_wallace_cska16_and_14_4 fa_xor1=u_wallace_cska16_fa15_xor1 fa_or0=u_wallace_cska16_fa15_or0
.subckt and_gate a=a[15] b=b[4] out=u_wallace_cska16_and_15_4
.subckt and_gate a=a[14] b=b[5] out=u_wallace_cska16_and_14_5
.subckt fa a=u_wallace_cska16_fa15_or0 b=u_wallace_cska16_and_15_4 cin=u_wallace_cska16_and_14_5 fa_xor1=u_wallace_cska16_fa16_xor1 fa_or0=u_wallace_cska16_fa16_or0
.subckt and_gate a=a[15] b=b[5] out=u_wallace_cska16_and_15_5
.subckt and_gate a=a[14] b=b[6] out=u_wallace_cska16_and_14_6
.subckt fa a=u_wallace_cska16_fa16_or0 b=u_wallace_cska16_and_15_5 cin=u_wallace_cska16_and_14_6 fa_xor1=u_wallace_cska16_fa17_xor1 fa_or0=u_wallace_cska16_fa17_or0
.subckt and_gate a=a[15] b=b[6] out=u_wallace_cska16_and_15_6
.subckt and_gate a=a[14] b=b[7] out=u_wallace_cska16_and_14_7
.subckt fa a=u_wallace_cska16_fa17_or0 b=u_wallace_cska16_and_15_6 cin=u_wallace_cska16_and_14_7 fa_xor1=u_wallace_cska16_fa18_xor1 fa_or0=u_wallace_cska16_fa18_or0
.subckt and_gate a=a[15] b=b[7] out=u_wallace_cska16_and_15_7
.subckt and_gate a=a[14] b=b[8] out=u_wallace_cska16_and_14_8
.subckt fa a=u_wallace_cska16_fa18_or0 b=u_wallace_cska16_and_15_7 cin=u_wallace_cska16_and_14_8 fa_xor1=u_wallace_cska16_fa19_xor1 fa_or0=u_wallace_cska16_fa19_or0
.subckt and_gate a=a[15] b=b[8] out=u_wallace_cska16_and_15_8
.subckt and_gate a=a[14] b=b[9] out=u_wallace_cska16_and_14_9
.subckt fa a=u_wallace_cska16_fa19_or0 b=u_wallace_cska16_and_15_8 cin=u_wallace_cska16_and_14_9 fa_xor1=u_wallace_cska16_fa20_xor1 fa_or0=u_wallace_cska16_fa20_or0
.subckt and_gate a=a[15] b=b[9] out=u_wallace_cska16_and_15_9
.subckt and_gate a=a[14] b=b[10] out=u_wallace_cska16_and_14_10
.subckt fa a=u_wallace_cska16_fa20_or0 b=u_wallace_cska16_and_15_9 cin=u_wallace_cska16_and_14_10 fa_xor1=u_wallace_cska16_fa21_xor1 fa_or0=u_wallace_cska16_fa21_or0
.subckt and_gate a=a[15] b=b[10] out=u_wallace_cska16_and_15_10
.subckt and_gate a=a[14] b=b[11] out=u_wallace_cska16_and_14_11
.subckt fa a=u_wallace_cska16_fa21_or0 b=u_wallace_cska16_and_15_10 cin=u_wallace_cska16_and_14_11 fa_xor1=u_wallace_cska16_fa22_xor1 fa_or0=u_wallace_cska16_fa22_or0
.subckt and_gate a=a[15] b=b[11] out=u_wallace_cska16_and_15_11
.subckt and_gate a=a[14] b=b[12] out=u_wallace_cska16_and_14_12
.subckt fa a=u_wallace_cska16_fa22_or0 b=u_wallace_cska16_and_15_11 cin=u_wallace_cska16_and_14_12 fa_xor1=u_wallace_cska16_fa23_xor1 fa_or0=u_wallace_cska16_fa23_or0
.subckt and_gate a=a[15] b=b[12] out=u_wallace_cska16_and_15_12
.subckt and_gate a=a[14] b=b[13] out=u_wallace_cska16_and_14_13
.subckt fa a=u_wallace_cska16_fa23_or0 b=u_wallace_cska16_and_15_12 cin=u_wallace_cska16_and_14_13 fa_xor1=u_wallace_cska16_fa24_xor1 fa_or0=u_wallace_cska16_fa24_or0
.subckt and_gate a=a[15] b=b[13] out=u_wallace_cska16_and_15_13
.subckt and_gate a=a[14] b=b[14] out=u_wallace_cska16_and_14_14
.subckt fa a=u_wallace_cska16_fa24_or0 b=u_wallace_cska16_and_15_13 cin=u_wallace_cska16_and_14_14 fa_xor1=u_wallace_cska16_fa25_xor1 fa_or0=u_wallace_cska16_fa25_or0
.subckt and_gate a=a[1] b=b[2] out=u_wallace_cska16_and_1_2
.subckt and_gate a=a[0] b=b[3] out=u_wallace_cska16_and_0_3
.subckt ha a=u_wallace_cska16_and_1_2 b=u_wallace_cska16_and_0_3 ha_xor0=u_wallace_cska16_ha1_xor0 ha_and0=u_wallace_cska16_ha1_and0
.subckt and_gate a=a[2] b=b[2] out=u_wallace_cska16_and_2_2
.subckt and_gate a=a[1] b=b[3] out=u_wallace_cska16_and_1_3
.subckt fa a=u_wallace_cska16_ha1_and0 b=u_wallace_cska16_and_2_2 cin=u_wallace_cska16_and_1_3 fa_xor1=u_wallace_cska16_fa26_xor1 fa_or0=u_wallace_cska16_fa26_or0
.subckt and_gate a=a[3] b=b[2] out=u_wallace_cska16_and_3_2
.subckt and_gate a=a[2] b=b[3] out=u_wallace_cska16_and_2_3
.subckt fa a=u_wallace_cska16_fa26_or0 b=u_wallace_cska16_and_3_2 cin=u_wallace_cska16_and_2_3 fa_xor1=u_wallace_cska16_fa27_xor1 fa_or0=u_wallace_cska16_fa27_or0
.subckt and_gate a=a[4] b=b[2] out=u_wallace_cska16_and_4_2
.subckt and_gate a=a[3] b=b[3] out=u_wallace_cska16_and_3_3
.subckt fa a=u_wallace_cska16_fa27_or0 b=u_wallace_cska16_and_4_2 cin=u_wallace_cska16_and_3_3 fa_xor1=u_wallace_cska16_fa28_xor1 fa_or0=u_wallace_cska16_fa28_or0
.subckt and_gate a=a[5] b=b[2] out=u_wallace_cska16_and_5_2
.subckt and_gate a=a[4] b=b[3] out=u_wallace_cska16_and_4_3
.subckt fa a=u_wallace_cska16_fa28_or0 b=u_wallace_cska16_and_5_2 cin=u_wallace_cska16_and_4_3 fa_xor1=u_wallace_cska16_fa29_xor1 fa_or0=u_wallace_cska16_fa29_or0
.subckt and_gate a=a[6] b=b[2] out=u_wallace_cska16_and_6_2
.subckt and_gate a=a[5] b=b[3] out=u_wallace_cska16_and_5_3
.subckt fa a=u_wallace_cska16_fa29_or0 b=u_wallace_cska16_and_6_2 cin=u_wallace_cska16_and_5_3 fa_xor1=u_wallace_cska16_fa30_xor1 fa_or0=u_wallace_cska16_fa30_or0
.subckt and_gate a=a[7] b=b[2] out=u_wallace_cska16_and_7_2
.subckt and_gate a=a[6] b=b[3] out=u_wallace_cska16_and_6_3
.subckt fa a=u_wallace_cska16_fa30_or0 b=u_wallace_cska16_and_7_2 cin=u_wallace_cska16_and_6_3 fa_xor1=u_wallace_cska16_fa31_xor1 fa_or0=u_wallace_cska16_fa31_or0
.subckt and_gate a=a[8] b=b[2] out=u_wallace_cska16_and_8_2
.subckt and_gate a=a[7] b=b[3] out=u_wallace_cska16_and_7_3
.subckt fa a=u_wallace_cska16_fa31_or0 b=u_wallace_cska16_and_8_2 cin=u_wallace_cska16_and_7_3 fa_xor1=u_wallace_cska16_fa32_xor1 fa_or0=u_wallace_cska16_fa32_or0
.subckt and_gate a=a[9] b=b[2] out=u_wallace_cska16_and_9_2
.subckt and_gate a=a[8] b=b[3] out=u_wallace_cska16_and_8_3
.subckt fa a=u_wallace_cska16_fa32_or0 b=u_wallace_cska16_and_9_2 cin=u_wallace_cska16_and_8_3 fa_xor1=u_wallace_cska16_fa33_xor1 fa_or0=u_wallace_cska16_fa33_or0
.subckt and_gate a=a[10] b=b[2] out=u_wallace_cska16_and_10_2
.subckt and_gate a=a[9] b=b[3] out=u_wallace_cska16_and_9_3
.subckt fa a=u_wallace_cska16_fa33_or0 b=u_wallace_cska16_and_10_2 cin=u_wallace_cska16_and_9_3 fa_xor1=u_wallace_cska16_fa34_xor1 fa_or0=u_wallace_cska16_fa34_or0
.subckt and_gate a=a[11] b=b[2] out=u_wallace_cska16_and_11_2
.subckt and_gate a=a[10] b=b[3] out=u_wallace_cska16_and_10_3
.subckt fa a=u_wallace_cska16_fa34_or0 b=u_wallace_cska16_and_11_2 cin=u_wallace_cska16_and_10_3 fa_xor1=u_wallace_cska16_fa35_xor1 fa_or0=u_wallace_cska16_fa35_or0
.subckt and_gate a=a[12] b=b[2] out=u_wallace_cska16_and_12_2
.subckt and_gate a=a[11] b=b[3] out=u_wallace_cska16_and_11_3
.subckt fa a=u_wallace_cska16_fa35_or0 b=u_wallace_cska16_and_12_2 cin=u_wallace_cska16_and_11_3 fa_xor1=u_wallace_cska16_fa36_xor1 fa_or0=u_wallace_cska16_fa36_or0
.subckt and_gate a=a[13] b=b[2] out=u_wallace_cska16_and_13_2
.subckt and_gate a=a[12] b=b[3] out=u_wallace_cska16_and_12_3
.subckt fa a=u_wallace_cska16_fa36_or0 b=u_wallace_cska16_and_13_2 cin=u_wallace_cska16_and_12_3 fa_xor1=u_wallace_cska16_fa37_xor1 fa_or0=u_wallace_cska16_fa37_or0
.subckt and_gate a=a[13] b=b[3] out=u_wallace_cska16_and_13_3
.subckt and_gate a=a[12] b=b[4] out=u_wallace_cska16_and_12_4
.subckt fa a=u_wallace_cska16_fa37_or0 b=u_wallace_cska16_and_13_3 cin=u_wallace_cska16_and_12_4 fa_xor1=u_wallace_cska16_fa38_xor1 fa_or0=u_wallace_cska16_fa38_or0
.subckt and_gate a=a[13] b=b[4] out=u_wallace_cska16_and_13_4
.subckt and_gate a=a[12] b=b[5] out=u_wallace_cska16_and_12_5
.subckt fa a=u_wallace_cska16_fa38_or0 b=u_wallace_cska16_and_13_4 cin=u_wallace_cska16_and_12_5 fa_xor1=u_wallace_cska16_fa39_xor1 fa_or0=u_wallace_cska16_fa39_or0
.subckt and_gate a=a[13] b=b[5] out=u_wallace_cska16_and_13_5
.subckt and_gate a=a[12] b=b[6] out=u_wallace_cska16_and_12_6
.subckt fa a=u_wallace_cska16_fa39_or0 b=u_wallace_cska16_and_13_5 cin=u_wallace_cska16_and_12_6 fa_xor1=u_wallace_cska16_fa40_xor1 fa_or0=u_wallace_cska16_fa40_or0
.subckt and_gate a=a[13] b=b[6] out=u_wallace_cska16_and_13_6
.subckt and_gate a=a[12] b=b[7] out=u_wallace_cska16_and_12_7
.subckt fa a=u_wallace_cska16_fa40_or0 b=u_wallace_cska16_and_13_6 cin=u_wallace_cska16_and_12_7 fa_xor1=u_wallace_cska16_fa41_xor1 fa_or0=u_wallace_cska16_fa41_or0
.subckt and_gate a=a[13] b=b[7] out=u_wallace_cska16_and_13_7
.subckt and_gate a=a[12] b=b[8] out=u_wallace_cska16_and_12_8
.subckt fa a=u_wallace_cska16_fa41_or0 b=u_wallace_cska16_and_13_7 cin=u_wallace_cska16_and_12_8 fa_xor1=u_wallace_cska16_fa42_xor1 fa_or0=u_wallace_cska16_fa42_or0
.subckt and_gate a=a[13] b=b[8] out=u_wallace_cska16_and_13_8
.subckt and_gate a=a[12] b=b[9] out=u_wallace_cska16_and_12_9
.subckt fa a=u_wallace_cska16_fa42_or0 b=u_wallace_cska16_and_13_8 cin=u_wallace_cska16_and_12_9 fa_xor1=u_wallace_cska16_fa43_xor1 fa_or0=u_wallace_cska16_fa43_or0
.subckt and_gate a=a[13] b=b[9] out=u_wallace_cska16_and_13_9
.subckt and_gate a=a[12] b=b[10] out=u_wallace_cska16_and_12_10
.subckt fa a=u_wallace_cska16_fa43_or0 b=u_wallace_cska16_and_13_9 cin=u_wallace_cska16_and_12_10 fa_xor1=u_wallace_cska16_fa44_xor1 fa_or0=u_wallace_cska16_fa44_or0
.subckt and_gate a=a[13] b=b[10] out=u_wallace_cska16_and_13_10
.subckt and_gate a=a[12] b=b[11] out=u_wallace_cska16_and_12_11
.subckt fa a=u_wallace_cska16_fa44_or0 b=u_wallace_cska16_and_13_10 cin=u_wallace_cska16_and_12_11 fa_xor1=u_wallace_cska16_fa45_xor1 fa_or0=u_wallace_cska16_fa45_or0
.subckt and_gate a=a[13] b=b[11] out=u_wallace_cska16_and_13_11
.subckt and_gate a=a[12] b=b[12] out=u_wallace_cska16_and_12_12
.subckt fa a=u_wallace_cska16_fa45_or0 b=u_wallace_cska16_and_13_11 cin=u_wallace_cska16_and_12_12 fa_xor1=u_wallace_cska16_fa46_xor1 fa_or0=u_wallace_cska16_fa46_or0
.subckt and_gate a=a[13] b=b[12] out=u_wallace_cska16_and_13_12
.subckt and_gate a=a[12] b=b[13] out=u_wallace_cska16_and_12_13
.subckt fa a=u_wallace_cska16_fa46_or0 b=u_wallace_cska16_and_13_12 cin=u_wallace_cska16_and_12_13 fa_xor1=u_wallace_cska16_fa47_xor1 fa_or0=u_wallace_cska16_fa47_or0
.subckt and_gate a=a[13] b=b[13] out=u_wallace_cska16_and_13_13
.subckt and_gate a=a[12] b=b[14] out=u_wallace_cska16_and_12_14
.subckt fa a=u_wallace_cska16_fa47_or0 b=u_wallace_cska16_and_13_13 cin=u_wallace_cska16_and_12_14 fa_xor1=u_wallace_cska16_fa48_xor1 fa_or0=u_wallace_cska16_fa48_or0
.subckt and_gate a=a[13] b=b[14] out=u_wallace_cska16_and_13_14
.subckt and_gate a=a[12] b=b[15] out=u_wallace_cska16_and_12_15
.subckt fa a=u_wallace_cska16_fa48_or0 b=u_wallace_cska16_and_13_14 cin=u_wallace_cska16_and_12_15 fa_xor1=u_wallace_cska16_fa49_xor1 fa_or0=u_wallace_cska16_fa49_or0
.subckt and_gate a=a[0] b=b[4] out=u_wallace_cska16_and_0_4
.subckt ha a=u_wallace_cska16_and_0_4 b=u_wallace_cska16_fa1_xor1 ha_xor0=u_wallace_cska16_ha2_xor0 ha_and0=u_wallace_cska16_ha2_and0
.subckt and_gate a=a[1] b=b[4] out=u_wallace_cska16_and_1_4
.subckt and_gate a=a[0] b=b[5] out=u_wallace_cska16_and_0_5
.subckt fa a=u_wallace_cska16_ha2_and0 b=u_wallace_cska16_and_1_4 cin=u_wallace_cska16_and_0_5 fa_xor1=u_wallace_cska16_fa50_xor1 fa_or0=u_wallace_cska16_fa50_or0
.subckt and_gate a=a[2] b=b[4] out=u_wallace_cska16_and_2_4
.subckt and_gate a=a[1] b=b[5] out=u_wallace_cska16_and_1_5
.subckt fa a=u_wallace_cska16_fa50_or0 b=u_wallace_cska16_and_2_4 cin=u_wallace_cska16_and_1_5 fa_xor1=u_wallace_cska16_fa51_xor1 fa_or0=u_wallace_cska16_fa51_or0
.subckt and_gate a=a[3] b=b[4] out=u_wallace_cska16_and_3_4
.subckt and_gate a=a[2] b=b[5] out=u_wallace_cska16_and_2_5
.subckt fa a=u_wallace_cska16_fa51_or0 b=u_wallace_cska16_and_3_4 cin=u_wallace_cska16_and_2_5 fa_xor1=u_wallace_cska16_fa52_xor1 fa_or0=u_wallace_cska16_fa52_or0
.subckt and_gate a=a[4] b=b[4] out=u_wallace_cska16_and_4_4
.subckt and_gate a=a[3] b=b[5] out=u_wallace_cska16_and_3_5
.subckt fa a=u_wallace_cska16_fa52_or0 b=u_wallace_cska16_and_4_4 cin=u_wallace_cska16_and_3_5 fa_xor1=u_wallace_cska16_fa53_xor1 fa_or0=u_wallace_cska16_fa53_or0
.subckt and_gate a=a[5] b=b[4] out=u_wallace_cska16_and_5_4
.subckt and_gate a=a[4] b=b[5] out=u_wallace_cska16_and_4_5
.subckt fa a=u_wallace_cska16_fa53_or0 b=u_wallace_cska16_and_5_4 cin=u_wallace_cska16_and_4_5 fa_xor1=u_wallace_cska16_fa54_xor1 fa_or0=u_wallace_cska16_fa54_or0
.subckt and_gate a=a[6] b=b[4] out=u_wallace_cska16_and_6_4
.subckt and_gate a=a[5] b=b[5] out=u_wallace_cska16_and_5_5
.subckt fa a=u_wallace_cska16_fa54_or0 b=u_wallace_cska16_and_6_4 cin=u_wallace_cska16_and_5_5 fa_xor1=u_wallace_cska16_fa55_xor1 fa_or0=u_wallace_cska16_fa55_or0
.subckt and_gate a=a[7] b=b[4] out=u_wallace_cska16_and_7_4
.subckt and_gate a=a[6] b=b[5] out=u_wallace_cska16_and_6_5
.subckt fa a=u_wallace_cska16_fa55_or0 b=u_wallace_cska16_and_7_4 cin=u_wallace_cska16_and_6_5 fa_xor1=u_wallace_cska16_fa56_xor1 fa_or0=u_wallace_cska16_fa56_or0
.subckt and_gate a=a[8] b=b[4] out=u_wallace_cska16_and_8_4
.subckt and_gate a=a[7] b=b[5] out=u_wallace_cska16_and_7_5
.subckt fa a=u_wallace_cska16_fa56_or0 b=u_wallace_cska16_and_8_4 cin=u_wallace_cska16_and_7_5 fa_xor1=u_wallace_cska16_fa57_xor1 fa_or0=u_wallace_cska16_fa57_or0
.subckt and_gate a=a[9] b=b[4] out=u_wallace_cska16_and_9_4
.subckt and_gate a=a[8] b=b[5] out=u_wallace_cska16_and_8_5
.subckt fa a=u_wallace_cska16_fa57_or0 b=u_wallace_cska16_and_9_4 cin=u_wallace_cska16_and_8_5 fa_xor1=u_wallace_cska16_fa58_xor1 fa_or0=u_wallace_cska16_fa58_or0
.subckt and_gate a=a[10] b=b[4] out=u_wallace_cska16_and_10_4
.subckt and_gate a=a[9] b=b[5] out=u_wallace_cska16_and_9_5
.subckt fa a=u_wallace_cska16_fa58_or0 b=u_wallace_cska16_and_10_4 cin=u_wallace_cska16_and_9_5 fa_xor1=u_wallace_cska16_fa59_xor1 fa_or0=u_wallace_cska16_fa59_or0
.subckt and_gate a=a[11] b=b[4] out=u_wallace_cska16_and_11_4
.subckt and_gate a=a[10] b=b[5] out=u_wallace_cska16_and_10_5
.subckt fa a=u_wallace_cska16_fa59_or0 b=u_wallace_cska16_and_11_4 cin=u_wallace_cska16_and_10_5 fa_xor1=u_wallace_cska16_fa60_xor1 fa_or0=u_wallace_cska16_fa60_or0
.subckt and_gate a=a[11] b=b[5] out=u_wallace_cska16_and_11_5
.subckt and_gate a=a[10] b=b[6] out=u_wallace_cska16_and_10_6
.subckt fa a=u_wallace_cska16_fa60_or0 b=u_wallace_cska16_and_11_5 cin=u_wallace_cska16_and_10_6 fa_xor1=u_wallace_cska16_fa61_xor1 fa_or0=u_wallace_cska16_fa61_or0
.subckt and_gate a=a[11] b=b[6] out=u_wallace_cska16_and_11_6
.subckt and_gate a=a[10] b=b[7] out=u_wallace_cska16_and_10_7
.subckt fa a=u_wallace_cska16_fa61_or0 b=u_wallace_cska16_and_11_6 cin=u_wallace_cska16_and_10_7 fa_xor1=u_wallace_cska16_fa62_xor1 fa_or0=u_wallace_cska16_fa62_or0
.subckt and_gate a=a[11] b=b[7] out=u_wallace_cska16_and_11_7
.subckt and_gate a=a[10] b=b[8] out=u_wallace_cska16_and_10_8
.subckt fa a=u_wallace_cska16_fa62_or0 b=u_wallace_cska16_and_11_7 cin=u_wallace_cska16_and_10_8 fa_xor1=u_wallace_cska16_fa63_xor1 fa_or0=u_wallace_cska16_fa63_or0
.subckt and_gate a=a[11] b=b[8] out=u_wallace_cska16_and_11_8
.subckt and_gate a=a[10] b=b[9] out=u_wallace_cska16_and_10_9
.subckt fa a=u_wallace_cska16_fa63_or0 b=u_wallace_cska16_and_11_8 cin=u_wallace_cska16_and_10_9 fa_xor1=u_wallace_cska16_fa64_xor1 fa_or0=u_wallace_cska16_fa64_or0
.subckt and_gate a=a[11] b=b[9] out=u_wallace_cska16_and_11_9
.subckt and_gate a=a[10] b=b[10] out=u_wallace_cska16_and_10_10
.subckt fa a=u_wallace_cska16_fa64_or0 b=u_wallace_cska16_and_11_9 cin=u_wallace_cska16_and_10_10 fa_xor1=u_wallace_cska16_fa65_xor1 fa_or0=u_wallace_cska16_fa65_or0
.subckt and_gate a=a[11] b=b[10] out=u_wallace_cska16_and_11_10
.subckt and_gate a=a[10] b=b[11] out=u_wallace_cska16_and_10_11
.subckt fa a=u_wallace_cska16_fa65_or0 b=u_wallace_cska16_and_11_10 cin=u_wallace_cska16_and_10_11 fa_xor1=u_wallace_cska16_fa66_xor1 fa_or0=u_wallace_cska16_fa66_or0
.subckt and_gate a=a[11] b=b[11] out=u_wallace_cska16_and_11_11
.subckt and_gate a=a[10] b=b[12] out=u_wallace_cska16_and_10_12
.subckt fa a=u_wallace_cska16_fa66_or0 b=u_wallace_cska16_and_11_11 cin=u_wallace_cska16_and_10_12 fa_xor1=u_wallace_cska16_fa67_xor1 fa_or0=u_wallace_cska16_fa67_or0
.subckt and_gate a=a[11] b=b[12] out=u_wallace_cska16_and_11_12
.subckt and_gate a=a[10] b=b[13] out=u_wallace_cska16_and_10_13
.subckt fa a=u_wallace_cska16_fa67_or0 b=u_wallace_cska16_and_11_12 cin=u_wallace_cska16_and_10_13 fa_xor1=u_wallace_cska16_fa68_xor1 fa_or0=u_wallace_cska16_fa68_or0
.subckt and_gate a=a[11] b=b[13] out=u_wallace_cska16_and_11_13
.subckt and_gate a=a[10] b=b[14] out=u_wallace_cska16_and_10_14
.subckt fa a=u_wallace_cska16_fa68_or0 b=u_wallace_cska16_and_11_13 cin=u_wallace_cska16_and_10_14 fa_xor1=u_wallace_cska16_fa69_xor1 fa_or0=u_wallace_cska16_fa69_or0
.subckt and_gate a=a[11] b=b[14] out=u_wallace_cska16_and_11_14
.subckt and_gate a=a[10] b=b[15] out=u_wallace_cska16_and_10_15
.subckt fa a=u_wallace_cska16_fa69_or0 b=u_wallace_cska16_and_11_14 cin=u_wallace_cska16_and_10_15 fa_xor1=u_wallace_cska16_fa70_xor1 fa_or0=u_wallace_cska16_fa70_or0
.subckt and_gate a=a[11] b=b[15] out=u_wallace_cska16_and_11_15
.subckt fa a=u_wallace_cska16_fa70_or0 b=u_wallace_cska16_and_11_15 cin=u_wallace_cska16_fa23_xor1 fa_xor1=u_wallace_cska16_fa71_xor1 fa_or0=u_wallace_cska16_fa71_or0
.subckt ha a=u_wallace_cska16_fa2_xor1 b=u_wallace_cska16_fa27_xor1 ha_xor0=u_wallace_cska16_ha3_xor0 ha_and0=u_wallace_cska16_ha3_and0
.subckt and_gate a=a[0] b=b[6] out=u_wallace_cska16_and_0_6
.subckt fa a=u_wallace_cska16_ha3_and0 b=u_wallace_cska16_and_0_6 cin=u_wallace_cska16_fa3_xor1 fa_xor1=u_wallace_cska16_fa72_xor1 fa_or0=u_wallace_cska16_fa72_or0
.subckt and_gate a=a[1] b=b[6] out=u_wallace_cska16_and_1_6
.subckt and_gate a=a[0] b=b[7] out=u_wallace_cska16_and_0_7
.subckt fa a=u_wallace_cska16_fa72_or0 b=u_wallace_cska16_and_1_6 cin=u_wallace_cska16_and_0_7 fa_xor1=u_wallace_cska16_fa73_xor1 fa_or0=u_wallace_cska16_fa73_or0
.subckt and_gate a=a[2] b=b[6] out=u_wallace_cska16_and_2_6
.subckt and_gate a=a[1] b=b[7] out=u_wallace_cska16_and_1_7
.subckt fa a=u_wallace_cska16_fa73_or0 b=u_wallace_cska16_and_2_6 cin=u_wallace_cska16_and_1_7 fa_xor1=u_wallace_cska16_fa74_xor1 fa_or0=u_wallace_cska16_fa74_or0
.subckt and_gate a=a[3] b=b[6] out=u_wallace_cska16_and_3_6
.subckt and_gate a=a[2] b=b[7] out=u_wallace_cska16_and_2_7
.subckt fa a=u_wallace_cska16_fa74_or0 b=u_wallace_cska16_and_3_6 cin=u_wallace_cska16_and_2_7 fa_xor1=u_wallace_cska16_fa75_xor1 fa_or0=u_wallace_cska16_fa75_or0
.subckt and_gate a=a[4] b=b[6] out=u_wallace_cska16_and_4_6
.subckt and_gate a=a[3] b=b[7] out=u_wallace_cska16_and_3_7
.subckt fa a=u_wallace_cska16_fa75_or0 b=u_wallace_cska16_and_4_6 cin=u_wallace_cska16_and_3_7 fa_xor1=u_wallace_cska16_fa76_xor1 fa_or0=u_wallace_cska16_fa76_or0
.subckt and_gate a=a[5] b=b[6] out=u_wallace_cska16_and_5_6
.subckt and_gate a=a[4] b=b[7] out=u_wallace_cska16_and_4_7
.subckt fa a=u_wallace_cska16_fa76_or0 b=u_wallace_cska16_and_5_6 cin=u_wallace_cska16_and_4_7 fa_xor1=u_wallace_cska16_fa77_xor1 fa_or0=u_wallace_cska16_fa77_or0
.subckt and_gate a=a[6] b=b[6] out=u_wallace_cska16_and_6_6
.subckt and_gate a=a[5] b=b[7] out=u_wallace_cska16_and_5_7
.subckt fa a=u_wallace_cska16_fa77_or0 b=u_wallace_cska16_and_6_6 cin=u_wallace_cska16_and_5_7 fa_xor1=u_wallace_cska16_fa78_xor1 fa_or0=u_wallace_cska16_fa78_or0
.subckt and_gate a=a[7] b=b[6] out=u_wallace_cska16_and_7_6
.subckt and_gate a=a[6] b=b[7] out=u_wallace_cska16_and_6_7
.subckt fa a=u_wallace_cska16_fa78_or0 b=u_wallace_cska16_and_7_6 cin=u_wallace_cska16_and_6_7 fa_xor1=u_wallace_cska16_fa79_xor1 fa_or0=u_wallace_cska16_fa79_or0
.subckt and_gate a=a[8] b=b[6] out=u_wallace_cska16_and_8_6
.subckt and_gate a=a[7] b=b[7] out=u_wallace_cska16_and_7_7
.subckt fa a=u_wallace_cska16_fa79_or0 b=u_wallace_cska16_and_8_6 cin=u_wallace_cska16_and_7_7 fa_xor1=u_wallace_cska16_fa80_xor1 fa_or0=u_wallace_cska16_fa80_or0
.subckt and_gate a=a[9] b=b[6] out=u_wallace_cska16_and_9_6
.subckt and_gate a=a[8] b=b[7] out=u_wallace_cska16_and_8_7
.subckt fa a=u_wallace_cska16_fa80_or0 b=u_wallace_cska16_and_9_6 cin=u_wallace_cska16_and_8_7 fa_xor1=u_wallace_cska16_fa81_xor1 fa_or0=u_wallace_cska16_fa81_or0
.subckt and_gate a=a[9] b=b[7] out=u_wallace_cska16_and_9_7
.subckt and_gate a=a[8] b=b[8] out=u_wallace_cska16_and_8_8
.subckt fa a=u_wallace_cska16_fa81_or0 b=u_wallace_cska16_and_9_7 cin=u_wallace_cska16_and_8_8 fa_xor1=u_wallace_cska16_fa82_xor1 fa_or0=u_wallace_cska16_fa82_or0
.subckt and_gate a=a[9] b=b[8] out=u_wallace_cska16_and_9_8
.subckt and_gate a=a[8] b=b[9] out=u_wallace_cska16_and_8_9
.subckt fa a=u_wallace_cska16_fa82_or0 b=u_wallace_cska16_and_9_8 cin=u_wallace_cska16_and_8_9 fa_xor1=u_wallace_cska16_fa83_xor1 fa_or0=u_wallace_cska16_fa83_or0
.subckt and_gate a=a[9] b=b[9] out=u_wallace_cska16_and_9_9
.subckt and_gate a=a[8] b=b[10] out=u_wallace_cska16_and_8_10
.subckt fa a=u_wallace_cska16_fa83_or0 b=u_wallace_cska16_and_9_9 cin=u_wallace_cska16_and_8_10 fa_xor1=u_wallace_cska16_fa84_xor1 fa_or0=u_wallace_cska16_fa84_or0
.subckt and_gate a=a[9] b=b[10] out=u_wallace_cska16_and_9_10
.subckt and_gate a=a[8] b=b[11] out=u_wallace_cska16_and_8_11
.subckt fa a=u_wallace_cska16_fa84_or0 b=u_wallace_cska16_and_9_10 cin=u_wallace_cska16_and_8_11 fa_xor1=u_wallace_cska16_fa85_xor1 fa_or0=u_wallace_cska16_fa85_or0
.subckt and_gate a=a[9] b=b[11] out=u_wallace_cska16_and_9_11
.subckt and_gate a=a[8] b=b[12] out=u_wallace_cska16_and_8_12
.subckt fa a=u_wallace_cska16_fa85_or0 b=u_wallace_cska16_and_9_11 cin=u_wallace_cska16_and_8_12 fa_xor1=u_wallace_cska16_fa86_xor1 fa_or0=u_wallace_cska16_fa86_or0
.subckt and_gate a=a[9] b=b[12] out=u_wallace_cska16_and_9_12
.subckt and_gate a=a[8] b=b[13] out=u_wallace_cska16_and_8_13
.subckt fa a=u_wallace_cska16_fa86_or0 b=u_wallace_cska16_and_9_12 cin=u_wallace_cska16_and_8_13 fa_xor1=u_wallace_cska16_fa87_xor1 fa_or0=u_wallace_cska16_fa87_or0
.subckt and_gate a=a[9] b=b[13] out=u_wallace_cska16_and_9_13
.subckt and_gate a=a[8] b=b[14] out=u_wallace_cska16_and_8_14
.subckt fa a=u_wallace_cska16_fa87_or0 b=u_wallace_cska16_and_9_13 cin=u_wallace_cska16_and_8_14 fa_xor1=u_wallace_cska16_fa88_xor1 fa_or0=u_wallace_cska16_fa88_or0
.subckt and_gate a=a[9] b=b[14] out=u_wallace_cska16_and_9_14
.subckt and_gate a=a[8] b=b[15] out=u_wallace_cska16_and_8_15
.subckt fa a=u_wallace_cska16_fa88_or0 b=u_wallace_cska16_and_9_14 cin=u_wallace_cska16_and_8_15 fa_xor1=u_wallace_cska16_fa89_xor1 fa_or0=u_wallace_cska16_fa89_or0
.subckt and_gate a=a[9] b=b[15] out=u_wallace_cska16_and_9_15
.subckt fa a=u_wallace_cska16_fa89_or0 b=u_wallace_cska16_and_9_15 cin=u_wallace_cska16_fa21_xor1 fa_xor1=u_wallace_cska16_fa90_xor1 fa_or0=u_wallace_cska16_fa90_or0
.subckt fa a=u_wallace_cska16_fa90_or0 b=u_wallace_cska16_fa22_xor1 cin=u_wallace_cska16_fa47_xor1 fa_xor1=u_wallace_cska16_fa91_xor1 fa_or0=u_wallace_cska16_fa91_or0
.subckt ha a=u_wallace_cska16_fa28_xor1 b=u_wallace_cska16_fa51_xor1 ha_xor0=u_wallace_cska16_ha4_xor0 ha_and0=u_wallace_cska16_ha4_and0
.subckt fa a=u_wallace_cska16_ha4_and0 b=u_wallace_cska16_fa4_xor1 cin=u_wallace_cska16_fa29_xor1 fa_xor1=u_wallace_cska16_fa92_xor1 fa_or0=u_wallace_cska16_fa92_or0
.subckt and_gate a=a[0] b=b[8] out=u_wallace_cska16_and_0_8
.subckt fa a=u_wallace_cska16_fa92_or0 b=u_wallace_cska16_and_0_8 cin=u_wallace_cska16_fa5_xor1 fa_xor1=u_wallace_cska16_fa93_xor1 fa_or0=u_wallace_cska16_fa93_or0
.subckt and_gate a=a[1] b=b[8] out=u_wallace_cska16_and_1_8
.subckt and_gate a=a[0] b=b[9] out=u_wallace_cska16_and_0_9
.subckt fa a=u_wallace_cska16_fa93_or0 b=u_wallace_cska16_and_1_8 cin=u_wallace_cska16_and_0_9 fa_xor1=u_wallace_cska16_fa94_xor1 fa_or0=u_wallace_cska16_fa94_or0
.subckt and_gate a=a[2] b=b[8] out=u_wallace_cska16_and_2_8
.subckt and_gate a=a[1] b=b[9] out=u_wallace_cska16_and_1_9
.subckt fa a=u_wallace_cska16_fa94_or0 b=u_wallace_cska16_and_2_8 cin=u_wallace_cska16_and_1_9 fa_xor1=u_wallace_cska16_fa95_xor1 fa_or0=u_wallace_cska16_fa95_or0
.subckt and_gate a=a[3] b=b[8] out=u_wallace_cska16_and_3_8
.subckt and_gate a=a[2] b=b[9] out=u_wallace_cska16_and_2_9
.subckt fa a=u_wallace_cska16_fa95_or0 b=u_wallace_cska16_and_3_8 cin=u_wallace_cska16_and_2_9 fa_xor1=u_wallace_cska16_fa96_xor1 fa_or0=u_wallace_cska16_fa96_or0
.subckt and_gate a=a[4] b=b[8] out=u_wallace_cska16_and_4_8
.subckt and_gate a=a[3] b=b[9] out=u_wallace_cska16_and_3_9
.subckt fa a=u_wallace_cska16_fa96_or0 b=u_wallace_cska16_and_4_8 cin=u_wallace_cska16_and_3_9 fa_xor1=u_wallace_cska16_fa97_xor1 fa_or0=u_wallace_cska16_fa97_or0
.subckt and_gate a=a[5] b=b[8] out=u_wallace_cska16_and_5_8
.subckt and_gate a=a[4] b=b[9] out=u_wallace_cska16_and_4_9
.subckt fa a=u_wallace_cska16_fa97_or0 b=u_wallace_cska16_and_5_8 cin=u_wallace_cska16_and_4_9 fa_xor1=u_wallace_cska16_fa98_xor1 fa_or0=u_wallace_cska16_fa98_or0
.subckt and_gate a=a[6] b=b[8] out=u_wallace_cska16_and_6_8
.subckt and_gate a=a[5] b=b[9] out=u_wallace_cska16_and_5_9
.subckt fa a=u_wallace_cska16_fa98_or0 b=u_wallace_cska16_and_6_8 cin=u_wallace_cska16_and_5_9 fa_xor1=u_wallace_cska16_fa99_xor1 fa_or0=u_wallace_cska16_fa99_or0
.subckt and_gate a=a[7] b=b[8] out=u_wallace_cska16_and_7_8
.subckt and_gate a=a[6] b=b[9] out=u_wallace_cska16_and_6_9
.subckt fa a=u_wallace_cska16_fa99_or0 b=u_wallace_cska16_and_7_8 cin=u_wallace_cska16_and_6_9 fa_xor1=u_wallace_cska16_fa100_xor1 fa_or0=u_wallace_cska16_fa100_or0
.subckt and_gate a=a[7] b=b[9] out=u_wallace_cska16_and_7_9
.subckt and_gate a=a[6] b=b[10] out=u_wallace_cska16_and_6_10
.subckt fa a=u_wallace_cska16_fa100_or0 b=u_wallace_cska16_and_7_9 cin=u_wallace_cska16_and_6_10 fa_xor1=u_wallace_cska16_fa101_xor1 fa_or0=u_wallace_cska16_fa101_or0
.subckt and_gate a=a[7] b=b[10] out=u_wallace_cska16_and_7_10
.subckt and_gate a=a[6] b=b[11] out=u_wallace_cska16_and_6_11
.subckt fa a=u_wallace_cska16_fa101_or0 b=u_wallace_cska16_and_7_10 cin=u_wallace_cska16_and_6_11 fa_xor1=u_wallace_cska16_fa102_xor1 fa_or0=u_wallace_cska16_fa102_or0
.subckt and_gate a=a[7] b=b[11] out=u_wallace_cska16_and_7_11
.subckt and_gate a=a[6] b=b[12] out=u_wallace_cska16_and_6_12
.subckt fa a=u_wallace_cska16_fa102_or0 b=u_wallace_cska16_and_7_11 cin=u_wallace_cska16_and_6_12 fa_xor1=u_wallace_cska16_fa103_xor1 fa_or0=u_wallace_cska16_fa103_or0
.subckt and_gate a=a[7] b=b[12] out=u_wallace_cska16_and_7_12
.subckt and_gate a=a[6] b=b[13] out=u_wallace_cska16_and_6_13
.subckt fa a=u_wallace_cska16_fa103_or0 b=u_wallace_cska16_and_7_12 cin=u_wallace_cska16_and_6_13 fa_xor1=u_wallace_cska16_fa104_xor1 fa_or0=u_wallace_cska16_fa104_or0
.subckt and_gate a=a[7] b=b[13] out=u_wallace_cska16_and_7_13
.subckt and_gate a=a[6] b=b[14] out=u_wallace_cska16_and_6_14
.subckt fa a=u_wallace_cska16_fa104_or0 b=u_wallace_cska16_and_7_13 cin=u_wallace_cska16_and_6_14 fa_xor1=u_wallace_cska16_fa105_xor1 fa_or0=u_wallace_cska16_fa105_or0
.subckt and_gate a=a[7] b=b[14] out=u_wallace_cska16_and_7_14
.subckt and_gate a=a[6] b=b[15] out=u_wallace_cska16_and_6_15
.subckt fa a=u_wallace_cska16_fa105_or0 b=u_wallace_cska16_and_7_14 cin=u_wallace_cska16_and_6_15 fa_xor1=u_wallace_cska16_fa106_xor1 fa_or0=u_wallace_cska16_fa106_or0
.subckt and_gate a=a[7] b=b[15] out=u_wallace_cska16_and_7_15
.subckt fa a=u_wallace_cska16_fa106_or0 b=u_wallace_cska16_and_7_15 cin=u_wallace_cska16_fa19_xor1 fa_xor1=u_wallace_cska16_fa107_xor1 fa_or0=u_wallace_cska16_fa107_or0
.subckt fa a=u_wallace_cska16_fa107_or0 b=u_wallace_cska16_fa20_xor1 cin=u_wallace_cska16_fa45_xor1 fa_xor1=u_wallace_cska16_fa108_xor1 fa_or0=u_wallace_cska16_fa108_or0
.subckt fa a=u_wallace_cska16_fa108_or0 b=u_wallace_cska16_fa46_xor1 cin=u_wallace_cska16_fa69_xor1 fa_xor1=u_wallace_cska16_fa109_xor1 fa_or0=u_wallace_cska16_fa109_or0
.subckt ha a=u_wallace_cska16_fa52_xor1 b=u_wallace_cska16_fa73_xor1 ha_xor0=u_wallace_cska16_ha5_xor0 ha_and0=u_wallace_cska16_ha5_and0
.subckt fa a=u_wallace_cska16_ha5_and0 b=u_wallace_cska16_fa30_xor1 cin=u_wallace_cska16_fa53_xor1 fa_xor1=u_wallace_cska16_fa110_xor1 fa_or0=u_wallace_cska16_fa110_or0
.subckt fa a=u_wallace_cska16_fa110_or0 b=u_wallace_cska16_fa6_xor1 cin=u_wallace_cska16_fa31_xor1 fa_xor1=u_wallace_cska16_fa111_xor1 fa_or0=u_wallace_cska16_fa111_or0
.subckt and_gate a=a[0] b=b[10] out=u_wallace_cska16_and_0_10
.subckt fa a=u_wallace_cska16_fa111_or0 b=u_wallace_cska16_and_0_10 cin=u_wallace_cska16_fa7_xor1 fa_xor1=u_wallace_cska16_fa112_xor1 fa_or0=u_wallace_cska16_fa112_or0
.subckt and_gate a=a[1] b=b[10] out=u_wallace_cska16_and_1_10
.subckt and_gate a=a[0] b=b[11] out=u_wallace_cska16_and_0_11
.subckt fa a=u_wallace_cska16_fa112_or0 b=u_wallace_cska16_and_1_10 cin=u_wallace_cska16_and_0_11 fa_xor1=u_wallace_cska16_fa113_xor1 fa_or0=u_wallace_cska16_fa113_or0
.subckt and_gate a=a[2] b=b[10] out=u_wallace_cska16_and_2_10
.subckt and_gate a=a[1] b=b[11] out=u_wallace_cska16_and_1_11
.subckt fa a=u_wallace_cska16_fa113_or0 b=u_wallace_cska16_and_2_10 cin=u_wallace_cska16_and_1_11 fa_xor1=u_wallace_cska16_fa114_xor1 fa_or0=u_wallace_cska16_fa114_or0
.subckt and_gate a=a[3] b=b[10] out=u_wallace_cska16_and_3_10
.subckt and_gate a=a[2] b=b[11] out=u_wallace_cska16_and_2_11
.subckt fa a=u_wallace_cska16_fa114_or0 b=u_wallace_cska16_and_3_10 cin=u_wallace_cska16_and_2_11 fa_xor1=u_wallace_cska16_fa115_xor1 fa_or0=u_wallace_cska16_fa115_or0
.subckt and_gate a=a[4] b=b[10] out=u_wallace_cska16_and_4_10
.subckt and_gate a=a[3] b=b[11] out=u_wallace_cska16_and_3_11
.subckt fa a=u_wallace_cska16_fa115_or0 b=u_wallace_cska16_and_4_10 cin=u_wallace_cska16_and_3_11 fa_xor1=u_wallace_cska16_fa116_xor1 fa_or0=u_wallace_cska16_fa116_or0
.subckt and_gate a=a[5] b=b[10] out=u_wallace_cska16_and_5_10
.subckt and_gate a=a[4] b=b[11] out=u_wallace_cska16_and_4_11
.subckt fa a=u_wallace_cska16_fa116_or0 b=u_wallace_cska16_and_5_10 cin=u_wallace_cska16_and_4_11 fa_xor1=u_wallace_cska16_fa117_xor1 fa_or0=u_wallace_cska16_fa117_or0
.subckt and_gate a=a[5] b=b[11] out=u_wallace_cska16_and_5_11
.subckt and_gate a=a[4] b=b[12] out=u_wallace_cska16_and_4_12
.subckt fa a=u_wallace_cska16_fa117_or0 b=u_wallace_cska16_and_5_11 cin=u_wallace_cska16_and_4_12 fa_xor1=u_wallace_cska16_fa118_xor1 fa_or0=u_wallace_cska16_fa118_or0
.subckt and_gate a=a[5] b=b[12] out=u_wallace_cska16_and_5_12
.subckt and_gate a=a[4] b=b[13] out=u_wallace_cska16_and_4_13
.subckt fa a=u_wallace_cska16_fa118_or0 b=u_wallace_cska16_and_5_12 cin=u_wallace_cska16_and_4_13 fa_xor1=u_wallace_cska16_fa119_xor1 fa_or0=u_wallace_cska16_fa119_or0
.subckt and_gate a=a[5] b=b[13] out=u_wallace_cska16_and_5_13
.subckt and_gate a=a[4] b=b[14] out=u_wallace_cska16_and_4_14
.subckt fa a=u_wallace_cska16_fa119_or0 b=u_wallace_cska16_and_5_13 cin=u_wallace_cska16_and_4_14 fa_xor1=u_wallace_cska16_fa120_xor1 fa_or0=u_wallace_cska16_fa120_or0
.subckt and_gate a=a[5] b=b[14] out=u_wallace_cska16_and_5_14
.subckt and_gate a=a[4] b=b[15] out=u_wallace_cska16_and_4_15
.subckt fa a=u_wallace_cska16_fa120_or0 b=u_wallace_cska16_and_5_14 cin=u_wallace_cska16_and_4_15 fa_xor1=u_wallace_cska16_fa121_xor1 fa_or0=u_wallace_cska16_fa121_or0
.subckt and_gate a=a[5] b=b[15] out=u_wallace_cska16_and_5_15
.subckt fa a=u_wallace_cska16_fa121_or0 b=u_wallace_cska16_and_5_15 cin=u_wallace_cska16_fa17_xor1 fa_xor1=u_wallace_cska16_fa122_xor1 fa_or0=u_wallace_cska16_fa122_or0
.subckt fa a=u_wallace_cska16_fa122_or0 b=u_wallace_cska16_fa18_xor1 cin=u_wallace_cska16_fa43_xor1 fa_xor1=u_wallace_cska16_fa123_xor1 fa_or0=u_wallace_cska16_fa123_or0
.subckt fa a=u_wallace_cska16_fa123_or0 b=u_wallace_cska16_fa44_xor1 cin=u_wallace_cska16_fa67_xor1 fa_xor1=u_wallace_cska16_fa124_xor1 fa_or0=u_wallace_cska16_fa124_or0
.subckt fa a=u_wallace_cska16_fa124_or0 b=u_wallace_cska16_fa68_xor1 cin=u_wallace_cska16_fa89_xor1 fa_xor1=u_wallace_cska16_fa125_xor1 fa_or0=u_wallace_cska16_fa125_or0
.subckt ha a=u_wallace_cska16_fa74_xor1 b=u_wallace_cska16_fa93_xor1 ha_xor0=u_wallace_cska16_ha6_xor0 ha_and0=u_wallace_cska16_ha6_and0
.subckt fa a=u_wallace_cska16_ha6_and0 b=u_wallace_cska16_fa54_xor1 cin=u_wallace_cska16_fa75_xor1 fa_xor1=u_wallace_cska16_fa126_xor1 fa_or0=u_wallace_cska16_fa126_or0
.subckt fa a=u_wallace_cska16_fa126_or0 b=u_wallace_cska16_fa32_xor1 cin=u_wallace_cska16_fa55_xor1 fa_xor1=u_wallace_cska16_fa127_xor1 fa_or0=u_wallace_cska16_fa127_or0
.subckt fa a=u_wallace_cska16_fa127_or0 b=u_wallace_cska16_fa8_xor1 cin=u_wallace_cska16_fa33_xor1 fa_xor1=u_wallace_cska16_fa128_xor1 fa_or0=u_wallace_cska16_fa128_or0
.subckt and_gate a=a[0] b=b[12] out=u_wallace_cska16_and_0_12
.subckt fa a=u_wallace_cska16_fa128_or0 b=u_wallace_cska16_and_0_12 cin=u_wallace_cska16_fa9_xor1 fa_xor1=u_wallace_cska16_fa129_xor1 fa_or0=u_wallace_cska16_fa129_or0
.subckt and_gate a=a[1] b=b[12] out=u_wallace_cska16_and_1_12
.subckt and_gate a=a[0] b=b[13] out=u_wallace_cska16_and_0_13
.subckt fa a=u_wallace_cska16_fa129_or0 b=u_wallace_cska16_and_1_12 cin=u_wallace_cska16_and_0_13 fa_xor1=u_wallace_cska16_fa130_xor1 fa_or0=u_wallace_cska16_fa130_or0
.subckt and_gate a=a[2] b=b[12] out=u_wallace_cska16_and_2_12
.subckt and_gate a=a[1] b=b[13] out=u_wallace_cska16_and_1_13
.subckt fa a=u_wallace_cska16_fa130_or0 b=u_wallace_cska16_and_2_12 cin=u_wallace_cska16_and_1_13 fa_xor1=u_wallace_cska16_fa131_xor1 fa_or0=u_wallace_cska16_fa131_or0
.subckt and_gate a=a[3] b=b[12] out=u_wallace_cska16_and_3_12
.subckt and_gate a=a[2] b=b[13] out=u_wallace_cska16_and_2_13
.subckt fa a=u_wallace_cska16_fa131_or0 b=u_wallace_cska16_and_3_12 cin=u_wallace_cska16_and_2_13 fa_xor1=u_wallace_cska16_fa132_xor1 fa_or0=u_wallace_cska16_fa132_or0
.subckt and_gate a=a[3] b=b[13] out=u_wallace_cska16_and_3_13
.subckt and_gate a=a[2] b=b[14] out=u_wallace_cska16_and_2_14
.subckt fa a=u_wallace_cska16_fa132_or0 b=u_wallace_cska16_and_3_13 cin=u_wallace_cska16_and_2_14 fa_xor1=u_wallace_cska16_fa133_xor1 fa_or0=u_wallace_cska16_fa133_or0
.subckt and_gate a=a[3] b=b[14] out=u_wallace_cska16_and_3_14
.subckt and_gate a=a[2] b=b[15] out=u_wallace_cska16_and_2_15
.subckt fa a=u_wallace_cska16_fa133_or0 b=u_wallace_cska16_and_3_14 cin=u_wallace_cska16_and_2_15 fa_xor1=u_wallace_cska16_fa134_xor1 fa_or0=u_wallace_cska16_fa134_or0
.subckt and_gate a=a[3] b=b[15] out=u_wallace_cska16_and_3_15
.subckt fa a=u_wallace_cska16_fa134_or0 b=u_wallace_cska16_and_3_15 cin=u_wallace_cska16_fa15_xor1 fa_xor1=u_wallace_cska16_fa135_xor1 fa_or0=u_wallace_cska16_fa135_or0
.subckt fa a=u_wallace_cska16_fa135_or0 b=u_wallace_cska16_fa16_xor1 cin=u_wallace_cska16_fa41_xor1 fa_xor1=u_wallace_cska16_fa136_xor1 fa_or0=u_wallace_cska16_fa136_or0
.subckt fa a=u_wallace_cska16_fa136_or0 b=u_wallace_cska16_fa42_xor1 cin=u_wallace_cska16_fa65_xor1 fa_xor1=u_wallace_cska16_fa137_xor1 fa_or0=u_wallace_cska16_fa137_or0
.subckt fa a=u_wallace_cska16_fa137_or0 b=u_wallace_cska16_fa66_xor1 cin=u_wallace_cska16_fa87_xor1 fa_xor1=u_wallace_cska16_fa138_xor1 fa_or0=u_wallace_cska16_fa138_or0
.subckt fa a=u_wallace_cska16_fa138_or0 b=u_wallace_cska16_fa88_xor1 cin=u_wallace_cska16_fa107_xor1 fa_xor1=u_wallace_cska16_fa139_xor1 fa_or0=u_wallace_cska16_fa139_or0
.subckt ha a=u_wallace_cska16_fa94_xor1 b=u_wallace_cska16_fa111_xor1 ha_xor0=u_wallace_cska16_ha7_xor0 ha_and0=u_wallace_cska16_ha7_and0
.subckt fa a=u_wallace_cska16_ha7_and0 b=u_wallace_cska16_fa76_xor1 cin=u_wallace_cska16_fa95_xor1 fa_xor1=u_wallace_cska16_fa140_xor1 fa_or0=u_wallace_cska16_fa140_or0
.subckt fa a=u_wallace_cska16_fa140_or0 b=u_wallace_cska16_fa56_xor1 cin=u_wallace_cska16_fa77_xor1 fa_xor1=u_wallace_cska16_fa141_xor1 fa_or0=u_wallace_cska16_fa141_or0
.subckt fa a=u_wallace_cska16_fa141_or0 b=u_wallace_cska16_fa34_xor1 cin=u_wallace_cska16_fa57_xor1 fa_xor1=u_wallace_cska16_fa142_xor1 fa_or0=u_wallace_cska16_fa142_or0
.subckt fa a=u_wallace_cska16_fa142_or0 b=u_wallace_cska16_fa10_xor1 cin=u_wallace_cska16_fa35_xor1 fa_xor1=u_wallace_cska16_fa143_xor1 fa_or0=u_wallace_cska16_fa143_or0
.subckt and_gate a=a[0] b=b[14] out=u_wallace_cska16_and_0_14
.subckt fa a=u_wallace_cska16_fa143_or0 b=u_wallace_cska16_and_0_14 cin=u_wallace_cska16_fa11_xor1 fa_xor1=u_wallace_cska16_fa144_xor1 fa_or0=u_wallace_cska16_fa144_or0
.subckt and_gate a=a[1] b=b[14] out=u_wallace_cska16_and_1_14
.subckt and_gate a=a[0] b=b[15] out=u_wallace_cska16_and_0_15
.subckt fa a=u_wallace_cska16_fa144_or0 b=u_wallace_cska16_and_1_14 cin=u_wallace_cska16_and_0_15 fa_xor1=u_wallace_cska16_fa145_xor1 fa_or0=u_wallace_cska16_fa145_or0
.subckt and_gate a=a[1] b=b[15] out=u_wallace_cska16_and_1_15
.subckt fa a=u_wallace_cska16_fa145_or0 b=u_wallace_cska16_and_1_15 cin=u_wallace_cska16_fa13_xor1 fa_xor1=u_wallace_cska16_fa146_xor1 fa_or0=u_wallace_cska16_fa146_or0
.subckt fa a=u_wallace_cska16_fa146_or0 b=u_wallace_cska16_fa14_xor1 cin=u_wallace_cska16_fa39_xor1 fa_xor1=u_wallace_cska16_fa147_xor1 fa_or0=u_wallace_cska16_fa147_or0
.subckt fa a=u_wallace_cska16_fa147_or0 b=u_wallace_cska16_fa40_xor1 cin=u_wallace_cska16_fa63_xor1 fa_xor1=u_wallace_cska16_fa148_xor1 fa_or0=u_wallace_cska16_fa148_or0
.subckt fa a=u_wallace_cska16_fa148_or0 b=u_wallace_cska16_fa64_xor1 cin=u_wallace_cska16_fa85_xor1 fa_xor1=u_wallace_cska16_fa149_xor1 fa_or0=u_wallace_cska16_fa149_or0
.subckt fa a=u_wallace_cska16_fa149_or0 b=u_wallace_cska16_fa86_xor1 cin=u_wallace_cska16_fa105_xor1 fa_xor1=u_wallace_cska16_fa150_xor1 fa_or0=u_wallace_cska16_fa150_or0
.subckt fa a=u_wallace_cska16_fa150_or0 b=u_wallace_cska16_fa106_xor1 cin=u_wallace_cska16_fa123_xor1 fa_xor1=u_wallace_cska16_fa151_xor1 fa_or0=u_wallace_cska16_fa151_or0
.subckt ha a=u_wallace_cska16_fa112_xor1 b=u_wallace_cska16_fa127_xor1 ha_xor0=u_wallace_cska16_ha8_xor0 ha_and0=u_wallace_cska16_ha8_and0
.subckt fa a=u_wallace_cska16_ha8_and0 b=u_wallace_cska16_fa96_xor1 cin=u_wallace_cska16_fa113_xor1 fa_xor1=u_wallace_cska16_fa152_xor1 fa_or0=u_wallace_cska16_fa152_or0
.subckt fa a=u_wallace_cska16_fa152_or0 b=u_wallace_cska16_fa78_xor1 cin=u_wallace_cska16_fa97_xor1 fa_xor1=u_wallace_cska16_fa153_xor1 fa_or0=u_wallace_cska16_fa153_or0
.subckt fa a=u_wallace_cska16_fa153_or0 b=u_wallace_cska16_fa58_xor1 cin=u_wallace_cska16_fa79_xor1 fa_xor1=u_wallace_cska16_fa154_xor1 fa_or0=u_wallace_cska16_fa154_or0
.subckt fa a=u_wallace_cska16_fa154_or0 b=u_wallace_cska16_fa36_xor1 cin=u_wallace_cska16_fa59_xor1 fa_xor1=u_wallace_cska16_fa155_xor1 fa_or0=u_wallace_cska16_fa155_or0
.subckt fa a=u_wallace_cska16_fa155_or0 b=u_wallace_cska16_fa12_xor1 cin=u_wallace_cska16_fa37_xor1 fa_xor1=u_wallace_cska16_fa156_xor1 fa_or0=u_wallace_cska16_fa156_or0
.subckt fa a=u_wallace_cska16_fa156_or0 b=u_wallace_cska16_fa38_xor1 cin=u_wallace_cska16_fa61_xor1 fa_xor1=u_wallace_cska16_fa157_xor1 fa_or0=u_wallace_cska16_fa157_or0
.subckt fa a=u_wallace_cska16_fa157_or0 b=u_wallace_cska16_fa62_xor1 cin=u_wallace_cska16_fa83_xor1 fa_xor1=u_wallace_cska16_fa158_xor1 fa_or0=u_wallace_cska16_fa158_or0
.subckt fa a=u_wallace_cska16_fa158_or0 b=u_wallace_cska16_fa84_xor1 cin=u_wallace_cska16_fa103_xor1 fa_xor1=u_wallace_cska16_fa159_xor1 fa_or0=u_wallace_cska16_fa159_or0
.subckt fa a=u_wallace_cska16_fa159_or0 b=u_wallace_cska16_fa104_xor1 cin=u_wallace_cska16_fa121_xor1 fa_xor1=u_wallace_cska16_fa160_xor1 fa_or0=u_wallace_cska16_fa160_or0
.subckt fa a=u_wallace_cska16_fa160_or0 b=u_wallace_cska16_fa122_xor1 cin=u_wallace_cska16_fa137_xor1 fa_xor1=u_wallace_cska16_fa161_xor1 fa_or0=u_wallace_cska16_fa161_or0
.subckt ha a=u_wallace_cska16_fa128_xor1 b=u_wallace_cska16_fa141_xor1 ha_xor0=u_wallace_cska16_ha9_xor0 ha_and0=u_wallace_cska16_ha9_and0
.subckt fa a=u_wallace_cska16_ha9_and0 b=u_wallace_cska16_fa114_xor1 cin=u_wallace_cska16_fa129_xor1 fa_xor1=u_wallace_cska16_fa162_xor1 fa_or0=u_wallace_cska16_fa162_or0
.subckt fa a=u_wallace_cska16_fa162_or0 b=u_wallace_cska16_fa98_xor1 cin=u_wallace_cska16_fa115_xor1 fa_xor1=u_wallace_cska16_fa163_xor1 fa_or0=u_wallace_cska16_fa163_or0
.subckt fa a=u_wallace_cska16_fa163_or0 b=u_wallace_cska16_fa80_xor1 cin=u_wallace_cska16_fa99_xor1 fa_xor1=u_wallace_cska16_fa164_xor1 fa_or0=u_wallace_cska16_fa164_or0
.subckt fa a=u_wallace_cska16_fa164_or0 b=u_wallace_cska16_fa60_xor1 cin=u_wallace_cska16_fa81_xor1 fa_xor1=u_wallace_cska16_fa165_xor1 fa_or0=u_wallace_cska16_fa165_or0
.subckt fa a=u_wallace_cska16_fa165_or0 b=u_wallace_cska16_fa82_xor1 cin=u_wallace_cska16_fa101_xor1 fa_xor1=u_wallace_cska16_fa166_xor1 fa_or0=u_wallace_cska16_fa166_or0
.subckt fa a=u_wallace_cska16_fa166_or0 b=u_wallace_cska16_fa102_xor1 cin=u_wallace_cska16_fa119_xor1 fa_xor1=u_wallace_cska16_fa167_xor1 fa_or0=u_wallace_cska16_fa167_or0
.subckt fa a=u_wallace_cska16_fa167_or0 b=u_wallace_cska16_fa120_xor1 cin=u_wallace_cska16_fa135_xor1 fa_xor1=u_wallace_cska16_fa168_xor1 fa_or0=u_wallace_cska16_fa168_or0
.subckt fa a=u_wallace_cska16_fa168_or0 b=u_wallace_cska16_fa136_xor1 cin=u_wallace_cska16_fa149_xor1 fa_xor1=u_wallace_cska16_fa169_xor1 fa_or0=u_wallace_cska16_fa169_or0
.subckt ha a=u_wallace_cska16_fa142_xor1 b=u_wallace_cska16_fa153_xor1 ha_xor0=u_wallace_cska16_ha10_xor0 ha_and0=u_wallace_cska16_ha10_and0
.subckt fa a=u_wallace_cska16_ha10_and0 b=u_wallace_cska16_fa130_xor1 cin=u_wallace_cska16_fa143_xor1 fa_xor1=u_wallace_cska16_fa170_xor1 fa_or0=u_wallace_cska16_fa170_or0
.subckt fa a=u_wallace_cska16_fa170_or0 b=u_wallace_cska16_fa116_xor1 cin=u_wallace_cska16_fa131_xor1 fa_xor1=u_wallace_cska16_fa171_xor1 fa_or0=u_wallace_cska16_fa171_or0
.subckt fa a=u_wallace_cska16_fa171_or0 b=u_wallace_cska16_fa100_xor1 cin=u_wallace_cska16_fa117_xor1 fa_xor1=u_wallace_cska16_fa172_xor1 fa_or0=u_wallace_cska16_fa172_or0
.subckt fa a=u_wallace_cska16_fa172_or0 b=u_wallace_cska16_fa118_xor1 cin=u_wallace_cska16_fa133_xor1 fa_xor1=u_wallace_cska16_fa173_xor1 fa_or0=u_wallace_cska16_fa173_or0
.subckt fa a=u_wallace_cska16_fa173_or0 b=u_wallace_cska16_fa134_xor1 cin=u_wallace_cska16_fa147_xor1 fa_xor1=u_wallace_cska16_fa174_xor1 fa_or0=u_wallace_cska16_fa174_or0
.subckt fa a=u_wallace_cska16_fa174_or0 b=u_wallace_cska16_fa148_xor1 cin=u_wallace_cska16_fa159_xor1 fa_xor1=u_wallace_cska16_fa175_xor1 fa_or0=u_wallace_cska16_fa175_or0
.subckt ha a=u_wallace_cska16_fa154_xor1 b=u_wallace_cska16_fa163_xor1 ha_xor0=u_wallace_cska16_ha11_xor0 ha_and0=u_wallace_cska16_ha11_and0
.subckt fa a=u_wallace_cska16_ha11_and0 b=u_wallace_cska16_fa144_xor1 cin=u_wallace_cska16_fa155_xor1 fa_xor1=u_wallace_cska16_fa176_xor1 fa_or0=u_wallace_cska16_fa176_or0
.subckt fa a=u_wallace_cska16_fa176_or0 b=u_wallace_cska16_fa132_xor1 cin=u_wallace_cska16_fa145_xor1 fa_xor1=u_wallace_cska16_fa177_xor1 fa_or0=u_wallace_cska16_fa177_or0
.subckt fa a=u_wallace_cska16_fa177_or0 b=u_wallace_cska16_fa146_xor1 cin=u_wallace_cska16_fa157_xor1 fa_xor1=u_wallace_cska16_fa178_xor1 fa_or0=u_wallace_cska16_fa178_or0
.subckt fa a=u_wallace_cska16_fa178_or0 b=u_wallace_cska16_fa158_xor1 cin=u_wallace_cska16_fa167_xor1 fa_xor1=u_wallace_cska16_fa179_xor1 fa_or0=u_wallace_cska16_fa179_or0
.subckt ha a=u_wallace_cska16_fa164_xor1 b=u_wallace_cska16_fa171_xor1 ha_xor0=u_wallace_cska16_ha12_xor0 ha_and0=u_wallace_cska16_ha12_and0
.subckt fa a=u_wallace_cska16_ha12_and0 b=u_wallace_cska16_fa156_xor1 cin=u_wallace_cska16_fa165_xor1 fa_xor1=u_wallace_cska16_fa180_xor1 fa_or0=u_wallace_cska16_fa180_or0
.subckt fa a=u_wallace_cska16_fa180_or0 b=u_wallace_cska16_fa166_xor1 cin=u_wallace_cska16_fa173_xor1 fa_xor1=u_wallace_cska16_fa181_xor1 fa_or0=u_wallace_cska16_fa181_or0
.subckt ha a=u_wallace_cska16_fa172_xor1 b=u_wallace_cska16_fa177_xor1 ha_xor0=u_wallace_cska16_ha13_xor0 ha_and0=u_wallace_cska16_ha13_and0
.subckt ha a=u_wallace_cska16_ha13_and0 b=u_wallace_cska16_fa178_xor1 ha_xor0=u_wallace_cska16_ha14_xor0 ha_and0=u_wallace_cska16_ha14_and0
.subckt fa a=u_wallace_cska16_ha14_and0 b=u_wallace_cska16_fa181_or0 cin=u_wallace_cska16_fa174_xor1 fa_xor1=u_wallace_cska16_fa182_xor1 fa_or0=u_wallace_cska16_fa182_or0
.subckt fa a=u_wallace_cska16_fa182_or0 b=u_wallace_cska16_fa179_or0 cin=u_wallace_cska16_fa168_xor1 fa_xor1=u_wallace_cska16_fa183_xor1 fa_or0=u_wallace_cska16_fa183_or0
.subckt fa a=u_wallace_cska16_fa183_or0 b=u_wallace_cska16_fa175_or0 cin=u_wallace_cska16_fa160_xor1 fa_xor1=u_wallace_cska16_fa184_xor1 fa_or0=u_wallace_cska16_fa184_or0
.subckt fa a=u_wallace_cska16_fa184_or0 b=u_wallace_cska16_fa169_or0 cin=u_wallace_cska16_fa150_xor1 fa_xor1=u_wallace_cska16_fa185_xor1 fa_or0=u_wallace_cska16_fa185_or0
.subckt fa a=u_wallace_cska16_fa185_or0 b=u_wallace_cska16_fa161_or0 cin=u_wallace_cska16_fa138_xor1 fa_xor1=u_wallace_cska16_fa186_xor1 fa_or0=u_wallace_cska16_fa186_or0
.subckt fa a=u_wallace_cska16_fa186_or0 b=u_wallace_cska16_fa151_or0 cin=u_wallace_cska16_fa124_xor1 fa_xor1=u_wallace_cska16_fa187_xor1 fa_or0=u_wallace_cska16_fa187_or0
.subckt fa a=u_wallace_cska16_fa187_or0 b=u_wallace_cska16_fa139_or0 cin=u_wallace_cska16_fa108_xor1 fa_xor1=u_wallace_cska16_fa188_xor1 fa_or0=u_wallace_cska16_fa188_or0
.subckt fa a=u_wallace_cska16_fa188_or0 b=u_wallace_cska16_fa125_or0 cin=u_wallace_cska16_fa90_xor1 fa_xor1=u_wallace_cska16_fa189_xor1 fa_or0=u_wallace_cska16_fa189_or0
.subckt fa a=u_wallace_cska16_fa189_or0 b=u_wallace_cska16_fa109_or0 cin=u_wallace_cska16_fa70_xor1 fa_xor1=u_wallace_cska16_fa190_xor1 fa_or0=u_wallace_cska16_fa190_or0
.subckt fa a=u_wallace_cska16_fa190_or0 b=u_wallace_cska16_fa91_or0 cin=u_wallace_cska16_fa48_xor1 fa_xor1=u_wallace_cska16_fa191_xor1 fa_or0=u_wallace_cska16_fa191_or0
.subckt fa a=u_wallace_cska16_fa191_or0 b=u_wallace_cska16_fa71_or0 cin=u_wallace_cska16_fa24_xor1 fa_xor1=u_wallace_cska16_fa192_xor1 fa_or0=u_wallace_cska16_fa192_or0
.subckt and_gate a=a[13] b=b[15] out=u_wallace_cska16_and_13_15
.subckt fa a=u_wallace_cska16_fa192_or0 b=u_wallace_cska16_fa49_or0 cin=u_wallace_cska16_and_13_15 fa_xor1=u_wallace_cska16_fa193_xor1 fa_or0=u_wallace_cska16_fa193_or0
.subckt and_gate a=a[15] b=b[14] out=u_wallace_cska16_and_15_14
.subckt fa a=u_wallace_cska16_fa193_or0 b=u_wallace_cska16_fa25_or0 cin=u_wallace_cska16_and_15_14 fa_xor1=u_wallace_cska16_fa194_xor1 fa_or0=u_wallace_cska16_fa194_or0
.subckt and_gate a=a[0] b=b[0] out=u_wallace_cska16_and_0_0
.subckt and_gate a=a[1] b=b[0] out=u_wallace_cska16_and_1_0
.subckt and_gate a=a[0] b=b[2] out=u_wallace_cska16_and_0_2
.subckt and_gate a=a[14] b=b[15] out=u_wallace_cska16_and_14_15
.subckt and_gate a=a[0] b=b[1] out=u_wallace_cska16_and_0_1
.subckt and_gate a=a[15] b=b[15] out=u_wallace_cska16_and_15_15
.names u_wallace_cska16_and_1_0 u_wallace_cska16_u_cska30_a[0]
1 1
.names u_wallace_cska16_and_0_2 u_wallace_cska16_u_cska30_a[1]
1 1
.names u_wallace_cska16_fa0_xor1 u_wallace_cska16_u_cska30_a[2]
1 1
.names u_wallace_cska16_fa26_xor1 u_wallace_cska16_u_cska30_a[3]
1 1
.names u_wallace_cska16_fa50_xor1 u_wallace_cska16_u_cska30_a[4]
1 1
.names u_wallace_cska16_fa72_xor1 u_wallace_cska16_u_cska30_a[5]
1 1
.names u_wallace_cska16_fa92_xor1 u_wallace_cska16_u_cska30_a[6]
1 1
.names u_wallace_cska16_fa110_xor1 u_wallace_cska16_u_cska30_a[7]
1 1
.names u_wallace_cska16_fa126_xor1 u_wallace_cska16_u_cska30_a[8]
1 1
.names u_wallace_cska16_fa140_xor1 u_wallace_cska16_u_cska30_a[9]
1 1
.names u_wallace_cska16_fa152_xor1 u_wallace_cska16_u_cska30_a[10]
1 1
.names u_wallace_cska16_fa162_xor1 u_wallace_cska16_u_cska30_a[11]
1 1
.names u_wallace_cska16_fa170_xor1 u_wallace_cska16_u_cska30_a[12]
1 1
.names u_wallace_cska16_fa176_xor1 u_wallace_cska16_u_cska30_a[13]
1 1
.names u_wallace_cska16_fa180_xor1 u_wallace_cska16_u_cska30_a[14]
1 1
.names u_wallace_cska16_fa181_xor1 u_wallace_cska16_u_cska30_a[15]
1 1
.names u_wallace_cska16_fa179_xor1 u_wallace_cska16_u_cska30_a[16]
1 1
.names u_wallace_cska16_fa175_xor1 u_wallace_cska16_u_cska30_a[17]
1 1
.names u_wallace_cska16_fa169_xor1 u_wallace_cska16_u_cska30_a[18]
1 1
.names u_wallace_cska16_fa161_xor1 u_wallace_cska16_u_cska30_a[19]
1 1
.names u_wallace_cska16_fa151_xor1 u_wallace_cska16_u_cska30_a[20]
1 1
.names u_wallace_cska16_fa139_xor1 u_wallace_cska16_u_cska30_a[21]
1 1
.names u_wallace_cska16_fa125_xor1 u_wallace_cska16_u_cska30_a[22]
1 1
.names u_wallace_cska16_fa109_xor1 u_wallace_cska16_u_cska30_a[23]
1 1
.names u_wallace_cska16_fa91_xor1 u_wallace_cska16_u_cska30_a[24]
1 1
.names u_wallace_cska16_fa71_xor1 u_wallace_cska16_u_cska30_a[25]
1 1
.names u_wallace_cska16_fa49_xor1 u_wallace_cska16_u_cska30_a[26]
1 1
.names u_wallace_cska16_fa25_xor1 u_wallace_cska16_u_cska30_a[27]
1 1
.names u_wallace_cska16_and_14_15 u_wallace_cska16_u_cska30_a[28]
1 1
.names u_wallace_cska16_fa194_or0 u_wallace_cska16_u_cska30_a[29]
1 1
.names u_wallace_cska16_and_0_1 u_wallace_cska16_u_cska30_b[0]
1 1
.names u_wallace_cska16_ha0_xor0 u_wallace_cska16_u_cska30_b[1]
1 1
.names u_wallace_cska16_ha1_xor0 u_wallace_cska16_u_cska30_b[2]
1 1
.names u_wallace_cska16_ha2_xor0 u_wallace_cska16_u_cska30_b[3]
1 1
.names u_wallace_cska16_ha3_xor0 u_wallace_cska16_u_cska30_b[4]
1 1
.names u_wallace_cska16_ha4_xor0 u_wallace_cska16_u_cska30_b[5]
1 1
.names u_wallace_cska16_ha5_xor0 u_wallace_cska16_u_cska30_b[6]
1 1
.names u_wallace_cska16_ha6_xor0 u_wallace_cska16_u_cska30_b[7]
1 1
.names u_wallace_cska16_ha7_xor0 u_wallace_cska16_u_cska30_b[8]
1 1
.names u_wallace_cska16_ha8_xor0 u_wallace_cska16_u_cska30_b[9]
1 1
.names u_wallace_cska16_ha9_xor0 u_wallace_cska16_u_cska30_b[10]
1 1
.names u_wallace_cska16_ha10_xor0 u_wallace_cska16_u_cska30_b[11]
1 1
.names u_wallace_cska16_ha11_xor0 u_wallace_cska16_u_cska30_b[12]
1 1
.names u_wallace_cska16_ha12_xor0 u_wallace_cska16_u_cska30_b[13]
1 1
.names u_wallace_cska16_ha13_xor0 u_wallace_cska16_u_cska30_b[14]
1 1
.names u_wallace_cska16_ha14_xor0 u_wallace_cska16_u_cska30_b[15]
1 1
.names u_wallace_cska16_fa182_xor1 u_wallace_cska16_u_cska30_b[16]
1 1
.names u_wallace_cska16_fa183_xor1 u_wallace_cska16_u_cska30_b[17]
1 1
.names u_wallace_cska16_fa184_xor1 u_wallace_cska16_u_cska30_b[18]
1 1
.names u_wallace_cska16_fa185_xor1 u_wallace_cska16_u_cska30_b[19]
1 1
.names u_wallace_cska16_fa186_xor1 u_wallace_cska16_u_cska30_b[20]
1 1
.names u_wallace_cska16_fa187_xor1 u_wallace_cska16_u_cska30_b[21]
1 1
.names u_wallace_cska16_fa188_xor1 u_wallace_cska16_u_cska30_b[22]
1 1
.names u_wallace_cska16_fa189_xor1 u_wallace_cska16_u_cska30_b[23]
1 1
.names u_wallace_cska16_fa190_xor1 u_wallace_cska16_u_cska30_b[24]
1 1
.names u_wallace_cska16_fa191_xor1 u_wallace_cska16_u_cska30_b[25]
1 1
.names u_wallace_cska16_fa192_xor1 u_wallace_cska16_u_cska30_b[26]
1 1
.names u_wallace_cska16_fa193_xor1 u_wallace_cska16_u_cska30_b[27]
1 1
.names u_wallace_cska16_fa194_xor1 u_wallace_cska16_u_cska30_b[28]
1 1
.names u_wallace_cska16_and_15_15 u_wallace_cska16_u_cska30_b[29]
1 1
.subckt u_cska30 a[0]=u_wallace_cska16_u_cska30_a[0] a[1]=u_wallace_cska16_u_cska30_a[1] a[2]=u_wallace_cska16_u_cska30_a[2] a[3]=u_wallace_cska16_u_cska30_a[3] a[4]=u_wallace_cska16_u_cska30_a[4] a[5]=u_wallace_cska16_u_cska30_a[5] a[6]=u_wallace_cska16_u_cska30_a[6] a[7]=u_wallace_cska16_u_cska30_a[7] a[8]=u_wallace_cska16_u_cska30_a[8] a[9]=u_wallace_cska16_u_cska30_a[9] a[10]=u_wallace_cska16_u_cska30_a[10] a[11]=u_wallace_cska16_u_cska30_a[11] a[12]=u_wallace_cska16_u_cska30_a[12] a[13]=u_wallace_cska16_u_cska30_a[13] a[14]=u_wallace_cska16_u_cska30_a[14] a[15]=u_wallace_cska16_u_cska30_a[15] a[16]=u_wallace_cska16_u_cska30_a[16] a[17]=u_wallace_cska16_u_cska30_a[17] a[18]=u_wallace_cska16_u_cska30_a[18] a[19]=u_wallace_cska16_u_cska30_a[19] a[20]=u_wallace_cska16_u_cska30_a[20] a[21]=u_wallace_cska16_u_cska30_a[21] a[22]=u_wallace_cska16_u_cska30_a[22] a[23]=u_wallace_cska16_u_cska30_a[23] a[24]=u_wallace_cska16_u_cska30_a[24] a[25]=u_wallace_cska16_u_cska30_a[25] a[26]=u_wallace_cska16_u_cska30_a[26] a[27]=u_wallace_cska16_u_cska30_a[27] a[28]=u_wallace_cska16_u_cska30_a[28] a[29]=u_wallace_cska16_u_cska30_a[29] b[0]=u_wallace_cska16_u_cska30_b[0] b[1]=u_wallace_cska16_u_cska30_b[1] b[2]=u_wallace_cska16_u_cska30_b[2] b[3]=u_wallace_cska16_u_cska30_b[3] b[4]=u_wallace_cska16_u_cska30_b[4] b[5]=u_wallace_cska16_u_cska30_b[5] b[6]=u_wallace_cska16_u_cska30_b[6] b[7]=u_wallace_cska16_u_cska30_b[7] b[8]=u_wallace_cska16_u_cska30_b[8] b[9]=u_wallace_cska16_u_cska30_b[9] b[10]=u_wallace_cska16_u_cska30_b[10] b[11]=u_wallace_cska16_u_cska30_b[11] b[12]=u_wallace_cska16_u_cska30_b[12] b[13]=u_wallace_cska16_u_cska30_b[13] b[14]=u_wallace_cska16_u_cska30_b[14] b[15]=u_wallace_cska16_u_cska30_b[15] b[16]=u_wallace_cska16_u_cska30_b[16] b[17]=u_wallace_cska16_u_cska30_b[17] b[18]=u_wallace_cska16_u_cska30_b[18] b[19]=u_wallace_cska16_u_cska30_b[19] b[20]=u_wallace_cska16_u_cska30_b[20] b[21]=u_wallace_cska16_u_cska30_b[21] b[22]=u_wallace_cska16_u_cska30_b[22] b[23]=u_wallace_cska16_u_cska30_b[23] b[24]=u_wallace_cska16_u_cska30_b[24] b[25]=u_wallace_cska16_u_cska30_b[25] b[26]=u_wallace_cska16_u_cska30_b[26] b[27]=u_wallace_cska16_u_cska30_b[27] b[28]=u_wallace_cska16_u_cska30_b[28] b[29]=u_wallace_cska16_u_cska30_b[29] u_cska30_out[0]=u_wallace_cska16_u_cska30_ha0_xor0 u_cska30_out[1]=u_wallace_cska16_u_cska30_fa0_xor1 u_cska30_out[2]=u_wallace_cska16_u_cska30_fa1_xor1 u_cska30_out[3]=u_wallace_cska16_u_cska30_fa2_xor1 u_cska30_out[4]=u_wallace_cska16_u_cska30_fa3_xor1 u_cska30_out[5]=u_wallace_cska16_u_cska30_fa4_xor1 u_cska30_out[6]=u_wallace_cska16_u_cska30_fa5_xor1 u_cska30_out[7]=u_wallace_cska16_u_cska30_fa6_xor1 u_cska30_out[8]=u_wallace_cska16_u_cska30_fa7_xor1 u_cska30_out[9]=u_wallace_cska16_u_cska30_fa8_xor1 u_cska30_out[10]=u_wallace_cska16_u_cska30_fa9_xor1 u_cska30_out[11]=u_wallace_cska16_u_cska30_fa10_xor1 u_cska30_out[12]=u_wallace_cska16_u_cska30_fa11_xor1 u_cska30_out[13]=u_wallace_cska16_u_cska30_fa12_xor1 u_cska30_out[14]=u_wallace_cska16_u_cska30_fa13_xor1 u_cska30_out[15]=u_wallace_cska16_u_cska30_fa14_xor1 u_cska30_out[16]=u_wallace_cska16_u_cska30_fa15_xor1 u_cska30_out[17]=u_wallace_cska16_u_cska30_fa16_xor1 u_cska30_out[18]=u_wallace_cska16_u_cska30_fa17_xor1 u_cska30_out[19]=u_wallace_cska16_u_cska30_fa18_xor1 u_cska30_out[20]=u_wallace_cska16_u_cska30_fa19_xor1 u_cska30_out[21]=u_wallace_cska16_u_cska30_fa20_xor1 u_cska30_out[22]=u_wallace_cska16_u_cska30_fa21_xor1 u_cska30_out[23]=u_wallace_cska16_u_cska30_fa22_xor1 u_cska30_out[24]=u_wallace_cska16_u_cska30_fa23_xor1 u_cska30_out[25]=u_wallace_cska16_u_cska30_fa24_xor1 u_cska30_out[26]=u_wallace_cska16_u_cska30_fa25_xor1 u_cska30_out[27]=u_wallace_cska16_u_cska30_fa26_xor1 u_cska30_out[28]=u_wallace_cska16_u_cska30_fa27_xor1 u_cska30_out[29]=u_wallace_cska16_u_cska30_fa28_xor1 u_cska30_out[30]=u_wallace_cska16_u_cska30_mux2to17_xor0
.names u_wallace_cska16_and_0_0 u_wallace_cska16_out[0]
1 1
.names u_wallace_cska16_u_cska30_ha0_xor0 u_wallace_cska16_out[1]
1 1
.names u_wallace_cska16_u_cska30_fa0_xor1 u_wallace_cska16_out[2]
1 1
.names u_wallace_cska16_u_cska30_fa1_xor1 u_wallace_cska16_out[3]
1 1
.names u_wallace_cska16_u_cska30_fa2_xor1 u_wallace_cska16_out[4]
1 1
.names u_wallace_cska16_u_cska30_fa3_xor1 u_wallace_cska16_out[5]
1 1
.names u_wallace_cska16_u_cska30_fa4_xor1 u_wallace_cska16_out[6]
1 1
.names u_wallace_cska16_u_cska30_fa5_xor1 u_wallace_cska16_out[7]
1 1
.names u_wallace_cska16_u_cska30_fa6_xor1 u_wallace_cska16_out[8]
1 1
.names u_wallace_cska16_u_cska30_fa7_xor1 u_wallace_cska16_out[9]
1 1
.names u_wallace_cska16_u_cska30_fa8_xor1 u_wallace_cska16_out[10]
1 1
.names u_wallace_cska16_u_cska30_fa9_xor1 u_wallace_cska16_out[11]
1 1
.names u_wallace_cska16_u_cska30_fa10_xor1 u_wallace_cska16_out[12]
1 1
.names u_wallace_cska16_u_cska30_fa11_xor1 u_wallace_cska16_out[13]
1 1
.names u_wallace_cska16_u_cska30_fa12_xor1 u_wallace_cska16_out[14]
1 1
.names u_wallace_cska16_u_cska30_fa13_xor1 u_wallace_cska16_out[15]
1 1
.names u_wallace_cska16_u_cska30_fa14_xor1 u_wallace_cska16_out[16]
1 1
.names u_wallace_cska16_u_cska30_fa15_xor1 u_wallace_cska16_out[17]
1 1
.names u_wallace_cska16_u_cska30_fa16_xor1 u_wallace_cska16_out[18]
1 1
.names u_wallace_cska16_u_cska30_fa17_xor1 u_wallace_cska16_out[19]
1 1
.names u_wallace_cska16_u_cska30_fa18_xor1 u_wallace_cska16_out[20]
1 1
.names u_wallace_cska16_u_cska30_fa19_xor1 u_wallace_cska16_out[21]
1 1
.names u_wallace_cska16_u_cska30_fa20_xor1 u_wallace_cska16_out[22]
1 1
.names u_wallace_cska16_u_cska30_fa21_xor1 u_wallace_cska16_out[23]
1 1
.names u_wallace_cska16_u_cska30_fa22_xor1 u_wallace_cska16_out[24]
1 1
.names u_wallace_cska16_u_cska30_fa23_xor1 u_wallace_cska16_out[25]
1 1
.names u_wallace_cska16_u_cska30_fa24_xor1 u_wallace_cska16_out[26]
1 1
.names u_wallace_cska16_u_cska30_fa25_xor1 u_wallace_cska16_out[27]
1 1
.names u_wallace_cska16_u_cska30_fa26_xor1 u_wallace_cska16_out[28]
1 1
.names u_wallace_cska16_u_cska30_fa27_xor1 u_wallace_cska16_out[29]
1 1
.names u_wallace_cska16_u_cska30_fa28_xor1 u_wallace_cska16_out[30]
1 1
.names u_wallace_cska16_u_cska30_mux2to17_xor0 u_wallace_cska16_out[31]
1 1
.end

.model u_cska30
.inputs a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] a[8] a[9] a[10] a[11] a[12] a[13] a[14] a[15] a[16] a[17] a[18] a[19] a[20] a[21] a[22] a[23] a[24] a[25] a[26] a[27] a[28] a[29] b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9] b[10] b[11] b[12] b[13] b[14] b[15] b[16] b[17] b[18] b[19] b[20] b[21] b[22] b[23] b[24] b[25] b[26] b[27] b[28] b[29]
.outputs u_cska30_out[0] u_cska30_out[1] u_cska30_out[2] u_cska30_out[3] u_cska30_out[4] u_cska30_out[5] u_cska30_out[6] u_cska30_out[7] u_cska30_out[8] u_cska30_out[9] u_cska30_out[10] u_cska30_out[11] u_cska30_out[12] u_cska30_out[13] u_cska30_out[14] u_cska30_out[15] u_cska30_out[16] u_cska30_out[17] u_cska30_out[18] u_cska30_out[19] u_cska30_out[20] u_cska30_out[21] u_cska30_out[22] u_cska30_out[23] u_cska30_out[24] u_cska30_out[25] u_cska30_out[26] u_cska30_out[27] u_cska30_out[28] u_cska30_out[29] u_cska30_out[30]
.names vdd
1
.names gnd
0
.subckt xor_gate a=a[0] b=b[0] out=u_cska30_xor0
.subckt ha a=a[0] b=b[0] ha_xor0=u_cska30_ha0_xor0 ha_and0=u_cska30_ha0_and0
.subckt xor_gate a=a[1] b=b[1] out=u_cska30_xor1
.subckt fa a=a[1] b=b[1] cin=u_cska30_ha0_and0 fa_xor1=u_cska30_fa0_xor1 fa_or0=u_cska30_fa0_or0
.subckt xor_gate a=a[2] b=b[2] out=u_cska30_xor2
.subckt fa a=a[2] b=b[2] cin=u_cska30_fa0_or0 fa_xor1=u_cska30_fa1_xor1 fa_or0=u_cska30_fa1_or0
.subckt xor_gate a=a[3] b=b[3] out=u_cska30_xor3
.subckt fa a=a[3] b=b[3] cin=u_cska30_fa1_or0 fa_xor1=u_cska30_fa2_xor1 fa_or0=u_cska30_fa2_or0
.subckt and_gate a=u_cska30_xor0 b=u_cska30_xor2 out=u_cska30_and_propagate00
.subckt and_gate a=u_cska30_xor1 b=u_cska30_xor3 out=u_cska30_and_propagate01
.subckt and_gate a=u_cska30_and_propagate00 b=u_cska30_and_propagate01 out=u_cska30_and_propagate02
.subckt mux2to1 d0=u_cska30_fa2_or0 d1=gnd sel=u_cska30_and_propagate02 mux2to1_xor0=u_cska30_mux2to10_and1
.subckt xor_gate a=a[4] b=b[4] out=u_cska30_xor4
.subckt fa a=a[4] b=b[4] cin=u_cska30_mux2to10_and1 fa_xor1=u_cska30_fa3_xor1 fa_or0=u_cska30_fa3_or0
.subckt xor_gate a=a[5] b=b[5] out=u_cska30_xor5
.subckt fa a=a[5] b=b[5] cin=u_cska30_fa3_or0 fa_xor1=u_cska30_fa4_xor1 fa_or0=u_cska30_fa4_or0
.subckt xor_gate a=a[6] b=b[6] out=u_cska30_xor6
.subckt fa a=a[6] b=b[6] cin=u_cska30_fa4_or0 fa_xor1=u_cska30_fa5_xor1 fa_or0=u_cska30_fa5_or0
.subckt xor_gate a=a[7] b=b[7] out=u_cska30_xor7
.subckt fa a=a[7] b=b[7] cin=u_cska30_fa5_or0 fa_xor1=u_cska30_fa6_xor1 fa_or0=u_cska30_fa6_or0
.subckt and_gate a=u_cska30_xor4 b=u_cska30_xor6 out=u_cska30_and_propagate13
.subckt and_gate a=u_cska30_xor5 b=u_cska30_xor7 out=u_cska30_and_propagate14
.subckt and_gate a=u_cska30_and_propagate13 b=u_cska30_and_propagate14 out=u_cska30_and_propagate15
.subckt mux2to1 d0=u_cska30_fa6_or0 d1=u_cska30_mux2to10_and1 sel=u_cska30_and_propagate15 mux2to1_xor0=u_cska30_mux2to11_xor0
.subckt xor_gate a=a[8] b=b[8] out=u_cska30_xor8
.subckt fa a=a[8] b=b[8] cin=u_cska30_mux2to11_xor0 fa_xor1=u_cska30_fa7_xor1 fa_or0=u_cska30_fa7_or0
.subckt xor_gate a=a[9] b=b[9] out=u_cska30_xor9
.subckt fa a=a[9] b=b[9] cin=u_cska30_fa7_or0 fa_xor1=u_cska30_fa8_xor1 fa_or0=u_cska30_fa8_or0
.subckt xor_gate a=a[10] b=b[10] out=u_cska30_xor10
.subckt fa a=a[10] b=b[10] cin=u_cska30_fa8_or0 fa_xor1=u_cska30_fa9_xor1 fa_or0=u_cska30_fa9_or0
.subckt xor_gate a=a[11] b=b[11] out=u_cska30_xor11
.subckt fa a=a[11] b=b[11] cin=u_cska30_fa9_or0 fa_xor1=u_cska30_fa10_xor1 fa_or0=u_cska30_fa10_or0
.subckt and_gate a=u_cska30_xor8 b=u_cska30_xor10 out=u_cska30_and_propagate26
.subckt and_gate a=u_cska30_xor9 b=u_cska30_xor11 out=u_cska30_and_propagate27
.subckt and_gate a=u_cska30_and_propagate26 b=u_cska30_and_propagate27 out=u_cska30_and_propagate28
.subckt mux2to1 d0=u_cska30_fa10_or0 d1=u_cska30_mux2to11_xor0 sel=u_cska30_and_propagate28 mux2to1_xor0=u_cska30_mux2to12_xor0
.subckt xor_gate a=a[12] b=b[12] out=u_cska30_xor12
.subckt fa a=a[12] b=b[12] cin=u_cska30_mux2to12_xor0 fa_xor1=u_cska30_fa11_xor1 fa_or0=u_cska30_fa11_or0
.subckt xor_gate a=a[13] b=b[13] out=u_cska30_xor13
.subckt fa a=a[13] b=b[13] cin=u_cska30_fa11_or0 fa_xor1=u_cska30_fa12_xor1 fa_or0=u_cska30_fa12_or0
.subckt xor_gate a=a[14] b=b[14] out=u_cska30_xor14
.subckt fa a=a[14] b=b[14] cin=u_cska30_fa12_or0 fa_xor1=u_cska30_fa13_xor1 fa_or0=u_cska30_fa13_or0
.subckt xor_gate a=a[15] b=b[15] out=u_cska30_xor15
.subckt fa a=a[15] b=b[15] cin=u_cska30_fa13_or0 fa_xor1=u_cska30_fa14_xor1 fa_or0=u_cska30_fa14_or0
.subckt and_gate a=u_cska30_xor12 b=u_cska30_xor14 out=u_cska30_and_propagate39
.subckt and_gate a=u_cska30_xor13 b=u_cska30_xor15 out=u_cska30_and_propagate310
.subckt and_gate a=u_cska30_and_propagate39 b=u_cska30_and_propagate310 out=u_cska30_and_propagate311
.subckt mux2to1 d0=u_cska30_fa14_or0 d1=u_cska30_mux2to12_xor0 sel=u_cska30_and_propagate311 mux2to1_xor0=u_cska30_mux2to13_xor0
.subckt xor_gate a=a[16] b=b[16] out=u_cska30_xor16
.subckt fa a=a[16] b=b[16] cin=u_cska30_mux2to13_xor0 fa_xor1=u_cska30_fa15_xor1 fa_or0=u_cska30_fa15_or0
.subckt xor_gate a=a[17] b=b[17] out=u_cska30_xor17
.subckt fa a=a[17] b=b[17] cin=u_cska30_fa15_or0 fa_xor1=u_cska30_fa16_xor1 fa_or0=u_cska30_fa16_or0
.subckt xor_gate a=a[18] b=b[18] out=u_cska30_xor18
.subckt fa a=a[18] b=b[18] cin=u_cska30_fa16_or0 fa_xor1=u_cska30_fa17_xor1 fa_or0=u_cska30_fa17_or0
.subckt xor_gate a=a[19] b=b[19] out=u_cska30_xor19
.subckt fa a=a[19] b=b[19] cin=u_cska30_fa17_or0 fa_xor1=u_cska30_fa18_xor1 fa_or0=u_cska30_fa18_or0
.subckt and_gate a=u_cska30_xor16 b=u_cska30_xor18 out=u_cska30_and_propagate412
.subckt and_gate a=u_cska30_xor17 b=u_cska30_xor19 out=u_cska30_and_propagate413
.subckt and_gate a=u_cska30_and_propagate412 b=u_cska30_and_propagate413 out=u_cska30_and_propagate414
.subckt mux2to1 d0=u_cska30_fa18_or0 d1=u_cska30_mux2to13_xor0 sel=u_cska30_and_propagate414 mux2to1_xor0=u_cska30_mux2to14_xor0
.subckt xor_gate a=a[20] b=b[20] out=u_cska30_xor20
.subckt fa a=a[20] b=b[20] cin=u_cska30_mux2to14_xor0 fa_xor1=u_cska30_fa19_xor1 fa_or0=u_cska30_fa19_or0
.subckt xor_gate a=a[21] b=b[21] out=u_cska30_xor21
.subckt fa a=a[21] b=b[21] cin=u_cska30_fa19_or0 fa_xor1=u_cska30_fa20_xor1 fa_or0=u_cska30_fa20_or0
.subckt xor_gate a=a[22] b=b[22] out=u_cska30_xor22
.subckt fa a=a[22] b=b[22] cin=u_cska30_fa20_or0 fa_xor1=u_cska30_fa21_xor1 fa_or0=u_cska30_fa21_or0
.subckt xor_gate a=a[23] b=b[23] out=u_cska30_xor23
.subckt fa a=a[23] b=b[23] cin=u_cska30_fa21_or0 fa_xor1=u_cska30_fa22_xor1 fa_or0=u_cska30_fa22_or0
.subckt and_gate a=u_cska30_xor20 b=u_cska30_xor22 out=u_cska30_and_propagate515
.subckt and_gate a=u_cska30_xor21 b=u_cska30_xor23 out=u_cska30_and_propagate516
.subckt and_gate a=u_cska30_and_propagate515 b=u_cska30_and_propagate516 out=u_cska30_and_propagate517
.subckt mux2to1 d0=u_cska30_fa22_or0 d1=u_cska30_mux2to14_xor0 sel=u_cska30_and_propagate517 mux2to1_xor0=u_cska30_mux2to15_xor0
.subckt xor_gate a=a[24] b=b[24] out=u_cska30_xor24
.subckt fa a=a[24] b=b[24] cin=u_cska30_mux2to15_xor0 fa_xor1=u_cska30_fa23_xor1 fa_or0=u_cska30_fa23_or0
.subckt xor_gate a=a[25] b=b[25] out=u_cska30_xor25
.subckt fa a=a[25] b=b[25] cin=u_cska30_fa23_or0 fa_xor1=u_cska30_fa24_xor1 fa_or0=u_cska30_fa24_or0
.subckt xor_gate a=a[26] b=b[26] out=u_cska30_xor26
.subckt fa a=a[26] b=b[26] cin=u_cska30_fa24_or0 fa_xor1=u_cska30_fa25_xor1 fa_or0=u_cska30_fa25_or0
.subckt xor_gate a=a[27] b=b[27] out=u_cska30_xor27
.subckt fa a=a[27] b=b[27] cin=u_cska30_fa25_or0 fa_xor1=u_cska30_fa26_xor1 fa_or0=u_cska30_fa26_or0
.subckt and_gate a=u_cska30_xor24 b=u_cska30_xor26 out=u_cska30_and_propagate618
.subckt and_gate a=u_cska30_xor25 b=u_cska30_xor27 out=u_cska30_and_propagate619
.subckt and_gate a=u_cska30_and_propagate618 b=u_cska30_and_propagate619 out=u_cska30_and_propagate620
.subckt mux2to1 d0=u_cska30_fa26_or0 d1=u_cska30_mux2to15_xor0 sel=u_cska30_and_propagate620 mux2to1_xor0=u_cska30_mux2to16_xor0
.subckt xor_gate a=a[28] b=b[28] out=u_cska30_xor28
.subckt fa a=a[28] b=b[28] cin=u_cska30_mux2to16_xor0 fa_xor1=u_cska30_fa27_xor1 fa_or0=u_cska30_fa27_or0
.subckt xor_gate a=a[29] b=b[29] out=u_cska30_xor29
.subckt fa a=a[29] b=b[29] cin=u_cska30_fa27_or0 fa_xor1=u_cska30_fa28_xor1 fa_or0=u_cska30_fa28_or0
.subckt and_gate a=u_cska30_xor28 b=u_cska30_xor29 out=u_cska30_and_propagate721
.subckt mux2to1 d0=u_cska30_fa28_or0 d1=u_cska30_mux2to16_xor0 sel=u_cska30_and_propagate721 mux2to1_xor0=u_cska30_mux2to17_xor0
.names u_cska30_ha0_xor0 u_cska30_out[0]
1 1
.names u_cska30_fa0_xor1 u_cska30_out[1]
1 1
.names u_cska30_fa1_xor1 u_cska30_out[2]
1 1
.names u_cska30_fa2_xor1 u_cska30_out[3]
1 1
.names u_cska30_fa3_xor1 u_cska30_out[4]
1 1
.names u_cska30_fa4_xor1 u_cska30_out[5]
1 1
.names u_cska30_fa5_xor1 u_cska30_out[6]
1 1
.names u_cska30_fa6_xor1 u_cska30_out[7]
1 1
.names u_cska30_fa7_xor1 u_cska30_out[8]
1 1
.names u_cska30_fa8_xor1 u_cska30_out[9]
1 1
.names u_cska30_fa9_xor1 u_cska30_out[10]
1 1
.names u_cska30_fa10_xor1 u_cska30_out[11]
1 1
.names u_cska30_fa11_xor1 u_cska30_out[12]
1 1
.names u_cska30_fa12_xor1 u_cska30_out[13]
1 1
.names u_cska30_fa13_xor1 u_cska30_out[14]
1 1
.names u_cska30_fa14_xor1 u_cska30_out[15]
1 1
.names u_cska30_fa15_xor1 u_cska30_out[16]
1 1
.names u_cska30_fa16_xor1 u_cska30_out[17]
1 1
.names u_cska30_fa17_xor1 u_cska30_out[18]
1 1
.names u_cska30_fa18_xor1 u_cska30_out[19]
1 1
.names u_cska30_fa19_xor1 u_cska30_out[20]
1 1
.names u_cska30_fa20_xor1 u_cska30_out[21]
1 1
.names u_cska30_fa21_xor1 u_cska30_out[22]
1 1
.names u_cska30_fa22_xor1 u_cska30_out[23]
1 1
.names u_cska30_fa23_xor1 u_cska30_out[24]
1 1
.names u_cska30_fa24_xor1 u_cska30_out[25]
1 1
.names u_cska30_fa25_xor1 u_cska30_out[26]
1 1
.names u_cska30_fa26_xor1 u_cska30_out[27]
1 1
.names u_cska30_fa27_xor1 u_cska30_out[28]
1 1
.names u_cska30_fa28_xor1 u_cska30_out[29]
1 1
.names u_cska30_mux2to17_xor0 u_cska30_out[30]
1 1
.end

.model mux2to1
.inputs d0 d1 sel
.outputs mux2to1_xor0
.names vdd
1
.names gnd
0
.subckt and_gate a=d1 b=sel out=mux2to1_and0
.subckt not_gate a=sel out=mux2to1_not0
.subckt and_gate a=d0 b=mux2to1_not0 out=mux2to1_and1
.subckt xor_gate a=mux2to1_and0 b=mux2to1_and1 out=mux2to1_xor0
.end

.model fa
.inputs a b cin
.outputs fa_xor1 fa_or0
.names vdd
1
.names gnd
0
.subckt xor_gate a=a b=b out=fa_xor0
.subckt and_gate a=a b=b out=fa_and0
.subckt xor_gate a=fa_xor0 b=cin out=fa_xor1
.subckt and_gate a=fa_xor0 b=cin out=fa_and1
.subckt or_gate a=fa_and0 b=fa_and1 out=fa_or0
.end

.model ha
.inputs a b
.outputs ha_xor0 ha_and0
.names vdd
1
.names gnd
0
.subckt xor_gate a=a b=b out=ha_xor0
.subckt and_gate a=a b=b out=ha_and0
.end

.model not_gate
.inputs a
.outputs out
.names vdd
1
.names gnd
0
.names a out
0 1
.end

.model or_gate
.inputs a b
.outputs out
.names vdd
1
.names gnd
0
.names a b out
1- 1
-1 1
.end

.model xor_gate
.inputs a b
.outputs out
.names vdd
1
.names gnd
0
.names a b out
01 1
10 1
.end

.model and_gate
.inputs a b
.outputs out
.names vdd
1
.names gnd
0
.names a b out
11 1
.end