3 Commits

Author	SHA1	Message	Date
honzastor	e16de78c2b	Updated logic behind generating export representations, mainly focused around circuit and its buses and subcomponents namings.	2021-09-07 17:39:39 +02:00
honzastor	ad1c6ec557	Updated circuits documentation.	2021-04-21 13:42:07 +02:00
honzastor	8e950fc51f	Optimized circuits generation, refactored code, fixed cla, added new csa, array divider circuits and create yosys equivalence check script. TBD: Documentation and sample generated circuits.	2021-04-21 11:33:07 +02:00