honzastor
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5788b6a879
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Pushing circuits generation example.
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2021-03-22 10:49:54 +01:00 |
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honzastor
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792d0c5db1
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Did some code refactoring concerning one bit circuits generation. Added multiple one/multi bit circuits. TBD: Generate and test different circuits, implement divider circuits, comment code, add verification/optimization of Verilog/BLIF files using yosys tool.
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2021-03-22 00:22:01 +01:00 |
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honzastor
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d86ddcac09
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Implemented unsigned dadda multiplier circuit. Updated generation of export formats. TBD: Proper testing, modification of dadda with cla adder, write shell script for Verilog and Blif equivalence check.
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2021-03-15 01:08:47 +01:00 |
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honzastor
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f28069da5f
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Refactored code and made some small bugfixes for generating exports.
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2021-03-04 18:57:32 +01:00 |
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honzastor
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e4722c662d
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Implemented multiplier circuits, verilog and cgp export generation and changed generator's structure. Prone to error! Needs proper testing. TBD
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2021-03-01 21:32:29 +01:00 |
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