9 Commits

Author	SHA1	Message	Date
Vojta Mrazek	995107eecc	Removing of file closing	2021-09-23 08:50:18 +02:00
honzastor	eba0a7a938	Made some minor changes concerning proper exportation of multiplier circuits.	2021-09-09 13:57:36 +02:00
honzastor	e16de78c2b	Updated logic behind generating export representations, mainly focused around circuit and its buses and subcomponents namings.	2021-09-07 17:39:39 +02:00
Vojta Mrazek	8c0f24cd2d	General MAC circuit	2021-09-06 12:52:13 +02:00
Vojta Mrazek	0a487ee699	CGP format	2021-06-23 14:08:49 +02:00
Vojta Mrazek	c6e542231c	CGP tests; reversed output order	2021-06-23 13:43:58 +02:00
honzastor	0f66c5a2e9	Fixed proper connections in submodules instantiation in hierarchical Verilog generation. Sample generated circuits were also accordingly updated.	2021-04-23 11:49:24 +02:00
honzastor	670ba45ee5	Generated sample circuits for various representations. Updated C code circuits testing simulations and did some cleanup.	2021-04-23 02:44:14 +02:00
honzastor	8e950fc51f	Optimized circuits generation, refactored code, fixed cla, added new csa, array divider circuits and create yosys equivalence check script. TBD: Documentation and sample generated circuits.	2021-04-21 11:33:07 +02:00