Honza
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13c085f169
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Fixed a small bug – missing ending semicolon in generation of library desired HA/FA to Verilog. Added script for generation of AX multipliers.
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2022-01-13 13:11:24 +01:00 |
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Vojta Mrazek
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d641595c3e
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Support of PDK in HA and FA
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2022-01-13 12:37:09 +01:00 |
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honzastor
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670ba45ee5
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Generated sample circuits for various representations. Updated C code circuits testing simulations and did some cleanup.
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2021-04-23 02:44:14 +02:00 |
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honzastor
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ad1c6ec557
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Updated circuits documentation.
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2021-04-21 13:42:07 +02:00 |
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honzastor
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8e950fc51f
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Optimized circuits generation, refactored code, fixed cla, added new csa, array divider circuits and create yosys equivalence check script. TBD: Documentation and sample generated circuits.
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2021-04-21 11:33:07 +02:00 |
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honzastor
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068def0226
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Added documentation of classes methods.
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2021-04-06 01:39:11 +02:00 |
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honzastor
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a336a683e7
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Added some code documentation and updated git action to generate it.
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2021-03-31 04:40:54 +02:00 |
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Jan Klhůfek
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82d2d02ef5
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Delete ariths_gen/one_bit_circuits/logic_gates/__pycache__ directory
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2021-03-30 03:13:15 +02:00 |
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Jan Klhůfek
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debef13087
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Delete ariths_gen/one_bit_circuits/one_bit_components/__pycache__ directory
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2021-03-30 03:13:04 +02:00 |
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Jan Klhůfek
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1e2ae53df5
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Delete ariths_gen/one_bit_circuits/__pycache__ directory
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2021-03-30 03:11:57 +02:00 |
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honzastor
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69e2514852
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Updated project's structure. Renamed class names to properly fit Python naming convention. TBD: proper documentation.
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2021-03-30 03:04:48 +02:00 |
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